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f5bfa23f AP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2018 SiFive | |
4 | * Copyright (C) 2018 Andes Technology Corporation | |
5 | * Copyright (C) 2021 Western Digital Corporation or its affiliates. | |
6 | * | |
7 | */ | |
8 | ||
f117ae55 AG |
9 | #ifndef _RISCV_PMU_H |
10 | #define _RISCV_PMU_H | |
f5bfa23f AP |
11 | |
12 | #include <linux/perf_event.h> | |
13 | #include <linux/ptrace.h> | |
14 | #include <linux/interrupt.h> | |
15 | ||
16 | #ifdef CONFIG_RISCV_PMU | |
17 | ||
18 | /* | |
19 | * The RISCV_MAX_COUNTERS parameter should be specified. | |
20 | */ | |
21 | ||
22 | #define RISCV_MAX_COUNTERS 64 | |
23 | #define RISCV_OP_UNSUPP (-EOPNOTSUPP) | |
d5ac062d | 24 | #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" |
9b3e150e | 25 | #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" |
f5bfa23f AP |
26 | |
27 | #define RISCV_PMU_STOP_FLAG_RESET 1 | |
28 | ||
8929283a AP |
29 | #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 |
30 | ||
f5bfa23f AP |
31 | struct cpu_hw_events { |
32 | /* currently enabled events */ | |
33 | int n_events; | |
4905ec2f AP |
34 | /* Counter overflow interrupt */ |
35 | int irq; | |
f5bfa23f AP |
36 | /* currently enabled events */ |
37 | struct perf_event *events[RISCV_MAX_COUNTERS]; | |
e9991434 AP |
38 | /* currently enabled hardware counters */ |
39 | DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); | |
40 | /* currently enabled firmware counters */ | |
41 | DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); | |
f5bfa23f AP |
42 | }; |
43 | ||
44 | struct riscv_pmu { | |
45 | struct pmu pmu; | |
46 | char *name; | |
47 | ||
48 | irqreturn_t (*handle_irq)(int irq_num, void *dev); | |
49 | ||
1537bf26 | 50 | unsigned long cmask; |
f5bfa23f AP |
51 | u64 (*ctr_read)(struct perf_event *event); |
52 | int (*ctr_get_idx)(struct perf_event *event); | |
53 | int (*ctr_get_width)(int idx); | |
54 | void (*ctr_clear_idx)(struct perf_event *event); | |
55 | void (*ctr_start)(struct perf_event *event, u64 init_val); | |
56 | void (*ctr_stop)(struct perf_event *event, unsigned long flag); | |
57 | int (*event_map)(struct perf_event *event, u64 *config); | |
83c5e13b AG |
58 | void (*event_init)(struct perf_event *event); |
59 | void (*event_mapped)(struct perf_event *event, struct mm_struct *mm); | |
60 | void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm); | |
61 | uint8_t (*csr_index)(struct perf_event *event); | |
f5bfa23f AP |
62 | |
63 | struct cpu_hw_events __percpu *hw_events; | |
64 | struct hlist_node node; | |
e9a023f2 | 65 | struct notifier_block riscv_pm_nb; |
f5bfa23f AP |
66 | }; |
67 | ||
68 | #define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu)) | |
e9a023f2 EL |
69 | |
70 | void riscv_pmu_start(struct perf_event *event, int flags); | |
71 | void riscv_pmu_stop(struct perf_event *event, int flags); | |
f5bfa23f AP |
72 | unsigned long riscv_pmu_ctr_read_csr(unsigned long csr); |
73 | int riscv_pmu_event_set_period(struct perf_event *event); | |
74 | uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event); | |
75 | u64 riscv_pmu_event_update(struct perf_event *event); | |
9b3e150e AP |
76 | #ifdef CONFIG_RISCV_PMU_LEGACY |
77 | void riscv_pmu_legacy_skip_init(void); | |
78 | #else | |
79 | static inline void riscv_pmu_legacy_skip_init(void) {}; | |
80 | #endif | |
f5bfa23f | 81 | struct riscv_pmu *riscv_pmu_alloc(void); |
585e351f AP |
82 | #ifdef CONFIG_RISCV_PMU_SBI |
83 | int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); | |
84 | #endif | |
f5bfa23f AP |
85 | |
86 | #endif /* CONFIG_RISCV_PMU */ | |
87 | ||
f117ae55 | 88 | #endif /* _RISCV_PMU_H */ |