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7755cec6 MZ |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2012 ARM Ltd. | |
4 | */ | |
5 | ||
6 | #ifndef __PERF_ARM_PMUV3_H | |
7 | #define __PERF_ARM_PMUV3_H | |
8 | ||
9 | #define ARMV8_PMU_MAX_COUNTERS 32 | |
10 | #define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1) | |
11 | ||
12 | /* | |
13 | * Common architectural and microarchitectural event numbers. | |
14 | */ | |
15 | #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000 | |
16 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001 | |
17 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002 | |
18 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003 | |
19 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004 | |
20 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005 | |
21 | #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006 | |
22 | #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007 | |
23 | #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008 | |
24 | #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009 | |
25 | #define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A | |
26 | #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B | |
27 | #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C | |
28 | #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D | |
29 | #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E | |
30 | #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F | |
31 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010 | |
32 | #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011 | |
33 | #define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012 | |
34 | #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013 | |
35 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014 | |
36 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015 | |
37 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016 | |
38 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017 | |
39 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018 | |
40 | #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019 | |
41 | #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A | |
42 | #define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B | |
43 | #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C | |
44 | #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D | |
45 | #define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E | |
46 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F | |
47 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020 | |
48 | #define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021 | |
49 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022 | |
50 | #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023 | |
51 | #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024 | |
52 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025 | |
53 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026 | |
54 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027 | |
55 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028 | |
56 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029 | |
57 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A | |
58 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B | |
59 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C | |
60 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D | |
61 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E | |
62 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F | |
63 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030 | |
64 | #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031 | |
65 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032 | |
66 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033 | |
67 | #define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034 | |
68 | #define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035 | |
69 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036 | |
70 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037 | |
71 | #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038 | |
72 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039 | |
73 | #define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A | |
74 | #define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B | |
75 | #define ARMV8_PMUV3_PERFCTR_STALL 0x003C | |
76 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D | |
77 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E | |
78 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F | |
79 | ||
80 | /* Statistical profiling extension microarchitectural events */ | |
81 | #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000 | |
82 | #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001 | |
83 | #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002 | |
84 | #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003 | |
85 | ||
86 | /* AMUv1 architecture events */ | |
87 | #define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004 | |
88 | #define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005 | |
89 | ||
90 | /* long-latency read miss events */ | |
91 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006 | |
92 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009 | |
93 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A | |
94 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B | |
95 | ||
96 | /* Trace buffer events */ | |
97 | #define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C | |
98 | #define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E | |
99 | ||
100 | /* Trace unit events */ | |
101 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010 | |
102 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011 | |
103 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012 | |
104 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013 | |
105 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018 | |
106 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019 | |
107 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A | |
108 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B | |
109 | ||
110 | /* additional latency from alignment events */ | |
111 | #define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020 | |
112 | #define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021 | |
113 | #define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022 | |
114 | ||
115 | /* Armv8.5 Memory Tagging Extension events */ | |
116 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024 | |
117 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025 | |
118 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026 | |
119 | ||
120 | /* ARMv8 recommended implementation defined event types */ | |
121 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040 | |
122 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041 | |
123 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042 | |
124 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043 | |
125 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044 | |
126 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045 | |
127 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046 | |
128 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047 | |
129 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048 | |
130 | ||
131 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C | |
132 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D | |
133 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E | |
134 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F | |
135 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050 | |
136 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051 | |
137 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052 | |
138 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053 | |
139 | ||
140 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056 | |
141 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057 | |
142 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058 | |
143 | ||
144 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C | |
145 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D | |
146 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E | |
147 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F | |
148 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060 | |
149 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061 | |
150 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062 | |
151 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063 | |
152 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064 | |
153 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065 | |
154 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066 | |
155 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067 | |
156 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068 | |
157 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069 | |
158 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A | |
159 | ||
160 | #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C | |
161 | #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D | |
162 | #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E | |
163 | #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F | |
164 | #define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070 | |
165 | #define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071 | |
166 | #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072 | |
167 | #define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073 | |
168 | #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074 | |
169 | #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075 | |
170 | #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076 | |
171 | #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077 | |
172 | #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078 | |
173 | #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079 | |
174 | #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A | |
175 | ||
176 | #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C | |
177 | #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D | |
178 | #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E | |
179 | ||
180 | #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081 | |
181 | #define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082 | |
182 | #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083 | |
183 | #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084 | |
184 | ||
185 | #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086 | |
186 | #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087 | |
187 | #define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088 | |
188 | ||
189 | #define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A | |
190 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B | |
191 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C | |
192 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D | |
193 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E | |
194 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F | |
195 | #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090 | |
196 | #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091 | |
197 | ||
198 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0 | |
199 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1 | |
200 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2 | |
201 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3 | |
202 | ||
203 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6 | |
204 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7 | |
205 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8 | |
206 | ||
207 | /* | |
208 | * Per-CPU PMCR: config reg | |
209 | */ | |
210 | #define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */ | |
211 | #define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */ | |
212 | #define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */ | |
213 | #define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ | |
214 | #define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */ | |
215 | #define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ | |
216 | #define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ | |
217 | #define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */ | |
218 | #define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */ | |
219 | #define ARMV8_PMU_PMCR_N_MASK 0x1f | |
220 | #define ARMV8_PMU_PMCR_MASK 0xff /* Mask for writable bits */ | |
221 | ||
222 | /* | |
223 | * PMOVSR: counters overflow flag status reg | |
224 | */ | |
225 | #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ | |
226 | #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK | |
227 | ||
228 | /* | |
229 | * PMXEVTYPER: Event selection reg | |
230 | */ | |
231 | #define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */ | |
232 | #define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */ | |
233 | ||
234 | /* | |
235 | * Event filters for PMUv3 | |
236 | */ | |
ae8d3522 OU |
237 | #define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) |
238 | #define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) | |
239 | #define ARMV8_PMU_EXCLUDE_NS_EL1 (1U << 29) | |
240 | #define ARMV8_PMU_EXCLUDE_NS_EL0 (1U << 28) | |
241 | #define ARMV8_PMU_INCLUDE_EL2 (1U << 27) | |
242 | #define ARMV8_PMU_EXCLUDE_EL3 (1U << 26) | |
7755cec6 MZ |
243 | |
244 | /* | |
245 | * PMUSERENR: user enable reg | |
246 | */ | |
247 | #define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */ | |
248 | #define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */ | |
249 | #define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */ | |
250 | #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ | |
251 | #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ | |
252 | ||
253 | /* PMMIR_EL1.SLOTS mask */ | |
254 | #define ARMV8_PMU_SLOTS_MASK 0xff | |
255 | ||
256 | #define ARMV8_PMU_BUS_SLOTS_SHIFT 8 | |
257 | #define ARMV8_PMU_BUS_SLOTS_MASK 0xff | |
258 | #define ARMV8_PMU_BUS_WIDTH_SHIFT 16 | |
259 | #define ARMV8_PMU_BUS_WIDTH_MASK 0xf | |
260 | ||
df29ddf4 MZ |
261 | /* |
262 | * This code is really good | |
263 | */ | |
264 | ||
265 | #define PMEVN_CASE(n, case_macro) \ | |
266 | case n: case_macro(n); break | |
267 | ||
268 | #define PMEVN_SWITCH(x, case_macro) \ | |
269 | do { \ | |
270 | switch (x) { \ | |
271 | PMEVN_CASE(0, case_macro); \ | |
272 | PMEVN_CASE(1, case_macro); \ | |
273 | PMEVN_CASE(2, case_macro); \ | |
274 | PMEVN_CASE(3, case_macro); \ | |
275 | PMEVN_CASE(4, case_macro); \ | |
276 | PMEVN_CASE(5, case_macro); \ | |
277 | PMEVN_CASE(6, case_macro); \ | |
278 | PMEVN_CASE(7, case_macro); \ | |
279 | PMEVN_CASE(8, case_macro); \ | |
280 | PMEVN_CASE(9, case_macro); \ | |
281 | PMEVN_CASE(10, case_macro); \ | |
282 | PMEVN_CASE(11, case_macro); \ | |
283 | PMEVN_CASE(12, case_macro); \ | |
284 | PMEVN_CASE(13, case_macro); \ | |
285 | PMEVN_CASE(14, case_macro); \ | |
286 | PMEVN_CASE(15, case_macro); \ | |
287 | PMEVN_CASE(16, case_macro); \ | |
288 | PMEVN_CASE(17, case_macro); \ | |
289 | PMEVN_CASE(18, case_macro); \ | |
290 | PMEVN_CASE(19, case_macro); \ | |
291 | PMEVN_CASE(20, case_macro); \ | |
292 | PMEVN_CASE(21, case_macro); \ | |
293 | PMEVN_CASE(22, case_macro); \ | |
294 | PMEVN_CASE(23, case_macro); \ | |
295 | PMEVN_CASE(24, case_macro); \ | |
296 | PMEVN_CASE(25, case_macro); \ | |
297 | PMEVN_CASE(26, case_macro); \ | |
298 | PMEVN_CASE(27, case_macro); \ | |
299 | PMEVN_CASE(28, case_macro); \ | |
300 | PMEVN_CASE(29, case_macro); \ | |
301 | PMEVN_CASE(30, case_macro); \ | |
302 | default: WARN(1, "Invalid PMEV* index\n"); \ | |
303 | } \ | |
304 | } while (0) | |
305 | ||
7755cec6 | 306 | #endif |