Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
0f4f0672 JI |
2 | /* |
3 | * linux/arch/arm/include/asm/pmu.h | |
4 | * | |
5 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles | |
0f4f0672 JI |
6 | */ |
7 | ||
8 | #ifndef __ARM_PMU_H__ | |
9 | #define __ARM_PMU_H__ | |
10 | ||
0e25a5c9 | 11 | #include <linux/interrupt.h> |
0ce47080 | 12 | #include <linux/perf_event.h> |
167e6143 | 13 | #include <linux/platform_device.h> |
86cdd72a | 14 | #include <linux/sysfs.h> |
548a86ca MR |
15 | #include <asm/cputype.h> |
16 | ||
fa8ad788 | 17 | #ifdef CONFIG_ARM_PMU |
0ce47080 | 18 | |
ac8674dc | 19 | /* |
d8226d8c RHA |
20 | * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters. |
21 | * The Armv8.9/9.4 CPU PMU supports up to 33 event counters. | |
ac8674dc | 22 | */ |
d8226d8c | 23 | #ifdef CONFIG_ARM |
ac8674dc | 24 | #define ARMPMU_MAX_HWEVENTS 32 |
d8226d8c RHA |
25 | #else |
26 | #define ARMPMU_MAX_HWEVENTS 33 | |
27 | #endif | |
e2da97d3 SP |
28 | /* |
29 | * ARM PMU hw_event flags | |
30 | */ | |
91207f62 AK |
31 | #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */ |
32 | #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */ | |
8be3593b | 33 | #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */ |
91207f62 AK |
34 | |
35 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT); | |
36 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT); | |
8be3593b | 37 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT); |
e2da97d3 | 38 | |
ac8674dc MR |
39 | #define HW_OP_UNSUPPORTED 0xFFFF |
40 | #define C(_x) PERF_COUNT_HW_CACHE_##_x | |
41 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
42 | ||
1113ff98 MR |
43 | #define PERF_MAP_ALL_UNSUPPORTED \ |
44 | [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED | |
45 | ||
46 | #define PERF_CACHE_MAP_ALL_UNSUPPORTED \ | |
47 | [0 ... C(MAX) - 1] = { \ | |
48 | [0 ... C(OP_MAX) - 1] = { \ | |
49 | [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ | |
50 | }, \ | |
51 | } | |
52 | ||
0ce47080 MR |
53 | /* The events for a given PMU register set. */ |
54 | struct pmu_hw_events { | |
55 | /* | |
56 | * The events that are active on the PMU for the given index. | |
57 | */ | |
a4560846 | 58 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; |
0ce47080 MR |
59 | |
60 | /* | |
61 | * A 1 bit for an index indicates that the counter is being used for | |
62 | * an event. A 0 means that the counter can be used. | |
63 | */ | |
a4560846 | 64 | DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); |
0ce47080 | 65 | |
5ebd9200 MR |
66 | /* |
67 | * When using percpu IRQs, we need a percpu dev_id. Place it here as we | |
68 | * already have to allocate this struct per cpu. | |
69 | */ | |
70 | struct arm_pmu *percpu_pmu; | |
7ed98e01 MR |
71 | |
72 | int irq; | |
0ce47080 MR |
73 | }; |
74 | ||
86cdd72a | 75 | enum armpmu_attr_groups { |
48538b58 | 76 | ARMPMU_ATTR_GROUP_COMMON, |
86cdd72a MR |
77 | ARMPMU_ATTR_GROUP_EVENTS, |
78 | ARMPMU_ATTR_GROUP_FORMATS, | |
f5be3a61 | 79 | ARMPMU_ATTR_GROUP_CAPS, |
86cdd72a MR |
80 | ARMPMU_NR_ATTR_GROUPS |
81 | }; | |
82 | ||
0ce47080 MR |
83 | struct arm_pmu { |
84 | struct pmu pmu; | |
cc88116d | 85 | cpumask_t supported_cpus; |
4295b898 | 86 | char *name; |
8673e02e | 87 | int pmuver; |
0788f1e9 | 88 | irqreturn_t (*handle_irq)(struct arm_pmu *pmu); |
ed6f2a52 SK |
89 | void (*enable)(struct perf_event *event); |
90 | void (*disable)(struct perf_event *event); | |
0ce47080 | 91 | int (*get_event_idx)(struct pmu_hw_events *hw_events, |
ed6f2a52 | 92 | struct perf_event *event); |
eab443ef SB |
93 | void (*clear_event_idx)(struct pmu_hw_events *hw_events, |
94 | struct perf_event *event); | |
0ce47080 MR |
95 | int (*set_event_filter)(struct hw_perf_event *evt, |
96 | struct perf_event_attr *attr); | |
3a95200d SP |
97 | u64 (*read_counter)(struct perf_event *event); |
98 | void (*write_counter)(struct perf_event *event, u64 val); | |
ed6f2a52 SK |
99 | void (*start)(struct arm_pmu *); |
100 | void (*stop)(struct arm_pmu *); | |
0ce47080 MR |
101 | void (*reset)(void *); |
102 | int (*map_event)(struct perf_event *event); | |
bf5ffc8c | 103 | DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS); |
8d1a0ae7 | 104 | bool secure_access; /* 32-bit ARM only */ |
342e53bd | 105 | #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 |
4b1a9e69 | 106 | DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); |
342e53bd WD |
107 | #define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000 |
108 | DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); | |
0ce47080 | 109 | struct platform_device *plat_device; |
11679250 | 110 | struct pmu_hw_events __percpu *hw_events; |
6e103c0c | 111 | struct hlist_node node; |
da4e4f18 | 112 | struct notifier_block cpu_pm_nb; |
86cdd72a MR |
113 | /* the attr_groups array must be NULL-terminated */ |
114 | const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1]; | |
f5be3a61 SZ |
115 | /* store the PMMIR_EL1 to expose slots */ |
116 | u64 reg_pmmir; | |
45736a72 MR |
117 | |
118 | /* Only to be used by ACPI probing code */ | |
119 | unsigned long acpi_cpuid; | |
0ce47080 MR |
120 | }; |
121 | ||
122 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) | |
123 | ||
ed6f2a52 | 124 | u64 armpmu_event_update(struct perf_event *event); |
0ce47080 | 125 | |
ed6f2a52 | 126 | int armpmu_event_set_period(struct perf_event *event); |
0ce47080 | 127 | |
6dbc0029 WD |
128 | int armpmu_map_event(struct perf_event *event, |
129 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
130 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] | |
131 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
132 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
133 | u32 raw_event_mask); | |
134 | ||
083c5214 MR |
135 | typedef int (*armpmu_init_fn)(struct arm_pmu *); |
136 | ||
548a86ca MR |
137 | struct pmu_probe_info { |
138 | unsigned int cpuid; | |
139 | unsigned int mask; | |
083c5214 | 140 | armpmu_init_fn init; |
548a86ca MR |
141 | }; |
142 | ||
143 | #define PMU_PROBE(_cpuid, _mask, _fn) \ | |
144 | { \ | |
145 | .cpuid = (_cpuid), \ | |
146 | .mask = (_mask), \ | |
147 | .init = (_fn), \ | |
148 | } | |
149 | ||
150 | #define ARM_PMU_PROBE(_cpuid, _fn) \ | |
151 | PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn) | |
152 | ||
153 | #define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK) | |
154 | ||
155 | #define XSCALE_PMU_PROBE(_version, _fn) \ | |
156 | PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn) | |
157 | ||
cfdad299 MR |
158 | int arm_pmu_device_probe(struct platform_device *pdev, |
159 | const struct of_device_id *of_table, | |
160 | const struct pmu_probe_info *probe_table); | |
161 | ||
45736a72 MR |
162 | #ifdef CONFIG_ACPI |
163 | int arm_pmu_acpi_probe(armpmu_init_fn init_fn); | |
164 | #else | |
165 | static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } | |
166 | #endif | |
167 | ||
e840f42a MZ |
168 | #ifdef CONFIG_KVM |
169 | void kvm_host_pmu_init(struct arm_pmu *pmu); | |
170 | #else | |
171 | #define kvm_host_pmu_init(x) do { } while(0) | |
172 | #endif | |
173 | ||
d7a0fe9e DA |
174 | bool arm_pmu_irq_is_nmi(void); |
175 | ||
18bfcfe5 MR |
176 | /* Internal functions only for core arm_pmu code */ |
177 | struct arm_pmu *armpmu_alloc(void); | |
178 | void armpmu_free(struct arm_pmu *pmu); | |
179 | int armpmu_register(struct arm_pmu *pmu); | |
167e6143 MR |
180 | int armpmu_request_irq(int irq, int cpu); |
181 | void armpmu_free_irq(int irq, int cpu); | |
18bfcfe5 | 182 | |
85023b2e JL |
183 | #define ARMV8_PMU_PDEV_NAME "armv8-pmu" |
184 | ||
fa8ad788 | 185 | #endif /* CONFIG_ARM_PMU */ |
0ce47080 | 186 | |
d24a0c70 | 187 | #define ARMV8_SPE_PDEV_NAME "arm,spe-v1" |
1aa3d027 | 188 | #define ARMV8_TRBE_PDEV_NAME "arm,trbe" |
d24a0c70 | 189 | |
f6da8696 JC |
190 | /* Why does everything I do descend into this? */ |
191 | #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ | |
192 | (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi | |
193 | ||
194 | #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ | |
195 | __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) | |
196 | ||
197 | #define GEN_PMU_FORMAT_ATTR(name) \ | |
198 | PMU_FORMAT_ATTR(name, \ | |
199 | _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \ | |
200 | ATTR_CFG_FLD_##name##_LO, \ | |
201 | ATTR_CFG_FLD_##name##_HI)) | |
202 | ||
203 | #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \ | |
204 | ((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0)) | |
205 | ||
206 | #define ATTR_CFG_GET_FLD(attr, name) \ | |
207 | _ATTR_CFG_GET_FLD(attr, \ | |
208 | ATTR_CFG_FLD_##name##_CFG, \ | |
209 | ATTR_CFG_FLD_##name##_LO, \ | |
210 | ATTR_CFG_FLD_##name##_HI) | |
211 | ||
0f4f0672 | 212 | #endif /* __ARM_PMU_H__ */ |