[linux-block.git] / include / linux / perf / arm_pmu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  linux/arch/arm/include/asm/pmu.h
 *
 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 */

#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__

#include <linux/interrupt.h>
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <linux/sysfs.h>
#include <asm/cputype.h>

#ifdef CONFIG_ARM_PMU

/*
 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
 */
#ifdef CONFIG_ARM
#define ARMPMU_MAX_HWEVENTS		32
#else
#define ARMPMU_MAX_HWEVENTS		33
#endif
/*
 * ARM PMU hw_event flags
 */
#define ARMPMU_EVT_64BIT		0x00001 /* Event uses a 64bit counter */
#define ARMPMU_EVT_47BIT		0x00002 /* Event uses a 47bit counter */
#define ARMPMU_EVT_63BIT		0x00004 /* Event uses a 63bit counter */

static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT);
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT);
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT);

#define HW_OP_UNSUPPORTED		0xFFFF
#define C(_x)				PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED		0xFFFF

#define PERF_MAP_ALL_UNSUPPORTED					\
	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED

#define PERF_CACHE_MAP_ALL_UNSUPPORTED					\
[0 ... C(MAX) - 1] = {							\
	[0 ... C(OP_MAX) - 1] = {					\
		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
	},								\
}

/* The events for a given PMU register set. */
struct pmu_hw_events {
	/*
	 * The events that are active on the PMU for the given index.
	 */
	struct perf_event	*events[ARMPMU_MAX_HWEVENTS];

	/*
	 * A 1 bit for an index indicates that the counter is being used for
	 * an event. A 0 means that the counter can be used.
	 */
	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);

	/*
	 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
	 * already have to allocate this struct per cpu.
	 */
	struct arm_pmu		*percpu_pmu;

	int irq;
};

enum armpmu_attr_groups {
	ARMPMU_ATTR_GROUP_COMMON,
	ARMPMU_ATTR_GROUP_EVENTS,
	ARMPMU_ATTR_GROUP_FORMATS,
	ARMPMU_ATTR_GROUP_CAPS,
	ARMPMU_NR_ATTR_GROUPS
};

struct arm_pmu {
	struct pmu	pmu;
	cpumask_t	supported_cpus;
	char		*name;
	irqreturn_t	(*handle_irq)(struct arm_pmu *pmu);
	void		(*enable)(struct perf_event *event);
	void		(*disable)(struct perf_event *event);
	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	int		(*set_event_filter)(struct hw_perf_event *evt,
					    struct perf_event_attr *attr);
	u64		(*read_counter)(struct perf_event *event);
	void		(*write_counter)(struct perf_event *event, u64 val);
	void		(*start)(struct arm_pmu *);
	void		(*stop)(struct arm_pmu *);
	void		(*reset)(void *);
	int		(*map_event)(struct perf_event *event);
	/*
	 * Called by KVM to map the PMUv3 event space onto non-PMUv3 hardware.
	 */
	int		(*map_pmuv3_event)(unsigned int eventsel);
	DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
	bool		secure_access; /* 32-bit ARM only */
	struct platform_device	*plat_device;
	struct pmu_hw_events	__percpu *hw_events;
	struct hlist_node	node;
	struct notifier_block	cpu_pm_nb;
	/* the attr_groups array must be NULL-terminated */
	const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];

	/* PMUv3 only */
	int		pmuver;
	u64		reg_pmmir;
#define ARMV8_PMUV3_MAX_COMMON_EVENTS		0x40
	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE	0x4000
	DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);

	/* Only to be used by ACPI probing code */
	unsigned long acpi_cpuid;
};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

u64 armpmu_event_update(struct perf_event *event);

int armpmu_event_set_period(struct perf_event *event);

int armpmu_map_event(struct perf_event *event,
		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
						[PERF_COUNT_HW_CACHE_OP_MAX]
						[PERF_COUNT_HW_CACHE_RESULT_MAX],
		     u32 raw_event_mask);

typedef int (*armpmu_init_fn)(struct arm_pmu *);

struct pmu_probe_info {
	unsigned int cpuid;
	unsigned int mask;
	armpmu_init_fn init;
};

#define PMU_PROBE(_cpuid, _mask, _fn)	\
{					\
	.cpuid = (_cpuid),		\
	.mask = (_mask),		\
	.init = (_fn),			\
}

#define ARM_PMU_PROBE(_cpuid, _fn) \
	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)

#define ARM_PMU_XSCALE_MASK	((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)

#define XSCALE_PMU_PROBE(_version, _fn) \
	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)

int arm_pmu_device_probe(struct platform_device *pdev,
			 const struct of_device_id *of_table,
			 const struct pmu_probe_info *probe_table);

#ifdef CONFIG_ACPI
int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
#else
static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
#endif

#ifdef CONFIG_KVM
void kvm_host_pmu_init(struct arm_pmu *pmu);
#else
#define kvm_host_pmu_init(x)	do { } while(0)
#endif

bool arm_pmu_irq_is_nmi(void);

/* Internal functions only for core arm_pmu code */
struct arm_pmu *armpmu_alloc(void);
void armpmu_free(struct arm_pmu *pmu);
int armpmu_register(struct arm_pmu *pmu);
int armpmu_request_irq(int irq, int cpu);
void armpmu_free_irq(int irq, int cpu);

#define ARMV8_PMU_PDEV_NAME "armv8-pmu"

#endif /* CONFIG_ARM_PMU */

#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
#define ARMV8_TRBE_PDEV_NAME "arm,trbe"

/* Why does everything I do descend into this? */
#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)				\
	(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi

#define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi)				\
	__GEN_PMU_FORMAT_ATTR(cfg, lo, hi)

#define GEN_PMU_FORMAT_ATTR(name)					\
	PMU_FORMAT_ATTR(name,						\
	_GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG,			\
			     ATTR_CFG_FLD_##name##_LO,			\
			     ATTR_CFG_FLD_##name##_HI))

#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)				\
	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

#define ATTR_CFG_GET_FLD(attr, name)					\
	_ATTR_CFG_GET_FLD(attr,						\
			  ATTR_CFG_FLD_##name##_CFG,			\
			  ATTR_CFG_FLD_##name##_LO,			\
			  ATTR_CFG_FLD_##name##_HI)

#endif /* __ARM_PMU_H__ */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
0f4f0672 JI	2	/*
	3	* linux/arch/arm/include/asm/pmu.h
	4	*
	5	* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
0f4f0672 JI	6	*/
	7
	8	#ifndef __ARM_PMU_H__
	9	#define __ARM_PMU_H__
	10
0e25a5c9	11	#include <linux/interrupt.h>
0ce47080	12	#include <linux/perf_event.h>
167e6143	13	#include <linux/platform_device.h>
86cdd72a	14	#include <linux/sysfs.h>
548a86ca MR	15	#include <asm/cputype.h>
548a86ca MR	16
fa8ad788	17	#ifdef CONFIG_ARM_PMU
0ce47080	18
ac8674dc	19	/*
d8226d8c RHA	20	* The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
d8226d8c RHA	21	* The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
ac8674dc	22	*/
d8226d8c	23	#ifdef CONFIG_ARM
ac8674dc	24	#define ARMPMU_MAX_HWEVENTS 32
d8226d8c RHA	25	#else
	26	#define ARMPMU_MAX_HWEVENTS 33
	27	#endif
e2da97d3 SP	28	/*
	29	* ARM PMU hw_event flags
	30	*/
91207f62 AK	31	#define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
91207f62 AK	32	#define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
8be3593b	33	#define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
91207f62 AK	34
	35	static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT);
	36	static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT);
8be3593b	37	static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT);
e2da97d3	38
ac8674dc MR	39	#define HW_OP_UNSUPPORTED 0xFFFF
	40	#define C(_x) PERF_COUNT_HW_CACHE_##_x
	41	#define CACHE_OP_UNSUPPORTED 0xFFFF
	42
1113ff98 MR	43	#define PERF_MAP_ALL_UNSUPPORTED \
	44	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
	45
	46	#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
	47	[0 ... C(MAX) - 1] = { \
	48	[0 ... C(OP_MAX) - 1] = { \
	49	[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
	50	}, \
	51	}
	52
0ce47080 MR	53	/* The events for a given PMU register set. */
	54	struct pmu_hw_events {
	55	/*
	56	* The events that are active on the PMU for the given index.
	57	*/
a4560846	58	struct perf_event *events[ARMPMU_MAX_HWEVENTS];
0ce47080 MR	59
	60	/*
	61	* A 1 bit for an index indicates that the counter is being used for
	62	* an event. A 0 means that the counter can be used.
	63	*/
a4560846	64	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
0ce47080	65
5ebd9200 MR	66	/*
	67	* When using percpu IRQs, we need a percpu dev_id. Place it here as we
	68	* already have to allocate this struct per cpu.
	69	*/
	70	struct arm_pmu *percpu_pmu;
7ed98e01 MR	71
7ed98e01 MR	72	int irq;
0ce47080 MR	73	};
0ce47080 MR	74
86cdd72a	75	enum armpmu_attr_groups {
48538b58	76	ARMPMU_ATTR_GROUP_COMMON,
86cdd72a MR	77	ARMPMU_ATTR_GROUP_EVENTS,
86cdd72a MR	78	ARMPMU_ATTR_GROUP_FORMATS,
f5be3a61	79	ARMPMU_ATTR_GROUP_CAPS,
86cdd72a MR	80	ARMPMU_NR_ATTR_GROUPS
	81	};
	82
0ce47080 MR	83	struct arm_pmu {
0ce47080 MR	84	struct pmu pmu;
cc88116d	85	cpumask_t supported_cpus;
4295b898	86	char *name;
0788f1e9	87	irqreturn_t (handle_irq)(struct arm_pmu pmu);
ed6f2a52 SK	88	void (enable)(struct perf_event event);
ed6f2a52 SK	89	void (disable)(struct perf_event event);
0ce47080	90	int (get_event_idx)(struct pmu_hw_events hw_events,
ed6f2a52	91	struct perf_event *event);
eab443ef SB	92	void (clear_event_idx)(struct pmu_hw_events hw_events,
eab443ef SB	93	struct perf_event *event);
0ce47080 MR	94	int (set_event_filter)(struct hw_perf_event evt,
0ce47080 MR	95	struct perf_event_attr *attr);
3a95200d SP	96	u64 (read_counter)(struct perf_event event);
3a95200d SP	97	void (write_counter)(struct perf_event event, u64 val);
ed6f2a52 SK	98	void (start)(struct arm_pmu );
ed6f2a52 SK	99	void (stop)(struct arm_pmu );
0ce47080 MR	100	void (reset)(void );
0ce47080 MR	101	int (map_event)(struct perf_event event);
1e7dcbfa OU	102	/*
	103	* Called by KVM to map the PMUv3 event space onto non-PMUv3 hardware.
	104	*/
	105	int (*map_pmuv3_event)(unsigned int eventsel);
bf5ffc8c	106	DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
8d1a0ae7	107	bool secure_access; /* 32-bit ARM only */
0ce47080	108	struct platform_device *plat_device;
11679250	109	struct pmu_hw_events __percpu *hw_events;
6e103c0c	110	struct hlist_node node;
da4e4f18	111	struct notifier_block cpu_pm_nb;
86cdd72a MR	112	/* the attr_groups array must be NULL-terminated */
86cdd72a MR	113	const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
dc4d58a7 MR	114
	115	/* PMUv3 only */
	116	int pmuver;
f5be3a61	117	u64 reg_pmmir;
dc4d58a7 MR	118	#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
	119	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
	120	#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000
	121	DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
45736a72 MR	122
	123	/* Only to be used by ACPI probing code */
	124	unsigned long acpi_cpuid;
0ce47080 MR	125	};
	126
	127	#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
	128
ed6f2a52	129	u64 armpmu_event_update(struct perf_event *event);
0ce47080	130
ed6f2a52	131	int armpmu_event_set_period(struct perf_event *event);
0ce47080	132
6dbc0029 WD	133	int armpmu_map_event(struct perf_event *event,
	134	const unsigned (*event_map)[PERF_COUNT_HW_MAX],
	135	const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
	136	[PERF_COUNT_HW_CACHE_OP_MAX]
	137	[PERF_COUNT_HW_CACHE_RESULT_MAX],
	138	u32 raw_event_mask);
	139
083c5214 MR	140	typedef int (armpmu_init_fn)(struct arm_pmu );
083c5214 MR	141
548a86ca MR	142	struct pmu_probe_info {
	143	unsigned int cpuid;
	144	unsigned int mask;
083c5214	145	armpmu_init_fn init;
548a86ca MR	146	};
	147
	148	#define PMU_PROBE(_cpuid, _mask, _fn) \
	149	{ \
	150	.cpuid = (_cpuid), \
	151	.mask = (_mask), \
	152	.init = (_fn), \
	153	}
	154
	155	#define ARM_PMU_PROBE(_cpuid, _fn) \
	156	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
	157
	158	#define ARM_PMU_XSCALE_MASK ((0xff << 24) \| ARM_CPU_XSCALE_ARCH_MASK)
	159
	160	#define XSCALE_PMU_PROBE(_version, _fn) \
	161	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 \| _version, ARM_PMU_XSCALE_MASK, _fn)
	162
cfdad299 MR	163	int arm_pmu_device_probe(struct platform_device *pdev,
	164	const struct of_device_id *of_table,
	165	const struct pmu_probe_info *probe_table);
	166
45736a72 MR	167	#ifdef CONFIG_ACPI
	168	int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
	169	#else
	170	static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
	171	#endif
	172
e840f42a MZ	173	#ifdef CONFIG_KVM
	174	void kvm_host_pmu_init(struct arm_pmu *pmu);
	175	#else
	176	#define kvm_host_pmu_init(x) do { } while(0)
	177	#endif
	178
d7a0fe9e DA	179	bool arm_pmu_irq_is_nmi(void);
d7a0fe9e DA	180
18bfcfe5 MR	181	/* Internal functions only for core arm_pmu code */
	182	struct arm_pmu *armpmu_alloc(void);
	183	void armpmu_free(struct arm_pmu *pmu);
	184	int armpmu_register(struct arm_pmu *pmu);
167e6143 MR	185	int armpmu_request_irq(int irq, int cpu);
167e6143 MR	186	void armpmu_free_irq(int irq, int cpu);
18bfcfe5	187
85023b2e JL	188	#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
85023b2e JL	189
fa8ad788	190	#endif /* CONFIG_ARM_PMU */
0ce47080	191
d24a0c70	192	#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
1aa3d027	193	#define ARMV8_TRBE_PDEV_NAME "arm,trbe"
d24a0c70	194
f6da8696 JC	195	/* Why does everything I do descend into this? */
	196	#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
	197	(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
	198
	199	#define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
	200	__GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
	201
	202	#define GEN_PMU_FORMAT_ATTR(name) \
	203	PMU_FORMAT_ATTR(name, \
	204	_GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \
	205	ATTR_CFG_FLD_##name##_LO, \
	206	ATTR_CFG_FLD_##name##_HI))
	207
	208	#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
	209	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))
	210
	211	#define ATTR_CFG_GET_FLD(attr, name) \
	212	_ATTR_CFG_GET_FLD(attr, \
	213	ATTR_CFG_FLD_##name##_CFG, \
	214	ATTR_CFG_FLD_##name##_LO, \
	215	ATTR_CFG_FLD_##name##_HI)
	216
0f4f0672	217	#endif /* __ARM_PMU_H__ */