Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
0f4f0672 JI |
2 | /* |
3 | * linux/arch/arm/include/asm/pmu.h | |
4 | * | |
5 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles | |
0f4f0672 JI |
6 | */ |
7 | ||
8 | #ifndef __ARM_PMU_H__ | |
9 | #define __ARM_PMU_H__ | |
10 | ||
0e25a5c9 | 11 | #include <linux/interrupt.h> |
0ce47080 | 12 | #include <linux/perf_event.h> |
167e6143 | 13 | #include <linux/platform_device.h> |
86cdd72a | 14 | #include <linux/sysfs.h> |
548a86ca MR |
15 | #include <asm/cputype.h> |
16 | ||
fa8ad788 | 17 | #ifdef CONFIG_ARM_PMU |
0ce47080 | 18 | |
ac8674dc MR |
19 | /* |
20 | * The ARMv7 CPU PMU supports up to 32 event counters. | |
21 | */ | |
22 | #define ARMPMU_MAX_HWEVENTS 32 | |
23 | ||
e2da97d3 SP |
24 | /* |
25 | * ARM PMU hw_event flags | |
26 | */ | |
91207f62 AK |
27 | #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */ |
28 | #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */ | |
8be3593b | 29 | #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */ |
91207f62 AK |
30 | |
31 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT); | |
32 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT); | |
8be3593b | 33 | static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT); |
e2da97d3 | 34 | |
ac8674dc MR |
35 | #define HW_OP_UNSUPPORTED 0xFFFF |
36 | #define C(_x) PERF_COUNT_HW_CACHE_##_x | |
37 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
38 | ||
1113ff98 MR |
39 | #define PERF_MAP_ALL_UNSUPPORTED \ |
40 | [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED | |
41 | ||
42 | #define PERF_CACHE_MAP_ALL_UNSUPPORTED \ | |
43 | [0 ... C(MAX) - 1] = { \ | |
44 | [0 ... C(OP_MAX) - 1] = { \ | |
45 | [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ | |
46 | }, \ | |
47 | } | |
48 | ||
0ce47080 MR |
49 | /* The events for a given PMU register set. */ |
50 | struct pmu_hw_events { | |
51 | /* | |
52 | * The events that are active on the PMU for the given index. | |
53 | */ | |
a4560846 | 54 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; |
0ce47080 MR |
55 | |
56 | /* | |
57 | * A 1 bit for an index indicates that the counter is being used for | |
58 | * an event. A 0 means that the counter can be used. | |
59 | */ | |
a4560846 | 60 | DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); |
0ce47080 MR |
61 | |
62 | /* | |
63 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
64 | * read/modify/write sequences. | |
65 | */ | |
66 | raw_spinlock_t pmu_lock; | |
5ebd9200 MR |
67 | |
68 | /* | |
69 | * When using percpu IRQs, we need a percpu dev_id. Place it here as we | |
70 | * already have to allocate this struct per cpu. | |
71 | */ | |
72 | struct arm_pmu *percpu_pmu; | |
7ed98e01 MR |
73 | |
74 | int irq; | |
0ce47080 MR |
75 | }; |
76 | ||
86cdd72a | 77 | enum armpmu_attr_groups { |
48538b58 | 78 | ARMPMU_ATTR_GROUP_COMMON, |
86cdd72a MR |
79 | ARMPMU_ATTR_GROUP_EVENTS, |
80 | ARMPMU_ATTR_GROUP_FORMATS, | |
f5be3a61 | 81 | ARMPMU_ATTR_GROUP_CAPS, |
86cdd72a MR |
82 | ARMPMU_NR_ATTR_GROUPS |
83 | }; | |
84 | ||
0ce47080 MR |
85 | struct arm_pmu { |
86 | struct pmu pmu; | |
cc88116d | 87 | cpumask_t supported_cpus; |
4295b898 | 88 | char *name; |
8673e02e | 89 | int pmuver; |
0788f1e9 | 90 | irqreturn_t (*handle_irq)(struct arm_pmu *pmu); |
ed6f2a52 SK |
91 | void (*enable)(struct perf_event *event); |
92 | void (*disable)(struct perf_event *event); | |
0ce47080 | 93 | int (*get_event_idx)(struct pmu_hw_events *hw_events, |
ed6f2a52 | 94 | struct perf_event *event); |
eab443ef SB |
95 | void (*clear_event_idx)(struct pmu_hw_events *hw_events, |
96 | struct perf_event *event); | |
0ce47080 MR |
97 | int (*set_event_filter)(struct hw_perf_event *evt, |
98 | struct perf_event_attr *attr); | |
3a95200d SP |
99 | u64 (*read_counter)(struct perf_event *event); |
100 | void (*write_counter)(struct perf_event *event, u64 val); | |
ed6f2a52 SK |
101 | void (*start)(struct arm_pmu *); |
102 | void (*stop)(struct arm_pmu *); | |
0ce47080 MR |
103 | void (*reset)(void *); |
104 | int (*map_event)(struct perf_event *event); | |
105 | int num_events; | |
8d1a0ae7 | 106 | bool secure_access; /* 32-bit ARM only */ |
342e53bd | 107 | #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 |
4b1a9e69 | 108 | DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); |
342e53bd WD |
109 | #define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000 |
110 | DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); | |
0ce47080 | 111 | struct platform_device *plat_device; |
11679250 | 112 | struct pmu_hw_events __percpu *hw_events; |
6e103c0c | 113 | struct hlist_node node; |
da4e4f18 | 114 | struct notifier_block cpu_pm_nb; |
86cdd72a MR |
115 | /* the attr_groups array must be NULL-terminated */ |
116 | const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1]; | |
f5be3a61 SZ |
117 | /* store the PMMIR_EL1 to expose slots */ |
118 | u64 reg_pmmir; | |
45736a72 MR |
119 | |
120 | /* Only to be used by ACPI probing code */ | |
121 | unsigned long acpi_cpuid; | |
0ce47080 MR |
122 | }; |
123 | ||
124 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) | |
125 | ||
ed6f2a52 | 126 | u64 armpmu_event_update(struct perf_event *event); |
0ce47080 | 127 | |
ed6f2a52 | 128 | int armpmu_event_set_period(struct perf_event *event); |
0ce47080 | 129 | |
6dbc0029 WD |
130 | int armpmu_map_event(struct perf_event *event, |
131 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
132 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] | |
133 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
134 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
135 | u32 raw_event_mask); | |
136 | ||
083c5214 MR |
137 | typedef int (*armpmu_init_fn)(struct arm_pmu *); |
138 | ||
548a86ca MR |
139 | struct pmu_probe_info { |
140 | unsigned int cpuid; | |
141 | unsigned int mask; | |
083c5214 | 142 | armpmu_init_fn init; |
548a86ca MR |
143 | }; |
144 | ||
145 | #define PMU_PROBE(_cpuid, _mask, _fn) \ | |
146 | { \ | |
147 | .cpuid = (_cpuid), \ | |
148 | .mask = (_mask), \ | |
149 | .init = (_fn), \ | |
150 | } | |
151 | ||
152 | #define ARM_PMU_PROBE(_cpuid, _fn) \ | |
153 | PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn) | |
154 | ||
155 | #define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK) | |
156 | ||
157 | #define XSCALE_PMU_PROBE(_version, _fn) \ | |
158 | PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn) | |
159 | ||
cfdad299 MR |
160 | int arm_pmu_device_probe(struct platform_device *pdev, |
161 | const struct of_device_id *of_table, | |
162 | const struct pmu_probe_info *probe_table); | |
163 | ||
45736a72 MR |
164 | #ifdef CONFIG_ACPI |
165 | int arm_pmu_acpi_probe(armpmu_init_fn init_fn); | |
166 | #else | |
167 | static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } | |
168 | #endif | |
169 | ||
e840f42a MZ |
170 | #ifdef CONFIG_KVM |
171 | void kvm_host_pmu_init(struct arm_pmu *pmu); | |
172 | #else | |
173 | #define kvm_host_pmu_init(x) do { } while(0) | |
174 | #endif | |
175 | ||
d7a0fe9e DA |
176 | bool arm_pmu_irq_is_nmi(void); |
177 | ||
18bfcfe5 MR |
178 | /* Internal functions only for core arm_pmu code */ |
179 | struct arm_pmu *armpmu_alloc(void); | |
180 | void armpmu_free(struct arm_pmu *pmu); | |
181 | int armpmu_register(struct arm_pmu *pmu); | |
167e6143 MR |
182 | int armpmu_request_irq(int irq, int cpu); |
183 | void armpmu_free_irq(int irq, int cpu); | |
18bfcfe5 | 184 | |
85023b2e JL |
185 | #define ARMV8_PMU_PDEV_NAME "armv8-pmu" |
186 | ||
fa8ad788 | 187 | #endif /* CONFIG_ARM_PMU */ |
0ce47080 | 188 | |
d24a0c70 | 189 | #define ARMV8_SPE_PDEV_NAME "arm,spe-v1" |
1aa3d027 | 190 | #define ARMV8_TRBE_PDEV_NAME "arm,trbe" |
d24a0c70 | 191 | |
0f4f0672 | 192 | #endif /* __ARM_PMU_H__ */ |