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736759ef | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
1da177e4 LT |
2 | /* |
3 | * PCI HotPlug Core Functions | |
4 | * | |
5 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
6 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
7 | * Copyright (C) 2001 IBM Corp. | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
fb5f4d7a | 11 | * Send feedback to <kristen.c.accardi@intel.com> |
1da177e4 LT |
12 | * |
13 | */ | |
14 | #ifndef _PCI_HOTPLUG_H | |
15 | #define _PCI_HOTPLUG_H | |
16 | ||
1da177e4 LT |
17 | /** |
18 | * struct hotplug_slot_ops -the callbacks that the hotplug pci core can use | |
1da177e4 LT |
19 | * @enable_slot: Called when the user wants to enable a specific pci slot |
20 | * @disable_slot: Called when the user wants to disable a specific pci slot | |
21 | * @set_attention_status: Called to set the specific slot's attention LED to | |
22 | * the specified value | |
23 | * @hardware_test: Called to run a specified hardware test on the specified | |
24 | * slot. | |
25 | * @get_power_status: Called to get the current power status of a slot. | |
1da177e4 | 26 | * @get_attention_status: Called to get the current attention status of a slot. |
1da177e4 | 27 | * @get_latch_status: Called to get the current latch status of a slot. |
1da177e4 | 28 | * @get_adapter_status: Called to get see if an adapter is present in the slot or not. |
5c32b35b AW |
29 | * @reset_slot: Optional interface to allow override of a bus reset for the |
30 | * slot for cases where a secondary bus reset can result in spurious | |
31 | * hotplug events or where a slot can be reset independent of the bus. | |
1da177e4 LT |
32 | * |
33 | * The table of function pointers that is passed to the hotplug pci core by a | |
34 | * hotplug pci driver. These functions are called by the hotplug pci core when | |
35 | * the user wants to do something to a specific slot (query it for information, | |
36 | * set an LED, enable / disable power, etc.) | |
37 | */ | |
38 | struct hotplug_slot_ops { | |
1da177e4 LT |
39 | int (*enable_slot) (struct hotplug_slot *slot); |
40 | int (*disable_slot) (struct hotplug_slot *slot); | |
41 | int (*set_attention_status) (struct hotplug_slot *slot, u8 value); | |
42 | int (*hardware_test) (struct hotplug_slot *slot, u32 value); | |
43 | int (*get_power_status) (struct hotplug_slot *slot, u8 *value); | |
44 | int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); | |
45 | int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); | |
46 | int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); | |
5c32b35b | 47 | int (*reset_slot) (struct hotplug_slot *slot, int probe); |
1da177e4 LT |
48 | }; |
49 | ||
1da177e4 LT |
50 | /** |
51 | * struct hotplug_slot - used to register a physical slot with the hotplug pci core | |
1da177e4 | 52 | * @ops: pointer to the &struct hotplug_slot_ops to be used for this slot |
81c4b5bf LW |
53 | * @owner: The module owner of this structure |
54 | * @mod_name: The module name (KBUILD_MODNAME) of this structure | |
1da177e4 LT |
55 | */ |
56 | struct hotplug_slot { | |
81c4b5bf | 57 | const struct hotplug_slot_ops *ops; |
1da177e4 LT |
58 | |
59 | /* Variables below this are for use only by the hotplug pci core. */ | |
60 | struct list_head slot_list; | |
f46753c5 | 61 | struct pci_slot *pci_slot; |
81c4b5bf LW |
62 | struct module *owner; |
63 | const char *mod_name; | |
1da177e4 | 64 | }; |
1da177e4 | 65 | |
0ad772ec AC |
66 | static inline const char *hotplug_slot_name(const struct hotplug_slot *slot) |
67 | { | |
68 | return pci_slot_name(slot->pci_slot); | |
69 | } | |
70 | ||
f39d5b72 BH |
71 | int __pci_hp_register(struct hotplug_slot *slot, struct pci_bus *pbus, int nr, |
72 | const char *name, struct module *owner, | |
73 | const char *mod_name); | |
51bbf9be LW |
74 | int __pci_hp_initialize(struct hotplug_slot *slot, struct pci_bus *bus, int nr, |
75 | const char *name, struct module *owner, | |
76 | const char *mod_name); | |
77 | int pci_hp_add(struct hotplug_slot *slot); | |
78 | ||
79 | void pci_hp_del(struct hotplug_slot *slot); | |
80 | void pci_hp_destroy(struct hotplug_slot *slot); | |
81 | void pci_hp_deregister(struct hotplug_slot *slot); | |
82 | ||
eb5589a8 PG |
83 | /* use a define to avoid include chaining to get THIS_MODULE & friends */ |
84 | #define pci_hp_register(slot, pbus, devnr, name) \ | |
85 | __pci_hp_register(slot, pbus, devnr, name, THIS_MODULE, KBUILD_MODNAME) | |
51bbf9be LW |
86 | #define pci_hp_initialize(slot, bus, nr, name) \ |
87 | __pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME) | |
c825bc94 | 88 | |
e22b7350 KK |
89 | /* PCI Setting Record (Type 0) */ |
90 | struct hpp_type0 { | |
91 | u32 revision; | |
92 | u8 cache_line_size; | |
93 | u8 latency_timer; | |
94 | u8 enable_serr; | |
95 | u8 enable_perr; | |
96 | }; | |
97 | ||
98 | /* PCI-X Setting Record (Type 1) */ | |
99 | struct hpp_type1 { | |
100 | u32 revision; | |
101 | u8 max_mem_read; | |
102 | u8 avg_max_split; | |
103 | u16 tot_max_split; | |
104 | }; | |
105 | ||
106 | /* PCI Express Setting Record (Type 2) */ | |
107 | struct hpp_type2 { | |
108 | u32 revision; | |
109 | u32 unc_err_mask_and; | |
110 | u32 unc_err_mask_or; | |
111 | u32 unc_err_sever_and; | |
112 | u32 unc_err_sever_or; | |
113 | u32 cor_err_mask_and; | |
114 | u32 cor_err_mask_or; | |
115 | u32 adv_err_cap_and; | |
116 | u32 adv_err_cap_or; | |
117 | u16 pci_exp_devctl_and; | |
118 | u16 pci_exp_devctl_or; | |
119 | u16 pci_exp_lnkctl_and; | |
120 | u16 pci_exp_lnkctl_or; | |
121 | u32 sec_unc_err_sever_and; | |
122 | u32 sec_unc_err_sever_or; | |
123 | u32 sec_unc_err_mask_and; | |
124 | u32 sec_unc_err_mask_or; | |
125 | }; | |
126 | ||
f873c51a AG |
127 | /* |
128 | * _HPX PCI Express Setting Record (Type 3) | |
129 | */ | |
130 | struct hpx_type3 { | |
131 | u16 device_type; | |
132 | u16 function_type; | |
133 | u16 config_space_location; | |
134 | u16 pci_exp_cap_id; | |
135 | u16 pci_exp_cap_ver; | |
136 | u16 pci_exp_vendor_id; | |
137 | u16 dvsec_id; | |
138 | u16 dvsec_rev; | |
139 | u16 match_offset; | |
140 | u32 match_mask_and; | |
141 | u32 match_value; | |
142 | u16 reg_offset; | |
143 | u32 reg_mask_and; | |
144 | u32 reg_mask_or; | |
145 | }; | |
146 | ||
87fcf12e AG |
147 | struct hotplug_program_ops { |
148 | void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp); | |
149 | void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp); | |
150 | void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp); | |
f873c51a AG |
151 | void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp); |
152 | }; | |
153 | ||
154 | enum hpx_type3_dev_type { | |
155 | HPX_TYPE_ENDPOINT = BIT(0), | |
156 | HPX_TYPE_LEG_END = BIT(1), | |
157 | HPX_TYPE_RC_END = BIT(2), | |
158 | HPX_TYPE_RC_EC = BIT(3), | |
159 | HPX_TYPE_ROOT_PORT = BIT(4), | |
160 | HPX_TYPE_UPSTREAM = BIT(5), | |
161 | HPX_TYPE_DOWNSTREAM = BIT(6), | |
162 | HPX_TYPE_PCI_BRIDGE = BIT(7), | |
163 | HPX_TYPE_PCIE_BRIDGE = BIT(8), | |
164 | }; | |
165 | ||
166 | enum hpx_type3_fn_type { | |
167 | HPX_FN_NORMAL = BIT(0), | |
168 | HPX_FN_SRIOV_PHYS = BIT(1), | |
169 | HPX_FN_SRIOV_VIRT = BIT(2), | |
170 | }; | |
171 | ||
172 | enum hpx_type3_cfg_loc { | |
173 | HPX_CFG_PCICFG = 0, | |
174 | HPX_CFG_PCIE_CAP = 1, | |
175 | HPX_CFG_PCIE_CAP_EXT = 2, | |
176 | HPX_CFG_VEND_CAP = 3, | |
177 | HPX_CFG_DVSEC = 4, | |
178 | HPX_CFG_MAX, | |
783c49fc KA |
179 | }; |
180 | ||
181 | #ifdef CONFIG_ACPI | |
8b48463f | 182 | #include <linux/acpi.h> |
87fcf12e AG |
183 | int pci_acpi_program_hp_params(struct pci_dev *dev, |
184 | const struct hotplug_program_ops *hp_ops); | |
5352a44a | 185 | bool pciehp_is_native(struct pci_dev *bridge); |
6f77fa49 | 186 | int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge); |
90cc0c3c | 187 | bool shpchp_is_native(struct pci_dev *bridge); |
e8c331e9 | 188 | int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle); |
7f538669 | 189 | int acpi_pci_detect_ejectable(acpi_handle handle); |
8838400d | 190 | #else |
87fcf12e AG |
191 | static inline int pci_acpi_program_hp_params(struct pci_dev *dev, |
192 | const struct hotplug_program_ops *hp_ops) | |
8838400d BH |
193 | { |
194 | return -ENODEV; | |
195 | } | |
96a621e0 MW |
196 | |
197 | static inline int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge) | |
198 | { | |
199 | return 0; | |
200 | } | |
5352a44a | 201 | static inline bool pciehp_is_native(struct pci_dev *bridge) { return true; } |
90cc0c3c | 202 | static inline bool shpchp_is_native(struct pci_dev *bridge) { return true; } |
783c49fc | 203 | #endif |
95d969eb MW |
204 | |
205 | static inline bool hotplug_is_native(struct pci_dev *bridge) | |
206 | { | |
207 | return pciehp_is_native(bridge) || shpchp_is_native(bridge); | |
208 | } | |
1da177e4 | 209 | #endif |