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PCI: Deprecate pci_reset_bus() and pci_reset_slot() functions
[linux-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
1da177e4
LT		 17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
1da177e4 20
778382e0
DW		 21#include <linux/mod_devicetable.h>
22
1da177e4 23#include <linux/types.h>
98db6f19 24#include <linux/init.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/list.h>
4a7fb636 27#include <linux/compiler.h>
1da177e4 28#include <linux/errno.h>
f46753c5 29#include <linux/kobject.h>
60063497 30#include <linux/atomic.h>
1da177e4 31#include <linux/device.h>
704e8953 32#include <linux/interrupt.h>
1388cc96 33#include <linux/io.h>
14d76b68 34#include <linux/resource_ext.h>
607ca46e 35#include <uapi/linux/pci.h>
1da177e4 36
7e7a43c3
AB		 37#include <linux/pci_ids.h>
38
85467136
SK		 39/*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
f7625980
BH		 46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 48 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 49 * the following kernel-only defines are being added here.
85467136 50 */
0aa0f5d1 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
f46753c5
AC		 55/* pci_slot represents a physical slot */
56struct pci_slot {
0aa0f5d1
BH		 57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
f46753c5
AC		 62};
63
0ad772ec
AC		 64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
1da177e4
LT		 69/* File state for mmap()s on /proc/bus/pci/X/Y */
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
0aa0f5d1 75/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 76enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
0aa0f5d1 84 /* Device-specific resources */
d1b054da
YZ		 85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
0aa0f5d1 90 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
0aa0f5d1 97 /* Total resources associated with a PCI device */
fde09c6d
YZ		 98 PCI_NUM_RESOURCES,
99
0aa0f5d1 100 /* Preserve this for compatibility */
cda57bf9 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 102};
1da177e4 103
b352baf1
PB		 104/**
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
111 *
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
114 */
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123/* The number of legacy PCI INTx interrupts */
124#define PCI_NUM_INTX 4
125
224abb67
BH		 126/*
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
129 */
1da177e4
LT		 130typedef int __bitwise pci_power_t;
131
4352dfd5
GKH		 132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 137#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 139
00240c38
AS		 140/* Remember to update this when the list above changes! */
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
9661e783 145 return pci_power_names[1 + (__force int) state];
00240c38
AS		 146}
147
448bd857
HY		 148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
aa8c6c93 152
0aa0f5d1
BH		 153/**
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
392a1ce7 157 */
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
f7bdd12d
BK		 171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
f7625980 177 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
f7625980 180 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
ba698ad4
DM		 184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
0aa0f5d1 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 188 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 190 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 202 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 206 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 208};
209
e1d3a908
SA		 210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
6e325a62
MT		 215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
032c3d86
JD		 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 221};
222
0aa0f5d1 223/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
0aa0f5d1 230 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
0aa0f5d1 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 234};
235
536c8cb4
MW		 236/* Based on the PCI Hotplug Spec, but some values are made up by us */
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
536c8cb4
MW		 254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 259 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 260 PCIE_SPEED_16_0GT = 0x17,
536c8cb4
MW		 261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
24a4742f 264struct pci_cap_saved_data {
0aa0f5d1
BH		 265 u16 cap_nr;
266 bool cap_extended;
267 unsigned int size;
268 u32 data[0];
41017f0c
SL		 269};
270
24a4742f 271struct pci_cap_saved_state {
0aa0f5d1
BH		 272 struct hlist_node next;
273 struct pci_cap_saved_data cap;
24a4742f
AW		 274};
275
402723ad 276struct irq_affinity;
7d715a6c 277struct pcie_link_state;
ee69439c 278struct pci_vpd;
d1b054da 279struct pci_sriov;
302b4215 280struct pci_ats;
ee69439c 281
0aa0f5d1 282/* The pci_dev structure describes PCI devices */
1da177e4 283struct pci_dev {
0aa0f5d1
BH		 284 struct list_head bus_list; /* Node in per-bus list */
285 struct pci_bus *bus; /* Bus this device is on */
286 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 287
0aa0f5d1
BH		 288 void *sysdata; /* Hook for sys-specific extension */
289 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 290 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 291
0aa0f5d1 292 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 293 unsigned short vendor;
294 unsigned short device;
295 unsigned short subsystem_vendor;
296 unsigned short subsystem_device;
297 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 298 u8 revision; /* PCI revision, low byte of class word */
1da177e4 299 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 300#ifdef CONFIG_PCIEAER
301 u16 aer_cap; /* AER capability offset */
302#endif
f7625980 303 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 304 u8 msi_cap; /* MSI capability offset */
305 u8 msix_cap; /* MSI-X capability offset */
f7625980 306 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 307 u8 rom_base_reg; /* Config register controlling ROM */
308 u8 pin; /* Interrupt pin this device uses */
309 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
310 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 311
0aa0f5d1 312 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 313 u64 dma_mask; /* Mask of the bits of bus address this
314 device implements. Normally this is
315 0xffffffff. You only need to change
316 this if your device has broken DMA
317 or supports 64-bit transfers. */
318
4d57cdfa
FT		 319 struct device_dma_parameters dma_parms;
320
0aa0f5d1
BH		 321 pci_power_t current_state; /* Current operating state. In ACPI,
322 this is D0-D3, D0 being fully
323 functional, and D3 being off. */
703860ed 324 u8 pm_cap; /* PM capability offset */
337001b6
RW		 325 unsigned int pme_support:5; /* Bitmask of states from which PME#
326 can be generated */
379021d5 327 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 328 unsigned int d1_support:1; /* Low power state D1 is supported */
329 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 330 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
331 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 332 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 333 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 334 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
335 decoding during BAR sizing */
e80bb09d 336 unsigned int wakeup_prepared:1;
0aa0f5d1 337 unsigned int runtime_d3cold:1; /* Whether go through runtime
448bd857
HY		 338 D3cold, not set for devices
339 powered on/off by the
340 corresponding bridge */
b440bde7 341 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 342 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
343 controlled exclusively by
344 user sysfs */
1ae861e6 345 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 346 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 347
7d715a6c 348#ifdef CONFIG_PCIEASPM
f7625980 349 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 350 unsigned int ltr_path:1; /* Latency Tolerance Reporting
351 supported from root to here */
7d715a6c 352#endif
7ce3f912 353 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 354
0aa0f5d1
BH		 355 pci_channel_state_t error_state; /* Current connectivity state */
356 struct device dev; /* Generic device interface */
1da177e4 357
0aa0f5d1 358 int cfg_size; /* Size of config space */
1da177e4
LT		 359
360 /*
361 * Instead of touching interrupt line and base address registers
362 * directly, use the values stored here. They might be different!
363 */
364 unsigned int irq;
365 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
366
0aa0f5d1
BH		 367 bool match_driver; /* Skip attaching driver */
368
369 unsigned int transparent:1; /* Subtractive decode bridge */
370 unsigned int multifunction:1; /* Multi-function device */
371
8a1bc901 372 unsigned int is_added:1;
0aa0f5d1
BH		 373 unsigned int is_busmaster:1; /* Is busmaster */
374 unsigned int no_msi:1; /* May not use MSI */
375 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
376 unsigned int block_cfg_access:1; /* Config space access blocked */
377 unsigned int broken_parity_status:1; /* Generates false positive parity */
378 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 379 unsigned int msi_enabled:1;
99dc804d 380 unsigned int msix_enabled:1;
0aa0f5d1
BH		 381 unsigned int ari_enabled:1; /* ARI forwarding */
382 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 383 unsigned int pasid_enabled:1; /* Process Address Space ID */
384 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 385 unsigned int is_managed:1;
0aa0f5d1 386 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 387 unsigned int state_saved:1;
d1b054da 388 unsigned int is_physfn:1;
dd7cc44d 389 unsigned int is_virtfn:1;
711d5779 390 unsigned int reset_fn:1;
0aa0f5d1
BH		 391 unsigned int is_hotplug_bridge:1;
392 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
393 unsigned int __aer_firmware_first_valid:1;
affb72c3 394 unsigned int __aer_firmware_first:1;
0aa0f5d1
BH		 395 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
396 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 397 unsigned int irq_managed:1;
d0751b98 398 unsigned int has_secondary_link:1;
0aa0f5d1
BH		 399 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
400 unsigned int is_probed:1; /* Device probing in progress */
ba698ad4 401 pci_dev_flags_t dev_flags;
bae94d02 402 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 403
0aa0f5d1 404 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 405 struct hlist_head saved_cap_space;
0aa0f5d1
BH		 406 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
407 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 408 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 409 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 410
d22b3621
BH		 411#ifdef CONFIG_HOTPLUG_PCI_PCIE
412 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
413#endif
9bb04a0c
JY		 414#ifdef CONFIG_PCIE_PTM
415 unsigned int ptm_root:1;
416 unsigned int ptm_enabled:1;
8b2ec318 417 u8 ptm_granularity;
9bb04a0c 418#endif
ded86d8d 419#ifdef CONFIG_PCI_MSI
1c51b50c 420 const struct attribute_group **msi_irq_groups;
ded86d8d 421#endif
94e61088 422 struct pci_vpd *vpd;
466b3ddf 423#ifdef CONFIG_PCI_ATS
dd7cc44d 424 union {
0aa0f5d1
BH		 425 struct pci_sriov *sriov; /* PF: SR-IOV info */
426 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 427 };
67930995
BH		 428 u16 ats_cap; /* ATS Capability offset */
429 u8 ats_stu; /* ATS Smallest Translation Unit */
0aa0f5d1 430 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
4ebeb1ec
CT		 431#endif
432#ifdef CONFIG_PCI_PRI
433 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
434#endif
435#ifdef CONFIG_PCI_PASID
436 u16 pasid_features;
d1b054da 437#endif
0aa0f5d1
BH		 438 phys_addr_t rom; /* Physical address if not from BAR */
439 size_t romlen; /* Length if not from BAR */
440 char *driver_override; /* Driver name to force a match */
89ee9f76 441
0aa0f5d1 442 unsigned long priv_flags; /* Private flags for the PCI driver */
1da177e4
LT		 443};
444
dda56549
Y		 445static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
446{
447#ifdef CONFIG_PCI_IOV
448 if (dev->is_virtfn)
449 dev = dev->physfn;
450#endif
dda56549
Y		 451 return dev;
452}
453
3c6e6ae7 454struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 455
1da177e4
LT		 456#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
457#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
458
a7369f1f
LV		 459static inline int pci_channel_offline(struct pci_dev *pdev)
460{
461 return (pdev->error_state != pci_channel_io_normal);
462}
463
5a21d70d 464struct pci_host_bridge {
0aa0f5d1
BH		 465 struct device dev;
466 struct pci_bus *bus; /* Root bus */
467 struct pci_ops *ops;
468 void *sysdata;
469 int busnr;
14d76b68 470 struct list_head windows; /* resource_entry */
0aa0f5d1 471 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 472 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 473 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 474 void *release_data;
37d6a0a6 475 struct msi_controller *msi;
0aa0f5d1
BH		 476 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
477 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48 478 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 479 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 480 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 481 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 482 unsigned int native_ltr:1; /* OS may use PCIe LTR */
7c7a0e94
GP		 483 /* Resource alignment requirements */
484 resource_size_t (*align_resource)(struct pci_dev *dev,
485 const struct resource *res,
486 resource_size_t start,
487 resource_size_t size,
488 resource_size_t align);
0aa0f5d1 489 unsigned long private[0] ____cacheline_aligned;
5a21d70d 490};
41017f0c 491
7b543663 492#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 493
59094065
TR		 494static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
495{
496 return (void *)bridge->private;
497}
498
499static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
500{
501 return container_of(priv, struct pci_host_bridge, private);
502}
503
a52d1443 504struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 505struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
506 size_t priv);
dff79b91 507void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 508struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
509
4fa2649a 510void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 511 void (*release_fn)(struct pci_host_bridge *),
512 void *release_data);
7b543663 513
6c0cc950
RW		 514int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
515
2fe2abf8
BH		 516/*
517 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
518 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
519 * buses below host bridges or subtractive decode bridges) go in the list.
520 * Use pci_bus_for_each_resource() to iterate through all the resources.
521 */
522
523/*
524 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
525 * and there's no way to program the bridge with the details of the window.
526 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
527 * decode bit set, because they are explicit and can be programmed with _SRS.
528 */
529#define PCI_SUBTRACTIVE_DECODE 0x1
530
531struct pci_bus_resource {
0aa0f5d1
BH		 532 struct list_head list;
533 struct resource *res;
534 unsigned int flags;
2fe2abf8 535};
4352dfd5
GKH		 536
537#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 538
539struct pci_bus {
0aa0f5d1
BH		 540 struct list_head node; /* Node in list of buses */
541 struct pci_bus *parent; /* Parent bus this bridge is on */
542 struct list_head children; /* List of child buses */
543 struct list_head devices; /* List of devices on this bus */
544 struct pci_dev *self; /* Bridge device as seen by parent */
545 struct list_head slots; /* List of slots on this bus;
67546762 546 protected by pci_slot_mutex */
2fe2abf8 547 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 548 struct list_head resources; /* Address space routed to this bus */
549 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 550
0aa0f5d1 551 struct pci_ops *ops; /* Configuration access functions */
c2791b80 552 struct msi_controller *msi; /* MSI controller */
0aa0f5d1
BH		 553 void *sysdata; /* Hook for sys-specific extension */
554 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 555
0aa0f5d1
BH		 556 unsigned char number; /* Bus number */
557 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 558 unsigned char max_bus_speed; /* enum pci_bus_speed */
559 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 560#ifdef CONFIG_PCI_DOMAINS_GENERIC
561 int domain_nr;
562#endif
1da177e4
LT		 563
564 char name[48];
565
0aa0f5d1
BH		 566 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
567 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 568 struct device *bridge;
fd7d1ced 569 struct device dev;
0aa0f5d1
BH		 570 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
571 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 572 unsigned int is_added:1;
1da177e4
LT		 573};
574
fd7d1ced 575#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 576
79af72d7 577/*
f7625980 578 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 579 * false otherwise
77a0dfcd
BH		 580 *
581 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
582 * This is incorrect because "virtual" buses added for SR-IOV (via
583 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 584 */
585static inline bool pci_is_root_bus(struct pci_bus *pbus)
586{
587 return !(pbus->parent);
588}
589
1c86438c
YW		 590/**
591 * pci_is_bridge - check if the PCI device is a bridge
592 * @dev: PCI device
593 *
594 * Return true if the PCI device is bridge whether it has subordinate
595 * or not.
596 */
597static inline bool pci_is_bridge(struct pci_dev *dev)
598{
599 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
600 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
601}
602
24a0c654
AS		 603#define for_each_pci_bridge(dev, bus) \
604 list_for_each_entry(dev, &bus->devices, bus_list) \
605 if (!pci_is_bridge(dev)) {} else
606
c6bde215
BH		 607static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
608{
609 dev = pci_physfn(dev);
610 if (pci_is_root_bus(dev->bus))
611 return NULL;
612
613 return dev->bus->self;
614}
615
6675a601
MK		 616struct device *pci_get_host_bridge_device(struct pci_dev *dev);
617void pci_put_host_bridge_device(struct device *dev);
618
16cf0ebc
RW		 619#ifdef CONFIG_PCI_MSI
620static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
621{
622 return pci_dev->msi_enabled || pci_dev->msix_enabled;
623}
624#else
625static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
626#endif
627
0aa0f5d1 628/* Error values that may be returned by PCI functions */
1da177e4
LT		 629#define PCIBIOS_SUCCESSFUL 0x00
630#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
631#define PCIBIOS_BAD_VENDOR_ID 0x83
632#define PCIBIOS_DEVICE_NOT_FOUND 0x86
633#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
634#define PCIBIOS_SET_FAILED 0x88
635#define PCIBIOS_BUFFER_TOO_SMALL 0x89
636
0aa0f5d1 637/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 638static inline int pcibios_err_to_errno(int err)
639{
640 if (err <= PCIBIOS_SUCCESSFUL)
641 return err; /* Assume already errno */
642
643 switch (err) {
644 case PCIBIOS_FUNC_NOT_SUPPORTED:
645 return -ENOENT;
646 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 647 return -ENOTTY;
a6961651
AW		 648 case PCIBIOS_DEVICE_NOT_FOUND:
649 return -ENODEV;
650 case PCIBIOS_BAD_REGISTER_NUMBER:
651 return -EFAULT;
652 case PCIBIOS_SET_FAILED:
653 return -EIO;
654 case PCIBIOS_BUFFER_TOO_SMALL:
655 return -ENOSPC;
656 }
657
d97ffe23 658 return -ERANGE;
a6961651
AW		 659}
660
1da177e4
LT		 661/* Low-level architecture-dependent routines */
662
663struct pci_ops {
057bd2e0
TR		 664 int (*add_bus)(struct pci_bus *bus);
665 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 666 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 667 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
668 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
669};
670
b6ce068a
MW		 671/*
672 * ACPI needs to be able to access PCI config space before we've done a
673 * PCI bus scan and created pci_bus structures.
674 */
f39d5b72
BH		 675int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
676 int reg, int len, u32 *val);
677int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
678 int reg, int len, u32 val);
1da177e4 679
8e639079 680#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 681typedef u64 pci_bus_addr_t;
682#else
683typedef u32 pci_bus_addr_t;
684#endif
685
1da177e4 686struct pci_bus_region {
0aa0f5d1
BH		 687 pci_bus_addr_t start;
688 pci_bus_addr_t end;
1da177e4
LT		 689};
690
691struct pci_dynids {
0aa0f5d1
BH		 692 spinlock_t lock; /* Protects list, index */
693 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 694};
695
f7625980
BH		 696
697/*
698 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
699 * a set of callbacks in struct pci_error_handlers, that device driver
700 * will be notified of PCI bus errors, and will be driven to recovery
701 * when an error occurs.
392a1ce7 702 */
703
704typedef unsigned int __bitwise pci_ers_result_t;
705
706enum pci_ers_result {
0aa0f5d1 707 /* No result/none/not supported in device driver */
392a1ce7 708 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
709
710 /* Device driver can recover without slot reset */
711 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
712
0aa0f5d1 713 /* Device driver wants slot to be reset */
392a1ce7 714 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
715
716 /* Device has completely failed, is unrecoverable */
717 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
718
719 /* Device driver is fully recovered and operational */
720 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 721
722 /* No AER capabilities registered for the driver */
723 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 724};
725
726/* PCI bus error event callbacks */
05cca6e5 727struct pci_error_handlers {
392a1ce7 728 /* PCI bus error detected on this device */
729 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 730 enum pci_channel_state error);
392a1ce7 731
732 /* MMIO has been re-enabled, but not DMA */
733 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
734
392a1ce7 735 /* PCI slot has been reset */
736 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
737
3ebe7f9f 738 /* PCI function reset prepare or completed */
775755ed
CH		 739 void (*reset_prepare)(struct pci_dev *dev);
740 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 741
392a1ce7 742 /* Device driver may resume normal operations */
743 void (*resume)(struct pci_dev *dev);
744};
745
392a1ce7 746
1da177e4
LT		 747struct module;
748struct pci_driver {
0aa0f5d1
BH		 749 struct list_head node;
750 const char *name;
751 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
752 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
753 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
754 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
755 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
756 int (*resume_early)(struct pci_dev *dev);
757 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 758 void (*shutdown) (struct pci_dev *dev);
0aa0f5d1 759 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
49453028 760 const struct pci_error_handlers *err_handler;
92d50fc1 761 const struct attribute_group **groups;
1da177e4 762 struct device_driver driver;
0aa0f5d1 763 struct pci_dynids dynids;
1da177e4
LT		 764};
765
05cca6e5 766#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 767
768/**
0aa0f5d1 769 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 770 * @vend: the 16 bit PCI Vendor ID
771 * @dev: the 16 bit PCI Device ID
772 *
773 * This macro is used to create a struct pci_device_id that matches a
774 * specific device. The subvendor and subdevice fields will be set to
775 * PCI_ANY_ID.
776 */
777#define PCI_DEVICE(vend,dev) \
778 .vendor = (vend), .device = (dev), \
779 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
780
3d567e0e 781/**
0aa0f5d1 782 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 783 * @vend: the 16 bit PCI Vendor ID
784 * @dev: the 16 bit PCI Device ID
785 * @subvend: the 16 bit PCI Subvendor ID
786 * @subdev: the 16 bit PCI Subdevice ID
787 *
788 * This macro is used to create a struct pci_device_id that matches a
789 * specific device with subsystem information.
790 */
791#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
792 .vendor = (vend), .device = (dev), \
793 .subvendor = (subvend), .subdevice = (subdev)
794
1da177e4 795/**
0aa0f5d1 796 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 797 * @dev_class: the class, subclass, prog-if triple for this device
798 * @dev_class_mask: the class mask for this device
799 *
800 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 801 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 802 * fields will be set to PCI_ANY_ID.
803 */
804#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
805 .class = (dev_class), .class_mask = (dev_class_mask), \
806 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
807 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
808
1597cacb 809/**
0aa0f5d1 810 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 811 * @vend: the vendor name
812 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 813 *
814 * This macro is used to create a struct pci_device_id that matches a
815 * specific PCI device. The subvendor, and subdevice fields will be set
816 * to PCI_ANY_ID. The macro allows the next field to follow as the device
817 * private data.
818 */
c1309040
MR		 819#define PCI_VDEVICE(vend, dev) \
820 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
821 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 822
5bbe029f 823enum {
0aa0f5d1
BH		 824 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
825 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
826 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
827 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
828 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 829 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 830 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 831};
832
0aa0f5d1 833/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 834#ifdef CONFIG_PCI
835
5bbe029f
BH		 836extern unsigned int pci_flags;
837
838static inline void pci_set_flags(int flags) { pci_flags = flags; }
839static inline void pci_add_flags(int flags) { pci_flags |= flags; }
840static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
841static inline int pci_has_flag(int flag) { return pci_flags & flag; }
842
a58674ff 843void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 844
845enum pcie_bus_config_types {
0aa0f5d1
BH		 846 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
847 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
848 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
849 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
850 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 851};
852
853extern enum pcie_bus_config_types pcie_bus_config;
854
1da177e4
LT		 855extern struct bus_type pci_bus_type;
856
f7625980
BH		 857/* Do NOT directly access these two variables, unless you are arch-specific PCI
858 * code, or PCI core code. */
0aa0f5d1 859extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 860/* Some device drivers need know if PCI is initiated */
f39d5b72 861int no_pci_devices(void);
1da177e4 862
3c449ed0 863void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 864void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 865void pcibios_add_bus(struct pci_bus *bus);
866void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 867void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 868int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 869/* Architecture-specific versions may override this (weak) */
05cca6e5 870char *pcibios_setup(char *str);
1da177e4
LT		 871
872/* Used only when drivers/pci/setup.c is used */
3b7a17fc 873resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 874 resource_size_t,
e31dd6e4 875 resource_size_t);
1da177e4 876
2d1c8618
BH		 877/* Weak but can be overriden by arch */
878void pci_fixup_cardbus(struct pci_bus *);
879
1da177e4
LT		 880/* Generic PCI functions used internally */
881
fc279850 882void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 883 struct resource *res);
fc279850 884void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 885 struct pci_bus_region *region);
d1fd4fb6 886void pcibios_scan_specific_bus(int busn);
f39d5b72 887struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 888void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 889struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 890struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
891 struct pci_ops *ops, void *sysdata,
892 struct list_head *resources);
49b8e3f3 893int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 894int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
895int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
896void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 897struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 898 struct pci_ops *ops, void *sysdata,
899 struct list_head *resources);
1228c4b6 900int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 901struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
902 int busnr);
3749c51a 903void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 904struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 905 const char *name,
906 struct hotplug_slot *hotplug);
f46753c5 907void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 908#ifdef CONFIG_SYSFS
909void pci_dev_assign_slot(struct pci_dev *dev);
910#else
911static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
912#endif
1da177e4 913int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 914struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 915void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 916unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 917void pci_bus_add_device(struct pci_dev *dev);
1da177e4 918void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 919struct resource *pci_find_parent_resource(const struct pci_dev *dev,
920 struct resource *res);
c56d4450 921struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 922u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 923int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 924u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 925struct pci_dev *pci_dev_get(struct pci_dev *dev);
926void pci_dev_put(struct pci_dev *dev);
927void pci_remove_bus(struct pci_bus *b);
928void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 929void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 930void pci_stop_root_bus(struct pci_bus *bus);
931void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 932void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 933void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 934void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 935#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
936#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 937
938/* Generic PCI functions exported to card drivers */
939
388c8c16
JB		 940enum pci_lost_interrupt_reason {
941 PCI_LOST_IRQ_NO_INFORMATION = 0,
942 PCI_LOST_IRQ_DISABLE_MSI,
943 PCI_LOST_IRQ_DISABLE_MSIX,
944 PCI_LOST_IRQ_DISABLE_ACPI,
945};
946enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 947int pci_find_capability(struct pci_dev *dev, int cap);
948int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
949int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 950int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 951int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
952int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 953struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 954
d42552c3 955struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 956 struct pci_dev *from);
05cca6e5 957struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 958 unsigned int ss_vendor, unsigned int ss_device,
959 struct pci_dev *from);
05cca6e5 960struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 961struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
962 unsigned int devfn);
05cca6e5 963struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 964int pci_dev_present(const struct pci_device_id *ids);
965
05cca6e5
GKH		 966int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
967 int where, u8 *val);
968int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
969 int where, u16 *val);
970int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
971 int where, u32 *val);
972int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
973 int where, u8 val);
974int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
975 int where, u16 val);
976int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
977 int where, u32 val);
1f94a94f
RH		 978
979int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
980 int where, int size, u32 *val);
981int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
982 int where, int size, u32 val);
983int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
984 int where, int size, u32 *val);
985int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
986 int where, int size, u32 val);
987
a72b46c3 988struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 989
d3881e50
KB		 990int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
991int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
992int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
993int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
994int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
995int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 996
8c0d3a02
JL		 997int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
998int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
999int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1000int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1001int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1002 u16 clear, u16 set);
1003int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1004 u32 clear, u32 set);
1005
1006static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1007 u16 set)
1008{
1009 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1010}
1011
1012static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1013 u32 set)
1014{
1015 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1016}
1017
1018static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1019 u16 clear)
1020{
1021 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1022}
1023
1024static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1025 u32 clear)
1026{
1027 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1028}
1029
0aa0f5d1 1030/* User-space driven config access */
c63587d7
AW		 1031int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1032int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1033int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1034int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1035int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1036int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1037
4a7fb636 1038int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1039int __must_check pci_enable_device_io(struct pci_dev *dev);
1040int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1041int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1042int __must_check pcim_enable_device(struct pci_dev *pdev);
1043void pcim_pin_device(struct pci_dev *pdev);
1044
99b3c58f
PG		 1045static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1046{
1047 /*
1048 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1049 * writable and no quirk has marked the feature broken.
1050 */
1051 return !pdev->broken_intx_masking;
1052}
1053
296ccb08
YS		 1054static inline int pci_is_enabled(struct pci_dev *pdev)
1055{
1056 return (atomic_read(&pdev->enable_cnt) > 0);
1057}
1058
9ac7849e
TH		 1059static inline int pci_is_managed(struct pci_dev *pdev)
1060{
1061 return pdev->is_managed;
1062}
1063
1da177e4 1064void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1065
1066extern unsigned int pcibios_max_latency;
1da177e4 1067void pci_set_master(struct pci_dev *dev);
6a479079 1068void pci_clear_master(struct pci_dev *dev);
96c55900 1069
f7bdd12d 1070int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1071int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1072#define HAVE_PCI_SET_MWI
4a7fb636 1073int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1074int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1075int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1076void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1077void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1078bool pci_check_and_mask_intx(struct pci_dev *dev);
1079bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1080int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1081int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1082int pcix_get_max_mmrbc(struct pci_dev *dev);
1083int pcix_get_mmrbc(struct pci_dev *dev);
1084int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1085int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1086int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1087int pcie_get_mps(struct pci_dev *dev);
1088int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1089u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1090 enum pci_bus_speed *speed,
1091 enum pcie_link_width *width);
9e506a7b 1092void pcie_print_link_status(struct pci_dev *dev);
91295d79 1093int pcie_flr(struct pci_dev *dev);
a96d627a 1094int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1095int pci_reset_function(struct pci_dev *dev);
a477b9cd 1096int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1097int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1098int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1099int pci_probe_reset_bus(struct pci_bus *bus);
811c5cb3 1100int pci_try_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1101void pci_reset_secondary_bus(struct pci_dev *dev);
1102void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1103void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1104int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1105int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1106void pci_release_resource(struct pci_dev *dev, int resno);
1107int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1108int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1109bool pci_device_is_present(struct pci_dev *pdev);
08249651 1110void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1111
704e8953
CH		 1112int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1113 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1114 const char *fmt, ...);
1115void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1116
1da177e4 1117/* ROM control related routines */
e416de5e
AC		 1118int pci_enable_rom(struct pci_dev *pdev);
1119void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1120void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1121void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1122size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1123void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1124
1125/* Power management related routines */
1126int pci_save_state(struct pci_dev *dev);
1d3c16a8 1127void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1128struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1129int pci_load_saved_state(struct pci_dev *dev,
1130 struct pci_saved_state *state);
ffbdd3f7
AW		 1131int pci_load_and_free_saved_state(struct pci_dev *dev,
1132 struct pci_saved_state **state);
fd0f7f73
AW		 1133struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1134struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1135 u16 cap);
1136int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1137int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1138 u16 cap, unsigned int size);
0e5dd46b 1139int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1140int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1141pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1142bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1143void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1144int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1145int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1146int pci_prepare_to_sleep(struct pci_dev *dev);
1147int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1148bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1149bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1150void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1151void pci_d3cold_enable(struct pci_dev *dev);
1152void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1153bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
2a4d2c42
LW		 1154void pci_wakeup_bus(struct pci_bus *bus);
1155void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1156
425c1b22
AW		 1157/* PCI Virtual Channel */
1158int pci_save_vc_state(struct pci_dev *dev);
1159void pci_restore_vc_state(struct pci_dev *dev);
1160void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1161
bb209c82
BH		 1162/* For use by arch with custom probe code */
1163void set_pcie_port_type(struct pci_dev *pdev);
1164void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1165
ce5ccdef 1166/* Functions for PCI Hotplug drivers to use */
05cca6e5 1167int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1168unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1169unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1170void pci_lock_rescan_remove(void);
1171void pci_unlock_rescan_remove(void);
ce5ccdef 1172
0aa0f5d1 1173/* Vital Product Data routines */
287d19ce
SH		 1174ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1175ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1176int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1177
1da177e4 1178/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1179resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1180void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1181void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1182void pci_bus_size_bridges(struct pci_bus *bus);
1183int pci_claim_resource(struct pci_dev *, int);
8505e729 1184int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1185void pci_assign_unassigned_resources(void);
6841ec68 1186void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1187void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1188void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1189int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1190void pdev_enable_device(struct pci_dev *);
842de40d 1191int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1192void pci_assign_irq(struct pci_dev *dev);
afd29f90 1193struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1194#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1195int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1196int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1197void pci_release_regions(struct pci_dev *);
4a7fb636 1198int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1199int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1200void pci_release_region(struct pci_dev *, int);
c87deff7 1201int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1202int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1203void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1204
1205/* drivers/pci/bus.c */
fe830ef6
JL		 1206struct pci_bus *pci_bus_get(struct pci_bus *bus);
1207void pci_bus_put(struct pci_bus *bus);
45ca9e97 1208void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1209void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1210 resource_size_t offset);
45ca9e97 1211void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1212void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1213 unsigned int flags);
2fe2abf8
BH		 1214struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1215void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1216int devm_request_pci_bus_resources(struct device *dev,
1217 struct list_head *resources);
2fe2abf8 1218
89a74ecc 1219#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1220 for (i = 0; \
1221 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1222 i++)
89a74ecc 1223
4a7fb636
AM		 1224int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1225 struct resource *res, resource_size_t size,
1226 resource_size_t align, resource_size_t min,
664c2848 1227 unsigned long type_mask,
3b7a17fc
DB		 1228 resource_size_t (*alignf)(void *,
1229 const struct resource *,
b26b2d49
DB		 1230 resource_size_t,
1231 resource_size_t),
4a7fb636 1232 void *alignf_data);
1da177e4 1233
8b921acf 1234
fcfaab30
GP		 1235int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1236 resource_size_t size);
c5076cfe
TN		 1237unsigned long pci_address_to_pio(phys_addr_t addr);
1238phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1239int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
4d3f1384 1240void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1241void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1242 resource_size_t offset,
1243 resource_size_t size);
1244void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1245 struct resource *res);
8b921acf 1246
3a9ad0b4 1247static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1248{
1249 struct pci_bus_region region;
1250
1251 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1252 return region.start;
1253}
1254
863b18f4 1255/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1256int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1257 const char *mod_name);
bba81165 1258
0aa0f5d1 1259/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1260#define pci_register_driver(driver) \
1261 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1262
05cca6e5 1263void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1264
1265/**
1266 * module_pci_driver() - Helper macro for registering a PCI driver
1267 * @__pci_driver: pci_driver struct
1268 *
1269 * Helper macro for PCI drivers which do not do anything special in module
1270 * init/exit. This eliminates a lot of boilerplate. Each module may only
1271 * use this macro once, and calling it replaces module_init() and module_exit()
1272 */
1273#define module_pci_driver(__pci_driver) \
0aa0f5d1 1274 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1275
b4eb6cdb
PG		 1276/**
1277 * builtin_pci_driver() - Helper macro for registering a PCI driver
1278 * @__pci_driver: pci_driver struct
1279 *
1280 * Helper macro for PCI drivers which do not do anything special in their
1281 * init code. This eliminates a lot of boilerplate. Each driver may only
1282 * use this macro once, and calling it replaces device_initcall(...)
1283 */
1284#define builtin_pci_driver(__pci_driver) \
1285 builtin_driver(__pci_driver, pci_register_driver)
1286
05cca6e5 1287struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1288int pci_add_dynid(struct pci_driver *drv,
1289 unsigned int vendor, unsigned int device,
1290 unsigned int subvendor, unsigned int subdevice,
1291 unsigned int class, unsigned int class_mask,
1292 unsigned long driver_data);
05cca6e5
GKH		 1293const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1294 struct pci_dev *dev);
1295int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1296 int pass);
1da177e4 1297
70298c6e 1298void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1299 void *userdata);
ac7dc65a 1300int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1301unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1302void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1303resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1304 unsigned long type);
cecf4864 1305
3448a19d
DA		 1306#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1307#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1308
deb2d2ec 1309int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1310 unsigned int command_bits, u32 flags);
fe537670 1311
0aa0f5d1
BH		 1312#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1313#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1314#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1315#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
4fe0d154
CH		 1316#define PCI_IRQ_ALL_TYPES \
1317 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1318
1da177e4
LT		 1319/* kmem_cache style wrapper around pci_alloc_consistent() */
1320
f41b1771 1321#include <linux/pci-dma.h>
1da177e4
LT		 1322#include <linux/dmapool.h>
1323
1324#define pci_pool dma_pool
1325#define pci_pool_create(name, pdev, size, align, allocation) \
1326 dma_pool_create(name, &pdev->dev, size, align, allocation)
1327#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1328#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1329#define pci_pool_zalloc(pool, flags, handle) \
1330 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1331#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1332
1da177e4 1333struct msix_entry {
0aa0f5d1
BH		 1334 u32 vector; /* Kernel uses to write allocated vector */
1335 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1336};
1337
4c859804
BH		 1338#ifdef CONFIG_PCI_MSI
1339int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1340void pci_disable_msi(struct pci_dev *dev);
4c859804 1341int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1342void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1343void pci_restore_msi_state(struct pci_dev *dev);
1344int pci_msi_enabled(void);
4fe03955 1345int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1346int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1347 int minvec, int maxvec);
f7fc32cb
AG		 1348static inline int pci_enable_msix_exact(struct pci_dev *dev,
1349 struct msix_entry *entries, int nvec)
1350{
1351 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1352 if (rc < 0)
1353 return rc;
1354 return 0;
1355}
402723ad
CH		 1356int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1357 unsigned int max_vecs, unsigned int flags,
1358 const struct irq_affinity *affd);
1359
aff17164
CH		 1360void pci_free_irq_vectors(struct pci_dev *dev);
1361int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1362const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1363int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1364
4c859804 1365#else
2ee546c4 1366static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1367static inline void pci_disable_msi(struct pci_dev *dev) { }
1368static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1369static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1370static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1371static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1372static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1373{ return -ENOSYS; }
302a2523 1374static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1375 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1376{ return -ENOSYS; }
f7fc32cb 1377static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1378 struct msix_entry *entries, int nvec)
f7fc32cb 1379{ return -ENOSYS; }
402723ad
CH		 1380
1381static inline int
1382pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1383 unsigned int max_vecs, unsigned int flags,
1384 const struct irq_affinity *aff_desc)
aff17164 1385{
83b4605b
CH		 1386 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1387 return 1;
1388 return -ENOSPC;
aff17164 1389}
402723ad 1390
aff17164
CH		 1391static inline void pci_free_irq_vectors(struct pci_dev *dev)
1392{
1393}
1394
1395static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1396{
1397 if (WARN_ON_ONCE(nr > 0))
1398 return -EINVAL;
1399 return dev->irq;
1400}
ee8d41e5
TG		 1401static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1402 int vec)
1403{
1404 return cpu_possible_mask;
1405}
27ddb689
SL		 1406
1407static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1408{
1409 return first_online_node;
1410}
1da177e4
LT		 1411#endif
1412
402723ad
CH		 1413static inline int
1414pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1415 unsigned int max_vecs, unsigned int flags)
1416{
1417 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1418 NULL);
1419}
1420
0d58e6c1
PB		 1421/**
1422 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1423 * @d: the INTx IRQ domain
1424 * @node: the DT node for the device whose interrupt we're translating
1425 * @intspec: the interrupt specifier data from the DT
1426 * @intsize: the number of entries in @intspec
1427 * @out_hwirq: pointer at which to write the hwirq number
1428 * @out_type: pointer at which to write the interrupt type
1429 *
1430 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1431 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1432 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1433 * INTx value to obtain the hwirq number.
1434 *
1435 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1436 */
1437static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1438 struct device_node *node,
1439 const u32 *intspec,
1440 unsigned int intsize,
1441 unsigned long *out_hwirq,
1442 unsigned int *out_type)
1443{
1444 const u32 intx = intspec[0];
1445
1446 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1447 return -EINVAL;
1448
1449 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1450 return 0;
1451}
1452
ab0724ff 1453#ifdef CONFIG_PCIEPORTBUS
415e12b2 1454extern bool pcie_ports_disabled;
5352a44a 1455extern bool pcie_ports_native;
ab0724ff
MT		 1456#else
1457#define pcie_ports_disabled true
5352a44a 1458#define pcie_ports_native false
ab0724ff 1459#endif
415e12b2 1460
4c859804 1461#ifdef CONFIG_PCIEASPM
f39d5b72 1462bool pcie_aspm_support_enabled(void);
4c859804
BH		 1463#else
1464static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1465#endif
1466
415e12b2
RW		 1467#ifdef CONFIG_PCIEAER
1468void pci_no_aer(void);
1469bool pci_aer_available(void);
66b80809 1470int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1471#else
1472static inline void pci_no_aer(void) { }
1473static inline bool pci_aer_available(void) { return false; }
66b80809 1474static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1475#endif
1476
4c859804 1477#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1478void pcie_set_ecrc_checking(struct pci_dev *dev);
1479void pcie_ecrc_get_policy(char *str);
4c859804 1480#else
2ee546c4
BH		 1481static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1482static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1483#endif
1484
cef74409
GK		 1485bool pci_ats_disabled(void);
1486
edc90fee
BH		 1487#ifdef CONFIG_PCI_ATS
1488/* Address Translation Service */
1489void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1490int pci_enable_ats(struct pci_dev *dev, int ps);
1491void pci_disable_ats(struct pci_dev *dev);
1492int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1493#else
ff9bee89
BH		 1494static inline void pci_ats_init(struct pci_dev *d) { }
1495static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1496static inline void pci_disable_ats(struct pci_dev *d) { }
1497static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1498#endif
1499
eec097d4
BH		 1500#ifdef CONFIG_PCIE_PTM
1501int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1502#else
1503static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1504{ return -EINVAL; }
1505#endif
1506
f39d5b72
BH		 1507void pci_cfg_access_lock(struct pci_dev *dev);
1508bool pci_cfg_access_trylock(struct pci_dev *dev);
1509void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1510
4352dfd5
GKH		 1511/*
1512 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1513 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1514 * configuration space.
1515 */
32a2eea7
JG		 1516#ifdef CONFIG_PCI_DOMAINS
1517extern int pci_domains_supported;
1518#else
1519enum { pci_domains_supported = 0 };
2ee546c4
BH		 1520static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1521static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1522#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1523
670ba0c8
CM		 1524/*
1525 * Generic implementation for PCI domain support. If your
1526 * architecture does not need custom management of PCI
1527 * domains then this implementation will be used
1528 */
1529#ifdef CONFIG_PCI_DOMAINS_GENERIC
1530static inline int pci_domain_nr(struct pci_bus *bus)
1531{
1532 return bus->domain_nr;
1533}
2ab51dde
TN		 1534#ifdef CONFIG_ACPI
1535int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1536#else
2ab51dde
TN		 1537static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1538{ return 0; }
1539#endif
9c7cb891 1540int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1541#endif
1542
0aa0f5d1 1543/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1544typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1545 unsigned int command_bits, u32 flags);
f39d5b72 1546void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1547
be9d2e89
JT		 1548static inline int
1549pci_request_io_regions(struct pci_dev *pdev, const char *name)
1550{
1551 return pci_request_selected_regions(pdev,
1552 pci_select_bars(pdev, IORESOURCE_IO), name);
1553}
1554
1555static inline void
1556pci_release_io_regions(struct pci_dev *pdev)
1557{
1558 return pci_release_selected_regions(pdev,
1559 pci_select_bars(pdev, IORESOURCE_IO));
1560}
1561
1562static inline int
1563pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1564{
1565 return pci_request_selected_regions(pdev,
1566 pci_select_bars(pdev, IORESOURCE_MEM), name);
1567}
1568
1569static inline void
1570pci_release_mem_regions(struct pci_dev *pdev)
1571{
1572 return pci_release_selected_regions(pdev,
1573 pci_select_bars(pdev, IORESOURCE_MEM));
1574}
1575
4352dfd5 1576#else /* CONFIG_PCI is not enabled */
1da177e4 1577
5bbe029f
BH		 1578static inline void pci_set_flags(int flags) { }
1579static inline void pci_add_flags(int flags) { }
1580static inline void pci_clear_flags(int flags) { }
1581static inline int pci_has_flag(int flag) { return 0; }
1582
1da177e4 1583/*
0aa0f5d1
BH		 1584 * If the system does not have PCI, clearly these return errors. Define
1585 * these as simple inline functions to avoid hair in drivers.
1da177e4 1586 */
05cca6e5
GKH		 1587#define _PCI_NOP(o, s, t) \
1588 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1589 int where, t val) \
1da177e4 1590 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1591
1592#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1593 _PCI_NOP(o, word, u16 x) \
1594 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1595_PCI_NOP_ALL(read, *)
1596_PCI_NOP_ALL(write,)
1597
d42552c3 1598static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1599 unsigned int device,
1600 struct pci_dev *from)
2ee546c4 1601{ return NULL; }
d42552c3 1602
05cca6e5
GKH		 1603static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1604 unsigned int device,
1605 unsigned int ss_vendor,
1606 unsigned int ss_device,
b08508c4 1607 struct pci_dev *from)
2ee546c4 1608{ return NULL; }
1da177e4 1609
05cca6e5
GKH		 1610static inline struct pci_dev *pci_get_class(unsigned int class,
1611 struct pci_dev *from)
2ee546c4 1612{ return NULL; }
1da177e4
LT		 1613
1614#define pci_dev_present(ids) (0)
ed4aaadb 1615#define no_pci_devices() (1)
1da177e4
LT		 1616#define pci_dev_put(dev) do { } while (0)
1617
2ee546c4
BH		 1618static inline void pci_set_master(struct pci_dev *dev) { }
1619static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1620static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1621static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1622{ return -EBUSY; }
05cca6e5
GKH		 1623static inline int __pci_register_driver(struct pci_driver *drv,
1624 struct module *owner)
2ee546c4 1625{ return 0; }
05cca6e5 1626static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1627{ return 0; }
1628static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1629static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1630{ return 0; }
05cca6e5
GKH		 1631static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1632 int cap)
2ee546c4 1633{ return 0; }
05cca6e5 1634static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1635{ return 0; }
05cca6e5 1636
1da177e4 1637/* Power management related routines */
2ee546c4
BH		 1638static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1639static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1640static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1641{ return 0; }
3449248c 1642static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1643{ return 0; }
05cca6e5
GKH		 1644static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1645 pm_message_t state)
2ee546c4 1646{ return PCI_D0; }
05cca6e5
GKH		 1647static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1648 int enable)
2ee546c4 1649{ return 0; }
48a92a81 1650
afd29f90
MW		 1651static inline struct resource *pci_find_resource(struct pci_dev *dev,
1652 struct resource *res)
1653{ return NULL; }
05cca6e5 1654static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1655{ return -EIO; }
1656static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1657
c5076cfe
TN		 1658static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1659
2ee546c4 1660static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1661static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1662{ return 0; }
2ee546c4 1663static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1664
d80d0217
RD		 1665static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1666{ return NULL; }
d80d0217
RD		 1667static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1668 unsigned int devfn)
1669{ return NULL; }
7912af5c
RD		 1670static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1671 unsigned int bus, unsigned int devfn)
1672{ return NULL; }
d80d0217 1673
2ee546c4
BH		 1674static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1675static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 1676
fb8a0d9d
WM		 1677#define dev_is_pci(d) (false)
1678#define dev_is_pf(d) (false)
fe594932
GU		 1679static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1680{ return false; }
80db6f08
NC		 1681static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1682 struct device_node *node,
1683 const u32 *intspec,
1684 unsigned int intsize,
1685 unsigned long *out_hwirq,
1686 unsigned int *out_type)
1687{ return -EINVAL; }
4352dfd5 1688#endif /* CONFIG_PCI */
1da177e4 1689
4352dfd5
GKH		 1690/* Include architecture-dependent settings and functions */
1691
1692#include <asm/pci.h>
1da177e4 1693
f7195824
DW		 1694/* These two functions provide almost identical functionality. Depennding
1695 * on the architecture, one will be implemented as a wrapper around the
1696 * other (in drivers/pci/mmap.c).
1697 *
1698 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1699 * is expected to be an offset within that region.
1700 *
1701 * pci_mmap_page_range() is the legacy architecture-specific interface,
1702 * which accepts a "user visible" resource address converted by
1703 * pci_resource_to_user(), as used in the legacy mmap() interface in
1704 * /proc/bus/pci/.
1705 */
1706int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1707 struct vm_area_struct *vma,
1708 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1709int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1710 struct vm_area_struct *vma,
11df1954
DW		 1711 enum pci_mmap_state mmap_state, int write_combine);
1712
ae749c7a
DW		 1713#ifndef arch_can_pci_mmap_wc
1714#define arch_can_pci_mmap_wc() 0
1715#endif
2bea36fd 1716
e854d8b2
DW		 1717#ifndef arch_can_pci_mmap_io
1718#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1719#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1720#else
1721int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1722#endif
ae749c7a 1723
92016ba5
JO		 1724#ifndef pci_root_bus_fwnode
1725#define pci_root_bus_fwnode(bus) NULL
1726#endif
1727
0aa0f5d1
BH		 1728/*
1729 * These helpers provide future and backwards compatibility
1730 * for accessing popular PCI BAR info
1731 */
05cca6e5
GKH		 1732#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1733#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1734#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1735#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1736 ((pci_resource_start((dev), (bar)) == 0 && \
1737 pci_resource_end((dev), (bar)) == \
1738 pci_resource_start((dev), (bar))) ? 0 : \
1739 \
1740 (pci_resource_end((dev), (bar)) - \
1741 pci_resource_start((dev), (bar)) + 1))
1da177e4 1742
0aa0f5d1
BH		 1743/*
1744 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1745 * driver-specific data. They are really just a wrapper around
1746 * the generic device structure functions of these calls.
1747 */
05cca6e5 1748static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1749{
1750 return dev_get_drvdata(&pdev->dev);
1751}
1752
05cca6e5 1753static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1754{
1755 dev_set_drvdata(&pdev->dev, data);
1756}
1757
2fc90f61 1758static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1759{
c6c4f070 1760 return dev_name(&pdev->dev);
1da177e4
LT		 1761}
1762
2311b1f2 1763
0aa0f5d1
BH		 1764/*
1765 * Some archs don't want to expose struct resource to userland as-is
2311b1f2
ME		 1766 * in sysfs and /proc
1767 */
8221a013
BH		 1768#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1769void pci_resource_to_user(const struct pci_dev *dev, int bar,
1770 const struct resource *rsrc,
1771 resource_size_t *start, resource_size_t *end);
1772#else
2311b1f2 1773static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1774 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1775 resource_size_t *end)
2311b1f2
ME		 1776{
1777 *start = rsrc->start;
1778 *end = rsrc->end;
1779}
1780#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1781
1782
1da177e4 1783/*
0aa0f5d1
BH		 1784 * The world is not perfect and supplies us with broken PCI devices.
1785 * For at least a part of these bugs we need a work-around, so both
1786 * generic (drivers/pci/quirks.c) and per-architecture code can define
1787 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1788 */
1789
1790struct pci_fixup {
0aa0f5d1
BH		 1791 u16 vendor; /* Or PCI_ANY_ID */
1792 u16 device; /* Or PCI_ANY_ID */
1793 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 1794 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1795 void (*hook)(struct pci_dev *dev);
1796};
1797
1798enum pci_fixup_pass {
1799 pci_fixup_early, /* Before probing BARs */
1800 pci_fixup_header, /* After reading configuration header */
1801 pci_fixup_final, /* Final phase of device fixups */
1802 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1803 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1804 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1805 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1806 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1807};
1808
1809/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1810#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1811 class_shift, hook) \
ecf61c78 1812 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1813 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1814 = { vendor, device, class, class_shift, hook };
1815
1816#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1817 class_shift, hook) \
1818 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1819 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1820#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1821 class_shift, hook) \
1822 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1823 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1824#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1825 class_shift, hook) \
1826 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1827 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1828#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1829 class_shift, hook) \
1830 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1831 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1832#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1833 class_shift, hook) \
1834 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1835 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1836#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1837 class_shift, hook) \
1838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1839 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1840#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1841 class_shift, hook) \
1842 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1843 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 1844#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1845 class_shift, hook) \
1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1847 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 1848
1da177e4
LT		 1849#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1851 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1852#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1854 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1855#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1857 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1858#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1860 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1861#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1863 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1864#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1866 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1867#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1869 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1870#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1872 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 1873
93177a74 1874#ifdef CONFIG_PCI_QUIRKS
1da177e4 1875void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1876int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1877int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1878#else
1879static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1880 struct pci_dev *dev) { }
ad805758
AW		 1881static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1882 u16 acs_flags)
1883{
1884 return -ENOTTY;
1885}
c1d61c9b
AW		 1886static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1887{
1888 return -ENOTTY;
1889}
93177a74 1890#endif
1da177e4 1891
05cca6e5 1892void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1893void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1894void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1895int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1896int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1897 const char *name);
fb7ebfe4 1898void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1899
1da177e4 1900extern int pci_pci_problems;
236561e5 1901#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1902#define PCIPCI_TRITON 2
1903#define PCIPCI_NATOMA 4
1904#define PCIPCI_VIAETBF 8
1905#define PCIPCI_VSFX 16
236561e5
AC		 1906#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1907#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1908
4516a618
AN		 1909extern unsigned long pci_cardbus_io_size;
1910extern unsigned long pci_cardbus_mem_size;
15856ad5 1911extern u8 pci_dfl_cache_line_size;
ac1aa47b 1912extern u8 pci_cache_line_size;
4516a618 1913
28760489
EB		 1914extern unsigned long pci_hotplug_io_size;
1915extern unsigned long pci_hotplug_mem_size;
e16b4660 1916extern unsigned long pci_hotplug_bus_size;
28760489 1917
f7625980 1918/* Architecture-specific versions may override these (weak) */
19792a08 1919void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1920void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1921int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1922 enum pcie_reset_state state);
eca0d467 1923int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1924void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1925void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1926int pcibios_alloc_irq(struct pci_dev *dev);
1927void pcibios_free_irq(struct pci_dev *dev);
619e6f34 1928resource_size_t pcibios_default_alignment(void);
575e3348 1929
699c1985
SO		 1930#ifdef CONFIG_HIBERNATE_CALLBACKS
1931extern struct dev_pm_ops pcibios_pm_ops;
1932#endif
1933
935c760e 1934#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1935void __init pci_mmcfg_early_init(void);
1936void __init pci_mmcfg_late_init(void);
7752d5cf 1937#else
bb63b421 1938static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1939static inline void pci_mmcfg_late_init(void) { }
1940#endif
1941
642c92da 1942int pci_ext_cfg_avail(void);
0ef5f8f6 1943
1684f5dd 1944void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1945void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1946
dd7cc44d 1947#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1948int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1949int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1950
f39d5b72
BH		 1951int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1952void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 1953int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1954void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 1955int pci_num_vf(struct pci_dev *dev);
5a8eb242 1956int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1957int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1958int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 1959int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 1960resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 1961void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 1962
1963/* Arch may override these (weak) */
1964int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1965int pcibios_sriov_disable(struct pci_dev *pdev);
1966resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 1967#else
b07579c0
WY		 1968static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1969{
1970 return -ENOSYS;
1971}
1972static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1973{
1974 return -ENOSYS;
1975}
dd7cc44d 1976static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1977{ return -ENODEV; }
753f6124 1978static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 1979{
1980 return -ENOSYS;
1981}
1982static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 1983 int id) { }
2ee546c4 1984static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1985static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1986static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1987{ return 0; }
bff73156 1988static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1989{ return 0; }
bff73156 1990static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1991{ return 0; }
8effc395 1992#define pci_sriov_configure_simple NULL
0e6c9122
WY		 1993static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1994{ return 0; }
608c0d88 1995static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 1996#endif
1997
c825bc94 1998#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1999void pci_hp_create_module_link(struct pci_slot *pci_slot);
2000void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2001#endif
2002
d7b7e605
KK		 2003/**
2004 * pci_pcie_cap - get the saved PCIe capability offset
2005 * @dev: PCI device
2006 *
2007 * PCIe capability offset is calculated at PCI device initialization
2008 * time and saved in the data structure. This function returns saved
2009 * PCIe capability offset. Using this instead of pci_find_capability()
2010 * reduces unnecessary search in the PCI configuration space. If you
2011 * need to calculate PCIe capability offset from raw device for some
2012 * reasons, please use pci_find_capability() instead.
2013 */
2014static inline int pci_pcie_cap(struct pci_dev *dev)
2015{
2016 return dev->pcie_cap;
2017}
2018
7eb776c4
KK		 2019/**
2020 * pci_is_pcie - check if the PCI device is PCI Express capable
2021 * @dev: PCI device
2022 *
a895c28a 2023 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2024 */
2025static inline bool pci_is_pcie(struct pci_dev *dev)
2026{
a895c28a 2027 return pci_pcie_cap(dev);
7eb776c4
KK		 2028}
2029
7c9c003c
MS		 2030/**
2031 * pcie_caps_reg - get the PCIe Capabilities Register
2032 * @dev: PCI device
2033 */
2034static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2035{
2036 return dev->pcie_flags_reg;
2037}
2038
786e2288
YW		 2039/**
2040 * pci_pcie_type - get the PCIe device/port type
2041 * @dev: PCI device
2042 */
2043static inline int pci_pcie_type(const struct pci_dev *dev)
2044{
1c531d82 2045 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2046}
2047
e784930b
JT		 2048static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2049{
2050 while (1) {
2051 if (!pci_is_pcie(dev))
2052 break;
2053 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2054 return dev;
2055 if (!dev->bus->self)
2056 break;
2057 dev = dev->bus->self;
2058 }
2059 return NULL;
2060}
2061
5d990b62 2062void pci_request_acs(void);
ad805758
AW		 2063bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2064bool pci_acs_path_enabled(struct pci_dev *start,
2065 struct pci_dev *end, u16 acs_flags);
430a2368 2066int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2067
7ad506fa 2068#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2069#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2070
2071/* Large Resource Data Type Tag Item Names */
2072#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2073#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2074#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2075
2076#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2077#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2078#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2079
2080/* Small Resource Data Type Tag Item Names */
9eb45d5c 2081#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2082
9eb45d5c 2083#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2084
2085#define PCI_VPD_SRDT_TIN_MASK 0x78
2086#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2087#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2088
2089#define PCI_VPD_LRDT_TAG_SIZE 3
2090#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2091
e1d5bdab
MC		 2092#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2093
4067a854
MC		 2094#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2095#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2096#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2097#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2098
a2ce7662
MC		 2099/**
2100 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2101 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2102 *
2103 * Returns the extracted Large Resource Data Type length.
2104 */
2105static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2106{
2107 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2108}
2109
9eb45d5c
HR		 2110/**
2111 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2112 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2113 *
2114 * Returns the extracted Large Resource Data Type Tag item.
2115 */
2116static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2117{
0aa0f5d1 2118 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
9eb45d5c
HR		 2119}
2120
7ad506fa
MC		 2121/**
2122 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2123 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2124 *
2125 * Returns the extracted Small Resource Data Type length.
2126 */
2127static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2128{
2129 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2130}
2131
9eb45d5c
HR		 2132/**
2133 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2134 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2135 *
2136 * Returns the extracted Small Resource Data Type Tag Item.
2137 */
2138static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2139{
2140 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2141}
2142
e1d5bdab
MC		 2143/**
2144 * pci_vpd_info_field_size - Extracts the information field length
2145 * @lrdt: Pointer to the beginning of an information field header
2146 *
2147 * Returns the extracted information field length.
2148 */
2149static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2150{
2151 return info_field[2];
2152}
2153
b55ac1b2
MC		 2154/**
2155 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2156 * @buf: Pointer to buffered vpd data
2157 * @off: The offset into the buffer at which to begin the search
2158 * @len: The length of the vpd buffer
2159 * @rdt: The Resource Data Type to search for
2160 *
2161 * Returns the index where the Resource Data Type was found or
2162 * -ENOENT otherwise.
2163 */
2164int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2165
4067a854
MC		 2166/**
2167 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2168 * @buf: Pointer to buffered vpd data
2169 * @off: The offset into the buffer at which to begin the search
2170 * @len: The length of the buffer area, relative to off, in which to search
2171 * @kw: The keyword to search for
2172 *
2173 * Returns the index where the information field keyword was found or
2174 * -ENOENT otherwise.
2175 */
2176int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2177 unsigned int len, const char *kw);
2178
98d9f30c
BH		 2179/* PCI <-> OF binding helpers */
2180#ifdef CONFIG_OF
2181struct device_node;
b165e2b6 2182struct irq_domain;
f39d5b72
BH		 2183void pci_set_of_node(struct pci_dev *dev);
2184void pci_release_of_node(struct pci_dev *dev);
2185void pci_set_bus_of_node(struct pci_bus *bus);
2186void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2187struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
3a8f77e4
CP		 2188int pci_parse_request_of_pci_ranges(struct device *dev,
2189 struct list_head *resources,
2190 struct resource **bus_range);
98d9f30c
BH		 2191
2192/* Arch may override this (weak) */
723ec4d0 2193struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2194
0aa0f5d1 2195#else /* CONFIG_OF */
98d9f30c
BH		 2196static inline void pci_set_of_node(struct pci_dev *dev) { }
2197static inline void pci_release_of_node(struct pci_dev *dev) { }
2198static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2199static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
b165e2b6
MZ		 2200static inline struct irq_domain *
2201pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
3a8f77e4
CP		 2202static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2203 struct list_head *resources,
2204 struct resource **bus_range)
2205{
2206 return -EINVAL;
2207}
98d9f30c
BH		 2208#endif /* CONFIG_OF */
2209
ad32eb2d
BM		 2210static inline struct device_node *
2211pci_device_to_OF_node(const struct pci_dev *pdev)
2212{
2213 return pdev ? pdev->dev.of_node : NULL;
2214}
2215
2216static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2217{
2218 return bus ? bus->dev.of_node : NULL;
2219}
2220
471036b2
SS		 2221#ifdef CONFIG_ACPI
2222struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2223
2224void
2225pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2226#else
2227static inline struct irq_domain *
2228pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2229#endif
2230
eb740b5f
GS		 2231#ifdef CONFIG_EEH
2232static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2233{
2234 return pdev->dev.archdata.edev;
2235}
2236#endif
2237
f0af9593 2238void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2239bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2240int pci_for_each_dma_alias(struct pci_dev *pdev,
2241 int (*fn)(struct pci_dev *pdev,
2242 u16 alias, void *data), void *data);
2243
0aa0f5d1 2244/* Helper functions for operation of device flag */
ce052984
EZ		 2245static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2246{
2247 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2248}
2249static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2250{
2251 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2252}
2253static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2254{
2255 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2256}
19bdb6e4
AW		 2257
2258/**
2259 * pci_ari_enabled - query ARI forwarding status
2260 * @bus: the PCI bus
2261 *
2262 * Returns true if ARI forwarding is enabled.
2263 */
2264static inline bool pci_ari_enabled(struct pci_bus *bus)
2265{
2266 return bus->self && bus->self->ari_enabled;
2267}
bc4b024a 2268
8531e283
LW		 2269/**
2270 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2271 * @pdev: PCI device to check
2272 *
2273 * Walk upwards from @pdev and check for each encountered bridge if it's part
2274 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2275 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2276 */
2277static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2278{
2279 struct pci_dev *parent = pdev;
2280
2281 if (pdev->is_thunderbolt)
2282 return true;
2283
2284 while ((parent = pci_upstream_bridge(parent)))
2285 if (parent->is_thunderbolt)
2286 return true;
2287
2288 return false;
2289}
2290
2e28bc84 2291#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2292void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2293#endif
856e1eb9 2294
0aa0f5d1 2295/* Provide the legacy pci_dma_* API */
bc4b024a
CH		 2296#include <linux/pci-dma-compat.h>
2297
7506dc79
FL		 2298#define pci_printk(level, pdev, fmt, arg...) \
2299 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2300
2301#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2302#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2303#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2304#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2305#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2306#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2307#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2308#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2309
1da177e4 2310#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)