Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 LT |
53 | #include <linux/device.h> |
54 | ||
7e7a43c3 AB |
55 | /* Include the ID list */ |
56 | #include <linux/pci_ids.h> | |
57 | ||
f46753c5 AC |
58 | /* pci_slot represents a physical slot */ |
59 | struct pci_slot { | |
60 | struct pci_bus *bus; /* The bus this slot is on */ | |
61 | struct list_head list; /* node in list of slots on this bus */ | |
62 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
63 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
64 | struct kobject kobj; | |
65 | }; | |
66 | ||
1da177e4 LT |
67 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
68 | enum pci_mmap_state { | |
69 | pci_mmap_io, | |
70 | pci_mmap_mem | |
71 | }; | |
72 | ||
73 | /* This defines the direction arg to the DMA mapping routines. */ | |
74 | #define PCI_DMA_BIDIRECTIONAL 0 | |
75 | #define PCI_DMA_TODEVICE 1 | |
76 | #define PCI_DMA_FROMDEVICE 2 | |
77 | #define PCI_DMA_NONE 3 | |
78 | ||
1da177e4 LT |
79 | #define DEVICE_COUNT_RESOURCE 12 |
80 | ||
81 | typedef int __bitwise pci_power_t; | |
82 | ||
4352dfd5 GKH |
83 | #define PCI_D0 ((pci_power_t __force) 0) |
84 | #define PCI_D1 ((pci_power_t __force) 1) | |
85 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
86 | #define PCI_D3hot ((pci_power_t __force) 3) |
87 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 88 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 89 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 90 | |
392a1ce7 | 91 | /** The pci_channel state describes connectivity between the CPU and |
92 | * the pci device. If some PCI bus between here and the pci device | |
93 | * has crashed or locked up, this info is reflected here. | |
94 | */ | |
95 | typedef unsigned int __bitwise pci_channel_state_t; | |
96 | ||
97 | enum pci_channel_state { | |
98 | /* I/O channel is in normal state */ | |
99 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
100 | ||
101 | /* I/O to channel is blocked */ | |
102 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
103 | ||
104 | /* PCI card is dead */ | |
105 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
106 | }; | |
107 | ||
f7bdd12d BK |
108 | typedef unsigned int __bitwise pcie_reset_state_t; |
109 | ||
110 | enum pcie_reset_state { | |
111 | /* Reset is NOT asserted (Use to deassert reset) */ | |
112 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
113 | ||
114 | /* Use #PERST to reset PCI-E device */ | |
115 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
116 | ||
117 | /* Use PCI-E Hot Reset to reset device */ | |
118 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
119 | }; | |
120 | ||
ba698ad4 DM |
121 | typedef unsigned short __bitwise pci_dev_flags_t; |
122 | enum pci_dev_flags { | |
123 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
124 | * generation too. | |
125 | */ | |
126 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
127 | }; | |
128 | ||
6e325a62 MT |
129 | typedef unsigned short __bitwise pci_bus_flags_t; |
130 | enum pci_bus_flags { | |
d556ad4b PO |
131 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
132 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
133 | }; |
134 | ||
41017f0c SL |
135 | struct pci_cap_saved_state { |
136 | struct hlist_node next; | |
137 | char cap_nr; | |
138 | u32 data[0]; | |
139 | }; | |
140 | ||
7d715a6c | 141 | struct pcie_link_state; |
ee69439c JB |
142 | struct pci_vpd; |
143 | ||
1da177e4 LT |
144 | /* |
145 | * The pci_dev structure is used to describe PCI devices. | |
146 | */ | |
147 | struct pci_dev { | |
1da177e4 LT |
148 | struct list_head bus_list; /* node in per-bus list */ |
149 | struct pci_bus *bus; /* bus this device is on */ | |
150 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
151 | ||
152 | void *sysdata; /* hook for sys-specific extension */ | |
153 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 154 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
155 | |
156 | unsigned int devfn; /* encoded device & function index */ | |
157 | unsigned short vendor; | |
158 | unsigned short device; | |
159 | unsigned short subsystem_vendor; | |
160 | unsigned short subsystem_device; | |
161 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 162 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 163 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 164 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 165 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 166 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
167 | |
168 | struct pci_driver *driver; /* which driver has allocated this device */ | |
169 | u64 dma_mask; /* Mask of the bits of bus address this | |
170 | device implements. Normally this is | |
171 | 0xffffffff. You only need to change | |
172 | this if your device has broken DMA | |
173 | or supports 64-bit transfers. */ | |
174 | ||
4d57cdfa FT |
175 | struct device_dma_parameters dma_parms; |
176 | ||
1da177e4 LT |
177 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
178 | this is D0-D3, D0 being fully functional, | |
179 | and D3 being off. */ | |
337001b6 RW |
180 | int pm_cap; /* PM capability offset in the |
181 | configuration space */ | |
182 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
183 | can be generated */ | |
184 | unsigned int d1_support:1; /* Low power state D1 is supported */ | |
185 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
186 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
1da177e4 | 187 | |
7d715a6c SL |
188 | #ifdef CONFIG_PCIEASPM |
189 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
190 | #endif | |
191 | ||
392a1ce7 | 192 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
193 | struct device dev; /* Generic device interface */ |
194 | ||
1da177e4 LT |
195 | int cfg_size; /* Size of configuration space */ |
196 | ||
197 | /* | |
198 | * Instead of touching interrupt line and base address registers | |
199 | * directly, use the values stored here. They might be different! | |
200 | */ | |
201 | unsigned int irq; | |
202 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
203 | ||
204 | /* These fields are used by common fixups */ | |
205 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
206 | unsigned int multifunction:1;/* Part of multi-function device */ | |
207 | /* keep track of device state */ | |
8a1bc901 | 208 | unsigned int is_added:1; |
1da177e4 | 209 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 210 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 211 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 212 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
99dc804d SL |
213 | unsigned int msi_enabled:1; |
214 | unsigned int msix_enabled:1; | |
9ac7849e | 215 | unsigned int is_managed:1; |
994a65e2 | 216 | unsigned int is_pcie:1; |
ba698ad4 | 217 | pci_dev_flags_t dev_flags; |
bae94d02 | 218 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 219 | |
1da177e4 | 220 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 221 | struct hlist_head saved_cap_space; |
1da177e4 LT |
222 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
223 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
224 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 225 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 226 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 227 | struct list_head msi_list; |
ded86d8d | 228 | #endif |
94e61088 | 229 | struct pci_vpd *vpd; |
1da177e4 LT |
230 | }; |
231 | ||
65891215 ME |
232 | extern struct pci_dev *alloc_pci_dev(void); |
233 | ||
1da177e4 LT |
234 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
235 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
236 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
237 | ||
a7369f1f LV |
238 | static inline int pci_channel_offline(struct pci_dev *pdev) |
239 | { | |
240 | return (pdev->error_state != pci_channel_io_normal); | |
241 | } | |
242 | ||
41017f0c | 243 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 244 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
245 | { |
246 | struct pci_cap_saved_state *tmp; | |
247 | struct hlist_node *pos; | |
248 | ||
249 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
250 | if (tmp->cap_nr == cap) | |
251 | return tmp; | |
252 | } | |
253 | return NULL; | |
254 | } | |
255 | ||
256 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
257 | struct pci_cap_saved_state *new_cap) | |
258 | { | |
259 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
260 | } | |
261 | ||
1da177e4 LT |
262 | /* |
263 | * For PCI devices, the region numbers are assigned this way: | |
264 | * | |
265 | * 0-5 standard PCI regions | |
266 | * 6 expansion ROM | |
267 | * 7-10 bridges: address space assigned to buses behind the bridge | |
268 | */ | |
269 | ||
4352dfd5 GKH |
270 | #define PCI_ROM_RESOURCE 6 |
271 | #define PCI_BRIDGE_RESOURCES 7 | |
272 | #define PCI_NUM_RESOURCES 11 | |
1da177e4 LT |
273 | |
274 | #ifndef PCI_BUS_NUM_RESOURCES | |
30a18d6c | 275 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 276 | #endif |
4352dfd5 GKH |
277 | |
278 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
279 | |
280 | struct pci_bus { | |
281 | struct list_head node; /* node in list of buses */ | |
282 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
283 | struct list_head children; /* list of child buses */ | |
284 | struct list_head devices; /* list of devices on this bus */ | |
285 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 286 | struct list_head slots; /* list of slots on this bus */ |
1da177e4 LT |
287 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; |
288 | /* address space routed to this bus */ | |
289 | ||
290 | struct pci_ops *ops; /* configuration access functions */ | |
291 | void *sysdata; /* hook for sys-specific extension */ | |
292 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
293 | ||
294 | unsigned char number; /* bus number */ | |
295 | unsigned char primary; /* number of primary bridge */ | |
296 | unsigned char secondary; /* number of secondary bridge */ | |
297 | unsigned char subordinate; /* max number of subordinate buses */ | |
298 | ||
299 | char name[48]; | |
300 | ||
301 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 302 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 303 | struct device *bridge; |
fd7d1ced | 304 | struct device dev; |
1da177e4 LT |
305 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
306 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 307 | unsigned int is_added:1; |
1da177e4 LT |
308 | }; |
309 | ||
310 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 311 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 LT |
312 | |
313 | /* | |
314 | * Error values that may be returned by PCI functions. | |
315 | */ | |
316 | #define PCIBIOS_SUCCESSFUL 0x00 | |
317 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
318 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
319 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
320 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
321 | #define PCIBIOS_SET_FAILED 0x88 | |
322 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
323 | ||
324 | /* Low-level architecture-dependent routines */ | |
325 | ||
326 | struct pci_ops { | |
327 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
328 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
329 | }; | |
330 | ||
b6ce068a MW |
331 | /* |
332 | * ACPI needs to be able to access PCI config space before we've done a | |
333 | * PCI bus scan and created pci_bus structures. | |
334 | */ | |
335 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
336 | unsigned int devfn, int reg, int len, u32 *val); | |
337 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
338 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
339 | |
340 | struct pci_bus_region { | |
c40a22e0 BH |
341 | resource_size_t start; |
342 | resource_size_t end; | |
1da177e4 LT |
343 | }; |
344 | ||
345 | struct pci_dynids { | |
346 | spinlock_t lock; /* protects list, index */ | |
347 | struct list_head list; /* for IDs added at runtime */ | |
9433f6dd | 348 | unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */ |
1da177e4 LT |
349 | }; |
350 | ||
392a1ce7 | 351 | /* ---------------------------------------------------------------- */ |
352 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 353 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 354 | * will be notified of PCI bus errors, and will be driven to recovery |
355 | * when an error occurs. | |
356 | */ | |
357 | ||
358 | typedef unsigned int __bitwise pci_ers_result_t; | |
359 | ||
360 | enum pci_ers_result { | |
361 | /* no result/none/not supported in device driver */ | |
362 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
363 | ||
364 | /* Device driver can recover without slot reset */ | |
365 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
366 | ||
367 | /* Device driver wants slot to be reset. */ | |
368 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
369 | ||
370 | /* Device has completely failed, is unrecoverable */ | |
371 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
372 | ||
373 | /* Device driver is fully recovered and operational */ | |
374 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
375 | }; | |
376 | ||
377 | /* PCI bus error event callbacks */ | |
05cca6e5 | 378 | struct pci_error_handlers { |
392a1ce7 | 379 | /* PCI bus error detected on this device */ |
380 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 381 | enum pci_channel_state error); |
392a1ce7 | 382 | |
383 | /* MMIO has been re-enabled, but not DMA */ | |
384 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
385 | ||
386 | /* PCI Express link has been reset */ | |
387 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
388 | ||
389 | /* PCI slot has been reset */ | |
390 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
391 | ||
392 | /* Device driver may resume normal operations */ | |
393 | void (*resume)(struct pci_dev *dev); | |
394 | }; | |
395 | ||
396 | /* ---------------------------------------------------------------- */ | |
397 | ||
1da177e4 LT |
398 | struct module; |
399 | struct pci_driver { | |
400 | struct list_head node; | |
401 | char *name; | |
1da177e4 LT |
402 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
403 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
404 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
405 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
406 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
407 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 408 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 409 | void (*shutdown) (struct pci_dev *dev); |
bbb44d9f | 410 | struct pm_ext_ops *pm; |
392a1ce7 | 411 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
412 | struct device_driver driver; |
413 | struct pci_dynids dynids; | |
414 | }; | |
415 | ||
05cca6e5 | 416 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 417 | |
90a1ba0c | 418 | /** |
9f9351bb | 419 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
420 | * @_table: device table name |
421 | * | |
422 | * This macro is used to create a struct pci_device_id array (a device table) | |
423 | * in a generic manner. | |
424 | */ | |
9f9351bb | 425 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
426 | const struct pci_device_id _table[] __devinitconst |
427 | ||
1da177e4 LT |
428 | /** |
429 | * PCI_DEVICE - macro used to describe a specific pci device | |
430 | * @vend: the 16 bit PCI Vendor ID | |
431 | * @dev: the 16 bit PCI Device ID | |
432 | * | |
433 | * This macro is used to create a struct pci_device_id that matches a | |
434 | * specific device. The subvendor and subdevice fields will be set to | |
435 | * PCI_ANY_ID. | |
436 | */ | |
437 | #define PCI_DEVICE(vend,dev) \ | |
438 | .vendor = (vend), .device = (dev), \ | |
439 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
440 | ||
441 | /** | |
442 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
443 | * @dev_class: the class, subclass, prog-if triple for this device | |
444 | * @dev_class_mask: the class mask for this device | |
445 | * | |
446 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 447 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
448 | * fields will be set to PCI_ANY_ID. |
449 | */ | |
450 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
451 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
452 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
453 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
454 | ||
1597cacb AC |
455 | /** |
456 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
457 | * @vend: the vendor name | |
458 | * @dev: the 16 bit PCI Device ID | |
459 | * | |
460 | * This macro is used to create a struct pci_device_id that matches a | |
461 | * specific PCI device. The subvendor, and subdevice fields will be set | |
462 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
463 | * private data. | |
464 | */ | |
465 | ||
466 | #define PCI_VDEVICE(vendor, device) \ | |
467 | PCI_VENDOR_ID_##vendor, (device), \ | |
468 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
469 | ||
1da177e4 LT |
470 | /* these external functions are only available when PCI support is enabled */ |
471 | #ifdef CONFIG_PCI | |
472 | ||
473 | extern struct bus_type pci_bus_type; | |
474 | ||
475 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
476 | * code, or pci core code. */ | |
477 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
478 | /* Some device drivers need know if pci is initiated */ |
479 | extern int no_pci_devices(void); | |
1da177e4 LT |
480 | |
481 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 482 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 483 | char *pcibios_setup(char *str); |
1da177e4 LT |
484 | |
485 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
486 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
487 | resource_size_t); | |
1da177e4 LT |
488 | void pcibios_update_irq(struct pci_dev *, int irq); |
489 | ||
490 | /* Generic PCI functions used internally */ | |
491 | ||
492 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c431ada4 | 493 | void pci_bus_add_devices(struct pci_bus *bus); |
05cca6e5 GKH |
494 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
495 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 496 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 497 | void *sysdata) |
1da177e4 | 498 | { |
c431ada4 RS |
499 | struct pci_bus *root_bus; |
500 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
501 | if (root_bus) | |
502 | pci_bus_add_devices(root_bus); | |
503 | return root_bus; | |
1da177e4 | 504 | } |
05cca6e5 GKH |
505 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
506 | struct pci_ops *ops, void *sysdata); | |
507 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
508 | int busnr); | |
f46753c5 AC |
509 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
510 | const char *name); | |
511 | void pci_destroy_slot(struct pci_slot *slot); | |
512 | void pci_update_slot_number(struct pci_slot *slot, int slot_nr); | |
1da177e4 | 513 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 514 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 515 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 516 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 517 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 518 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
519 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
520 | struct resource *res); | |
1da177e4 LT |
521 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
522 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); | |
523 | extern void pci_dev_put(struct pci_dev *dev); | |
524 | extern void pci_remove_bus(struct pci_bus *b); | |
525 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 526 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 527 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 528 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
529 | |
530 | /* Generic PCI functions exported to card drivers */ | |
531 | ||
bd3989e0 | 532 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
533 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
534 | unsigned int device, | |
535 | const struct pci_dev *from); | |
536 | struct pci_dev __deprecated *pci_find_slot(unsigned int bus, | |
537 | unsigned int devfn); | |
bd3989e0 JG |
538 | #endif /* CONFIG_PCI_LEGACY */ |
539 | ||
05cca6e5 GKH |
540 | int pci_find_capability(struct pci_dev *dev, int cap); |
541 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
542 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
543 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
544 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 545 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 546 | |
d42552c3 AM |
547 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
548 | struct pci_dev *from); | |
05cca6e5 | 549 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 550 | unsigned int ss_vendor, unsigned int ss_device, |
95247b57 | 551 | const struct pci_dev *from); |
05cca6e5 GKH |
552 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
553 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); | |
554 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); | |
1da177e4 LT |
555 | int pci_dev_present(const struct pci_device_id *ids); |
556 | ||
05cca6e5 GKH |
557 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
558 | int where, u8 *val); | |
559 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
560 | int where, u16 *val); | |
561 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
562 | int where, u32 *val); | |
563 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
564 | int where, u8 val); | |
565 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
566 | int where, u16 val); | |
567 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
568 | int where, u32 val); | |
1da177e4 LT |
569 | |
570 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
571 | { | |
05cca6e5 | 572 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
573 | } |
574 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
575 | { | |
05cca6e5 | 576 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 577 | } |
05cca6e5 GKH |
578 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
579 | u32 *val) | |
1da177e4 | 580 | { |
05cca6e5 | 581 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
582 | } |
583 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
584 | { | |
05cca6e5 | 585 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
586 | } |
587 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
588 | { | |
05cca6e5 | 589 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 590 | } |
05cca6e5 GKH |
591 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
592 | u32 val) | |
1da177e4 | 593 | { |
05cca6e5 | 594 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
595 | } |
596 | ||
4a7fb636 | 597 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
598 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
599 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 600 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
601 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
602 | void pcim_pin_device(struct pci_dev *pdev); | |
603 | ||
604 | static inline int pci_is_managed(struct pci_dev *pdev) | |
605 | { | |
606 | return pdev->is_managed; | |
607 | } | |
608 | ||
1da177e4 LT |
609 | void pci_disable_device(struct pci_dev *dev); |
610 | void pci_set_master(struct pci_dev *dev); | |
f7bdd12d | 611 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 612 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 613 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 614 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 615 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 616 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 617 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
618 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
619 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 620 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 621 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
622 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
623 | int pcix_get_mmrbc(struct pci_dev *dev); | |
624 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 625 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 626 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
064b53db | 627 | void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); |
4a7fb636 | 628 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 629 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
630 | |
631 | /* ROM control related routines */ | |
144a50ea | 632 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 633 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
d7ad2254 | 634 | size_t pci_get_rom_size(void __iomem *rom, size_t size); |
1da177e4 LT |
635 | |
636 | /* Power management related routines */ | |
637 | int pci_save_state(struct pci_dev *dev); | |
638 | int pci_restore_state(struct pci_dev *dev); | |
9c8550ee LT |
639 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
640 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
641 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); | |
404cc2d8 RW |
642 | int pci_prepare_to_sleep(struct pci_dev *dev); |
643 | int pci_back_from_sleep(struct pci_dev *dev); | |
1da177e4 | 644 | |
ce5ccdef | 645 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 646 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
ce5ccdef | 647 | |
1da177e4 LT |
648 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
649 | void pci_bus_assign_resources(struct pci_bus *bus); | |
650 | void pci_bus_size_bridges(struct pci_bus *bus); | |
651 | int pci_claim_resource(struct pci_dev *, int); | |
652 | void pci_assign_unassigned_resources(void); | |
653 | void pdev_enable_device(struct pci_dev *); | |
654 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 655 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
656 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
657 | int (*)(struct pci_dev *, u8, u8)); | |
658 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 659 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
1da177e4 | 660 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 661 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 662 | void pci_release_region(struct pci_dev *, int); |
c87deff7 HS |
663 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
664 | void pci_release_selected_regions(struct pci_dev *, int); | |
1da177e4 LT |
665 | |
666 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
667 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
668 | struct resource *res, resource_size_t size, | |
669 | resource_size_t align, resource_size_t min, | |
670 | unsigned int type_mask, | |
671 | void (*alignf)(void *, struct resource *, | |
672 | resource_size_t, resource_size_t), | |
673 | void *alignf_data); | |
1da177e4 LT |
674 | void pci_enable_bridges(struct pci_bus *bus); |
675 | ||
863b18f4 | 676 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
677 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
678 | const char *mod_name); | |
4a7fb636 | 679 | static inline int __must_check pci_register_driver(struct pci_driver *driver) |
863b18f4 | 680 | { |
725522b5 | 681 | return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); |
863b18f4 L |
682 | } |
683 | ||
05cca6e5 GKH |
684 | void pci_unregister_driver(struct pci_driver *dev); |
685 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
686 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
687 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
688 | struct pci_dev *dev); | |
689 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
690 | int pass); | |
1da177e4 | 691 | |
cecf4864 PM |
692 | void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), |
693 | void *userdata); | |
70b9f7dc | 694 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 695 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 696 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 697 | |
1da177e4 LT |
698 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
699 | ||
700 | #include <linux/dmapool.h> | |
701 | ||
702 | #define pci_pool dma_pool | |
703 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
704 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
705 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
706 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
707 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
708 | ||
e24c2d96 DM |
709 | enum pci_dma_burst_strategy { |
710 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
711 | strategy_parameter is N/A */ | |
712 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
713 | byte boundaries */ | |
714 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
715 | strategy_parameter byte boundaries */ | |
716 | }; | |
717 | ||
1da177e4 LT |
718 | struct msix_entry { |
719 | u16 vector; /* kernel uses to write allocated vector */ | |
720 | u16 entry; /* driver uses to specify entry, OS writes */ | |
721 | }; | |
722 | ||
0366f8f7 | 723 | |
1da177e4 | 724 | #ifndef CONFIG_PCI_MSI |
05cca6e5 GKH |
725 | static inline int pci_enable_msi(struct pci_dev *dev) |
726 | { | |
727 | return -1; | |
728 | } | |
729 | ||
d52877c7 YL |
730 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
731 | { } | |
05cca6e5 GKH |
732 | static inline void pci_disable_msi(struct pci_dev *dev) |
733 | { } | |
734 | ||
735 | static inline int pci_enable_msix(struct pci_dev *dev, | |
736 | struct msix_entry *entries, int nvec) | |
737 | { | |
738 | return -1; | |
739 | } | |
740 | ||
d52877c7 YL |
741 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
742 | { } | |
05cca6e5 GKH |
743 | static inline void pci_disable_msix(struct pci_dev *dev) |
744 | { } | |
745 | ||
746 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
747 | { } | |
748 | ||
749 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
750 | { } | |
1da177e4 | 751 | #else |
1da177e4 | 752 | extern int pci_enable_msi(struct pci_dev *dev); |
d52877c7 | 753 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 754 | extern void pci_disable_msi(struct pci_dev *dev); |
05cca6e5 | 755 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 756 | struct msix_entry *entries, int nvec); |
d52877c7 | 757 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
758 | extern void pci_disable_msix(struct pci_dev *dev); |
759 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 760 | extern void pci_restore_msi_state(struct pci_dev *dev); |
1da177e4 LT |
761 | #endif |
762 | ||
8b955b0d | 763 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
764 | /* The functions a driver should call */ |
765 | int ht_create_irq(struct pci_dev *dev, int idx); | |
766 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
767 | #endif /* CONFIG_HT_IRQ */ |
768 | ||
e04b0ea2 BK |
769 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
770 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
771 | ||
4352dfd5 GKH |
772 | /* |
773 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
774 | * a PCI domain is defined to be a set of PCI busses which share | |
775 | * configuration space. | |
776 | */ | |
32a2eea7 JG |
777 | #ifdef CONFIG_PCI_DOMAINS |
778 | extern int pci_domains_supported; | |
779 | #else | |
780 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
781 | static inline int pci_domain_nr(struct pci_bus *bus) |
782 | { | |
783 | return 0; | |
784 | } | |
785 | ||
4352dfd5 GKH |
786 | static inline int pci_proc_domain(struct pci_bus *bus) |
787 | { | |
788 | return 0; | |
789 | } | |
32a2eea7 | 790 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 791 | |
4352dfd5 | 792 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
793 | |
794 | /* | |
795 | * If the system does not have PCI, clearly these return errors. Define | |
796 | * these as simple inline functions to avoid hair in drivers. | |
797 | */ | |
798 | ||
05cca6e5 GKH |
799 | #define _PCI_NOP(o, s, t) \ |
800 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
801 | int where, t val) \ | |
1da177e4 | 802 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
803 | |
804 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
805 | _PCI_NOP(o, word, u16 x) \ | |
806 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
807 | _PCI_NOP_ALL(read, *) |
808 | _PCI_NOP_ALL(write,) | |
809 | ||
05cca6e5 GKH |
810 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
811 | unsigned int device, | |
812 | const struct pci_dev *from) | |
813 | { | |
814 | return NULL; | |
815 | } | |
1da177e4 | 816 | |
05cca6e5 GKH |
817 | static inline struct pci_dev *pci_find_slot(unsigned int bus, |
818 | unsigned int devfn) | |
819 | { | |
820 | return NULL; | |
821 | } | |
1da177e4 | 822 | |
d42552c3 | 823 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
824 | unsigned int device, |
825 | struct pci_dev *from) | |
826 | { | |
827 | return NULL; | |
828 | } | |
d42552c3 | 829 | |
05cca6e5 GKH |
830 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
831 | unsigned int device, | |
832 | unsigned int ss_vendor, | |
833 | unsigned int ss_device, | |
95247b57 | 834 | const struct pci_dev *from) |
05cca6e5 GKH |
835 | { |
836 | return NULL; | |
837 | } | |
1da177e4 | 838 | |
05cca6e5 GKH |
839 | static inline struct pci_dev *pci_get_class(unsigned int class, |
840 | struct pci_dev *from) | |
841 | { | |
842 | return NULL; | |
843 | } | |
1da177e4 LT |
844 | |
845 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 846 | #define no_pci_devices() (1) |
1da177e4 LT |
847 | #define pci_dev_put(dev) do { } while (0) |
848 | ||
05cca6e5 GKH |
849 | static inline void pci_set_master(struct pci_dev *dev) |
850 | { } | |
851 | ||
852 | static inline int pci_enable_device(struct pci_dev *dev) | |
853 | { | |
854 | return -EIO; | |
855 | } | |
856 | ||
857 | static inline void pci_disable_device(struct pci_dev *dev) | |
858 | { } | |
859 | ||
860 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
861 | { | |
862 | return -EIO; | |
863 | } | |
864 | ||
80be0385 RD |
865 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
866 | { | |
867 | return -EIO; | |
868 | } | |
869 | ||
4d57cdfa FT |
870 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
871 | unsigned int size) | |
872 | { | |
873 | return -EIO; | |
874 | } | |
875 | ||
59fc67de FT |
876 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
877 | unsigned long mask) | |
878 | { | |
879 | return -EIO; | |
880 | } | |
881 | ||
05cca6e5 GKH |
882 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
883 | { | |
884 | return -EBUSY; | |
885 | } | |
886 | ||
887 | static inline int __pci_register_driver(struct pci_driver *drv, | |
888 | struct module *owner) | |
889 | { | |
890 | return 0; | |
891 | } | |
892 | ||
893 | static inline int pci_register_driver(struct pci_driver *drv) | |
894 | { | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
899 | { } | |
900 | ||
901 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
902 | { | |
903 | return 0; | |
904 | } | |
905 | ||
906 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
907 | int cap) | |
908 | { | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
913 | { | |
914 | return 0; | |
915 | } | |
916 | ||
1da177e4 | 917 | /* Power management related routines */ |
05cca6e5 GKH |
918 | static inline int pci_save_state(struct pci_dev *dev) |
919 | { | |
920 | return 0; | |
921 | } | |
922 | ||
923 | static inline int pci_restore_state(struct pci_dev *dev) | |
924 | { | |
925 | return 0; | |
926 | } | |
1da177e4 | 927 | |
05cca6e5 GKH |
928 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
929 | { | |
930 | return 0; | |
931 | } | |
932 | ||
933 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
934 | pm_message_t state) | |
935 | { | |
936 | return PCI_D0; | |
937 | } | |
938 | ||
939 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
940 | int enable) | |
941 | { | |
942 | return 0; | |
943 | } | |
944 | ||
945 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
946 | { | |
947 | return -EIO; | |
948 | } | |
949 | ||
950 | static inline void pci_release_regions(struct pci_dev *dev) | |
951 | { } | |
0da0ead9 | 952 | |
a46e8126 KG |
953 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
954 | ||
05cca6e5 GKH |
955 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
956 | { } | |
957 | ||
958 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
959 | { } | |
e04b0ea2 | 960 | |
d80d0217 RD |
961 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
962 | { return NULL; } | |
963 | ||
964 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
965 | unsigned int devfn) | |
966 | { return NULL; } | |
967 | ||
968 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
969 | unsigned int devfn) | |
970 | { return NULL; } | |
971 | ||
4352dfd5 | 972 | #endif /* CONFIG_PCI */ |
1da177e4 | 973 | |
4352dfd5 GKH |
974 | /* Include architecture-dependent settings and functions */ |
975 | ||
976 | #include <asm/pci.h> | |
1da177e4 LT |
977 | |
978 | /* these helpers provide future and backwards compatibility | |
979 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
980 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
981 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
982 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 983 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
984 | ((pci_resource_start((dev), (bar)) == 0 && \ |
985 | pci_resource_end((dev), (bar)) == \ | |
986 | pci_resource_start((dev), (bar))) ? 0 : \ | |
987 | \ | |
988 | (pci_resource_end((dev), (bar)) - \ | |
989 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
990 | |
991 | /* Similar to the helpers above, these manipulate per-pci_dev | |
992 | * driver-specific data. They are really just a wrapper around | |
993 | * the generic device structure functions of these calls. | |
994 | */ | |
05cca6e5 | 995 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
996 | { |
997 | return dev_get_drvdata(&pdev->dev); | |
998 | } | |
999 | ||
05cca6e5 | 1000 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1001 | { |
1002 | dev_set_drvdata(&pdev->dev, data); | |
1003 | } | |
1004 | ||
1005 | /* If you want to know what to call your pci_dev, ask this function. | |
1006 | * Again, it's a wrapper around the generic device. | |
1007 | */ | |
c6c4f070 | 1008 | static inline const char *pci_name(struct pci_dev *pdev) |
1da177e4 | 1009 | { |
c6c4f070 | 1010 | return dev_name(&pdev->dev); |
1da177e4 LT |
1011 | } |
1012 | ||
2311b1f2 ME |
1013 | |
1014 | /* Some archs don't want to expose struct resource to userland as-is | |
1015 | * in sysfs and /proc | |
1016 | */ | |
1017 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1018 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1019 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1020 | resource_size_t *end) |
2311b1f2 ME |
1021 | { |
1022 | *start = rsrc->start; | |
1023 | *end = rsrc->end; | |
1024 | } | |
1025 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1026 | ||
1027 | ||
1da177e4 LT |
1028 | /* |
1029 | * The world is not perfect and supplies us with broken PCI devices. | |
1030 | * For at least a part of these bugs we need a work-around, so both | |
1031 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1032 | * fixup hooks to be called for particular buggy devices. | |
1033 | */ | |
1034 | ||
1035 | struct pci_fixup { | |
1036 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1037 | void (*hook)(struct pci_dev *dev); | |
1038 | }; | |
1039 | ||
1040 | enum pci_fixup_pass { | |
1041 | pci_fixup_early, /* Before probing BARs */ | |
1042 | pci_fixup_header, /* After reading configuration header */ | |
1043 | pci_fixup_final, /* Final phase of device fixups */ | |
1044 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1045 | pci_fixup_resume, /* pci_device_resume() */ |
1046 | pci_fixup_suspend, /* pci_device_suspend */ | |
1047 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1048 | }; |
1049 | ||
1050 | /* Anonymous variables would be nice... */ | |
1051 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1052 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1053 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1054 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1055 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1056 | vendor##device##hook, vendor, device, hook) | |
1057 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1058 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1059 | vendor##device##hook, vendor, device, hook) | |
1060 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1061 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1062 | vendor##device##hook, vendor, device, hook) | |
1063 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1064 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1065 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1066 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1067 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1068 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1069 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1070 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1071 | resume_early##vendor##device##hook, vendor, device, hook) | |
1072 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1073 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1074 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
1075 | |
1076 | ||
1077 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
1078 | ||
05cca6e5 | 1079 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1080 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1081 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1082 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1083 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1084 | const char *name); | |
ec04b075 | 1085 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1086 | |
1da177e4 | 1087 | extern int pci_pci_problems; |
236561e5 | 1088 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1089 | #define PCIPCI_TRITON 2 |
1090 | #define PCIPCI_NATOMA 4 | |
1091 | #define PCIPCI_VIAETBF 8 | |
1092 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1093 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1094 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1095 | |
4516a618 AN |
1096 | extern unsigned long pci_cardbus_io_size; |
1097 | extern unsigned long pci_cardbus_mem_size; | |
1098 | ||
19792a08 AB |
1099 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1100 | void pcibios_disable_device(struct pci_dev *dev); | |
1101 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1102 | enum pcie_reset_state state); | |
575e3348 | 1103 | |
7752d5cf | 1104 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1105 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1106 | extern void __init pci_mmcfg_late_init(void); |
1107 | #else | |
bb63b421 | 1108 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1109 | static inline void pci_mmcfg_late_init(void) { } |
1110 | #endif | |
1111 | ||
1da177e4 LT |
1112 | #endif /* __KERNEL__ */ |
1113 | #endif /* LINUX_PCI_H */ |