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[PATCH] 64bit resource: change pci core and arch code to use resource_size_t
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4
LT		 22
23/* Include the ID list */
1da177e4
LT		 24#include <linux/pci_ids.h>
25
26/*
27 * The PCI interface treats multi-function devices as independent
28 * devices. The slot/function address of each device is encoded
29 * in a single byte as follows:
30 *
31 * 7:3 = slot
32 * 2:0 = function
33 */
34#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
35#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
36#define PCI_FUNC(devfn) ((devfn) & 0x07)
37
38/* Ioctls for /proc/bus/pci/X/Y nodes. */
39#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
40#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
41#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
42#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
43#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
44
45#ifdef __KERNEL__
46
778382e0
DW		 47#include <linux/mod_devicetable.h>
48
1da177e4 49#include <linux/types.h>
1da177e4
LT		 50#include <linux/ioport.h>
51#include <linux/list.h>
52#include <linux/errno.h>
53#include <linux/device.h>
54
55/* File state for mmap()s on /proc/bus/pci/X/Y */
56enum pci_mmap_state {
57 pci_mmap_io,
58 pci_mmap_mem
59};
60
61/* This defines the direction arg to the DMA mapping routines. */
62#define PCI_DMA_BIDIRECTIONAL 0
63#define PCI_DMA_TODEVICE 1
64#define PCI_DMA_FROMDEVICE 2
65#define PCI_DMA_NONE 3
66
67#define DEVICE_COUNT_COMPATIBLE 4
68#define DEVICE_COUNT_RESOURCE 12
69
70typedef int __bitwise pci_power_t;
71
4352dfd5
GKH		 72#define PCI_D0 ((pci_power_t __force) 0)
73#define PCI_D1 ((pci_power_t __force) 1)
74#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 75#define PCI_D3hot ((pci_power_t __force) 3)
76#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 77#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 78#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 79
392a1ce7 80/** The pci_channel state describes connectivity between the CPU and
81 * the pci device. If some PCI bus between here and the pci device
82 * has crashed or locked up, this info is reflected here.
83 */
84typedef unsigned int __bitwise pci_channel_state_t;
85
86enum pci_channel_state {
87 /* I/O channel is in normal state */
88 pci_channel_io_normal = (__force pci_channel_state_t) 1,
89
90 /* I/O to channel is blocked */
91 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
92
93 /* PCI card is dead */
94 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
95};
96
6e325a62
MT		 97typedef unsigned short __bitwise pci_bus_flags_t;
98enum pci_bus_flags {
e778272d 99 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 100};
101
41017f0c
SL		 102struct pci_cap_saved_state {
103 struct hlist_node next;
104 char cap_nr;
105 u32 data[0];
106};
107
1da177e4
LT		 108/*
109 * The pci_dev structure is used to describe PCI devices.
110 */
111struct pci_dev {
112 struct list_head global_list; /* node in list of all PCI devices */
113 struct list_head bus_list; /* node in per-bus list */
114 struct pci_bus *bus; /* bus this device is on */
115 struct pci_bus *subordinate; /* bus this device bridges to */
116
117 void *sysdata; /* hook for sys-specific extension */
118 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
119
120 unsigned int devfn; /* encoded device & function index */
121 unsigned short vendor;
122 unsigned short device;
123 unsigned short subsystem_vendor;
124 unsigned short subsystem_device;
125 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
126 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
127 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 128 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 129
130 struct pci_driver *driver; /* which driver has allocated this device */
131 u64 dma_mask; /* Mask of the bits of bus address this
132 device implements. Normally this is
133 0xffffffff. You only need to change
134 this if your device has broken DMA
135 or supports 64-bit transfers. */
136
137 pci_power_t current_state; /* Current operating state. In ACPI-speak,
138 this is D0-D3, D0 being fully functional,
139 and D3 being off. */
140
392a1ce7 141 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 142 struct device dev; /* Generic device interface */
143
144 /* device is compatible with these IDs */
145 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
146 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
147
148 int cfg_size; /* Size of configuration space */
149
150 /*
151 * Instead of touching interrupt line and base address registers
152 * directly, use the values stored here. They might be different!
153 */
154 unsigned int irq;
155 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
156
157 /* These fields are used by common fixups */
158 unsigned int transparent:1; /* Transparent PCI bridge */
159 unsigned int multifunction:1;/* Part of multi-function device */
160 /* keep track of device state */
161 unsigned int is_enabled:1; /* pci_enable_device has been called */
162 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 163 unsigned int no_msi:1; /* device may not use msi */
e04b0ea2 164 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 165 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 166 unsigned int msi_enabled:1;
167 unsigned int msix_enabled:1;
4602b88d 168
1da177e4 169 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 170 struct hlist_head saved_cap_space;
1da177e4
LT		 171 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
172 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
173 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
1da177e4
LT		 174};
175
176#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
177#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
178#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
179#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
180
41017f0c
SL		 181static inline struct pci_cap_saved_state *pci_find_saved_cap(
182 struct pci_dev *pci_dev,char cap)
183{
184 struct pci_cap_saved_state *tmp;
185 struct hlist_node *pos;
186
187 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
188 if (tmp->cap_nr == cap)
189 return tmp;
190 }
191 return NULL;
192}
193
194static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
195 struct pci_cap_saved_state *new_cap)
196{
197 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
198}
199
200static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
201{
202 hlist_del(&cap->next);
203}
204
1da177e4
LT		 205/*
206 * For PCI devices, the region numbers are assigned this way:
207 *
208 * 0-5 standard PCI regions
209 * 6 expansion ROM
210 * 7-10 bridges: address space assigned to buses behind the bridge
211 */
212
4352dfd5
GKH		 213#define PCI_ROM_RESOURCE 6
214#define PCI_BRIDGE_RESOURCES 7
215#define PCI_NUM_RESOURCES 11
1da177e4
LT		 216
217#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 218#define PCI_BUS_NUM_RESOURCES 8
1da177e4 219#endif
4352dfd5
GKH		 220
221#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 222
223struct pci_bus {
224 struct list_head node; /* node in list of buses */
225 struct pci_bus *parent; /* parent bus this bridge is on */
226 struct list_head children; /* list of child buses */
227 struct list_head devices; /* list of devices on this bus */
228 struct pci_dev *self; /* bridge device as seen by parent */
229 struct resource *resource[PCI_BUS_NUM_RESOURCES];
230 /* address space routed to this bus */
231
232 struct pci_ops *ops; /* configuration access functions */
233 void *sysdata; /* hook for sys-specific extension */
234 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
235
236 unsigned char number; /* bus number */
237 unsigned char primary; /* number of primary bridge */
238 unsigned char secondary; /* number of secondary bridge */
239 unsigned char subordinate; /* max number of subordinate buses */
240
241 char name[48];
242
243 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 244 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 245 struct device *bridge;
246 struct class_device class_dev;
247 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
248 struct bin_attribute *legacy_mem; /* legacy mem */
249};
250
251#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
252#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
253
254/*
255 * Error values that may be returned by PCI functions.
256 */
257#define PCIBIOS_SUCCESSFUL 0x00
258#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
259#define PCIBIOS_BAD_VENDOR_ID 0x83
260#define PCIBIOS_DEVICE_NOT_FOUND 0x86
261#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
262#define PCIBIOS_SET_FAILED 0x88
263#define PCIBIOS_BUFFER_TOO_SMALL 0x89
264
265/* Low-level architecture-dependent routines */
266
267struct pci_ops {
268 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
269 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
270};
271
272struct pci_raw_ops {
273 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
274 int reg, int len, u32 *val);
275 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
276 int reg, int len, u32 val);
277};
278
279extern struct pci_raw_ops *raw_pci_ops;
280
281struct pci_bus_region {
282 unsigned long start;
283 unsigned long end;
284};
285
286struct pci_dynids {
287 spinlock_t lock; /* protects list, index */
288 struct list_head list; /* for IDs added at runtime */
289 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
290};
291
392a1ce7 292/* ---------------------------------------------------------------- */
293/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
294 * a set fof callbacks in struct pci_error_handlers, then that device driver
295 * will be notified of PCI bus errors, and will be driven to recovery
296 * when an error occurs.
297 */
298
299typedef unsigned int __bitwise pci_ers_result_t;
300
301enum pci_ers_result {
302 /* no result/none/not supported in device driver */
303 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
304
305 /* Device driver can recover without slot reset */
306 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
307
308 /* Device driver wants slot to be reset. */
309 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
310
311 /* Device has completely failed, is unrecoverable */
312 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
313
314 /* Device driver is fully recovered and operational */
315 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
316};
317
318/* PCI bus error event callbacks */
319struct pci_error_handlers
320{
321 /* PCI bus error detected on this device */
322 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
323 enum pci_channel_state error);
324
325 /* MMIO has been re-enabled, but not DMA */
326 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
327
328 /* PCI Express link has been reset */
329 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
330
331 /* PCI slot has been reset */
332 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
333
334 /* Device driver may resume normal operations */
335 void (*resume)(struct pci_dev *dev);
336};
337
338/* ---------------------------------------------------------------- */
339
1da177e4
LT		 340struct module;
341struct pci_driver {
342 struct list_head node;
343 char *name;
1da177e4
LT		 344 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
345 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
346 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
347 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
348 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 349 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 350 void (*shutdown) (struct pci_dev *dev);
1da177e4 351
392a1ce7 352 struct pci_error_handlers *err_handler;
1da177e4
LT		 353 struct device_driver driver;
354 struct pci_dynids dynids;
355};
356
357#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
358
359/**
360 * PCI_DEVICE - macro used to describe a specific pci device
361 * @vend: the 16 bit PCI Vendor ID
362 * @dev: the 16 bit PCI Device ID
363 *
364 * This macro is used to create a struct pci_device_id that matches a
365 * specific device. The subvendor and subdevice fields will be set to
366 * PCI_ANY_ID.
367 */
368#define PCI_DEVICE(vend,dev) \
369 .vendor = (vend), .device = (dev), \
370 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
371
372/**
373 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
374 * @dev_class: the class, subclass, prog-if triple for this device
375 * @dev_class_mask: the class mask for this device
376 *
377 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 378 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 379 * fields will be set to PCI_ANY_ID.
380 */
381#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
382 .class = (dev_class), .class_mask = (dev_class_mask), \
383 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
384 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
385
4352dfd5 386/*
1da177e4
LT		 387 * pci_module_init is obsolete, this stays here till we fix up all usages of it
388 * in the tree.
389 */
390#define pci_module_init pci_register_driver
391
392/* these external functions are only available when PCI support is enabled */
393#ifdef CONFIG_PCI
394
395extern struct bus_type pci_bus_type;
396
397/* Do NOT directly access these two variables, unless you are arch specific pci
398 * code, or pci core code. */
399extern struct list_head pci_root_buses; /* list of all known PCI buses */
400extern struct list_head pci_devices; /* list of all devices */
401
402void pcibios_fixup_bus(struct pci_bus *);
403int pcibios_enable_device(struct pci_dev *, int mask);
404char *pcibios_setup (char *str);
405
406/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 407void pcibios_align_resource(void *, struct resource *, resource_size_t,
408 resource_size_t);
1da177e4
LT		 409void pcibios_update_irq(struct pci_dev *, int irq);
410
411/* Generic PCI functions used internally */
412
413extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 414void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 415struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
416static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
417{
c431ada4
RS		 418 struct pci_bus *root_bus;
419 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
420 if (root_bus)
421 pci_bus_add_devices(root_bus);
422 return root_bus;
1da177e4 423}
cdb9b9f7
PM		 424struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
425struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 426int pci_scan_slot(struct pci_bus *bus, int devfn);
427struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 428void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4
LT		 429unsigned int pci_scan_child_bus(struct pci_bus *bus);
430void pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 431void pci_read_bridge_bases(struct pci_bus *child);
432struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
433int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
434extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
435extern void pci_dev_put(struct pci_dev *dev);
436extern void pci_remove_bus(struct pci_bus *b);
437extern void pci_remove_bus_device(struct pci_dev *dev);
b3743fa4 438void pci_setup_cardbus(struct pci_bus *bus);
1da177e4
LT		 439
440/* Generic PCI functions exported to card drivers */
441
442struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
443struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
444struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
445int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 446int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 447int pci_find_ext_capability (struct pci_dev *dev, int cap);
1da177e4
LT		 448struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
449
450struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
451struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
452 unsigned int ss_vendor, unsigned int ss_device,
453 struct pci_dev *from);
454struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
455struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
456int pci_dev_present(const struct pci_device_id *ids);
457
458int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
459int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
460int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
461int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
462int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
463int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
464
465static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
466{
467 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
468}
469static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
470{
471 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
472}
473static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
474{
475 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
476}
477static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
478{
479 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
480}
481static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
482{
483 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
484}
485static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
486{
487 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
488}
489
9c8550ee
LT		 490int pci_enable_device(struct pci_dev *dev);
491int pci_enable_device_bars(struct pci_dev *dev, int mask);
1da177e4
LT		 492void pci_disable_device(struct pci_dev *dev);
493void pci_set_master(struct pci_dev *dev);
494#define HAVE_PCI_SET_MWI
9c8550ee 495int pci_set_mwi(struct pci_dev *dev);
1da177e4 496void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 497void pci_intx(struct pci_dev *dev, int enable);
9c8550ee
LT		 498int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
499int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 500void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
1da177e4 501int pci_assign_resource(struct pci_dev *dev, int i);
75acfeca 502int pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 503void pci_restore_bars(struct pci_dev *dev);
1da177e4
LT		 504
505/* ROM control related routines */
144a50ea
DJ		 506void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
507void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 508void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
509void pci_remove_rom(struct pci_dev *pdev);
510
511/* Power management related routines */
512int pci_save_state(struct pci_dev *dev);
513int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 514int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
515pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
516int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 517
518/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
519void pci_bus_assign_resources(struct pci_bus *bus);
520void pci_bus_size_bridges(struct pci_bus *bus);
521int pci_claim_resource(struct pci_dev *, int);
522void pci_assign_unassigned_resources(void);
523void pdev_enable_device(struct pci_dev *);
524void pdev_sort_resources(struct pci_dev *, struct resource_list *);
525void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
526 int (*)(struct pci_dev *, u8, u8));
527#define HAVE_PCI_REQ_REGIONS 2
3c990e92 528int pci_request_regions(struct pci_dev *, const char *);
1da177e4 529void pci_release_regions(struct pci_dev *);
3c990e92 530int pci_request_region(struct pci_dev *, int, const char *);
1da177e4
LT		 531void pci_release_region(struct pci_dev *, int);
532
533/* drivers/pci/bus.c */
534int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
e31dd6e4
GKH		 535 resource_size_t size, resource_size_t align,
536 resource_size_t min, unsigned int type_mask,
1da177e4 537 void (*alignf)(void *, struct resource *,
e31dd6e4 538 resource_size_t, resource_size_t),
1da177e4
LT		 539 void *alignf_data);
540void pci_enable_bridges(struct pci_bus *bus);
541
863b18f4
L		 542/* Proper probing supporting hot-pluggable devices */
543int __pci_register_driver(struct pci_driver *, struct module *);
544static inline int pci_register_driver(struct pci_driver *driver)
545{
546 return __pci_register_driver(driver, THIS_MODULE);
547}
548
1da177e4
LT		 549void pci_unregister_driver(struct pci_driver *);
550void pci_remove_behind_bridge(struct pci_dev *);
551struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 552const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
553const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 554int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
555
cecf4864
PM		 556void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
557 void *userdata);
ac7dc65a 558int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 559unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 560
1da177e4
LT		 561/* kmem_cache style wrapper around pci_alloc_consistent() */
562
563#include <linux/dmapool.h>
564
565#define pci_pool dma_pool
566#define pci_pool_create(name, pdev, size, align, allocation) \
567 dma_pool_create(name, &pdev->dev, size, align, allocation)
568#define pci_pool_destroy(pool) dma_pool_destroy(pool)
569#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
570#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
571
e24c2d96
DM		 572enum pci_dma_burst_strategy {
573 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
574 strategy_parameter is N/A */
575 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
576 byte boundaries */
577 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
578 strategy_parameter byte boundaries */
579};
580
1da177e4
LT		 581#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
582extern struct pci_dev *isa_bridge;
583#endif
584
585struct msix_entry {
586 u16 vector; /* kernel uses to write allocated vector */
587 u16 entry; /* driver uses to specify entry, OS writes */
588};
589
590#ifndef CONFIG_PCI_MSI
591static inline void pci_scan_msi_device(struct pci_dev *dev) {}
592static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
593static inline void pci_disable_msi(struct pci_dev *dev) {}
594static inline int pci_enable_msix(struct pci_dev* dev,
595 struct msix_entry *entries, int nvec) {return -1;}
596static inline void pci_disable_msix(struct pci_dev *dev) {}
597static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
598#else
599extern void pci_scan_msi_device(struct pci_dev *dev);
600extern int pci_enable_msi(struct pci_dev *dev);
601extern void pci_disable_msi(struct pci_dev *dev);
602extern int pci_enable_msix(struct pci_dev* dev,
603 struct msix_entry *entries, int nvec);
604extern void pci_disable_msix(struct pci_dev *dev);
605extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
606#endif
607
e04b0ea2
BK		 608extern void pci_block_user_cfg_access(struct pci_dev *dev);
609extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
610
4352dfd5
GKH		 611/*
612 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
613 * a PCI domain is defined to be a set of PCI busses which share
614 * configuration space.
615 */
616#ifndef CONFIG_PCI_DOMAINS
617static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
618static inline int pci_proc_domain(struct pci_bus *bus)
619{
620 return 0;
621}
622#endif
1da177e4 623
4352dfd5 624#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 625
626/*
627 * If the system does not have PCI, clearly these return errors. Define
628 * these as simple inline functions to avoid hair in drivers.
629 */
630
1da177e4
LT		 631#define _PCI_NOP(o,s,t) \
632 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
633 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
634#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
635 _PCI_NOP(o,word,u16 x) \
636 _PCI_NOP(o,dword,u32 x)
637_PCI_NOP_ALL(read, *)
638_PCI_NOP_ALL(write,)
639
640static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
641{ return NULL; }
642
643static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
644{ return NULL; }
645
646static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
647{ return NULL; }
648
649static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
650unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
651{ return NULL; }
652
653static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
654{ return NULL; }
655
656#define pci_dev_present(ids) (0)
657#define pci_dev_put(dev) do { } while (0)
658
659static inline void pci_set_master(struct pci_dev *dev) { }
660static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
661static inline void pci_disable_device(struct pci_dev *dev) { }
662static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 663static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 664static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 665static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
666static inline void pci_unregister_driver(struct pci_driver *drv) { }
667static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 668static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 669static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 670static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
671
672/* Power management related routines */
673static inline int pci_save_state(struct pci_dev *dev) { return 0; }
674static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
675static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 676static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 677static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
678
679#define isa_bridge ((struct pci_dev *)NULL)
680
a46e8126
KG		 681#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
682
e04b0ea2
BK		 683static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
684static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
685
4352dfd5 686#endif /* CONFIG_PCI */
1da177e4 687
4352dfd5
GKH		 688/* Include architecture-dependent settings and functions */
689
690#include <asm/pci.h>
1da177e4
LT		 691
692/* these helpers provide future and backwards compatibility
693 * for accessing popular PCI BAR info */
694#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
695#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
696#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
697#define pci_resource_len(dev,bar) \
698 ((pci_resource_start((dev),(bar)) == 0 && \
699 pci_resource_end((dev),(bar)) == \
700 pci_resource_start((dev),(bar))) ? 0 : \
701 \
702 (pci_resource_end((dev),(bar)) - \
703 pci_resource_start((dev),(bar)) + 1))
704
705/* Similar to the helpers above, these manipulate per-pci_dev
706 * driver-specific data. They are really just a wrapper around
707 * the generic device structure functions of these calls.
708 */
709static inline void *pci_get_drvdata (struct pci_dev *pdev)
710{
711 return dev_get_drvdata(&pdev->dev);
712}
713
714static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
715{
716 dev_set_drvdata(&pdev->dev, data);
717}
718
719/* If you want to know what to call your pci_dev, ask this function.
720 * Again, it's a wrapper around the generic device.
721 */
722static inline char *pci_name(struct pci_dev *pdev)
723{
724 return pdev->dev.bus_id;
725}
726
2311b1f2
ME		 727
728/* Some archs don't want to expose struct resource to userland as-is
729 * in sysfs and /proc
730 */
731#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
732static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 733 const struct resource *rsrc, resource_size_t *start,
734 resource_size_t *end)
2311b1f2
ME		 735{
736 *start = rsrc->start;
737 *end = rsrc->end;
738}
739#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
740
741
1da177e4
LT		 742/*
743 * The world is not perfect and supplies us with broken PCI devices.
744 * For at least a part of these bugs we need a work-around, so both
745 * generic (drivers/pci/quirks.c) and per-architecture code can define
746 * fixup hooks to be called for particular buggy devices.
747 */
748
749struct pci_fixup {
750 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
751 void (*hook)(struct pci_dev *dev);
752};
753
754enum pci_fixup_pass {
755 pci_fixup_early, /* Before probing BARs */
756 pci_fixup_header, /* After reading configuration header */
757 pci_fixup_final, /* Final phase of device fixups */
758 pci_fixup_enable, /* pci_enable_device() time */
759};
760
761/* Anonymous variables would be nice... */
762#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 763 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 764 __attribute__((__section__(#section))) = { vendor, device, hook };
765#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
766 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
767 vendor##device##hook, vendor, device, hook)
768#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
770 vendor##device##hook, vendor, device, hook)
771#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
772 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
773 vendor##device##hook, vendor, device, hook)
774#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
775 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
776 vendor##device##hook, vendor, device, hook)
777
778
779void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
780
781extern int pci_pci_problems;
782#define PCIPCI_FAIL 1
783#define PCIPCI_TRITON 2
784#define PCIPCI_NATOMA 4
785#define PCIPCI_VIAETBF 8
786#define PCIPCI_VSFX 16
787#define PCIPCI_ALIMAGIK 32
788
789#endif /* __KERNEL__ */
790#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)