Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
64c7f63c | 21 | #include <linux/io.h> |
1da177e4 | 22 | |
1da177e4 LT |
23 | /* |
24 | * The PCI interface treats multi-function devices as independent | |
25 | * devices. The slot/function address of each device is encoded | |
26 | * in a single byte as follows: | |
27 | * | |
28 | * 7:3 = slot | |
29 | * 2:0 = function | |
30 | */ | |
05cca6e5 | 31 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
32 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
33 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
34 | ||
35 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
36 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
37 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
38 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
39 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
40 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
41 | ||
42 | #ifdef __KERNEL__ | |
43 | ||
778382e0 DW |
44 | #include <linux/mod_devicetable.h> |
45 | ||
1da177e4 | 46 | #include <linux/types.h> |
98db6f19 | 47 | #include <linux/init.h> |
1da177e4 LT |
48 | #include <linux/ioport.h> |
49 | #include <linux/list.h> | |
4a7fb636 | 50 | #include <linux/compiler.h> |
1da177e4 | 51 | #include <linux/errno.h> |
f46753c5 | 52 | #include <linux/kobject.h> |
bae94d02 | 53 | #include <asm/atomic.h> |
1da177e4 LT |
54 | #include <linux/device.h> |
55 | ||
7e7a43c3 AB |
56 | /* Include the ID list */ |
57 | #include <linux/pci_ids.h> | |
58 | ||
f46753c5 AC |
59 | /* pci_slot represents a physical slot */ |
60 | struct pci_slot { | |
61 | struct pci_bus *bus; /* The bus this slot is on */ | |
62 | struct list_head list; /* node in list of slots on this bus */ | |
63 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
64 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
65 | struct kobject kobj; | |
66 | }; | |
67 | ||
1da177e4 LT |
68 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
69 | enum pci_mmap_state { | |
70 | pci_mmap_io, | |
71 | pci_mmap_mem | |
72 | }; | |
73 | ||
74 | /* This defines the direction arg to the DMA mapping routines. */ | |
75 | #define PCI_DMA_BIDIRECTIONAL 0 | |
76 | #define PCI_DMA_TODEVICE 1 | |
77 | #define PCI_DMA_FROMDEVICE 2 | |
78 | #define PCI_DMA_NONE 3 | |
79 | ||
1da177e4 LT |
80 | #define DEVICE_COUNT_RESOURCE 12 |
81 | ||
82 | typedef int __bitwise pci_power_t; | |
83 | ||
4352dfd5 GKH |
84 | #define PCI_D0 ((pci_power_t __force) 0) |
85 | #define PCI_D1 ((pci_power_t __force) 1) | |
86 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
87 | #define PCI_D3hot ((pci_power_t __force) 3) |
88 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 89 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 90 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 91 | |
392a1ce7 | 92 | /** The pci_channel state describes connectivity between the CPU and |
93 | * the pci device. If some PCI bus between here and the pci device | |
94 | * has crashed or locked up, this info is reflected here. | |
95 | */ | |
96 | typedef unsigned int __bitwise pci_channel_state_t; | |
97 | ||
98 | enum pci_channel_state { | |
99 | /* I/O channel is in normal state */ | |
100 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
101 | ||
102 | /* I/O to channel is blocked */ | |
103 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
104 | ||
105 | /* PCI card is dead */ | |
106 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
107 | }; | |
108 | ||
f7bdd12d BK |
109 | typedef unsigned int __bitwise pcie_reset_state_t; |
110 | ||
111 | enum pcie_reset_state { | |
112 | /* Reset is NOT asserted (Use to deassert reset) */ | |
113 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
114 | ||
115 | /* Use #PERST to reset PCI-E device */ | |
116 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
117 | ||
118 | /* Use PCI-E Hot Reset to reset device */ | |
119 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
120 | }; | |
121 | ||
ba698ad4 DM |
122 | typedef unsigned short __bitwise pci_dev_flags_t; |
123 | enum pci_dev_flags { | |
124 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
125 | * generation too. | |
126 | */ | |
127 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
128 | /* Device configuration is irrevocably lost if disabled into D3 */ |
129 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
ba698ad4 DM |
130 | }; |
131 | ||
6e325a62 MT |
132 | typedef unsigned short __bitwise pci_bus_flags_t; |
133 | enum pci_bus_flags { | |
d556ad4b PO |
134 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
135 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
136 | }; |
137 | ||
41017f0c SL |
138 | struct pci_cap_saved_state { |
139 | struct hlist_node next; | |
140 | char cap_nr; | |
141 | u32 data[0]; | |
142 | }; | |
143 | ||
7d715a6c | 144 | struct pcie_link_state; |
ee69439c JB |
145 | struct pci_vpd; |
146 | ||
1da177e4 LT |
147 | /* |
148 | * The pci_dev structure is used to describe PCI devices. | |
149 | */ | |
150 | struct pci_dev { | |
1da177e4 LT |
151 | struct list_head bus_list; /* node in per-bus list */ |
152 | struct pci_bus *bus; /* bus this device is on */ | |
153 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
154 | ||
155 | void *sysdata; /* hook for sys-specific extension */ | |
156 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 157 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
158 | |
159 | unsigned int devfn; /* encoded device & function index */ | |
160 | unsigned short vendor; | |
161 | unsigned short device; | |
162 | unsigned short subsystem_vendor; | |
163 | unsigned short subsystem_device; | |
164 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 165 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 166 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 167 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 168 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 169 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
170 | |
171 | struct pci_driver *driver; /* which driver has allocated this device */ | |
172 | u64 dma_mask; /* Mask of the bits of bus address this | |
173 | device implements. Normally this is | |
174 | 0xffffffff. You only need to change | |
175 | this if your device has broken DMA | |
176 | or supports 64-bit transfers. */ | |
177 | ||
4d57cdfa FT |
178 | struct device_dma_parameters dma_parms; |
179 | ||
1da177e4 LT |
180 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
181 | this is D0-D3, D0 being fully functional, | |
182 | and D3 being off. */ | |
337001b6 RW |
183 | int pm_cap; /* PM capability offset in the |
184 | configuration space */ | |
185 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
186 | can be generated */ | |
187 | unsigned int d1_support:1; /* Low power state D1 is supported */ | |
188 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
189 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
1da177e4 | 190 | |
7d715a6c SL |
191 | #ifdef CONFIG_PCIEASPM |
192 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
193 | #endif | |
194 | ||
392a1ce7 | 195 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
196 | struct device dev; /* Generic device interface */ |
197 | ||
1da177e4 LT |
198 | int cfg_size; /* Size of configuration space */ |
199 | ||
200 | /* | |
201 | * Instead of touching interrupt line and base address registers | |
202 | * directly, use the values stored here. They might be different! | |
203 | */ | |
204 | unsigned int irq; | |
205 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
206 | ||
207 | /* These fields are used by common fixups */ | |
208 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
209 | unsigned int multifunction:1;/* Part of multi-function device */ | |
210 | /* keep track of device state */ | |
8a1bc901 | 211 | unsigned int is_added:1; |
1da177e4 | 212 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 213 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 214 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 215 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
99dc804d SL |
216 | unsigned int msi_enabled:1; |
217 | unsigned int msix_enabled:1; | |
58c3a727 | 218 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 219 | unsigned int is_managed:1; |
994a65e2 | 220 | unsigned int is_pcie:1; |
ba698ad4 | 221 | pci_dev_flags_t dev_flags; |
bae94d02 | 222 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 223 | |
1da177e4 | 224 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 225 | struct hlist_head saved_cap_space; |
1da177e4 LT |
226 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
227 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
228 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 229 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 230 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 231 | struct list_head msi_list; |
ded86d8d | 232 | #endif |
94e61088 | 233 | struct pci_vpd *vpd; |
1da177e4 LT |
234 | }; |
235 | ||
65891215 ME |
236 | extern struct pci_dev *alloc_pci_dev(void); |
237 | ||
1da177e4 LT |
238 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
239 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
240 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
241 | ||
a7369f1f LV |
242 | static inline int pci_channel_offline(struct pci_dev *pdev) |
243 | { | |
244 | return (pdev->error_state != pci_channel_io_normal); | |
245 | } | |
246 | ||
41017f0c | 247 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 248 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
249 | { |
250 | struct pci_cap_saved_state *tmp; | |
251 | struct hlist_node *pos; | |
252 | ||
253 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
254 | if (tmp->cap_nr == cap) | |
255 | return tmp; | |
256 | } | |
257 | return NULL; | |
258 | } | |
259 | ||
260 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
261 | struct pci_cap_saved_state *new_cap) | |
262 | { | |
263 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
264 | } | |
265 | ||
1da177e4 LT |
266 | /* |
267 | * For PCI devices, the region numbers are assigned this way: | |
268 | * | |
269 | * 0-5 standard PCI regions | |
270 | * 6 expansion ROM | |
271 | * 7-10 bridges: address space assigned to buses behind the bridge | |
272 | */ | |
273 | ||
4352dfd5 GKH |
274 | #define PCI_ROM_RESOURCE 6 |
275 | #define PCI_BRIDGE_RESOURCES 7 | |
276 | #define PCI_NUM_RESOURCES 11 | |
1da177e4 LT |
277 | |
278 | #ifndef PCI_BUS_NUM_RESOURCES | |
30a18d6c | 279 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 280 | #endif |
4352dfd5 GKH |
281 | |
282 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
283 | |
284 | struct pci_bus { | |
285 | struct list_head node; /* node in list of buses */ | |
286 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
287 | struct list_head children; /* list of child buses */ | |
288 | struct list_head devices; /* list of devices on this bus */ | |
289 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 290 | struct list_head slots; /* list of slots on this bus */ |
1da177e4 LT |
291 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; |
292 | /* address space routed to this bus */ | |
293 | ||
294 | struct pci_ops *ops; /* configuration access functions */ | |
295 | void *sysdata; /* hook for sys-specific extension */ | |
296 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
297 | ||
298 | unsigned char number; /* bus number */ | |
299 | unsigned char primary; /* number of primary bridge */ | |
300 | unsigned char secondary; /* number of secondary bridge */ | |
301 | unsigned char subordinate; /* max number of subordinate buses */ | |
302 | ||
303 | char name[48]; | |
304 | ||
305 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 306 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 307 | struct device *bridge; |
fd7d1ced | 308 | struct device dev; |
1da177e4 LT |
309 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
310 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 311 | unsigned int is_added:1; |
1da177e4 LT |
312 | }; |
313 | ||
314 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 315 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 LT |
316 | |
317 | /* | |
318 | * Error values that may be returned by PCI functions. | |
319 | */ | |
320 | #define PCIBIOS_SUCCESSFUL 0x00 | |
321 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
322 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
323 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
324 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
325 | #define PCIBIOS_SET_FAILED 0x88 | |
326 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
327 | ||
328 | /* Low-level architecture-dependent routines */ | |
329 | ||
330 | struct pci_ops { | |
331 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
332 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
333 | }; | |
334 | ||
b6ce068a MW |
335 | /* |
336 | * ACPI needs to be able to access PCI config space before we've done a | |
337 | * PCI bus scan and created pci_bus structures. | |
338 | */ | |
339 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
340 | unsigned int devfn, int reg, int len, u32 *val); | |
341 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
342 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
343 | |
344 | struct pci_bus_region { | |
c40a22e0 BH |
345 | resource_size_t start; |
346 | resource_size_t end; | |
1da177e4 LT |
347 | }; |
348 | ||
349 | struct pci_dynids { | |
350 | spinlock_t lock; /* protects list, index */ | |
351 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
352 | }; |
353 | ||
392a1ce7 | 354 | /* ---------------------------------------------------------------- */ |
355 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 356 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 357 | * will be notified of PCI bus errors, and will be driven to recovery |
358 | * when an error occurs. | |
359 | */ | |
360 | ||
361 | typedef unsigned int __bitwise pci_ers_result_t; | |
362 | ||
363 | enum pci_ers_result { | |
364 | /* no result/none/not supported in device driver */ | |
365 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
366 | ||
367 | /* Device driver can recover without slot reset */ | |
368 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
369 | ||
370 | /* Device driver wants slot to be reset. */ | |
371 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
372 | ||
373 | /* Device has completely failed, is unrecoverable */ | |
374 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
375 | ||
376 | /* Device driver is fully recovered and operational */ | |
377 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
378 | }; | |
379 | ||
380 | /* PCI bus error event callbacks */ | |
05cca6e5 | 381 | struct pci_error_handlers { |
392a1ce7 | 382 | /* PCI bus error detected on this device */ |
383 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 384 | enum pci_channel_state error); |
392a1ce7 | 385 | |
386 | /* MMIO has been re-enabled, but not DMA */ | |
387 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
388 | ||
389 | /* PCI Express link has been reset */ | |
390 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
391 | ||
392 | /* PCI slot has been reset */ | |
393 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
394 | ||
395 | /* Device driver may resume normal operations */ | |
396 | void (*resume)(struct pci_dev *dev); | |
397 | }; | |
398 | ||
399 | /* ---------------------------------------------------------------- */ | |
400 | ||
1da177e4 LT |
401 | struct module; |
402 | struct pci_driver { | |
403 | struct list_head node; | |
404 | char *name; | |
1da177e4 LT |
405 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
406 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
407 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
408 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
409 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
410 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 411 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 412 | void (*shutdown) (struct pci_dev *dev); |
bbb44d9f | 413 | struct pm_ext_ops *pm; |
392a1ce7 | 414 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
415 | struct device_driver driver; |
416 | struct pci_dynids dynids; | |
417 | }; | |
418 | ||
05cca6e5 | 419 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 420 | |
90a1ba0c | 421 | /** |
9f9351bb | 422 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
423 | * @_table: device table name |
424 | * | |
425 | * This macro is used to create a struct pci_device_id array (a device table) | |
426 | * in a generic manner. | |
427 | */ | |
9f9351bb | 428 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
429 | const struct pci_device_id _table[] __devinitconst |
430 | ||
1da177e4 LT |
431 | /** |
432 | * PCI_DEVICE - macro used to describe a specific pci device | |
433 | * @vend: the 16 bit PCI Vendor ID | |
434 | * @dev: the 16 bit PCI Device ID | |
435 | * | |
436 | * This macro is used to create a struct pci_device_id that matches a | |
437 | * specific device. The subvendor and subdevice fields will be set to | |
438 | * PCI_ANY_ID. | |
439 | */ | |
440 | #define PCI_DEVICE(vend,dev) \ | |
441 | .vendor = (vend), .device = (dev), \ | |
442 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
443 | ||
444 | /** | |
445 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
446 | * @dev_class: the class, subclass, prog-if triple for this device | |
447 | * @dev_class_mask: the class mask for this device | |
448 | * | |
449 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 450 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
451 | * fields will be set to PCI_ANY_ID. |
452 | */ | |
453 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
454 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
455 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
456 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
457 | ||
1597cacb AC |
458 | /** |
459 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
460 | * @vendor: the vendor name |
461 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
462 | * |
463 | * This macro is used to create a struct pci_device_id that matches a | |
464 | * specific PCI device. The subvendor, and subdevice fields will be set | |
465 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
466 | * private data. | |
467 | */ | |
468 | ||
469 | #define PCI_VDEVICE(vendor, device) \ | |
470 | PCI_VENDOR_ID_##vendor, (device), \ | |
471 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
472 | ||
1da177e4 LT |
473 | /* these external functions are only available when PCI support is enabled */ |
474 | #ifdef CONFIG_PCI | |
475 | ||
476 | extern struct bus_type pci_bus_type; | |
477 | ||
478 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
479 | * code, or pci core code. */ | |
480 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
481 | /* Some device drivers need know if pci is initiated */ |
482 | extern int no_pci_devices(void); | |
1da177e4 LT |
483 | |
484 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 485 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 486 | char *pcibios_setup(char *str); |
1da177e4 LT |
487 | |
488 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
489 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
490 | resource_size_t); | |
1da177e4 LT |
491 | void pcibios_update_irq(struct pci_dev *, int irq); |
492 | ||
493 | /* Generic PCI functions used internally */ | |
494 | ||
495 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c431ada4 | 496 | void pci_bus_add_devices(struct pci_bus *bus); |
05cca6e5 GKH |
497 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
498 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 499 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 500 | void *sysdata) |
1da177e4 | 501 | { |
c431ada4 RS |
502 | struct pci_bus *root_bus; |
503 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
504 | if (root_bus) | |
505 | pci_bus_add_devices(root_bus); | |
506 | return root_bus; | |
1da177e4 | 507 | } |
05cca6e5 GKH |
508 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
509 | struct pci_ops *ops, void *sysdata); | |
510 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
511 | int busnr); | |
f46753c5 AC |
512 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
513 | const char *name); | |
514 | void pci_destroy_slot(struct pci_slot *slot); | |
d25b7c8d | 515 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 516 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 517 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 518 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 519 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 520 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 521 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
522 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
523 | struct resource *res); | |
1da177e4 LT |
524 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
525 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); | |
526 | extern void pci_dev_put(struct pci_dev *dev); | |
527 | extern void pci_remove_bus(struct pci_bus *b); | |
528 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 529 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 530 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 531 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
532 | |
533 | /* Generic PCI functions exported to card drivers */ | |
534 | ||
bd3989e0 | 535 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
536 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
537 | unsigned int device, | |
b08508c4 | 538 | struct pci_dev *from); |
05cca6e5 GKH |
539 | struct pci_dev __deprecated *pci_find_slot(unsigned int bus, |
540 | unsigned int devfn); | |
bd3989e0 JG |
541 | #endif /* CONFIG_PCI_LEGACY */ |
542 | ||
05cca6e5 GKH |
543 | int pci_find_capability(struct pci_dev *dev, int cap); |
544 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
545 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
546 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
547 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 548 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 549 | |
d42552c3 AM |
550 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
551 | struct pci_dev *from); | |
05cca6e5 | 552 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 553 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 554 | struct pci_dev *from); |
05cca6e5 GKH |
555 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
556 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); | |
557 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); | |
1da177e4 LT |
558 | int pci_dev_present(const struct pci_device_id *ids); |
559 | ||
05cca6e5 GKH |
560 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
561 | int where, u8 *val); | |
562 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
563 | int where, u16 *val); | |
564 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
565 | int where, u32 *val); | |
566 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
567 | int where, u8 val); | |
568 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
569 | int where, u16 val); | |
570 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
571 | int where, u32 val); | |
1da177e4 LT |
572 | |
573 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
574 | { | |
05cca6e5 | 575 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
576 | } |
577 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
578 | { | |
05cca6e5 | 579 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 580 | } |
05cca6e5 GKH |
581 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
582 | u32 *val) | |
1da177e4 | 583 | { |
05cca6e5 | 584 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
585 | } |
586 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
587 | { | |
05cca6e5 | 588 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
589 | } |
590 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
591 | { | |
05cca6e5 | 592 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 593 | } |
05cca6e5 GKH |
594 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
595 | u32 val) | |
1da177e4 | 596 | { |
05cca6e5 | 597 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
598 | } |
599 | ||
4a7fb636 | 600 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
601 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
602 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 603 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
604 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
605 | void pcim_pin_device(struct pci_dev *pdev); | |
606 | ||
607 | static inline int pci_is_managed(struct pci_dev *pdev) | |
608 | { | |
609 | return pdev->is_managed; | |
610 | } | |
611 | ||
1da177e4 LT |
612 | void pci_disable_device(struct pci_dev *dev); |
613 | void pci_set_master(struct pci_dev *dev); | |
f7bdd12d | 614 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 615 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 616 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 617 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 618 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 619 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 620 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
621 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
622 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 623 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 624 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
625 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
626 | int pcix_get_mmrbc(struct pci_dev *dev); | |
627 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 628 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 629 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
8dd7f803 SY |
630 | int pci_reset_function(struct pci_dev *dev); |
631 | int pci_execute_reset_function(struct pci_dev *dev); | |
064b53db | 632 | void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); |
4a7fb636 | 633 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 634 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
635 | |
636 | /* ROM control related routines */ | |
e416de5e AC |
637 | int pci_enable_rom(struct pci_dev *pdev); |
638 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 639 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 640 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
d7ad2254 | 641 | size_t pci_get_rom_size(void __iomem *rom, size_t size); |
1da177e4 LT |
642 | |
643 | /* Power management related routines */ | |
644 | int pci_save_state(struct pci_dev *dev); | |
645 | int pci_restore_state(struct pci_dev *dev); | |
9c8550ee LT |
646 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
647 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 648 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 649 | void pci_pme_active(struct pci_dev *dev, bool enable); |
9c8550ee | 650 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); |
0235c4fc | 651 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 652 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
653 | int pci_prepare_to_sleep(struct pci_dev *dev); |
654 | int pci_back_from_sleep(struct pci_dev *dev); | |
1da177e4 | 655 | |
ce5ccdef | 656 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 657 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
ce5ccdef | 658 | |
1da177e4 LT |
659 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
660 | void pci_bus_assign_resources(struct pci_bus *bus); | |
661 | void pci_bus_size_bridges(struct pci_bus *bus); | |
662 | int pci_claim_resource(struct pci_dev *, int); | |
663 | void pci_assign_unassigned_resources(void); | |
664 | void pdev_enable_device(struct pci_dev *); | |
665 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 666 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
667 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
668 | int (*)(struct pci_dev *, u8, u8)); | |
669 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 670 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
1da177e4 | 671 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 672 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 673 | void pci_release_region(struct pci_dev *, int); |
c87deff7 HS |
674 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
675 | void pci_release_selected_regions(struct pci_dev *, int); | |
1da177e4 LT |
676 | |
677 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
678 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
679 | struct resource *res, resource_size_t size, | |
680 | resource_size_t align, resource_size_t min, | |
681 | unsigned int type_mask, | |
682 | void (*alignf)(void *, struct resource *, | |
683 | resource_size_t, resource_size_t), | |
684 | void *alignf_data); | |
1da177e4 LT |
685 | void pci_enable_bridges(struct pci_bus *bus); |
686 | ||
863b18f4 | 687 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
688 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
689 | const char *mod_name); | |
bba81165 AM |
690 | |
691 | /* | |
692 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
693 | */ | |
694 | #define pci_register_driver(driver) \ | |
695 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 696 | |
05cca6e5 GKH |
697 | void pci_unregister_driver(struct pci_driver *dev); |
698 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
699 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
700 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
701 | struct pci_dev *dev); | |
702 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
703 | int pass); | |
1da177e4 | 704 | |
cecf4864 PM |
705 | void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), |
706 | void *userdata); | |
70b9f7dc | 707 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 708 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 709 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 710 | |
1da177e4 LT |
711 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
712 | ||
713 | #include <linux/dmapool.h> | |
714 | ||
715 | #define pci_pool dma_pool | |
716 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
717 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
718 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
719 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
720 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
721 | ||
e24c2d96 DM |
722 | enum pci_dma_burst_strategy { |
723 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
724 | strategy_parameter is N/A */ | |
725 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
726 | byte boundaries */ | |
727 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
728 | strategy_parameter byte boundaries */ | |
729 | }; | |
730 | ||
1da177e4 | 731 | struct msix_entry { |
16dbef4a | 732 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
733 | u16 entry; /* driver uses to specify entry, OS writes */ |
734 | }; | |
735 | ||
0366f8f7 | 736 | |
1da177e4 | 737 | #ifndef CONFIG_PCI_MSI |
05cca6e5 GKH |
738 | static inline int pci_enable_msi(struct pci_dev *dev) |
739 | { | |
740 | return -1; | |
741 | } | |
742 | ||
d52877c7 YL |
743 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
744 | { } | |
05cca6e5 GKH |
745 | static inline void pci_disable_msi(struct pci_dev *dev) |
746 | { } | |
747 | ||
748 | static inline int pci_enable_msix(struct pci_dev *dev, | |
749 | struct msix_entry *entries, int nvec) | |
750 | { | |
751 | return -1; | |
752 | } | |
753 | ||
d52877c7 YL |
754 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
755 | { } | |
05cca6e5 GKH |
756 | static inline void pci_disable_msix(struct pci_dev *dev) |
757 | { } | |
758 | ||
759 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
760 | { } | |
761 | ||
762 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
763 | { } | |
1da177e4 | 764 | #else |
1da177e4 | 765 | extern int pci_enable_msi(struct pci_dev *dev); |
d52877c7 | 766 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 767 | extern void pci_disable_msi(struct pci_dev *dev); |
05cca6e5 | 768 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 769 | struct msix_entry *entries, int nvec); |
d52877c7 | 770 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
771 | extern void pci_disable_msix(struct pci_dev *dev); |
772 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 773 | extern void pci_restore_msi_state(struct pci_dev *dev); |
1da177e4 LT |
774 | #endif |
775 | ||
8b955b0d | 776 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
777 | /* The functions a driver should call */ |
778 | int ht_create_irq(struct pci_dev *dev, int idx); | |
779 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
780 | #endif /* CONFIG_HT_IRQ */ |
781 | ||
e04b0ea2 BK |
782 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
783 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
784 | ||
4352dfd5 GKH |
785 | /* |
786 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
787 | * a PCI domain is defined to be a set of PCI busses which share | |
788 | * configuration space. | |
789 | */ | |
32a2eea7 JG |
790 | #ifdef CONFIG_PCI_DOMAINS |
791 | extern int pci_domains_supported; | |
792 | #else | |
793 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
794 | static inline int pci_domain_nr(struct pci_bus *bus) |
795 | { | |
796 | return 0; | |
797 | } | |
798 | ||
4352dfd5 GKH |
799 | static inline int pci_proc_domain(struct pci_bus *bus) |
800 | { | |
801 | return 0; | |
802 | } | |
32a2eea7 | 803 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 804 | |
4352dfd5 | 805 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
806 | |
807 | /* | |
808 | * If the system does not have PCI, clearly these return errors. Define | |
809 | * these as simple inline functions to avoid hair in drivers. | |
810 | */ | |
811 | ||
05cca6e5 GKH |
812 | #define _PCI_NOP(o, s, t) \ |
813 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
814 | int where, t val) \ | |
1da177e4 | 815 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
816 | |
817 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
818 | _PCI_NOP(o, word, u16 x) \ | |
819 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
820 | _PCI_NOP_ALL(read, *) |
821 | _PCI_NOP_ALL(write,) | |
822 | ||
05cca6e5 GKH |
823 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
824 | unsigned int device, | |
b08508c4 | 825 | struct pci_dev *from) |
05cca6e5 GKH |
826 | { |
827 | return NULL; | |
828 | } | |
1da177e4 | 829 | |
05cca6e5 GKH |
830 | static inline struct pci_dev *pci_find_slot(unsigned int bus, |
831 | unsigned int devfn) | |
832 | { | |
833 | return NULL; | |
834 | } | |
1da177e4 | 835 | |
d42552c3 | 836 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
837 | unsigned int device, |
838 | struct pci_dev *from) | |
839 | { | |
840 | return NULL; | |
841 | } | |
d42552c3 | 842 | |
05cca6e5 GKH |
843 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
844 | unsigned int device, | |
845 | unsigned int ss_vendor, | |
846 | unsigned int ss_device, | |
b08508c4 | 847 | struct pci_dev *from) |
05cca6e5 GKH |
848 | { |
849 | return NULL; | |
850 | } | |
1da177e4 | 851 | |
05cca6e5 GKH |
852 | static inline struct pci_dev *pci_get_class(unsigned int class, |
853 | struct pci_dev *from) | |
854 | { | |
855 | return NULL; | |
856 | } | |
1da177e4 LT |
857 | |
858 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 859 | #define no_pci_devices() (1) |
1da177e4 LT |
860 | #define pci_dev_put(dev) do { } while (0) |
861 | ||
05cca6e5 GKH |
862 | static inline void pci_set_master(struct pci_dev *dev) |
863 | { } | |
864 | ||
865 | static inline int pci_enable_device(struct pci_dev *dev) | |
866 | { | |
867 | return -EIO; | |
868 | } | |
869 | ||
870 | static inline void pci_disable_device(struct pci_dev *dev) | |
871 | { } | |
872 | ||
873 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
874 | { | |
875 | return -EIO; | |
876 | } | |
877 | ||
80be0385 RD |
878 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
879 | { | |
880 | return -EIO; | |
881 | } | |
882 | ||
4d57cdfa FT |
883 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
884 | unsigned int size) | |
885 | { | |
886 | return -EIO; | |
887 | } | |
888 | ||
59fc67de FT |
889 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
890 | unsigned long mask) | |
891 | { | |
892 | return -EIO; | |
893 | } | |
894 | ||
05cca6e5 GKH |
895 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
896 | { | |
897 | return -EBUSY; | |
898 | } | |
899 | ||
900 | static inline int __pci_register_driver(struct pci_driver *drv, | |
901 | struct module *owner) | |
902 | { | |
903 | return 0; | |
904 | } | |
905 | ||
906 | static inline int pci_register_driver(struct pci_driver *drv) | |
907 | { | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
912 | { } | |
913 | ||
914 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
915 | { | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
920 | int cap) | |
921 | { | |
922 | return 0; | |
923 | } | |
924 | ||
925 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
926 | { | |
927 | return 0; | |
928 | } | |
929 | ||
1da177e4 | 930 | /* Power management related routines */ |
05cca6e5 GKH |
931 | static inline int pci_save_state(struct pci_dev *dev) |
932 | { | |
933 | return 0; | |
934 | } | |
935 | ||
936 | static inline int pci_restore_state(struct pci_dev *dev) | |
937 | { | |
938 | return 0; | |
939 | } | |
1da177e4 | 940 | |
05cca6e5 GKH |
941 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
942 | { | |
943 | return 0; | |
944 | } | |
945 | ||
946 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
947 | pm_message_t state) | |
948 | { | |
949 | return PCI_D0; | |
950 | } | |
951 | ||
952 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
953 | int enable) | |
954 | { | |
955 | return 0; | |
956 | } | |
957 | ||
958 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
959 | { | |
960 | return -EIO; | |
961 | } | |
962 | ||
963 | static inline void pci_release_regions(struct pci_dev *dev) | |
964 | { } | |
0da0ead9 | 965 | |
a46e8126 KG |
966 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
967 | ||
05cca6e5 GKH |
968 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
969 | { } | |
970 | ||
971 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
972 | { } | |
e04b0ea2 | 973 | |
d80d0217 RD |
974 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
975 | { return NULL; } | |
976 | ||
977 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
978 | unsigned int devfn) | |
979 | { return NULL; } | |
980 | ||
981 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
982 | unsigned int devfn) | |
983 | { return NULL; } | |
984 | ||
4352dfd5 | 985 | #endif /* CONFIG_PCI */ |
1da177e4 | 986 | |
4352dfd5 GKH |
987 | /* Include architecture-dependent settings and functions */ |
988 | ||
989 | #include <asm/pci.h> | |
1da177e4 LT |
990 | |
991 | /* these helpers provide future and backwards compatibility | |
992 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
993 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
994 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
995 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 996 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
997 | ((pci_resource_start((dev), (bar)) == 0 && \ |
998 | pci_resource_end((dev), (bar)) == \ | |
999 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1000 | \ | |
1001 | (pci_resource_end((dev), (bar)) - \ | |
1002 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1003 | |
1004 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1005 | * driver-specific data. They are really just a wrapper around | |
1006 | * the generic device structure functions of these calls. | |
1007 | */ | |
05cca6e5 | 1008 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1009 | { |
1010 | return dev_get_drvdata(&pdev->dev); | |
1011 | } | |
1012 | ||
05cca6e5 | 1013 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1014 | { |
1015 | dev_set_drvdata(&pdev->dev, data); | |
1016 | } | |
1017 | ||
1018 | /* If you want to know what to call your pci_dev, ask this function. | |
1019 | * Again, it's a wrapper around the generic device. | |
1020 | */ | |
c6c4f070 | 1021 | static inline const char *pci_name(struct pci_dev *pdev) |
1da177e4 | 1022 | { |
c6c4f070 | 1023 | return dev_name(&pdev->dev); |
1da177e4 LT |
1024 | } |
1025 | ||
2311b1f2 ME |
1026 | |
1027 | /* Some archs don't want to expose struct resource to userland as-is | |
1028 | * in sysfs and /proc | |
1029 | */ | |
1030 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1031 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1032 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1033 | resource_size_t *end) |
2311b1f2 ME |
1034 | { |
1035 | *start = rsrc->start; | |
1036 | *end = rsrc->end; | |
1037 | } | |
1038 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1039 | ||
1040 | ||
1da177e4 LT |
1041 | /* |
1042 | * The world is not perfect and supplies us with broken PCI devices. | |
1043 | * For at least a part of these bugs we need a work-around, so both | |
1044 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1045 | * fixup hooks to be called for particular buggy devices. | |
1046 | */ | |
1047 | ||
1048 | struct pci_fixup { | |
1049 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1050 | void (*hook)(struct pci_dev *dev); | |
1051 | }; | |
1052 | ||
1053 | enum pci_fixup_pass { | |
1054 | pci_fixup_early, /* Before probing BARs */ | |
1055 | pci_fixup_header, /* After reading configuration header */ | |
1056 | pci_fixup_final, /* Final phase of device fixups */ | |
1057 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1058 | pci_fixup_resume, /* pci_device_resume() */ |
1059 | pci_fixup_suspend, /* pci_device_suspend */ | |
1060 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1061 | }; |
1062 | ||
1063 | /* Anonymous variables would be nice... */ | |
1064 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1065 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1066 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1067 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1068 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1069 | vendor##device##hook, vendor, device, hook) | |
1070 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1071 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1072 | vendor##device##hook, vendor, device, hook) | |
1073 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1074 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1075 | vendor##device##hook, vendor, device, hook) | |
1076 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1077 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1078 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1079 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1080 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1081 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1082 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1083 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1084 | resume_early##vendor##device##hook, vendor, device, hook) | |
1085 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1086 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1087 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
1088 | |
1089 | ||
1090 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
1091 | ||
05cca6e5 | 1092 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1093 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1094 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1095 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1096 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1097 | const char *name); | |
ec04b075 | 1098 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1099 | |
1da177e4 | 1100 | extern int pci_pci_problems; |
236561e5 | 1101 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1102 | #define PCIPCI_TRITON 2 |
1103 | #define PCIPCI_NATOMA 4 | |
1104 | #define PCIPCI_VIAETBF 8 | |
1105 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1106 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1107 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1108 | |
4516a618 AN |
1109 | extern unsigned long pci_cardbus_io_size; |
1110 | extern unsigned long pci_cardbus_mem_size; | |
1111 | ||
19792a08 AB |
1112 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1113 | void pcibios_disable_device(struct pci_dev *dev); | |
1114 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1115 | enum pcie_reset_state state); | |
575e3348 | 1116 | |
7752d5cf | 1117 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1118 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1119 | extern void __init pci_mmcfg_late_init(void); |
1120 | #else | |
bb63b421 | 1121 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1122 | static inline void pci_mmcfg_late_init(void) { } |
1123 | #endif | |
1124 | ||
96499871 | 1125 | #ifdef CONFIG_HAS_IOMEM |
aa42d7c6 AV |
1126 | static inline void * pci_ioremap_bar(struct pci_dev *pdev, int bar) |
1127 | { | |
1128 | /* | |
1129 | * Make sure the BAR is actually a memory resource, not an IO resource | |
1130 | */ | |
1131 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1132 | WARN_ON(1); | |
1133 | return NULL; | |
1134 | } | |
1135 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
1136 | pci_resource_len(pdev, bar)); | |
1137 | } | |
96499871 | 1138 | #endif |
aa42d7c6 | 1139 | |
1da177e4 LT |
1140 | #endif /* __KERNEL__ */ |
1141 | #endif /* LINUX_PCI_H */ |