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PCI/DPC: Expose dpc_process_error(), dpc_reset_link() for use by EDR
[linux-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
7ce2e76a
KW		 9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
1da177e4
LT		 14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
7ce2e76a 20 * PCI Express Specification
1da177e4
LT		 21 * PCI System Design Guide
22 */
1da177e4
LT		 23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
1da177e4 26
778382e0
DW		 27#include <linux/mod_devicetable.h>
28
1da177e4 29#include <linux/types.h>
98db6f19 30#include <linux/init.h>
1da177e4
LT		 31#include <linux/ioport.h>
32#include <linux/list.h>
4a7fb636 33#include <linux/compiler.h>
1da177e4 34#include <linux/errno.h>
f46753c5 35#include <linux/kobject.h>
60063497 36#include <linux/atomic.h>
1da177e4 37#include <linux/device.h>
704e8953 38#include <linux/interrupt.h>
1388cc96 39#include <linux/io.h>
14d76b68 40#include <linux/resource_ext.h>
607ca46e 41#include <uapi/linux/pci.h>
1da177e4 42
7e7a43c3
AB		 43#include <linux/pci_ids.h>
44
85467136
SK		 45/*
46 * The PCI interface treats multi-function devices as independent
47 * devices. The slot/function address of each device is encoded
48 * in a single byte as follows:
49 *
50 * 7:3 = slot
51 * 2:0 = function
f7625980
BH		 52 *
53 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 54 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 55 * the following kernel-only defines are being added here.
85467136 56 */
0aa0f5d1 57#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 58/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
59#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
60
f46753c5
AC		 61/* pci_slot represents a physical slot */
62struct pci_slot {
0aa0f5d1
BH		 63 struct pci_bus *bus; /* Bus this slot is on */
64 struct list_head list; /* Node in list of slots */
65 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
66 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
67 struct kobject kobj;
f46753c5
AC		 68};
69
0ad772ec
AC		 70static inline const char *pci_slot_name(const struct pci_slot *slot)
71{
72 return kobject_name(&slot->kobj);
73}
74
1da177e4
LT		 75/* File state for mmap()s on /proc/bus/pci/X/Y */
76enum pci_mmap_state {
77 pci_mmap_io,
78 pci_mmap_mem
79};
80
0aa0f5d1 81/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 82enum {
83 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCES,
c9c13ba4 85 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
fde09c6d
YZ		 86
87 /* #6: expansion ROM resource */
88 PCI_ROM_RESOURCE,
89
0aa0f5d1 90 /* Device-specific resources */
d1b054da
YZ		 91#ifdef CONFIG_PCI_IOV
92 PCI_IOV_RESOURCES,
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94#endif
95
0aa0f5d1 96 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 97#define PCI_BRIDGE_RESOURCE_NUM 4
98
99 PCI_BRIDGE_RESOURCES,
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
102
0aa0f5d1 103 /* Total resources associated with a PCI device */
fde09c6d
YZ		 104 PCI_NUM_RESOURCES,
105
0aa0f5d1 106 /* Preserve this for compatibility */
cda57bf9 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 108};
1da177e4 109
b352baf1
PB		 110/**
111 * enum pci_interrupt_pin - PCI INTx interrupt values
112 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
113 * @PCI_INTERRUPT_INTA: PCI INTA pin
114 * @PCI_INTERRUPT_INTB: PCI INTB pin
115 * @PCI_INTERRUPT_INTC: PCI INTC pin
116 * @PCI_INTERRUPT_INTD: PCI INTD pin
117 *
118 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
119 * PCI_INTERRUPT_PIN register.
120 */
121enum pci_interrupt_pin {
122 PCI_INTERRUPT_UNKNOWN,
123 PCI_INTERRUPT_INTA,
124 PCI_INTERRUPT_INTB,
125 PCI_INTERRUPT_INTC,
126 PCI_INTERRUPT_INTD,
127};
128
129/* The number of legacy PCI INTx interrupts */
130#define PCI_NUM_INTX 4
131
224abb67
BH		 132/*
133 * pci_power_t values must match the bits in the Capabilities PME_Support
134 * and Control/Status PowerState fields in the Power Management capability.
135 */
1da177e4
LT		 136typedef int __bitwise pci_power_t;
137
4352dfd5
GKH		 138#define PCI_D0 ((pci_power_t __force) 0)
139#define PCI_D1 ((pci_power_t __force) 1)
140#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 141#define PCI_D3hot ((pci_power_t __force) 3)
142#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 143#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 144#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 145
00240c38
AS		 146/* Remember to update this when the list above changes! */
147extern const char *pci_power_names[];
148
149static inline const char *pci_power_name(pci_power_t state)
150{
9661e783 151 return pci_power_names[1 + (__force int) state];
00240c38
AS		 152}
153
0aa0f5d1 154/**
229b4e07
CD		 155 * typedef pci_channel_state_t
156 *
0aa0f5d1
BH		 157 * The pci_channel state describes connectivity between the CPU and
158 * the PCI device. If some PCI bus between here and the PCI device
159 * has crashed or locked up, this info is reflected here.
392a1ce7 160 */
161typedef unsigned int __bitwise pci_channel_state_t;
162
163enum pci_channel_state {
164 /* I/O channel is in normal state */
165 pci_channel_io_normal = (__force pci_channel_state_t) 1,
166
167 /* I/O to channel is blocked */
168 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
169
170 /* PCI card is dead */
171 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
172};
173
f7bdd12d
BK		 174typedef unsigned int __bitwise pcie_reset_state_t;
175
176enum pcie_reset_state {
177 /* Reset is NOT asserted (Use to deassert reset) */
178 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
179
f7625980 180 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 181 pcie_warm_reset = (__force pcie_reset_state_t) 2,
182
f7625980 183 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 184 pcie_hot_reset = (__force pcie_reset_state_t) 3
185};
186
ba698ad4
DM		 187typedef unsigned short __bitwise pci_dev_flags_t;
188enum pci_dev_flags {
0aa0f5d1 189 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 191 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 193 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 205 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 209 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 211};
212
e1d3a908
SA		 213enum pci_irq_reroute_variant {
214 INTEL_IRQ_REROUTE_VARIANT = 1,
215 MAX_IRQ_REROUTE_VARIANTS = 3
216};
217
6e325a62
MT		 218typedef unsigned short __bitwise pci_bus_flags_t;
219enum pci_bus_flags {
032c3d86
JD		 220 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
221 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 223 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 224};
225
0aa0f5d1 226/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 227enum pcie_link_width {
228 PCIE_LNK_WIDTH_RESRV = 0x00,
229 PCIE_LNK_X1 = 0x01,
230 PCIE_LNK_X2 = 0x02,
231 PCIE_LNK_X4 = 0x04,
232 PCIE_LNK_X8 = 0x08,
0aa0f5d1 233 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 234 PCIE_LNK_X16 = 0x10,
235 PCIE_LNK_X32 = 0x20,
0aa0f5d1 236 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 237};
238
536c8cb4
MW		 239/* Based on the PCI Hotplug Spec, but some values are made up by us */
240enum pci_bus_speed {
241 PCI_SPEED_33MHz = 0x00,
242 PCI_SPEED_66MHz = 0x01,
243 PCI_SPEED_66MHz_PCIX = 0x02,
244 PCI_SPEED_100MHz_PCIX = 0x03,
245 PCI_SPEED_133MHz_PCIX = 0x04,
246 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
247 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
248 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
249 PCI_SPEED_66MHz_PCIX_266 = 0x09,
250 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
251 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 252 AGP_UNKNOWN = 0x0c,
253 AGP_1X = 0x0d,
254 AGP_2X = 0x0e,
255 AGP_4X = 0x0f,
256 AGP_8X = 0x10,
536c8cb4
MW		 257 PCI_SPEED_66MHz_PCIX_533 = 0x11,
258 PCI_SPEED_100MHz_PCIX_533 = 0x12,
259 PCI_SPEED_133MHz_PCIX_533 = 0x13,
260 PCIE_SPEED_2_5GT = 0x14,
261 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 262 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 263 PCIE_SPEED_16_0GT = 0x17,
de76cda2 264 PCIE_SPEED_32_0GT = 0x18,
536c8cb4
MW		 265 PCI_SPEED_UNKNOWN = 0xff,
266};
267
576c7218
AD		 268enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
269enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
270
24a4742f 271struct pci_cap_saved_data {
0aa0f5d1
BH		 272 u16 cap_nr;
273 bool cap_extended;
274 unsigned int size;
275 u32 data[0];
41017f0c
SL		 276};
277
24a4742f 278struct pci_cap_saved_state {
0aa0f5d1
BH		 279 struct hlist_node next;
280 struct pci_cap_saved_data cap;
24a4742f
AW		 281};
282
402723ad 283struct irq_affinity;
7d715a6c 284struct pcie_link_state;
ee69439c 285struct pci_vpd;
d1b054da 286struct pci_sriov;
52916982 287struct pci_p2pdma;
ee69439c 288
0aa0f5d1 289/* The pci_dev structure describes PCI devices */
1da177e4 290struct pci_dev {
0aa0f5d1
BH		 291 struct list_head bus_list; /* Node in per-bus list */
292 struct pci_bus *bus; /* Bus this device is on */
293 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 294
0aa0f5d1
BH		 295 void *sysdata; /* Hook for sys-specific extension */
296 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 297 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 298
0aa0f5d1 299 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 300 unsigned short vendor;
301 unsigned short device;
302 unsigned short subsystem_vendor;
303 unsigned short subsystem_device;
304 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 305 u8 revision; /* PCI revision, low byte of class word */
1da177e4 306 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 307#ifdef CONFIG_PCIEAER
308 u16 aer_cap; /* AER capability offset */
db89ccbe 309 struct aer_stats *aer_stats; /* AER stats for this device */
66b80809 310#endif
f7625980 311 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 312 u8 msi_cap; /* MSI capability offset */
313 u8 msix_cap; /* MSI-X capability offset */
f7625980 314 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 315 u8 rom_base_reg; /* Config register controlling ROM */
316 u8 pin; /* Interrupt pin this device uses */
317 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
318 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 319
0aa0f5d1 320 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 321 u64 dma_mask; /* Mask of the bits of bus address this
322 device implements. Normally this is
323 0xffffffff. You only need to change
324 this if your device has broken DMA
325 or supports 64-bit transfers. */
326
4d57cdfa
FT		 327 struct device_dma_parameters dma_parms;
328
0aa0f5d1
BH		 329 pci_power_t current_state; /* Current operating state. In ACPI,
330 this is D0-D3, D0 being fully
331 functional, and D3 being off. */
d6112f8d 332 unsigned int imm_ready:1; /* Supports Immediate Readiness */
703860ed 333 u8 pm_cap; /* PM capability offset */
337001b6
RW		 334 unsigned int pme_support:5; /* Bitmask of states from which PME#
335 can be generated */
379021d5 336 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 337 unsigned int d1_support:1; /* Low power state D1 is supported */
338 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 339 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
340 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 341 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 342 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 343 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
344 decoding during BAR sizing */
e80bb09d 345 unsigned int wakeup_prepared:1;
0aa0f5d1 346 unsigned int runtime_d3cold:1; /* Whether go through runtime
448bd857
HY		 347 D3cold, not set for devices
348 powered on/off by the
349 corresponding bridge */
d491f2b7 350 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 351 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 352 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
353 controlled exclusively by
354 user sysfs */
4ec73791
SM		 355 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
356 bit manually */
1ae861e6 357 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 358 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 359
7d715a6c 360#ifdef CONFIG_PCIEASPM
f7625980 361 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 362 unsigned int ltr_path:1; /* Latency Tolerance Reporting
363 supported from root to here */
7d715a6c 364#endif
7ce3f912 365 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 366
0aa0f5d1
BH		 367 pci_channel_state_t error_state; /* Current connectivity state */
368 struct device dev; /* Generic device interface */
1da177e4 369
0aa0f5d1 370 int cfg_size; /* Size of config space */
1da177e4
LT		 371
372 /*
373 * Instead of touching interrupt line and base address registers
374 * directly, use the values stored here. They might be different!
375 */
376 unsigned int irq;
377 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
378
0aa0f5d1
BH		 379 bool match_driver; /* Skip attaching driver */
380
381 unsigned int transparent:1; /* Subtractive decode bridge */
51c48b31
BH		 382 unsigned int io_window:1; /* Bridge has I/O window */
383 unsigned int pref_window:1; /* Bridge has pref mem window */
384 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
0aa0f5d1
BH		 385 unsigned int multifunction:1; /* Multi-function device */
386
0aa0f5d1
BH		 387 unsigned int is_busmaster:1; /* Is busmaster */
388 unsigned int no_msi:1; /* May not use MSI */
f6b6aefe 389 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
0aa0f5d1
BH		 390 unsigned int block_cfg_access:1; /* Config space access blocked */
391 unsigned int broken_parity_status:1; /* Generates false positive parity */
392 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 393 unsigned int msi_enabled:1;
99dc804d 394 unsigned int msix_enabled:1;
0aa0f5d1
BH		 395 unsigned int ari_enabled:1; /* ARI forwarding */
396 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 397 unsigned int pasid_enabled:1; /* Process Address Space ID */
398 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 399 unsigned int is_managed:1;
0aa0f5d1 400 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 401 unsigned int state_saved:1;
d1b054da 402 unsigned int is_physfn:1;
dd7cc44d 403 unsigned int is_virtfn:1;
711d5779 404 unsigned int reset_fn:1;
0aa0f5d1 405 unsigned int is_hotplug_bridge:1;
b03799b0 406 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
0aa0f5d1 407 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
617654aa
MW		 408 /*
409 * Devices marked being untrusted are the ones that can potentially
410 * execute DMA attacks and similar. They are typically connected
411 * through external ports such as Thunderbolt but not limited to
412 * that. When an IOMMU is enabled they should be getting full
413 * mappings to make sure they cannot access arbitrary memory.
414 */
415 unsigned int untrusted:1;
0aa0f5d1 416 unsigned int __aer_firmware_first_valid:1;
affb72c3 417 unsigned int __aer_firmware_first:1;
0aa0f5d1
BH		 418 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
419 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 420 unsigned int irq_managed:1;
0aa0f5d1
BH		 421 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
422 unsigned int is_probed:1; /* Device probing in progress */
f0157160 423 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
aff68a5a 424 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
ba698ad4 425 pci_dev_flags_t dev_flags;
bae94d02 426 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 427
0aa0f5d1 428 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 429 struct hlist_head saved_cap_space;
0aa0f5d1
BH		 430 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
431 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 432 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 433 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 434
d22b3621
BH		 435#ifdef CONFIG_HOTPLUG_PCI_PCIE
436 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
437#endif
9bb04a0c
JY		 438#ifdef CONFIG_PCIE_PTM
439 unsigned int ptm_root:1;
440 unsigned int ptm_enabled:1;
8b2ec318 441 u8 ptm_granularity;
9bb04a0c 442#endif
ded86d8d 443#ifdef CONFIG_PCI_MSI
1c51b50c 444 const struct attribute_group **msi_irq_groups;
ded86d8d 445#endif
94e61088 446 struct pci_vpd *vpd;
be06c1b4
BH		 447#ifdef CONFIG_PCIE_DPC
448 u16 dpc_cap;
449 unsigned int dpc_rp_extensions:1;
450 u8 dpc_rp_log_size;
451#endif
466b3ddf 452#ifdef CONFIG_PCI_ATS
dd7cc44d 453 union {
0aa0f5d1
BH		 454 struct pci_sriov *sriov; /* PF: SR-IOV info */
455 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 456 };
67930995
BH		 457 u16 ats_cap; /* ATS Capability offset */
458 u8 ats_stu; /* ATS Smallest Translation Unit */
4ebeb1ec
CT		 459#endif
460#ifdef CONFIG_PCI_PRI
c065190b 461 u16 pri_cap; /* PRI Capability offset */
4ebeb1ec 462 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
e5adf79a 463 unsigned int pasid_required:1; /* PRG Response PASID Required */
4ebeb1ec
CT		 464#endif
465#ifdef CONFIG_PCI_PASID
751035b8 466 u16 pasid_cap; /* PASID Capability offset */
4ebeb1ec 467 u16 pasid_features;
52916982
LG		 468#endif
469#ifdef CONFIG_PCI_P2PDMA
470 struct pci_p2pdma *p2pdma;
d1b054da 471#endif
0aa0f5d1
BH		 472 phys_addr_t rom; /* Physical address if not from BAR */
473 size_t romlen; /* Length if not from BAR */
474 char *driver_override; /* Driver name to force a match */
89ee9f76 475
0aa0f5d1 476 unsigned long priv_flags; /* Private flags for the PCI driver */
1da177e4
LT		 477};
478
dda56549
Y		 479static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
480{
481#ifdef CONFIG_PCI_IOV
482 if (dev->is_virtfn)
483 dev = dev->physfn;
484#endif
dda56549
Y		 485 return dev;
486}
487
3c6e6ae7 488struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 489
1da177e4
LT		 490#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
491#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
492
a7369f1f
LV		 493static inline int pci_channel_offline(struct pci_dev *pdev)
494{
495 return (pdev->error_state != pci_channel_io_normal);
496}
497
5a21d70d 498struct pci_host_bridge {
0aa0f5d1
BH		 499 struct device dev;
500 struct pci_bus *bus; /* Root bus */
501 struct pci_ops *ops;
502 void *sysdata;
503 int busnr;
14d76b68 504 struct list_head windows; /* resource_entry */
e80a91ad 505 struct list_head dma_ranges; /* dma ranges resource list */
0aa0f5d1 506 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 507 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 508 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 509 void *release_data;
37d6a0a6 510 struct msi_controller *msi;
0aa0f5d1
BH		 511 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
512 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48 513 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 514 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 515 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 516 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 517 unsigned int native_ltr:1; /* OS may use PCIe LTR */
a78cf965
BH		 518 unsigned int preserve_config:1; /* Preserve FW resource setup */
519
7c7a0e94
GP		 520 /* Resource alignment requirements */
521 resource_size_t (*align_resource)(struct pci_dev *dev,
522 const struct resource *res,
523 resource_size_t start,
524 resource_size_t size,
525 resource_size_t align);
0aa0f5d1 526 unsigned long private[0] ____cacheline_aligned;
5a21d70d 527};
41017f0c 528
7b543663 529#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 530
59094065
TR		 531static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
532{
533 return (void *)bridge->private;
534}
535
536static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
537{
538 return container_of(priv, struct pci_host_bridge, private);
539}
540
a52d1443 541struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 542struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
543 size_t priv);
dff79b91 544void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 545struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
546
4fa2649a 547void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 548 void (*release_fn)(struct pci_host_bridge *),
549 void *release_data);
7b543663 550
6c0cc950
RW		 551int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
552
2fe2abf8
BH		 553/*
554 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
555 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
556 * buses below host bridges or subtractive decode bridges) go in the list.
557 * Use pci_bus_for_each_resource() to iterate through all the resources.
558 */
559
560/*
561 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
562 * and there's no way to program the bridge with the details of the window.
563 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
564 * decode bit set, because they are explicit and can be programmed with _SRS.
565 */
566#define PCI_SUBTRACTIVE_DECODE 0x1
567
568struct pci_bus_resource {
0aa0f5d1
BH		 569 struct list_head list;
570 struct resource *res;
571 unsigned int flags;
2fe2abf8 572};
4352dfd5
GKH		 573
574#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 575
576struct pci_bus {
0aa0f5d1
BH		 577 struct list_head node; /* Node in list of buses */
578 struct pci_bus *parent; /* Parent bus this bridge is on */
579 struct list_head children; /* List of child buses */
580 struct list_head devices; /* List of devices on this bus */
581 struct pci_dev *self; /* Bridge device as seen by parent */
582 struct list_head slots; /* List of slots on this bus;
67546762 583 protected by pci_slot_mutex */
2fe2abf8 584 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 585 struct list_head resources; /* Address space routed to this bus */
586 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 587
0aa0f5d1 588 struct pci_ops *ops; /* Configuration access functions */
c2791b80 589 struct msi_controller *msi; /* MSI controller */
0aa0f5d1
BH		 590 void *sysdata; /* Hook for sys-specific extension */
591 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 592
0aa0f5d1
BH		 593 unsigned char number; /* Bus number */
594 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 595 unsigned char max_bus_speed; /* enum pci_bus_speed */
596 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 597#ifdef CONFIG_PCI_DOMAINS_GENERIC
598 int domain_nr;
599#endif
1da177e4
LT		 600
601 char name[48];
602
0aa0f5d1
BH		 603 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
604 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 605 struct device *bridge;
fd7d1ced 606 struct device dev;
0aa0f5d1
BH		 607 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
608 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 609 unsigned int is_added:1;
1da177e4
LT		 610};
611
fd7d1ced 612#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 613
4e544bac
HK		 614static inline u16 pci_dev_id(struct pci_dev *dev)
615{
616 return PCI_DEVID(dev->bus->number, dev->devfn);
617}
618
79af72d7 619/*
f7625980 620 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 621 * false otherwise
77a0dfcd
BH		 622 *
623 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
624 * This is incorrect because "virtual" buses added for SR-IOV (via
625 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 626 */
627static inline bool pci_is_root_bus(struct pci_bus *pbus)
628{
629 return !(pbus->parent);
630}
631
1c86438c
YW		 632/**
633 * pci_is_bridge - check if the PCI device is a bridge
634 * @dev: PCI device
635 *
636 * Return true if the PCI device is bridge whether it has subordinate
637 * or not.
638 */
639static inline bool pci_is_bridge(struct pci_dev *dev)
640{
641 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
642 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
643}
644
24a0c654
AS		 645#define for_each_pci_bridge(dev, bus) \
646 list_for_each_entry(dev, &bus->devices, bus_list) \
647 if (!pci_is_bridge(dev)) {} else
648
c6bde215
BH		 649static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
650{
651 dev = pci_physfn(dev);
652 if (pci_is_root_bus(dev->bus))
653 return NULL;
654
655 return dev->bus->self;
656}
657
16cf0ebc
RW		 658#ifdef CONFIG_PCI_MSI
659static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
660{
661 return pci_dev->msi_enabled || pci_dev->msix_enabled;
662}
663#else
664static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
665#endif
666
0aa0f5d1 667/* Error values that may be returned by PCI functions */
1da177e4
LT		 668#define PCIBIOS_SUCCESSFUL 0x00
669#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
670#define PCIBIOS_BAD_VENDOR_ID 0x83
671#define PCIBIOS_DEVICE_NOT_FOUND 0x86
672#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
673#define PCIBIOS_SET_FAILED 0x88
674#define PCIBIOS_BUFFER_TOO_SMALL 0x89
675
0aa0f5d1 676/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 677static inline int pcibios_err_to_errno(int err)
678{
679 if (err <= PCIBIOS_SUCCESSFUL)
680 return err; /* Assume already errno */
681
682 switch (err) {
683 case PCIBIOS_FUNC_NOT_SUPPORTED:
684 return -ENOENT;
685 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 686 return -ENOTTY;
a6961651
AW		 687 case PCIBIOS_DEVICE_NOT_FOUND:
688 return -ENODEV;
689 case PCIBIOS_BAD_REGISTER_NUMBER:
690 return -EFAULT;
691 case PCIBIOS_SET_FAILED:
692 return -EIO;
693 case PCIBIOS_BUFFER_TOO_SMALL:
694 return -ENOSPC;
695 }
696
d97ffe23 697 return -ERANGE;
a6961651
AW		 698}
699
1da177e4
LT		 700/* Low-level architecture-dependent routines */
701
702struct pci_ops {
057bd2e0
TR		 703 int (*add_bus)(struct pci_bus *bus);
704 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 705 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 706 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
707 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
708};
709
b6ce068a
MW		 710/*
711 * ACPI needs to be able to access PCI config space before we've done a
712 * PCI bus scan and created pci_bus structures.
713 */
f39d5b72
BH		 714int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
715 int reg, int len, u32 *val);
716int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
717 int reg, int len, u32 val);
1da177e4 718
8e639079 719#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 720typedef u64 pci_bus_addr_t;
721#else
722typedef u32 pci_bus_addr_t;
723#endif
724
1da177e4 725struct pci_bus_region {
0aa0f5d1
BH		 726 pci_bus_addr_t start;
727 pci_bus_addr_t end;
1da177e4
LT		 728};
729
730struct pci_dynids {
0aa0f5d1
BH		 731 spinlock_t lock; /* Protects list, index */
732 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 733};
734
f7625980
BH		 735
736/*
737 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
738 * a set of callbacks in struct pci_error_handlers, that device driver
739 * will be notified of PCI bus errors, and will be driven to recovery
740 * when an error occurs.
392a1ce7 741 */
742
743typedef unsigned int __bitwise pci_ers_result_t;
744
745enum pci_ers_result {
0aa0f5d1 746 /* No result/none/not supported in device driver */
392a1ce7 747 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
748
749 /* Device driver can recover without slot reset */
750 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
751
0aa0f5d1 752 /* Device driver wants slot to be reset */
392a1ce7 753 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
754
755 /* Device has completely failed, is unrecoverable */
756 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
757
758 /* Device driver is fully recovered and operational */
759 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 760
761 /* No AER capabilities registered for the driver */
762 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 763};
764
765/* PCI bus error event callbacks */
05cca6e5 766struct pci_error_handlers {
392a1ce7 767 /* PCI bus error detected on this device */
768 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 769 enum pci_channel_state error);
392a1ce7 770
771 /* MMIO has been re-enabled, but not DMA */
772 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
773
392a1ce7 774 /* PCI slot has been reset */
775 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
776
3ebe7f9f 777 /* PCI function reset prepare or completed */
775755ed
CH		 778 void (*reset_prepare)(struct pci_dev *dev);
779 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 780
392a1ce7 781 /* Device driver may resume normal operations */
782 void (*resume)(struct pci_dev *dev);
783};
784
392a1ce7 785
1da177e4 786struct module;
229b4e07
CD		 787
788/**
789 * struct pci_driver - PCI driver structure
790 * @node: List of driver structures.
791 * @name: Driver name.
792 * @id_table: Pointer to table of device IDs the driver is
793 * interested in. Most drivers should export this
794 * table using MODULE_DEVICE_TABLE(pci,...).
795 * @probe: This probing function gets called (during execution
796 * of pci_register_driver() for already existing
797 * devices or later if a new device gets inserted) for
798 * all PCI devices which match the ID table and are not
799 * "owned" by the other drivers yet. This function gets
800 * passed a "struct pci_dev \*" for each device whose
801 * entry in the ID table matches the device. The probe
802 * function returns zero when the driver chooses to
803 * take "ownership" of the device or an error code
804 * (negative number) otherwise.
805 * The probe function always gets called from process
806 * context, so it can sleep.
807 * @remove: The remove() function gets called whenever a device
808 * being handled by this driver is removed (either during
809 * deregistration of the driver or when it's manually
810 * pulled out of a hot-pluggable slot).
811 * The remove function always gets called from process
812 * context, so it can sleep.
813 * @suspend: Put device into low power state.
229b4e07 814 * @resume: Wake device from low power state.
151f4e2b 815 * (Please see Documentation/power/pci.rst for descriptions
229b4e07
CD		 816 * of PCI Power Management and the related functions.)
817 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
818 * Intended to stop any idling DMA operations.
819 * Useful for enabling wake-on-lan (NIC) or changing
820 * the power state of a device before reboot.
821 * e.g. drivers/net/e100.c.
822 * @sriov_configure: Optional driver callback to allow configuration of
823 * number of VFs to enable via sysfs "sriov_numvfs" file.
824 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
825 * @groups: Sysfs attribute groups.
826 * @driver: Driver model structure.
827 * @dynids: List of dynamically added device IDs.
828 */
1da177e4 829struct pci_driver {
0aa0f5d1
BH		 830 struct list_head node;
831 const char *name;
832 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
833 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
834 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
835 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
7cb30264
BY		 836 int (*resume)(struct pci_dev *dev); /* Device woken up */
837 void (*shutdown)(struct pci_dev *dev);
838 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
49453028 839 const struct pci_error_handlers *err_handler;
92d50fc1 840 const struct attribute_group **groups;
1da177e4 841 struct device_driver driver;
0aa0f5d1 842 struct pci_dynids dynids;
1da177e4
LT		 843};
844
05cca6e5 845#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 846
847/**
0aa0f5d1 848 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 849 * @vend: the 16 bit PCI Vendor ID
850 * @dev: the 16 bit PCI Device ID
851 *
852 * This macro is used to create a struct pci_device_id that matches a
853 * specific device. The subvendor and subdevice fields will be set to
854 * PCI_ANY_ID.
855 */
856#define PCI_DEVICE(vend,dev) \
857 .vendor = (vend), .device = (dev), \
858 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
859
3d567e0e 860/**
0aa0f5d1 861 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 862 * @vend: the 16 bit PCI Vendor ID
863 * @dev: the 16 bit PCI Device ID
864 * @subvend: the 16 bit PCI Subvendor ID
865 * @subdev: the 16 bit PCI Subdevice ID
866 *
867 * This macro is used to create a struct pci_device_id that matches a
868 * specific device with subsystem information.
869 */
870#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
871 .vendor = (vend), .device = (dev), \
872 .subvendor = (subvend), .subdevice = (subdev)
873
1da177e4 874/**
0aa0f5d1 875 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 876 * @dev_class: the class, subclass, prog-if triple for this device
877 * @dev_class_mask: the class mask for this device
878 *
879 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 880 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 881 * fields will be set to PCI_ANY_ID.
882 */
883#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
884 .class = (dev_class), .class_mask = (dev_class_mask), \
885 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
886 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
887
1597cacb 888/**
0aa0f5d1 889 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 890 * @vend: the vendor name
891 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 892 *
893 * This macro is used to create a struct pci_device_id that matches a
894 * specific PCI device. The subvendor, and subdevice fields will be set
895 * to PCI_ANY_ID. The macro allows the next field to follow as the device
896 * private data.
897 */
c1309040
MR		 898#define PCI_VDEVICE(vend, dev) \
899 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
900 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 901
b72ae8ca
AS		 902/**
903 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
904 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
905 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
906 * @data: the driver data to be filled
907 *
908 * This macro is used to create a struct pci_device_id that matches a
909 * specific PCI device. The subvendor, and subdevice fields will be set
910 * to PCI_ANY_ID.
911 */
912#define PCI_DEVICE_DATA(vend, dev, data) \
913 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
914 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
915 .driver_data = (kernel_ulong_t)(data)
916
5bbe029f 917enum {
0aa0f5d1
BH		 918 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
919 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
920 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
921 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
922 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 923 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 924 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 925};
926
0d8006dd
HX		 927#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
928#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
929#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
930#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
931
0aa0f5d1 932/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 933#ifdef CONFIG_PCI
934
5bbe029f
BH		 935extern unsigned int pci_flags;
936
937static inline void pci_set_flags(int flags) { pci_flags = flags; }
938static inline void pci_add_flags(int flags) { pci_flags |= flags; }
939static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
940static inline int pci_has_flag(int flag) { return pci_flags & flag; }
941
a58674ff 942void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 943
944enum pcie_bus_config_types {
0aa0f5d1
BH		 945 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
946 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
947 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
948 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
949 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 950};
951
952extern enum pcie_bus_config_types pcie_bus_config;
953
1da177e4
LT		 954extern struct bus_type pci_bus_type;
955
f7625980
BH		 956/* Do NOT directly access these two variables, unless you are arch-specific PCI
957 * code, or PCI core code. */
0aa0f5d1 958extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 959/* Some device drivers need know if PCI is initiated */
f39d5b72 960int no_pci_devices(void);
1da177e4 961
3c449ed0 962void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 963void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 964void pcibios_add_bus(struct pci_bus *bus);
965void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 966void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 967int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 968/* Architecture-specific versions may override this (weak) */
05cca6e5 969char *pcibios_setup(char *str);
1da177e4
LT		 970
971/* Used only when drivers/pci/setup.c is used */
3b7a17fc 972resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 973 resource_size_t,
e31dd6e4 974 resource_size_t);
1da177e4 975
d1bbf38a 976/* Weak but can be overridden by arch */
2d1c8618
BH		 977void pci_fixup_cardbus(struct pci_bus *);
978
1da177e4
LT		 979/* Generic PCI functions used internally */
980
fc279850 981void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 982 struct resource *res);
fc279850 983void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 984 struct pci_bus_region *region);
d1fd4fb6 985void pcibios_scan_specific_bus(int busn);
f39d5b72 986struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 987void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 988struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 989struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
990 struct pci_ops *ops, void *sysdata,
991 struct list_head *resources);
49b8e3f3 992int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 993int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
994int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
995void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 996struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 997 struct pci_ops *ops, void *sysdata,
998 struct list_head *resources);
1228c4b6 999int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 1000struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1001 int busnr);
f46753c5 1002struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 1003 const char *name,
1004 struct hotplug_slot *hotplug);
f46753c5 1005void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 1006#ifdef CONFIG_SYSFS
1007void pci_dev_assign_slot(struct pci_dev *dev);
1008#else
1009static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1010#endif
1da177e4 1011int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 1012struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 1013void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 1014unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 1015void pci_bus_add_device(struct pci_dev *dev);
1da177e4 1016void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 1017struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1018 struct resource *res);
c56d4450 1019struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 1020u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 1021int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 1022u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 1023struct pci_dev *pci_dev_get(struct pci_dev *dev);
1024void pci_dev_put(struct pci_dev *dev);
1025void pci_remove_bus(struct pci_bus *b);
1026void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 1027void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 1028void pci_stop_root_bus(struct pci_bus *bus);
1029void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 1030void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 1031void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 1032void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 1033#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1034#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 1035
1036/* Generic PCI functions exported to card drivers */
1037
388c8c16
JB		 1038enum pci_lost_interrupt_reason {
1039 PCI_LOST_IRQ_NO_INFORMATION = 0,
1040 PCI_LOST_IRQ_DISABLE_MSI,
1041 PCI_LOST_IRQ_DISABLE_MSIX,
1042 PCI_LOST_IRQ_DISABLE_ACPI,
1043};
1044enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 1045int pci_find_capability(struct pci_dev *dev, int cap);
1046int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1047int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 1048int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 1049int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1050int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 1051struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 1052
d42552c3 1053struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 1054 struct pci_dev *from);
05cca6e5 1055struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 1056 unsigned int ss_vendor, unsigned int ss_device,
1057 struct pci_dev *from);
05cca6e5 1058struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 1059struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1060 unsigned int devfn);
05cca6e5 1061struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 1062int pci_dev_present(const struct pci_device_id *ids);
1063
05cca6e5
GKH		 1064int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1065 int where, u8 *val);
1066int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1067 int where, u16 *val);
1068int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1069 int where, u32 *val);
1070int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1071 int where, u8 val);
1072int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1073 int where, u16 val);
1074int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1075 int where, u32 val);
1f94a94f
RH		 1076
1077int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1078 int where, int size, u32 *val);
1079int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1080 int where, int size, u32 val);
1081int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1082 int where, int size, u32 *val);
1083int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1084 int where, int size, u32 val);
1085
a72b46c3 1086struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1087
d3881e50
KB		 1088int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1089int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1090int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1091int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1092int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1093int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 1094
8c0d3a02
JL		 1095int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1096int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1097int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1098int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1099int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1100 u16 clear, u16 set);
1101int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1102 u32 clear, u32 set);
1103
1104static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1105 u16 set)
1106{
1107 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1108}
1109
1110static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1111 u32 set)
1112{
1113 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1114}
1115
1116static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1117 u16 clear)
1118{
1119 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1120}
1121
1122static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1123 u32 clear)
1124{
1125 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1126}
1127
0aa0f5d1 1128/* User-space driven config access */
c63587d7
AW		 1129int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1130int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1131int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1132int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1133int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1134int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1135
4a7fb636 1136int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1137int __must_check pci_enable_device_io(struct pci_dev *dev);
1138int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1139int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1140int __must_check pcim_enable_device(struct pci_dev *pdev);
1141void pcim_pin_device(struct pci_dev *pdev);
1142
99b3c58f
PG		 1143static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1144{
1145 /*
1146 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1147 * writable and no quirk has marked the feature broken.
1148 */
1149 return !pdev->broken_intx_masking;
1150}
1151
296ccb08
YS		 1152static inline int pci_is_enabled(struct pci_dev *pdev)
1153{
1154 return (atomic_read(&pdev->enable_cnt) > 0);
1155}
1156
9ac7849e
TH		 1157static inline int pci_is_managed(struct pci_dev *pdev)
1158{
1159 return pdev->is_managed;
1160}
1161
1da177e4 1162void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1163
1164extern unsigned int pcibios_max_latency;
1da177e4 1165void pci_set_master(struct pci_dev *dev);
6a479079 1166void pci_clear_master(struct pci_dev *dev);
96c55900 1167
f7bdd12d 1168int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1169int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1170#define HAVE_PCI_SET_MWI
4a7fb636 1171int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1172int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1173int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1174void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1175void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1176bool pci_check_and_mask_intx(struct pci_dev *dev);
1177bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1178int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1179int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1180int pcix_get_max_mmrbc(struct pci_dev *dev);
1181int pcix_get_mmrbc(struct pci_dev *dev);
1182int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1183int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1184int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1185int pcie_get_mps(struct pci_dev *dev);
1186int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1187u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1188 enum pci_bus_speed *speed,
1189 enum pcie_link_width *width);
9e506a7b 1190void pcie_print_link_status(struct pci_dev *dev);
2d2917f7 1191bool pcie_has_flr(struct pci_dev *dev);
91295d79 1192int pcie_flr(struct pci_dev *dev);
a96d627a 1193int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1194int pci_reset_function(struct pci_dev *dev);
a477b9cd 1195int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1196int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1197int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1198int pci_probe_reset_bus(struct pci_bus *bus);
c6a44ba9 1199int pci_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1200void pci_reset_secondary_bus(struct pci_dev *dev);
1201void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1202void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1203int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1204int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1205void pci_release_resource(struct pci_dev *dev, int resno);
1206int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1207int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1208bool pci_device_is_present(struct pci_dev *pdev);
08249651 1209void pci_ignore_hotplug(struct pci_dev *dev);
2856ba60 1210struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1da177e4 1211
704e8953
CH		 1212int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1213 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1214 const char *fmt, ...);
1215void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1216
1da177e4 1217/* ROM control related routines */
e416de5e
AC		 1218int pci_enable_rom(struct pci_dev *pdev);
1219void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1220void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1221void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
fffe01f7 1222void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1223
1224/* Power management related routines */
1225int pci_save_state(struct pci_dev *dev);
1d3c16a8 1226void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1227struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1228int pci_load_saved_state(struct pci_dev *dev,
1229 struct pci_saved_state *state);
ffbdd3f7
AW		 1230int pci_load_and_free_saved_state(struct pci_dev *dev,
1231 struct pci_saved_state **state);
fd0f7f73
AW		 1232struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1233struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1234 u16 cap);
1235int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1236int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1237 u16 cap, unsigned int size);
d6aa37cd 1238int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1239int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1240pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1241bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1242void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1243int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1244int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1245int pci_prepare_to_sleep(struct pci_dev *dev);
1246int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1247bool pci_dev_run_wake(struct pci_dev *dev);
9d26d3a8
MW		 1248void pci_d3cold_enable(struct pci_dev *dev);
1249void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1250bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
2a4d2c42
LW		 1251void pci_wakeup_bus(struct pci_bus *bus);
1252void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1253
bb209c82
BH		 1254/* For use by arch with custom probe code */
1255void set_pcie_port_type(struct pci_dev *pdev);
1256void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1257
ce5ccdef 1258/* Functions for PCI Hotplug drivers to use */
05cca6e5 1259int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1260unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1261unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1262void pci_lock_rescan_remove(void);
1263void pci_unlock_rescan_remove(void);
ce5ccdef 1264
0aa0f5d1 1265/* Vital Product Data routines */
287d19ce
SH		 1266ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1267ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1268int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1269
1da177e4 1270/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1271resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1272void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1273void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1274void pci_bus_size_bridges(struct pci_bus *bus);
1275int pci_claim_resource(struct pci_dev *, int);
8505e729 1276int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1277void pci_assign_unassigned_resources(void);
6841ec68 1278void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1279void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1280void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1281int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1282void pdev_enable_device(struct pci_dev *);
842de40d 1283int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1284void pci_assign_irq(struct pci_dev *dev);
afd29f90 1285struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1286#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1287int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1288int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1289void pci_release_regions(struct pci_dev *);
4a7fb636 1290int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 1291void pci_release_region(struct pci_dev *, int);
c87deff7 1292int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1293int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1294void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1295
1296/* drivers/pci/bus.c */
45ca9e97 1297void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1298void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1299 resource_size_t offset);
45ca9e97 1300void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1301void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1302 unsigned int flags);
2fe2abf8
BH		 1303struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1304void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1305int devm_request_pci_bus_resources(struct device *dev,
1306 struct list_head *resources);
2fe2abf8 1307
bfc45606
DD		 1308/* Temporary until new and working PCI SBR API in place */
1309int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1310
89a74ecc 1311#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1312 for (i = 0; \
1313 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1314 i++)
89a74ecc 1315
4a7fb636
AM		 1316int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1317 struct resource *res, resource_size_t size,
1318 resource_size_t align, resource_size_t min,
664c2848 1319 unsigned long type_mask,
3b7a17fc
DB		 1320 resource_size_t (*alignf)(void *,
1321 const struct resource *,
b26b2d49
DB		 1322 resource_size_t,
1323 resource_size_t),
4a7fb636 1324 void *alignf_data);
1da177e4 1325
8b921acf 1326
fcfaab30
GP		 1327int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1328 resource_size_t size);
c5076cfe
TN		 1329unsigned long pci_address_to_pio(phys_addr_t addr);
1330phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1331int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
a5fb9fb0
SS		 1332int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1333 phys_addr_t phys_addr);
4d3f1384 1334void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1335void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1336 resource_size_t offset,
1337 resource_size_t size);
1338void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1339 struct resource *res);
8b921acf 1340
3a9ad0b4 1341static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1342{
1343 struct pci_bus_region region;
1344
1345 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1346 return region.start;
1347}
1348
863b18f4 1349/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1350int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1351 const char *mod_name);
bba81165 1352
0aa0f5d1 1353/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1354#define pci_register_driver(driver) \
1355 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1356
05cca6e5 1357void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1358
1359/**
1360 * module_pci_driver() - Helper macro for registering a PCI driver
1361 * @__pci_driver: pci_driver struct
1362 *
1363 * Helper macro for PCI drivers which do not do anything special in module
1364 * init/exit. This eliminates a lot of boilerplate. Each module may only
1365 * use this macro once, and calling it replaces module_init() and module_exit()
1366 */
1367#define module_pci_driver(__pci_driver) \
0aa0f5d1 1368 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1369
b4eb6cdb
PG		 1370/**
1371 * builtin_pci_driver() - Helper macro for registering a PCI driver
1372 * @__pci_driver: pci_driver struct
1373 *
1374 * Helper macro for PCI drivers which do not do anything special in their
1375 * init code. This eliminates a lot of boilerplate. Each driver may only
1376 * use this macro once, and calling it replaces device_initcall(...)
1377 */
1378#define builtin_pci_driver(__pci_driver) \
1379 builtin_driver(__pci_driver, pci_register_driver)
1380
05cca6e5 1381struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1382int pci_add_dynid(struct pci_driver *drv,
1383 unsigned int vendor, unsigned int device,
1384 unsigned int subvendor, unsigned int subdevice,
1385 unsigned int class, unsigned int class_mask,
1386 unsigned long driver_data);
05cca6e5
GKH		 1387const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1388 struct pci_dev *dev);
1389int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1390 int pass);
1da177e4 1391
70298c6e 1392void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1393 void *userdata);
ac7dc65a 1394int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1395unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1396void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1397resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1398 unsigned long type);
cecf4864 1399
3448a19d
DA		 1400#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1401#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1402
deb2d2ec 1403int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1404 unsigned int command_bits, u32 flags);
fe537670 1405
d7cc609f
LG		 1406/*
1407 * Virtual interrupts allow for more interrupts to be allocated
1408 * than the device has interrupts for. These are not programmed
1409 * into the device's MSI-X table and must be handled by some
1410 * other driver means.
1411 */
1412#define PCI_IRQ_VIRTUAL (1 << 4)
1413
4fe0d154
CH		 1414#define PCI_IRQ_ALL_TYPES \
1415 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1416
1da177e4
LT		 1417/* kmem_cache style wrapper around pci_alloc_consistent() */
1418
1419#include <linux/dmapool.h>
1420
1421#define pci_pool dma_pool
1422#define pci_pool_create(name, pdev, size, align, allocation) \
1423 dma_pool_create(name, &pdev->dev, size, align, allocation)
1424#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1425#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1426#define pci_pool_zalloc(pool, flags, handle) \
1427 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1428#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1429
1da177e4 1430struct msix_entry {
0aa0f5d1
BH		 1431 u32 vector; /* Kernel uses to write allocated vector */
1432 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1433};
1434
4c859804
BH		 1435#ifdef CONFIG_PCI_MSI
1436int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1437void pci_disable_msi(struct pci_dev *dev);
4c859804 1438int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1439void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1440void pci_restore_msi_state(struct pci_dev *dev);
1441int pci_msi_enabled(void);
4fe03955 1442int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1443int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1444 int minvec, int maxvec);
f7fc32cb
AG		 1445static inline int pci_enable_msix_exact(struct pci_dev *dev,
1446 struct msix_entry *entries, int nvec)
1447{
1448 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1449 if (rc < 0)
1450 return rc;
1451 return 0;
1452}
402723ad
CH		 1453int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1454 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1455 struct irq_affinity *affd);
402723ad 1456
aff17164
CH		 1457void pci_free_irq_vectors(struct pci_dev *dev);
1458int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1459const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
aff17164 1460
4c859804 1461#else
2ee546c4 1462static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1463static inline void pci_disable_msi(struct pci_dev *dev) { }
1464static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1465static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1466static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1467static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1468static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1469{ return -ENOSYS; }
302a2523 1470static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1471 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1472{ return -ENOSYS; }
f7fc32cb 1473static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1474 struct msix_entry *entries, int nvec)
f7fc32cb 1475{ return -ENOSYS; }
402723ad
CH		 1476
1477static inline int
1478pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1479 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1480 struct irq_affinity *aff_desc)
aff17164 1481{
83b4605b
CH		 1482 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1483 return 1;
1484 return -ENOSPC;
aff17164 1485}
402723ad 1486
aff17164
CH		 1487static inline void pci_free_irq_vectors(struct pci_dev *dev)
1488{
1489}
1490
1491static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1492{
1493 if (WARN_ON_ONCE(nr > 0))
1494 return -EINVAL;
1495 return dev->irq;
1496}
ee8d41e5
TG		 1497static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1498 int vec)
1499{
1500 return cpu_possible_mask;
1501}
1da177e4
LT		 1502#endif
1503
0d58e6c1
PB		 1504/**
1505 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1506 * @d: the INTx IRQ domain
1507 * @node: the DT node for the device whose interrupt we're translating
1508 * @intspec: the interrupt specifier data from the DT
1509 * @intsize: the number of entries in @intspec
1510 * @out_hwirq: pointer at which to write the hwirq number
1511 * @out_type: pointer at which to write the interrupt type
1512 *
1513 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1514 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1515 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1516 * INTx value to obtain the hwirq number.
1517 *
1518 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1519 */
1520static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1521 struct device_node *node,
1522 const u32 *intspec,
1523 unsigned int intsize,
1524 unsigned long *out_hwirq,
1525 unsigned int *out_type)
1526{
1527 const u32 intx = intspec[0];
1528
1529 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1530 return -EINVAL;
1531
1532 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1533 return 0;
1534}
1535
ab0724ff 1536#ifdef CONFIG_PCIEPORTBUS
415e12b2 1537extern bool pcie_ports_disabled;
5352a44a 1538extern bool pcie_ports_native;
ab0724ff
MT		 1539#else
1540#define pcie_ports_disabled true
5352a44a 1541#define pcie_ports_native false
ab0724ff 1542#endif
415e12b2 1543
aff5d055
HK		 1544#define PCIE_LINK_STATE_L0S BIT(0)
1545#define PCIE_LINK_STATE_L1 BIT(1)
1546#define PCIE_LINK_STATE_CLKPM BIT(2)
1547#define PCIE_LINK_STATE_L1_1 BIT(3)
1548#define PCIE_LINK_STATE_L1_2 BIT(4)
1549#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1550#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
7ce2e76a 1551
4c859804 1552#ifdef CONFIG_PCIEASPM
7ce2e76a
KW		 1553int pci_disable_link_state(struct pci_dev *pdev, int state);
1554int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1555void pcie_no_aspm(void);
f39d5b72 1556bool pcie_aspm_support_enabled(void);
accd2dd7 1557bool pcie_aspm_enabled(struct pci_dev *pdev);
4c859804 1558#else
7ce2e76a
KW		 1559static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1560{ return 0; }
1561static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1562{ return 0; }
1563static inline void pcie_no_aspm(void) { }
4c859804 1564static inline bool pcie_aspm_support_enabled(void) { return false; }
accd2dd7 1565static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
3e1b1600
AP		 1566#endif
1567
415e12b2 1568#ifdef CONFIG_PCIEAER
415e12b2
RW		 1569bool pci_aer_available(void);
1570#else
415e12b2
RW		 1571static inline bool pci_aer_available(void) { return false; }
1572#endif
1573
cef74409
GK		 1574bool pci_ats_disabled(void);
1575
f39d5b72
BH		 1576void pci_cfg_access_lock(struct pci_dev *dev);
1577bool pci_cfg_access_trylock(struct pci_dev *dev);
1578void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1579
4352dfd5
GKH		 1580/*
1581 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1582 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1583 * configuration space.
1584 */
32a2eea7
JG		 1585#ifdef CONFIG_PCI_DOMAINS
1586extern int pci_domains_supported;
1587#else
1588enum { pci_domains_supported = 0 };
2ee546c4
BH		 1589static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1590static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1591#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1592
670ba0c8
CM		 1593/*
1594 * Generic implementation for PCI domain support. If your
1595 * architecture does not need custom management of PCI
1596 * domains then this implementation will be used
1597 */
1598#ifdef CONFIG_PCI_DOMAINS_GENERIC
1599static inline int pci_domain_nr(struct pci_bus *bus)
1600{
1601 return bus->domain_nr;
1602}
2ab51dde
TN		 1603#ifdef CONFIG_ACPI
1604int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1605#else
2ab51dde
TN		 1606static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1607{ return 0; }
1608#endif
9c7cb891 1609int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1610#endif
1611
0aa0f5d1 1612/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1613typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1614 unsigned int command_bits, u32 flags);
f39d5b72 1615void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1616
be9d2e89
JT		 1617static inline int
1618pci_request_io_regions(struct pci_dev *pdev, const char *name)
1619{
1620 return pci_request_selected_regions(pdev,
1621 pci_select_bars(pdev, IORESOURCE_IO), name);
1622}
1623
1624static inline void
1625pci_release_io_regions(struct pci_dev *pdev)
1626{
1627 return pci_release_selected_regions(pdev,
1628 pci_select_bars(pdev, IORESOURCE_IO));
1629}
1630
1631static inline int
1632pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1633{
1634 return pci_request_selected_regions(pdev,
1635 pci_select_bars(pdev, IORESOURCE_MEM), name);
1636}
1637
1638static inline void
1639pci_release_mem_regions(struct pci_dev *pdev)
1640{
1641 return pci_release_selected_regions(pdev,
1642 pci_select_bars(pdev, IORESOURCE_MEM));
1643}
1644
4352dfd5 1645#else /* CONFIG_PCI is not enabled */
1da177e4 1646
5bbe029f
BH		 1647static inline void pci_set_flags(int flags) { }
1648static inline void pci_add_flags(int flags) { }
1649static inline void pci_clear_flags(int flags) { }
1650static inline int pci_has_flag(int flag) { return 0; }
1651
1da177e4 1652/*
0aa0f5d1
BH		 1653 * If the system does not have PCI, clearly these return errors. Define
1654 * these as simple inline functions to avoid hair in drivers.
1da177e4 1655 */
05cca6e5
GKH		 1656#define _PCI_NOP(o, s, t) \
1657 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1658 int where, t val) \
1da177e4 1659 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1660
1661#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1662 _PCI_NOP(o, word, u16 x) \
1663 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1664_PCI_NOP_ALL(read, *)
1665_PCI_NOP_ALL(write,)
1666
d42552c3 1667static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1668 unsigned int device,
1669 struct pci_dev *from)
2ee546c4 1670{ return NULL; }
d42552c3 1671
05cca6e5
GKH		 1672static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1673 unsigned int device,
1674 unsigned int ss_vendor,
1675 unsigned int ss_device,
b08508c4 1676 struct pci_dev *from)
2ee546c4 1677{ return NULL; }
1da177e4 1678
05cca6e5
GKH		 1679static inline struct pci_dev *pci_get_class(unsigned int class,
1680 struct pci_dev *from)
2ee546c4 1681{ return NULL; }
1da177e4
LT		 1682
1683#define pci_dev_present(ids) (0)
ed4aaadb 1684#define no_pci_devices() (1)
1da177e4
LT		 1685#define pci_dev_put(dev) do { } while (0)
1686
2ee546c4
BH		 1687static inline void pci_set_master(struct pci_dev *dev) { }
1688static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1689static inline void pci_disable_device(struct pci_dev *dev) { }
977da073 1690static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
05cca6e5 1691static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1692{ return -EBUSY; }
05cca6e5
GKH		 1693static inline int __pci_register_driver(struct pci_driver *drv,
1694 struct module *owner)
2ee546c4 1695{ return 0; }
05cca6e5 1696static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1697{ return 0; }
1698static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1699static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1700{ return 0; }
05cca6e5
GKH		 1701static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1702 int cap)
2ee546c4 1703{ return 0; }
05cca6e5 1704static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1705{ return 0; }
05cca6e5 1706
1da177e4 1707/* Power management related routines */
2ee546c4
BH		 1708static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1709static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1710static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1711{ return 0; }
3449248c 1712static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1713{ return 0; }
05cca6e5
GKH		 1714static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1715 pm_message_t state)
2ee546c4 1716{ return PCI_D0; }
05cca6e5
GKH		 1717static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1718 int enable)
2ee546c4 1719{ return 0; }
48a92a81 1720
afd29f90
MW		 1721static inline struct resource *pci_find_resource(struct pci_dev *dev,
1722 struct resource *res)
1723{ return NULL; }
05cca6e5 1724static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1725{ return -EIO; }
1726static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1727
c5076cfe
TN		 1728static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1729
d80d0217
RD		 1730static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1731{ return NULL; }
d80d0217
RD		 1732static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1733 unsigned int devfn)
1734{ return NULL; }
7912af5c
RD		 1735static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1736 unsigned int bus, unsigned int devfn)
1737{ return NULL; }
d80d0217 1738
2ee546c4
BH		 1739static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1740static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 1741
fb8a0d9d
WM		 1742#define dev_is_pci(d) (false)
1743#define dev_is_pf(d) (false)
fe594932
GU		 1744static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1745{ return false; }
80db6f08
NC		 1746static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1747 struct device_node *node,
1748 const u32 *intspec,
1749 unsigned int intsize,
1750 unsigned long *out_hwirq,
1751 unsigned int *out_type)
1752{ return -EINVAL; }
9c212009
LR		 1753
1754static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1755 struct pci_dev *dev)
1756{ return NULL; }
b9ae16d8 1757static inline bool pci_ats_disabled(void) { return true; }
0d8006dd
HX		 1758
1759static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1760{
1761 return -EINVAL;
1762}
1763
1764static inline int
1765pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1766 unsigned int max_vecs, unsigned int flags,
1767 struct irq_affinity *aff_desc)
1768{
1769 return -ENOSPC;
1770}
4352dfd5 1771#endif /* CONFIG_PCI */
1da177e4 1772
0d8006dd
HX		 1773static inline int
1774pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1775 unsigned int max_vecs, unsigned int flags)
1776{
1777 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1778 NULL);
1779}
1780
4352dfd5
GKH		 1781/* Include architecture-dependent settings and functions */
1782
1783#include <asm/pci.h>
1da177e4 1784
d1bbf38a 1785/* These two functions provide almost identical functionality. Depending
f7195824
DW		 1786 * on the architecture, one will be implemented as a wrapper around the
1787 * other (in drivers/pci/mmap.c).
1788 *
1789 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1790 * is expected to be an offset within that region.
1791 *
1792 * pci_mmap_page_range() is the legacy architecture-specific interface,
1793 * which accepts a "user visible" resource address converted by
1794 * pci_resource_to_user(), as used in the legacy mmap() interface in
1795 * /proc/bus/pci/.
1796 */
1797int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1798 struct vm_area_struct *vma,
1799 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1800int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1801 struct vm_area_struct *vma,
11df1954
DW		 1802 enum pci_mmap_state mmap_state, int write_combine);
1803
ae749c7a
DW		 1804#ifndef arch_can_pci_mmap_wc
1805#define arch_can_pci_mmap_wc() 0
1806#endif
2bea36fd 1807
e854d8b2
DW		 1808#ifndef arch_can_pci_mmap_io
1809#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1810#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1811#else
1812int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1813#endif
ae749c7a 1814
92016ba5
JO		 1815#ifndef pci_root_bus_fwnode
1816#define pci_root_bus_fwnode(bus) NULL
1817#endif
1818
0aa0f5d1
BH		 1819/*
1820 * These helpers provide future and backwards compatibility
1821 * for accessing popular PCI BAR info
1822 */
05cca6e5
GKH		 1823#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1824#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1825#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1826#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1827 ((pci_resource_start((dev), (bar)) == 0 && \
1828 pci_resource_end((dev), (bar)) == \
1829 pci_resource_start((dev), (bar))) ? 0 : \
1830 \
1831 (pci_resource_end((dev), (bar)) - \
1832 pci_resource_start((dev), (bar)) + 1))
1da177e4 1833
0aa0f5d1
BH		 1834/*
1835 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1836 * driver-specific data. They are really just a wrapper around
1837 * the generic device structure functions of these calls.
1838 */
05cca6e5 1839static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1840{
1841 return dev_get_drvdata(&pdev->dev);
1842}
1843
05cca6e5 1844static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1845{
1846 dev_set_drvdata(&pdev->dev, data);
1847}
1848
2fc90f61 1849static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1850{
c6c4f070 1851 return dev_name(&pdev->dev);
1da177e4
LT		 1852}
1853
8221a013
BH		 1854void pci_resource_to_user(const struct pci_dev *dev, int bar,
1855 const struct resource *rsrc,
1856 resource_size_t *start, resource_size_t *end);
2311b1f2 1857
1da177e4 1858/*
0aa0f5d1
BH		 1859 * The world is not perfect and supplies us with broken PCI devices.
1860 * For at least a part of these bugs we need a work-around, so both
1861 * generic (drivers/pci/quirks.c) and per-architecture code can define
1862 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1863 */
1864
1865struct pci_fixup {
0aa0f5d1
BH		 1866 u16 vendor; /* Or PCI_ANY_ID */
1867 u16 device; /* Or PCI_ANY_ID */
1868 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 1869 unsigned int class_shift; /* should be 0, 8, 16 */
c9d8b55f
AB		 1870#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1871 int hook_offset;
1872#else
1da177e4 1873 void (*hook)(struct pci_dev *dev);
c9d8b55f 1874#endif
1da177e4
LT		 1875};
1876
1877enum pci_fixup_pass {
1878 pci_fixup_early, /* Before probing BARs */
1879 pci_fixup_header, /* After reading configuration header */
1880 pci_fixup_final, /* Final phase of device fixups */
1881 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1882 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1883 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1884 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1885 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1886};
1887
c9d8b55f
AB		 1888#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1889#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1890 class_shift, hook) \
1891 __ADDRESSABLE(hook) \
1892 asm(".section " #sec ", \"a\" \n" \
1893 ".balign 16 \n" \
1894 ".short " #vendor ", " #device " \n" \
1895 ".long " #class ", " #class_shift " \n" \
1896 ".long " #hook " - . \n" \
1897 ".previous \n");
1898#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1899 class_shift, hook) \
1900 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1901 class_shift, hook)
1902#else
1da177e4 1903/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1904#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1905 class_shift, hook) \
ecf61c78 1906 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1907 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1908 = { vendor, device, class, class_shift, hook };
c9d8b55f 1909#endif
f4ca5c6a
YL		 1910
1911#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1912 class_shift, hook) \
1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1914 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1915#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1916 class_shift, hook) \
1917 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1918 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1919#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1920 class_shift, hook) \
1921 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1922 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1923#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1924 class_shift, hook) \
1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1926 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1927#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1928 class_shift, hook) \
1929 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1930 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1931#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1932 class_shift, hook) \
1933 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1934 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1935#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1936 class_shift, hook) \
1937 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1938 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 1939#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1940 class_shift, hook) \
1941 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1942 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 1943
1da177e4
LT		 1944#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1945 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1946 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1947#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1948 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1949 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1950#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1952 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1953#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1954 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1955 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1956#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1957 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1958 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1959#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1960 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1961 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1962#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1964 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1965#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1967 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 1968
93177a74 1969#ifdef CONFIG_PCI_QUIRKS
1da177e4 1970void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1971#else
1972static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1973 struct pci_dev *dev) { }
93177a74 1974#endif
1da177e4 1975
05cca6e5 1976void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1977void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1978void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1979int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1980int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1981 const char *name);
fb7ebfe4 1982void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1983
1da177e4 1984extern int pci_pci_problems;
236561e5 1985#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1986#define PCIPCI_TRITON 2
1987#define PCIPCI_NATOMA 4
1988#define PCIPCI_VIAETBF 8
1989#define PCIPCI_VSFX 16
236561e5
AC		 1990#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1991#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1992
4516a618
AN		 1993extern unsigned long pci_cardbus_io_size;
1994extern unsigned long pci_cardbus_mem_size;
15856ad5 1995extern u8 pci_dfl_cache_line_size;
ac1aa47b 1996extern u8 pci_cache_line_size;
4516a618 1997
f7625980 1998/* Architecture-specific versions may override these (weak) */
19792a08 1999void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 2000void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 2001int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2002 enum pcie_reset_state state);
eca0d467 2003int pcibios_add_device(struct pci_dev *dev);
6ae32c53 2004void pcibios_release_device(struct pci_dev *dev);
5d32a665 2005#ifdef CONFIG_PCI
a43ae58c 2006void pcibios_penalize_isa_irq(int irq, int active);
5d32a665
SK		 2007#else
2008static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2009#endif
890e4847
JL		 2010int pcibios_alloc_irq(struct pci_dev *dev);
2011void pcibios_free_irq(struct pci_dev *dev);
619e6f34 2012resource_size_t pcibios_default_alignment(void);
575e3348 2013
699c1985
SO		 2014#ifdef CONFIG_HIBERNATE_CALLBACKS
2015extern struct dev_pm_ops pcibios_pm_ops;
2016#endif
2017
935c760e 2018#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 2019void __init pci_mmcfg_early_init(void);
2020void __init pci_mmcfg_late_init(void);
7752d5cf 2021#else
bb63b421 2022static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 2023static inline void pci_mmcfg_late_init(void) { }
2024#endif
2025
642c92da 2026int pci_ext_cfg_avail(void);
0ef5f8f6 2027
1684f5dd 2028void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 2029void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 2030
dd7cc44d 2031#ifdef CONFIG_PCI_IOV
b07579c0
WY		 2032int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2033int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2034
f39d5b72
BH		 2035int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2036void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 2037int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2038void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 2039int pci_num_vf(struct pci_dev *dev);
5a8eb242 2040int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 2041int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2042int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 2043int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 2044resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 2045void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 2046
2047/* Arch may override these (weak) */
2048int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2049int pcibios_sriov_disable(struct pci_dev *pdev);
2050resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 2051#else
b07579c0
WY		 2052static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2053{
2054 return -ENOSYS;
2055}
2056static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2057{
2058 return -ENOSYS;
2059}
dd7cc44d 2060static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2061{ return -ENODEV; }
753f6124 2062static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2063{
2064 return -ENOSYS;
2065}
2066static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2067 int id) { }
2ee546c4 2068static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2069static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2070static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2071{ return 0; }
bff73156 2072static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2073{ return 0; }
bff73156 2074static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2075{ return 0; }
8effc395 2076#define pci_sriov_configure_simple NULL
0e6c9122
WY		 2077static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2078{ return 0; }
608c0d88 2079static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 2080#endif
2081
c825bc94 2082#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2083void pci_hp_create_module_link(struct pci_slot *pci_slot);
2084void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2085#endif
2086
d7b7e605
KK		 2087/**
2088 * pci_pcie_cap - get the saved PCIe capability offset
2089 * @dev: PCI device
2090 *
2091 * PCIe capability offset is calculated at PCI device initialization
2092 * time and saved in the data structure. This function returns saved
2093 * PCIe capability offset. Using this instead of pci_find_capability()
2094 * reduces unnecessary search in the PCI configuration space. If you
2095 * need to calculate PCIe capability offset from raw device for some
2096 * reasons, please use pci_find_capability() instead.
2097 */
2098static inline int pci_pcie_cap(struct pci_dev *dev)
2099{
2100 return dev->pcie_cap;
2101}
2102
7eb776c4
KK		 2103/**
2104 * pci_is_pcie - check if the PCI device is PCI Express capable
2105 * @dev: PCI device
2106 *
a895c28a 2107 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2108 */
2109static inline bool pci_is_pcie(struct pci_dev *dev)
2110{
a895c28a 2111 return pci_pcie_cap(dev);
7eb776c4
KK		 2112}
2113
7c9c003c
MS		 2114/**
2115 * pcie_caps_reg - get the PCIe Capabilities Register
2116 * @dev: PCI device
2117 */
2118static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2119{
2120 return dev->pcie_flags_reg;
2121}
2122
786e2288
YW		 2123/**
2124 * pci_pcie_type - get the PCIe device/port type
2125 * @dev: PCI device
2126 */
2127static inline int pci_pcie_type(const struct pci_dev *dev)
2128{
1c531d82 2129 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2130}
2131
e784930b
JT		 2132static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2133{
2134 while (1) {
2135 if (!pci_is_pcie(dev))
2136 break;
2137 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2138 return dev;
2139 if (!dev->bus->self)
2140 break;
2141 dev = dev->bus->self;
2142 }
2143 return NULL;
2144}
2145
5d990b62 2146void pci_request_acs(void);
ad805758
AW		 2147bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2148bool pci_acs_path_enabled(struct pci_dev *start,
2149 struct pci_dev *end, u16 acs_flags);
430a2368 2150int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2151
7ad506fa 2152#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2153#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2154
2155/* Large Resource Data Type Tag Item Names */
2156#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2157#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2158#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2159
2160#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2161#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2162#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2163
2164/* Small Resource Data Type Tag Item Names */
9eb45d5c 2165#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2166
9eb45d5c 2167#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2168
2169#define PCI_VPD_SRDT_TIN_MASK 0x78
2170#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2171#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2172
2173#define PCI_VPD_LRDT_TAG_SIZE 3
2174#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2175
e1d5bdab
MC		 2176#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2177
4067a854
MC		 2178#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2179#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2180#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2181#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2182
a2ce7662
MC		 2183/**
2184 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2185 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2186 *
2187 * Returns the extracted Large Resource Data Type length.
2188 */
2189static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2190{
2191 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2192}
2193
9eb45d5c
HR		 2194/**
2195 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2196 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2197 *
2198 * Returns the extracted Large Resource Data Type Tag item.
2199 */
2200static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2201{
0aa0f5d1 2202 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
9eb45d5c
HR		 2203}
2204
7ad506fa
MC		 2205/**
2206 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2207 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2208 *
2209 * Returns the extracted Small Resource Data Type length.
2210 */
2211static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2212{
2213 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2214}
2215
9eb45d5c
HR		 2216/**
2217 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2218 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2219 *
2220 * Returns the extracted Small Resource Data Type Tag Item.
2221 */
2222static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2223{
2224 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2225}
2226
e1d5bdab
MC		 2227/**
2228 * pci_vpd_info_field_size - Extracts the information field length
229b4e07 2229 * @info_field: Pointer to the beginning of an information field header
e1d5bdab
MC		 2230 *
2231 * Returns the extracted information field length.
2232 */
2233static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2234{
2235 return info_field[2];
2236}
2237
b55ac1b2
MC		 2238/**
2239 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2240 * @buf: Pointer to buffered vpd data
2241 * @off: The offset into the buffer at which to begin the search
2242 * @len: The length of the vpd buffer
2243 * @rdt: The Resource Data Type to search for
2244 *
2245 * Returns the index where the Resource Data Type was found or
2246 * -ENOENT otherwise.
2247 */
2248int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2249
4067a854
MC		 2250/**
2251 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2252 * @buf: Pointer to buffered vpd data
2253 * @off: The offset into the buffer at which to begin the search
2254 * @len: The length of the buffer area, relative to off, in which to search
2255 * @kw: The keyword to search for
2256 *
2257 * Returns the index where the information field keyword was found or
2258 * -ENOENT otherwise.
2259 */
2260int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2261 unsigned int len, const char *kw);
2262
98d9f30c
BH		 2263/* PCI <-> OF binding helpers */
2264#ifdef CONFIG_OF
2265struct device_node;
b165e2b6 2266struct irq_domain;
b165e2b6 2267struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
3a8f77e4
CP		 2268int pci_parse_request_of_pci_ranges(struct device *dev,
2269 struct list_head *resources,
331f6345 2270 struct list_head *ib_resources,
3a8f77e4 2271 struct resource **bus_range);
98d9f30c
BH		 2272
2273/* Arch may override this (weak) */
723ec4d0 2274struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2275
0aa0f5d1 2276#else /* CONFIG_OF */
b165e2b6
MZ		 2277static inline struct irq_domain *
2278pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
331f6345
RH		 2279static inline int
2280pci_parse_request_of_pci_ranges(struct device *dev,
2281 struct list_head *resources,
2282 struct list_head *ib_resources,
2283 struct resource **bus_range)
3a8f77e4
CP		 2284{
2285 return -EINVAL;
2286}
98d9f30c
BH		 2287#endif /* CONFIG_OF */
2288
ad32eb2d
BM		 2289static inline struct device_node *
2290pci_device_to_OF_node(const struct pci_dev *pdev)
2291{
2292 return pdev ? pdev->dev.of_node : NULL;
2293}
2294
2295static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2296{
2297 return bus ? bus->dev.of_node : NULL;
2298}
2299
471036b2
SS		 2300#ifdef CONFIG_ACPI
2301struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2302
2303void
2304pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
52525b7a 2305bool pci_pr3_present(struct pci_dev *pdev);
471036b2
SS		 2306#else
2307static inline struct irq_domain *
2308pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
46b4bff6 2309static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
471036b2
SS		 2310#endif
2311
eb740b5f
GS		 2312#ifdef CONFIG_EEH
2313static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2314{
2315 return pdev->dev.archdata.edev;
2316}
2317#endif
2318
09298542 2319void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
338c3149 2320bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2321int pci_for_each_dma_alias(struct pci_dev *pdev,
2322 int (*fn)(struct pci_dev *pdev,
2323 u16 alias, void *data), void *data);
2324
0aa0f5d1 2325/* Helper functions for operation of device flag */
ce052984
EZ		 2326static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2327{
2328 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2329}
2330static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2331{
2332 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2333}
2334static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2335{
2336 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2337}
19bdb6e4
AW		 2338
2339/**
2340 * pci_ari_enabled - query ARI forwarding status
2341 * @bus: the PCI bus
2342 *
2343 * Returns true if ARI forwarding is enabled.
2344 */
2345static inline bool pci_ari_enabled(struct pci_bus *bus)
2346{
2347 return bus->self && bus->self->ari_enabled;
2348}
bc4b024a 2349
8531e283
LW		 2350/**
2351 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2352 * @pdev: PCI device to check
2353 *
2354 * Walk upwards from @pdev and check for each encountered bridge if it's part
2355 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2356 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2357 */
2358static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2359{
2360 struct pci_dev *parent = pdev;
2361
2362 if (pdev->is_thunderbolt)
2363 return true;
2364
2365 while ((parent = pci_upstream_bridge(parent)))
2366 if (parent->is_thunderbolt)
2367 return true;
2368
2369 return false;
2370}
2371
2e28bc84 2372#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2373void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2374#endif
856e1eb9 2375
0aa0f5d1 2376/* Provide the legacy pci_dma_* API */
bc4b024a
CH		 2377#include <linux/pci-dma-compat.h>
2378
7506dc79
FL		 2379#define pci_printk(level, pdev, fmt, arg...) \
2380 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2381
2382#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2383#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2384#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2385#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2386#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2387#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2388#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2389#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2390
a88a7b3e
BH		 2391#define pci_notice_ratelimited(pdev, fmt, arg...) \
2392 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2393
7f1c62c4
KW		 2394#define pci_info_ratelimited(pdev, fmt, arg...) \
2395 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2396
12bcae44
BH		 2397#define pci_WARN(pdev, condition, fmt, arg...) \
2398 WARN(condition, "%s %s: " fmt, \
2399 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2400
2401#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2402 WARN_ONCE(condition, "%s %s: " fmt, \
2403 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2404
1da177e4 2405#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)