Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 | 53 | #include <linux/device.h> |
1388cc96 | 54 | #include <linux/io.h> |
74bb1bcc | 55 | #include <linux/irqreturn.h> |
1da177e4 | 56 | |
7e7a43c3 AB |
57 | /* Include the ID list */ |
58 | #include <linux/pci_ids.h> | |
59 | ||
f46753c5 AC |
60 | /* pci_slot represents a physical slot */ |
61 | struct pci_slot { | |
62 | struct pci_bus *bus; /* The bus this slot is on */ | |
63 | struct list_head list; /* node in list of slots on this bus */ | |
64 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
65 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
66 | struct kobject kobj; | |
67 | }; | |
68 | ||
0ad772ec AC |
69 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
70 | { | |
71 | return kobject_name(&slot->kobj); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
75 | enum pci_mmap_state { | |
76 | pci_mmap_io, | |
77 | pci_mmap_mem | |
78 | }; | |
79 | ||
80 | /* This defines the direction arg to the DMA mapping routines. */ | |
81 | #define PCI_DMA_BIDIRECTIONAL 0 | |
82 | #define PCI_DMA_TODEVICE 1 | |
83 | #define PCI_DMA_FROMDEVICE 2 | |
84 | #define PCI_DMA_NONE 3 | |
85 | ||
fde09c6d YZ |
86 | /* |
87 | * For PCI devices, the region numbers are assigned this way: | |
88 | */ | |
89 | enum { | |
90 | /* #0-5: standard PCI resources */ | |
91 | PCI_STD_RESOURCES, | |
92 | PCI_STD_RESOURCE_END = 5, | |
93 | ||
94 | /* #6: expansion ROM resource */ | |
95 | PCI_ROM_RESOURCE, | |
96 | ||
d1b054da YZ |
97 | /* device specific resources */ |
98 | #ifdef CONFIG_PCI_IOV | |
99 | PCI_IOV_RESOURCES, | |
100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
101 | #endif | |
102 | ||
fde09c6d YZ |
103 | /* resources assigned to buses behind the bridge */ |
104 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
105 | ||
106 | PCI_BRIDGE_RESOURCES, | |
107 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
108 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
109 | ||
110 | /* total resources associated with a PCI device */ | |
111 | PCI_NUM_RESOURCES, | |
112 | ||
113 | /* preserve this for compatibility */ | |
114 | DEVICE_COUNT_RESOURCE | |
115 | }; | |
1da177e4 LT |
116 | |
117 | typedef int __bitwise pci_power_t; | |
118 | ||
4352dfd5 GKH |
119 | #define PCI_D0 ((pci_power_t __force) 0) |
120 | #define PCI_D1 ((pci_power_t __force) 1) | |
121 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
122 | #define PCI_D3hot ((pci_power_t __force) 3) |
123 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 124 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 125 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 126 | |
00240c38 AS |
127 | /* Remember to update this when the list above changes! */ |
128 | extern const char *pci_power_names[]; | |
129 | ||
130 | static inline const char *pci_power_name(pci_power_t state) | |
131 | { | |
132 | return pci_power_names[1 + (int) state]; | |
133 | } | |
134 | ||
aa8c6c93 RW |
135 | #define PCI_PM_D2_DELAY 200 |
136 | #define PCI_PM_D3_WAIT 10 | |
137 | #define PCI_PM_BUS_WAIT 50 | |
138 | ||
392a1ce7 | 139 | /** The pci_channel state describes connectivity between the CPU and |
140 | * the pci device. If some PCI bus between here and the pci device | |
141 | * has crashed or locked up, this info is reflected here. | |
142 | */ | |
143 | typedef unsigned int __bitwise pci_channel_state_t; | |
144 | ||
145 | enum pci_channel_state { | |
146 | /* I/O channel is in normal state */ | |
147 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
148 | ||
149 | /* I/O to channel is blocked */ | |
150 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
151 | ||
152 | /* PCI card is dead */ | |
153 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
154 | }; | |
155 | ||
f7bdd12d BK |
156 | typedef unsigned int __bitwise pcie_reset_state_t; |
157 | ||
158 | enum pcie_reset_state { | |
159 | /* Reset is NOT asserted (Use to deassert reset) */ | |
160 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
161 | ||
162 | /* Use #PERST to reset PCI-E device */ | |
163 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
164 | ||
165 | /* Use PCI-E Hot Reset to reset device */ | |
166 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
167 | }; | |
168 | ||
ba698ad4 DM |
169 | typedef unsigned short __bitwise pci_dev_flags_t; |
170 | enum pci_dev_flags { | |
171 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
172 | * generation too. | |
173 | */ | |
174 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
175 | /* Device configuration is irrevocably lost if disabled into D3 */ |
176 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
ba698ad4 DM |
177 | }; |
178 | ||
e1d3a908 SA |
179 | enum pci_irq_reroute_variant { |
180 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
181 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
182 | }; | |
183 | ||
6e325a62 MT |
184 | typedef unsigned short __bitwise pci_bus_flags_t; |
185 | enum pci_bus_flags { | |
d556ad4b PO |
186 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
187 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
188 | }; |
189 | ||
536c8cb4 MW |
190 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
191 | enum pci_bus_speed { | |
192 | PCI_SPEED_33MHz = 0x00, | |
193 | PCI_SPEED_66MHz = 0x01, | |
194 | PCI_SPEED_66MHz_PCIX = 0x02, | |
195 | PCI_SPEED_100MHz_PCIX = 0x03, | |
196 | PCI_SPEED_133MHz_PCIX = 0x04, | |
197 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
198 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
199 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
200 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
201 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
202 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
203 | AGP_UNKNOWN = 0x0c, |
204 | AGP_1X = 0x0d, | |
205 | AGP_2X = 0x0e, | |
206 | AGP_4X = 0x0f, | |
207 | AGP_8X = 0x10, | |
536c8cb4 MW |
208 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
209 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
210 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
211 | PCIE_SPEED_2_5GT = 0x14, | |
212 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 213 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
214 | PCI_SPEED_UNKNOWN = 0xff, |
215 | }; | |
216 | ||
41017f0c SL |
217 | struct pci_cap_saved_state { |
218 | struct hlist_node next; | |
219 | char cap_nr; | |
220 | u32 data[0]; | |
221 | }; | |
222 | ||
7d715a6c | 223 | struct pcie_link_state; |
ee69439c | 224 | struct pci_vpd; |
d1b054da | 225 | struct pci_sriov; |
302b4215 | 226 | struct pci_ats; |
ee69439c | 227 | |
1da177e4 LT |
228 | /* |
229 | * The pci_dev structure is used to describe PCI devices. | |
230 | */ | |
231 | struct pci_dev { | |
1da177e4 LT |
232 | struct list_head bus_list; /* node in per-bus list */ |
233 | struct pci_bus *bus; /* bus this device is on */ | |
234 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
235 | ||
236 | void *sysdata; /* hook for sys-specific extension */ | |
237 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 238 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
239 | |
240 | unsigned int devfn; /* encoded device & function index */ | |
241 | unsigned short vendor; | |
242 | unsigned short device; | |
243 | unsigned short subsystem_vendor; | |
244 | unsigned short subsystem_device; | |
245 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 246 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 247 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
0efea000 | 248 | u8 pcie_cap; /* PCI-E capability offset */ |
994a65e2 | 249 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 250 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 251 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
252 | |
253 | struct pci_driver *driver; /* which driver has allocated this device */ | |
254 | u64 dma_mask; /* Mask of the bits of bus address this | |
255 | device implements. Normally this is | |
256 | 0xffffffff. You only need to change | |
257 | this if your device has broken DMA | |
258 | or supports 64-bit transfers. */ | |
259 | ||
4d57cdfa FT |
260 | struct device_dma_parameters dma_parms; |
261 | ||
1da177e4 LT |
262 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
263 | this is D0-D3, D0 being fully functional, | |
264 | and D3 being off. */ | |
337001b6 RW |
265 | int pm_cap; /* PM capability offset in the |
266 | configuration space */ | |
267 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
268 | can be generated */ | |
269 | unsigned int d1_support:1; /* Low power state D1 is supported */ | |
270 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
271 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
e80bb09d | 272 | unsigned int wakeup_prepared:1; |
1ae861e6 | 273 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
1da177e4 | 274 | |
7d715a6c SL |
275 | #ifdef CONFIG_PCIEASPM |
276 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
277 | #endif | |
278 | ||
392a1ce7 | 279 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
280 | struct device dev; /* Generic device interface */ |
281 | ||
1da177e4 LT |
282 | int cfg_size; /* Size of configuration space */ |
283 | ||
284 | /* | |
285 | * Instead of touching interrupt line and base address registers | |
286 | * directly, use the values stored here. They might be different! | |
287 | */ | |
288 | unsigned int irq; | |
289 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
290 | ||
291 | /* These fields are used by common fixups */ | |
292 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
293 | unsigned int multifunction:1;/* Part of multi-function device */ | |
294 | /* keep track of device state */ | |
8a1bc901 | 295 | unsigned int is_added:1; |
1da177e4 | 296 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 297 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 298 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 299 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 300 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
301 | unsigned int msi_enabled:1; |
302 | unsigned int msix_enabled:1; | |
58c3a727 | 303 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 304 | unsigned int is_managed:1; |
994a65e2 | 305 | unsigned int is_pcie:1; |
260d703a | 306 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 307 | unsigned int state_saved:1; |
d1b054da | 308 | unsigned int is_physfn:1; |
dd7cc44d | 309 | unsigned int is_virtfn:1; |
711d5779 | 310 | unsigned int reset_fn:1; |
28760489 | 311 | unsigned int is_hotplug_bridge:1; |
05843961 | 312 | unsigned int aer_firmware_first:1; |
ba698ad4 | 313 | pci_dev_flags_t dev_flags; |
bae94d02 | 314 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 315 | |
1da177e4 | 316 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 317 | struct hlist_head saved_cap_space; |
1da177e4 LT |
318 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
319 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
320 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 321 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 322 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 323 | struct list_head msi_list; |
ded86d8d | 324 | #endif |
94e61088 | 325 | struct pci_vpd *vpd; |
d1b054da | 326 | #ifdef CONFIG_PCI_IOV |
dd7cc44d YZ |
327 | union { |
328 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
329 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
330 | }; | |
302b4215 | 331 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 332 | #endif |
1da177e4 LT |
333 | }; |
334 | ||
65891215 ME |
335 | extern struct pci_dev *alloc_pci_dev(void); |
336 | ||
1da177e4 LT |
337 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
338 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
339 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
340 | ||
a7369f1f LV |
341 | static inline int pci_channel_offline(struct pci_dev *pdev) |
342 | { | |
343 | return (pdev->error_state != pci_channel_io_normal); | |
344 | } | |
345 | ||
41017f0c | 346 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 347 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
348 | { |
349 | struct pci_cap_saved_state *tmp; | |
350 | struct hlist_node *pos; | |
351 | ||
352 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
353 | if (tmp->cap_nr == cap) | |
354 | return tmp; | |
355 | } | |
356 | return NULL; | |
357 | } | |
358 | ||
359 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
360 | struct pci_cap_saved_state *new_cap) | |
361 | { | |
362 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
363 | } | |
364 | ||
1da177e4 | 365 | #ifndef PCI_BUS_NUM_RESOURCES |
30a18d6c | 366 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 367 | #endif |
4352dfd5 GKH |
368 | |
369 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
370 | |
371 | struct pci_bus { | |
372 | struct list_head node; /* node in list of buses */ | |
373 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
374 | struct list_head children; /* list of child buses */ | |
375 | struct list_head devices; /* list of devices on this bus */ | |
376 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 377 | struct list_head slots; /* list of slots on this bus */ |
1da177e4 LT |
378 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; |
379 | /* address space routed to this bus */ | |
380 | ||
381 | struct pci_ops *ops; /* configuration access functions */ | |
382 | void *sysdata; /* hook for sys-specific extension */ | |
383 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
384 | ||
385 | unsigned char number; /* bus number */ | |
386 | unsigned char primary; /* number of primary bridge */ | |
387 | unsigned char secondary; /* number of secondary bridge */ | |
388 | unsigned char subordinate; /* max number of subordinate buses */ | |
3749c51a MW |
389 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
390 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
1da177e4 LT |
391 | |
392 | char name[48]; | |
393 | ||
394 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 395 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 396 | struct device *bridge; |
fd7d1ced | 397 | struct device dev; |
1da177e4 LT |
398 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
399 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 400 | unsigned int is_added:1; |
1da177e4 LT |
401 | }; |
402 | ||
403 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 404 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 405 | |
79af72d7 KK |
406 | /* |
407 | * Returns true if the pci bus is root (behind host-pci bridge), | |
408 | * false otherwise | |
409 | */ | |
410 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
411 | { | |
412 | return !(pbus->parent); | |
413 | } | |
414 | ||
16cf0ebc RW |
415 | #ifdef CONFIG_PCI_MSI |
416 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
417 | { | |
418 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
419 | } | |
420 | #else | |
421 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
422 | #endif | |
423 | ||
1da177e4 LT |
424 | /* |
425 | * Error values that may be returned by PCI functions. | |
426 | */ | |
427 | #define PCIBIOS_SUCCESSFUL 0x00 | |
428 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
429 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
430 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
431 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
432 | #define PCIBIOS_SET_FAILED 0x88 | |
433 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
434 | ||
435 | /* Low-level architecture-dependent routines */ | |
436 | ||
437 | struct pci_ops { | |
438 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
439 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
440 | }; | |
441 | ||
b6ce068a MW |
442 | /* |
443 | * ACPI needs to be able to access PCI config space before we've done a | |
444 | * PCI bus scan and created pci_bus structures. | |
445 | */ | |
446 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
447 | unsigned int devfn, int reg, int len, u32 *val); | |
448 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
449 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
450 | |
451 | struct pci_bus_region { | |
c40a22e0 BH |
452 | resource_size_t start; |
453 | resource_size_t end; | |
1da177e4 LT |
454 | }; |
455 | ||
456 | struct pci_dynids { | |
457 | spinlock_t lock; /* protects list, index */ | |
458 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
459 | }; |
460 | ||
392a1ce7 | 461 | /* ---------------------------------------------------------------- */ |
462 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 463 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 464 | * will be notified of PCI bus errors, and will be driven to recovery |
465 | * when an error occurs. | |
466 | */ | |
467 | ||
468 | typedef unsigned int __bitwise pci_ers_result_t; | |
469 | ||
470 | enum pci_ers_result { | |
471 | /* no result/none/not supported in device driver */ | |
472 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
473 | ||
474 | /* Device driver can recover without slot reset */ | |
475 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
476 | ||
477 | /* Device driver wants slot to be reset. */ | |
478 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
479 | ||
480 | /* Device has completely failed, is unrecoverable */ | |
481 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
482 | ||
483 | /* Device driver is fully recovered and operational */ | |
484 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
485 | }; | |
486 | ||
487 | /* PCI bus error event callbacks */ | |
05cca6e5 | 488 | struct pci_error_handlers { |
392a1ce7 | 489 | /* PCI bus error detected on this device */ |
490 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 491 | enum pci_channel_state error); |
392a1ce7 | 492 | |
493 | /* MMIO has been re-enabled, but not DMA */ | |
494 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
495 | ||
496 | /* PCI Express link has been reset */ | |
497 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
498 | ||
499 | /* PCI slot has been reset */ | |
500 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
501 | ||
502 | /* Device driver may resume normal operations */ | |
503 | void (*resume)(struct pci_dev *dev); | |
504 | }; | |
505 | ||
506 | /* ---------------------------------------------------------------- */ | |
507 | ||
1da177e4 LT |
508 | struct module; |
509 | struct pci_driver { | |
510 | struct list_head node; | |
511 | char *name; | |
1da177e4 LT |
512 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
513 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
514 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
515 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
516 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
517 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 518 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 519 | void (*shutdown) (struct pci_dev *dev); |
392a1ce7 | 520 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
521 | struct device_driver driver; |
522 | struct pci_dynids dynids; | |
523 | }; | |
524 | ||
05cca6e5 | 525 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 526 | |
90a1ba0c | 527 | /** |
9f9351bb | 528 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
529 | * @_table: device table name |
530 | * | |
531 | * This macro is used to create a struct pci_device_id array (a device table) | |
532 | * in a generic manner. | |
533 | */ | |
9f9351bb | 534 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
535 | const struct pci_device_id _table[] __devinitconst |
536 | ||
1da177e4 LT |
537 | /** |
538 | * PCI_DEVICE - macro used to describe a specific pci device | |
539 | * @vend: the 16 bit PCI Vendor ID | |
540 | * @dev: the 16 bit PCI Device ID | |
541 | * | |
542 | * This macro is used to create a struct pci_device_id that matches a | |
543 | * specific device. The subvendor and subdevice fields will be set to | |
544 | * PCI_ANY_ID. | |
545 | */ | |
546 | #define PCI_DEVICE(vend,dev) \ | |
547 | .vendor = (vend), .device = (dev), \ | |
548 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
549 | ||
550 | /** | |
551 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
552 | * @dev_class: the class, subclass, prog-if triple for this device | |
553 | * @dev_class_mask: the class mask for this device | |
554 | * | |
555 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 556 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
557 | * fields will be set to PCI_ANY_ID. |
558 | */ | |
559 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
560 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
561 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
562 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
563 | ||
1597cacb AC |
564 | /** |
565 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
566 | * @vendor: the vendor name |
567 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
568 | * |
569 | * This macro is used to create a struct pci_device_id that matches a | |
570 | * specific PCI device. The subvendor, and subdevice fields will be set | |
571 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
572 | * private data. | |
573 | */ | |
574 | ||
575 | #define PCI_VDEVICE(vendor, device) \ | |
576 | PCI_VENDOR_ID_##vendor, (device), \ | |
577 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
578 | ||
1da177e4 LT |
579 | /* these external functions are only available when PCI support is enabled */ |
580 | #ifdef CONFIG_PCI | |
581 | ||
582 | extern struct bus_type pci_bus_type; | |
583 | ||
584 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
585 | * code, or pci core code. */ | |
586 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
587 | /* Some device drivers need know if pci is initiated */ |
588 | extern int no_pci_devices(void); | |
1da177e4 LT |
589 | |
590 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 591 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 592 | char *pcibios_setup(char *str); |
1da177e4 LT |
593 | |
594 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
595 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
596 | resource_size_t); | |
1da177e4 LT |
597 | void pcibios_update_irq(struct pci_dev *, int irq); |
598 | ||
2d1c8618 BH |
599 | /* Weak but can be overriden by arch */ |
600 | void pci_fixup_cardbus(struct pci_bus *); | |
601 | ||
1da177e4 LT |
602 | /* Generic PCI functions used internally */ |
603 | ||
604 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c48f1670 | 605 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
606 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
607 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 608 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 609 | void *sysdata) |
1da177e4 | 610 | { |
c431ada4 RS |
611 | struct pci_bus *root_bus; |
612 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
613 | if (root_bus) | |
614 | pci_bus_add_devices(root_bus); | |
615 | return root_bus; | |
1da177e4 | 616 | } |
05cca6e5 GKH |
617 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
618 | struct pci_ops *ops, void *sysdata); | |
619 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
620 | int busnr); | |
3749c51a | 621 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 622 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
623 | const char *name, |
624 | struct hotplug_slot *hotplug); | |
f46753c5 | 625 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 626 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 627 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 628 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 629 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 630 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 631 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 632 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
633 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
634 | struct resource *res); | |
57c2cf71 | 635 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
1da177e4 | 636 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 637 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
1da177e4 LT |
638 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
639 | extern void pci_dev_put(struct pci_dev *dev); | |
640 | extern void pci_remove_bus(struct pci_bus *b); | |
641 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 642 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 643 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 644 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
645 | |
646 | /* Generic PCI functions exported to card drivers */ | |
647 | ||
bd3989e0 | 648 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
649 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
650 | unsigned int device, | |
b08508c4 | 651 | struct pci_dev *from); |
bd3989e0 JG |
652 | #endif /* CONFIG_PCI_LEGACY */ |
653 | ||
388c8c16 JB |
654 | enum pci_lost_interrupt_reason { |
655 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
656 | PCI_LOST_IRQ_DISABLE_MSI, | |
657 | PCI_LOST_IRQ_DISABLE_MSIX, | |
658 | PCI_LOST_IRQ_DISABLE_ACPI, | |
659 | }; | |
660 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
661 | int pci_find_capability(struct pci_dev *dev, int cap); |
662 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
663 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
664 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
665 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 666 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 667 | |
d42552c3 AM |
668 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
669 | struct pci_dev *from); | |
05cca6e5 | 670 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 671 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 672 | struct pci_dev *from); |
05cca6e5 | 673 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
674 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
675 | unsigned int devfn); | |
676 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
677 | unsigned int devfn) | |
678 | { | |
679 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
680 | } | |
05cca6e5 | 681 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
682 | int pci_dev_present(const struct pci_device_id *ids); |
683 | ||
05cca6e5 GKH |
684 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
685 | int where, u8 *val); | |
686 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
687 | int where, u16 *val); | |
688 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
689 | int where, u32 *val); | |
690 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
691 | int where, u8 val); | |
692 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
693 | int where, u16 val); | |
694 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
695 | int where, u32 val); | |
a72b46c3 | 696 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 LT |
697 | |
698 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
699 | { | |
05cca6e5 | 700 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
701 | } |
702 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
703 | { | |
05cca6e5 | 704 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 705 | } |
05cca6e5 GKH |
706 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
707 | u32 *val) | |
1da177e4 | 708 | { |
05cca6e5 | 709 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
710 | } |
711 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
712 | { | |
05cca6e5 | 713 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
714 | } |
715 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
716 | { | |
05cca6e5 | 717 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 718 | } |
05cca6e5 GKH |
719 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
720 | u32 val) | |
1da177e4 | 721 | { |
05cca6e5 | 722 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
723 | } |
724 | ||
4a7fb636 | 725 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
726 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
727 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 728 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
729 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
730 | void pcim_pin_device(struct pci_dev *pdev); | |
731 | ||
296ccb08 YS |
732 | static inline int pci_is_enabled(struct pci_dev *pdev) |
733 | { | |
734 | return (atomic_read(&pdev->enable_cnt) > 0); | |
735 | } | |
736 | ||
9ac7849e TH |
737 | static inline int pci_is_managed(struct pci_dev *pdev) |
738 | { | |
739 | return pdev->is_managed; | |
740 | } | |
741 | ||
1da177e4 LT |
742 | void pci_disable_device(struct pci_dev *dev); |
743 | void pci_set_master(struct pci_dev *dev); | |
6a479079 | 744 | void pci_clear_master(struct pci_dev *dev); |
f7bdd12d | 745 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 746 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 747 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 748 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 749 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 750 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 751 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 752 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
753 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
754 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 755 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 756 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
757 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
758 | int pcix_get_mmrbc(struct pci_dev *dev); | |
759 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 760 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 761 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
8c1c699f | 762 | int __pci_reset_function(struct pci_dev *dev); |
8dd7f803 | 763 | int pci_reset_function(struct pci_dev *dev); |
14add80b | 764 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 765 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 766 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
767 | |
768 | /* ROM control related routines */ | |
e416de5e AC |
769 | int pci_enable_rom(struct pci_dev *pdev); |
770 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 771 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 772 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 773 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
1da177e4 LT |
774 | |
775 | /* Power management related routines */ | |
776 | int pci_save_state(struct pci_dev *dev); | |
777 | int pci_restore_state(struct pci_dev *dev); | |
0e5dd46b | 778 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
779 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
780 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 781 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 782 | void pci_pme_active(struct pci_dev *dev, bool enable); |
7d9a73f6 | 783 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 784 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 785 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
786 | int pci_prepare_to_sleep(struct pci_dev *dev); |
787 | int pci_back_from_sleep(struct pci_dev *dev); | |
1da177e4 | 788 | |
bb209c82 BH |
789 | /* For use by arch with custom probe code */ |
790 | void set_pcie_port_type(struct pci_dev *pdev); | |
791 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
792 | ||
ce5ccdef | 793 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 794 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
3ed4fd96 AC |
795 | #ifdef CONFIG_HOTPLUG |
796 | unsigned int pci_rescan_bus(struct pci_bus *bus); | |
797 | #endif | |
ce5ccdef | 798 | |
287d19ce SH |
799 | /* Vital product data routines */ |
800 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
801 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 802 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 803 | |
1da177e4 | 804 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
ea741551 | 805 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
806 | void pci_bus_size_bridges(struct pci_bus *bus); |
807 | int pci_claim_resource(struct pci_dev *, int); | |
808 | void pci_assign_unassigned_resources(void); | |
809 | void pdev_enable_device(struct pci_dev *); | |
810 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 811 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
812 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
813 | int (*)(struct pci_dev *, u8, u8)); | |
814 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 815 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 816 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 817 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 818 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 819 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 820 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 821 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 822 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 823 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
824 | |
825 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
826 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
827 | struct resource *res, resource_size_t size, | |
828 | resource_size_t align, resource_size_t min, | |
829 | unsigned int type_mask, | |
830 | void (*alignf)(void *, struct resource *, | |
831 | resource_size_t, resource_size_t), | |
832 | void *alignf_data); | |
1da177e4 LT |
833 | void pci_enable_bridges(struct pci_bus *bus); |
834 | ||
863b18f4 | 835 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
836 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
837 | const char *mod_name); | |
bba81165 AM |
838 | |
839 | /* | |
840 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
841 | */ | |
842 | #define pci_register_driver(driver) \ | |
843 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 844 | |
05cca6e5 GKH |
845 | void pci_unregister_driver(struct pci_driver *dev); |
846 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
847 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
9dba910e TH |
848 | int pci_add_dynid(struct pci_driver *drv, |
849 | unsigned int vendor, unsigned int device, | |
850 | unsigned int subvendor, unsigned int subdevice, | |
851 | unsigned int class, unsigned int class_mask, | |
852 | unsigned long driver_data); | |
05cca6e5 GKH |
853 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
854 | struct pci_dev *dev); | |
855 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
856 | int pass); | |
1da177e4 | 857 | |
70298c6e | 858 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 859 | void *userdata); |
70b9f7dc | 860 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 861 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 862 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 863 | |
deb2d2ec BH |
864 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
865 | unsigned int command_bits, bool change_bridge); | |
1da177e4 LT |
866 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
867 | ||
868 | #include <linux/dmapool.h> | |
869 | ||
870 | #define pci_pool dma_pool | |
871 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
872 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
873 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
874 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
875 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
876 | ||
e24c2d96 DM |
877 | enum pci_dma_burst_strategy { |
878 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
879 | strategy_parameter is N/A */ | |
880 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
881 | byte boundaries */ | |
882 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
883 | strategy_parameter byte boundaries */ | |
884 | }; | |
885 | ||
1da177e4 | 886 | struct msix_entry { |
16dbef4a | 887 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
888 | u16 entry; /* driver uses to specify entry, OS writes */ |
889 | }; | |
890 | ||
0366f8f7 | 891 | |
1da177e4 | 892 | #ifndef CONFIG_PCI_MSI |
1c8d7b0a | 893 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
05cca6e5 GKH |
894 | { |
895 | return -1; | |
896 | } | |
897 | ||
d52877c7 YL |
898 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
899 | { } | |
05cca6e5 GKH |
900 | static inline void pci_disable_msi(struct pci_dev *dev) |
901 | { } | |
902 | ||
a52e2e35 RW |
903 | static inline int pci_msix_table_size(struct pci_dev *dev) |
904 | { | |
905 | return 0; | |
906 | } | |
05cca6e5 GKH |
907 | static inline int pci_enable_msix(struct pci_dev *dev, |
908 | struct msix_entry *entries, int nvec) | |
909 | { | |
910 | return -1; | |
911 | } | |
912 | ||
d52877c7 YL |
913 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
914 | { } | |
05cca6e5 GKH |
915 | static inline void pci_disable_msix(struct pci_dev *dev) |
916 | { } | |
917 | ||
918 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
919 | { } | |
920 | ||
921 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
922 | { } | |
07ae95f9 AP |
923 | static inline int pci_msi_enabled(void) |
924 | { | |
925 | return 0; | |
926 | } | |
1da177e4 | 927 | #else |
1c8d7b0a | 928 | extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
d52877c7 | 929 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 930 | extern void pci_disable_msi(struct pci_dev *dev); |
a52e2e35 | 931 | extern int pci_msix_table_size(struct pci_dev *dev); |
05cca6e5 | 932 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 933 | struct msix_entry *entries, int nvec); |
d52877c7 | 934 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
935 | extern void pci_disable_msix(struct pci_dev *dev); |
936 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 937 | extern void pci_restore_msi_state(struct pci_dev *dev); |
07ae95f9 | 938 | extern int pci_msi_enabled(void); |
1da177e4 LT |
939 | #endif |
940 | ||
3e1b1600 AP |
941 | #ifndef CONFIG_PCIEASPM |
942 | static inline int pcie_aspm_enabled(void) | |
943 | { | |
944 | return 0; | |
945 | } | |
946 | #else | |
947 | extern int pcie_aspm_enabled(void); | |
948 | #endif | |
949 | ||
43c16408 AP |
950 | #ifndef CONFIG_PCIE_ECRC |
951 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) | |
952 | { | |
953 | return; | |
954 | } | |
955 | static inline void pcie_ecrc_get_policy(char *str) {}; | |
956 | #else | |
957 | extern void pcie_set_ecrc_checking(struct pci_dev *dev); | |
958 | extern void pcie_ecrc_get_policy(char *str); | |
959 | #endif | |
960 | ||
1c8d7b0a MW |
961 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
962 | ||
8b955b0d | 963 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
964 | /* The functions a driver should call */ |
965 | int ht_create_irq(struct pci_dev *dev, int idx); | |
966 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
967 | #endif /* CONFIG_HT_IRQ */ |
968 | ||
e04b0ea2 BK |
969 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
970 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
971 | ||
4352dfd5 GKH |
972 | /* |
973 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
974 | * a PCI domain is defined to be a set of PCI busses which share | |
975 | * configuration space. | |
976 | */ | |
32a2eea7 JG |
977 | #ifdef CONFIG_PCI_DOMAINS |
978 | extern int pci_domains_supported; | |
979 | #else | |
980 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
981 | static inline int pci_domain_nr(struct pci_bus *bus) |
982 | { | |
983 | return 0; | |
984 | } | |
985 | ||
4352dfd5 GKH |
986 | static inline int pci_proc_domain(struct pci_bus *bus) |
987 | { | |
988 | return 0; | |
989 | } | |
32a2eea7 | 990 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 991 | |
4352dfd5 | 992 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
993 | |
994 | /* | |
995 | * If the system does not have PCI, clearly these return errors. Define | |
996 | * these as simple inline functions to avoid hair in drivers. | |
997 | */ | |
998 | ||
05cca6e5 GKH |
999 | #define _PCI_NOP(o, s, t) \ |
1000 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1001 | int where, t val) \ | |
1da177e4 | 1002 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1003 | |
1004 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1005 | _PCI_NOP(o, word, u16 x) \ | |
1006 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1007 | _PCI_NOP_ALL(read, *) |
1008 | _PCI_NOP_ALL(write,) | |
1009 | ||
05cca6e5 GKH |
1010 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
1011 | unsigned int device, | |
b08508c4 | 1012 | struct pci_dev *from) |
05cca6e5 GKH |
1013 | { |
1014 | return NULL; | |
1015 | } | |
1da177e4 | 1016 | |
d42552c3 | 1017 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1018 | unsigned int device, |
1019 | struct pci_dev *from) | |
1020 | { | |
1021 | return NULL; | |
1022 | } | |
d42552c3 | 1023 | |
05cca6e5 GKH |
1024 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1025 | unsigned int device, | |
1026 | unsigned int ss_vendor, | |
1027 | unsigned int ss_device, | |
b08508c4 | 1028 | struct pci_dev *from) |
05cca6e5 GKH |
1029 | { |
1030 | return NULL; | |
1031 | } | |
1da177e4 | 1032 | |
05cca6e5 GKH |
1033 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1034 | struct pci_dev *from) | |
1035 | { | |
1036 | return NULL; | |
1037 | } | |
1da177e4 LT |
1038 | |
1039 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1040 | #define no_pci_devices() (1) |
1da177e4 LT |
1041 | #define pci_dev_put(dev) do { } while (0) |
1042 | ||
05cca6e5 GKH |
1043 | static inline void pci_set_master(struct pci_dev *dev) |
1044 | { } | |
1045 | ||
1046 | static inline int pci_enable_device(struct pci_dev *dev) | |
1047 | { | |
1048 | return -EIO; | |
1049 | } | |
1050 | ||
1051 | static inline void pci_disable_device(struct pci_dev *dev) | |
1052 | { } | |
1053 | ||
1054 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1055 | { | |
1056 | return -EIO; | |
1057 | } | |
1058 | ||
80be0385 RD |
1059 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1060 | { | |
1061 | return -EIO; | |
1062 | } | |
1063 | ||
4d57cdfa FT |
1064 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1065 | unsigned int size) | |
1066 | { | |
1067 | return -EIO; | |
1068 | } | |
1069 | ||
59fc67de FT |
1070 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1071 | unsigned long mask) | |
1072 | { | |
1073 | return -EIO; | |
1074 | } | |
1075 | ||
05cca6e5 GKH |
1076 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1077 | { | |
1078 | return -EBUSY; | |
1079 | } | |
1080 | ||
1081 | static inline int __pci_register_driver(struct pci_driver *drv, | |
1082 | struct module *owner) | |
1083 | { | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static inline int pci_register_driver(struct pci_driver *drv) | |
1088 | { | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
1093 | { } | |
1094 | ||
1095 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
1096 | { | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
1101 | int cap) | |
1102 | { | |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
1107 | { | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1da177e4 | 1111 | /* Power management related routines */ |
05cca6e5 GKH |
1112 | static inline int pci_save_state(struct pci_dev *dev) |
1113 | { | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static inline int pci_restore_state(struct pci_dev *dev) | |
1118 | { | |
1119 | return 0; | |
1120 | } | |
1da177e4 | 1121 | |
05cca6e5 GKH |
1122 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1123 | { | |
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
1128 | pm_message_t state) | |
1129 | { | |
1130 | return PCI_D0; | |
1131 | } | |
1132 | ||
1133 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1134 | int enable) | |
1135 | { | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
1140 | { | |
1141 | return -EIO; | |
1142 | } | |
1143 | ||
1144 | static inline void pci_release_regions(struct pci_dev *dev) | |
1145 | { } | |
0da0ead9 | 1146 | |
a46e8126 KG |
1147 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1148 | ||
05cca6e5 GKH |
1149 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
1150 | { } | |
1151 | ||
1152 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
1153 | { } | |
e04b0ea2 | 1154 | |
d80d0217 RD |
1155 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1156 | { return NULL; } | |
1157 | ||
1158 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1159 | unsigned int devfn) | |
1160 | { return NULL; } | |
1161 | ||
1162 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1163 | unsigned int devfn) | |
1164 | { return NULL; } | |
1165 | ||
4352dfd5 | 1166 | #endif /* CONFIG_PCI */ |
1da177e4 | 1167 | |
4352dfd5 GKH |
1168 | /* Include architecture-dependent settings and functions */ |
1169 | ||
1170 | #include <asm/pci.h> | |
1da177e4 | 1171 | |
1f82de10 YL |
1172 | #ifndef PCIBIOS_MAX_MEM_32 |
1173 | #define PCIBIOS_MAX_MEM_32 (-1) | |
1174 | #endif | |
1175 | ||
1da177e4 LT |
1176 | /* these helpers provide future and backwards compatibility |
1177 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1178 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1179 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1180 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1181 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1182 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1183 | pci_resource_end((dev), (bar)) == \ | |
1184 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1185 | \ | |
1186 | (pci_resource_end((dev), (bar)) - \ | |
1187 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1188 | |
1189 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1190 | * driver-specific data. They are really just a wrapper around | |
1191 | * the generic device structure functions of these calls. | |
1192 | */ | |
05cca6e5 | 1193 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1194 | { |
1195 | return dev_get_drvdata(&pdev->dev); | |
1196 | } | |
1197 | ||
05cca6e5 | 1198 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1199 | { |
1200 | dev_set_drvdata(&pdev->dev, data); | |
1201 | } | |
1202 | ||
1203 | /* If you want to know what to call your pci_dev, ask this function. | |
1204 | * Again, it's a wrapper around the generic device. | |
1205 | */ | |
2fc90f61 | 1206 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1207 | { |
c6c4f070 | 1208 | return dev_name(&pdev->dev); |
1da177e4 LT |
1209 | } |
1210 | ||
2311b1f2 ME |
1211 | |
1212 | /* Some archs don't want to expose struct resource to userland as-is | |
1213 | * in sysfs and /proc | |
1214 | */ | |
1215 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1216 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1217 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1218 | resource_size_t *end) |
2311b1f2 ME |
1219 | { |
1220 | *start = rsrc->start; | |
1221 | *end = rsrc->end; | |
1222 | } | |
1223 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1224 | ||
1225 | ||
1da177e4 LT |
1226 | /* |
1227 | * The world is not perfect and supplies us with broken PCI devices. | |
1228 | * For at least a part of these bugs we need a work-around, so both | |
1229 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1230 | * fixup hooks to be called for particular buggy devices. | |
1231 | */ | |
1232 | ||
1233 | struct pci_fixup { | |
1234 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1235 | void (*hook)(struct pci_dev *dev); | |
1236 | }; | |
1237 | ||
1238 | enum pci_fixup_pass { | |
1239 | pci_fixup_early, /* Before probing BARs */ | |
1240 | pci_fixup_header, /* After reading configuration header */ | |
1241 | pci_fixup_final, /* Final phase of device fixups */ | |
1242 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1243 | pci_fixup_resume, /* pci_device_resume() */ |
1244 | pci_fixup_suspend, /* pci_device_suspend */ | |
1245 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1246 | }; |
1247 | ||
1248 | /* Anonymous variables would be nice... */ | |
1249 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1250 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1251 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1252 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1253 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1254 | vendor##device##hook, vendor, device, hook) | |
1255 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1256 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1257 | vendor##device##hook, vendor, device, hook) | |
1258 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1259 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1260 | vendor##device##hook, vendor, device, hook) | |
1261 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1262 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1263 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1264 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1265 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1266 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1267 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1268 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1269 | resume_early##vendor##device##hook, vendor, device, hook) | |
1270 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1271 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1272 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 | 1273 | |
93177a74 | 1274 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1275 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
1276 | #else |
1277 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
1278 | struct pci_dev *dev) {} | |
1279 | #endif | |
1da177e4 | 1280 | |
05cca6e5 | 1281 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1282 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1283 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1284 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1285 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1286 | const char *name); | |
ec04b075 | 1287 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1288 | |
1da177e4 | 1289 | extern int pci_pci_problems; |
236561e5 | 1290 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1291 | #define PCIPCI_TRITON 2 |
1292 | #define PCIPCI_NATOMA 4 | |
1293 | #define PCIPCI_VIAETBF 8 | |
1294 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1295 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1296 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1297 | |
4516a618 AN |
1298 | extern unsigned long pci_cardbus_io_size; |
1299 | extern unsigned long pci_cardbus_mem_size; | |
491424c0 | 1300 | extern u8 __devinitdata pci_dfl_cache_line_size; |
ac1aa47b | 1301 | extern u8 pci_cache_line_size; |
4516a618 | 1302 | |
28760489 EB |
1303 | extern unsigned long pci_hotplug_io_size; |
1304 | extern unsigned long pci_hotplug_mem_size; | |
1305 | ||
19792a08 AB |
1306 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1307 | void pcibios_disable_device(struct pci_dev *dev); | |
1308 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1309 | enum pcie_reset_state state); | |
575e3348 | 1310 | |
7752d5cf | 1311 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1312 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1313 | extern void __init pci_mmcfg_late_init(void); |
1314 | #else | |
bb63b421 | 1315 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1316 | static inline void pci_mmcfg_late_init(void) { } |
1317 | #endif | |
1318 | ||
0ef5f8f6 AP |
1319 | int pci_ext_cfg_avail(struct pci_dev *dev); |
1320 | ||
1684f5dd | 1321 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1322 | |
dd7cc44d YZ |
1323 | #ifdef CONFIG_PCI_IOV |
1324 | extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); | |
1325 | extern void pci_disable_sriov(struct pci_dev *dev); | |
74bb1bcc | 1326 | extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
dd7cc44d YZ |
1327 | #else |
1328 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
1329 | { | |
1330 | return -ENODEV; | |
1331 | } | |
1332 | static inline void pci_disable_sriov(struct pci_dev *dev) | |
1333 | { | |
1334 | } | |
74bb1bcc YZ |
1335 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1336 | { | |
1337 | return IRQ_NONE; | |
1338 | } | |
dd7cc44d YZ |
1339 | #endif |
1340 | ||
c825bc94 KK |
1341 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
1342 | extern void pci_hp_create_module_link(struct pci_slot *pci_slot); | |
1343 | extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
1344 | #endif | |
1345 | ||
d7b7e605 KK |
1346 | /** |
1347 | * pci_pcie_cap - get the saved PCIe capability offset | |
1348 | * @dev: PCI device | |
1349 | * | |
1350 | * PCIe capability offset is calculated at PCI device initialization | |
1351 | * time and saved in the data structure. This function returns saved | |
1352 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1353 | * reduces unnecessary search in the PCI configuration space. If you | |
1354 | * need to calculate PCIe capability offset from raw device for some | |
1355 | * reasons, please use pci_find_capability() instead. | |
1356 | */ | |
1357 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1358 | { | |
1359 | return dev->pcie_cap; | |
1360 | } | |
1361 | ||
7eb776c4 KK |
1362 | /** |
1363 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1364 | * @dev: PCI device | |
1365 | * | |
1366 | * Retrun true if the PCI device is PCI Express capable, false otherwise. | |
1367 | */ | |
1368 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1369 | { | |
1370 | return !!pci_pcie_cap(dev); | |
1371 | } | |
1372 | ||
5d990b62 CW |
1373 | void pci_request_acs(void); |
1374 | ||
1da177e4 LT |
1375 | #endif /* __KERNEL__ */ |
1376 | #endif /* LINUX_PCI_H */ |