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fix CONFIG_SATA_SIS=y compile error
[linux-2.6-block.git] / include / linux / pci.h
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1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4 22
1da177e4
LT		 23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
778382e0
DW		 44#include <linux/mod_devicetable.h>
45
1da177e4 46#include <linux/types.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
bae94d02 51#include <asm/atomic.h>
1da177e4
LT		 52#include <linux/device.h>
53
7e7a43c3
AB		 54/* Include the ID list */
55#include <linux/pci_ids.h>
56
1da177e4
LT		 57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
4352dfd5
GKH		 74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 79#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 81
392a1ce7 82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
6e325a62
MT		 99typedef unsigned short __bitwise pci_bus_flags_t;
100enum pci_bus_flags {
e778272d 101 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 102};
103
41017f0c
SL		 104struct pci_cap_saved_state {
105 struct hlist_node next;
106 char cap_nr;
107 u32 data[0];
108};
109
1da177e4
LT		 110/*
111 * The pci_dev structure is used to describe PCI devices.
112 */
113struct pci_dev {
114 struct list_head global_list; /* node in list of all PCI devices */
115 struct list_head bus_list; /* node in per-bus list */
116 struct pci_bus *bus; /* bus this device is on */
117 struct pci_bus *subordinate; /* bus this device bridges to */
118
119 void *sysdata; /* hook for sys-specific extension */
120 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
121
122 unsigned int devfn; /* encoded device & function index */
123 unsigned short vendor;
124 unsigned short device;
125 unsigned short subsystem_vendor;
126 unsigned short subsystem_device;
127 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
128 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
129 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 130 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 131
132 struct pci_driver *driver; /* which driver has allocated this device */
133 u64 dma_mask; /* Mask of the bits of bus address this
134 device implements. Normally this is
135 0xffffffff. You only need to change
136 this if your device has broken DMA
137 or supports 64-bit transfers. */
138
139 pci_power_t current_state; /* Current operating state. In ACPI-speak,
140 this is D0-D3, D0 being fully functional,
141 and D3 being off. */
142
392a1ce7 143 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 144 struct device dev; /* Generic device interface */
145
146 /* device is compatible with these IDs */
147 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
148 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
149
150 int cfg_size; /* Size of configuration space */
151
152 /*
153 * Instead of touching interrupt line and base address registers
154 * directly, use the values stored here. They might be different!
155 */
156 unsigned int irq;
157 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
158
159 /* These fields are used by common fixups */
160 unsigned int transparent:1; /* Transparent PCI bridge */
161 unsigned int multifunction:1;/* Part of multi-function device */
162 /* keep track of device state */
1da177e4 163 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 164 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 165 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 166 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 167 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 168 unsigned int msi_enabled:1;
169 unsigned int msix_enabled:1;
bae94d02 170 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 171
1da177e4 172 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 173 struct hlist_head saved_cap_space;
1da177e4
LT		 174 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
175 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
176 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
ded86d8d
EB		 177#ifdef CONFIG_PCI_MSI
178 unsigned int first_msi_irq;
179#endif
1da177e4
LT		 180};
181
182#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
183#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
184#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
185#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
186
a7369f1f
LV		 187static inline int pci_channel_offline(struct pci_dev *pdev)
188{
189 return (pdev->error_state != pci_channel_io_normal);
190}
191
41017f0c
SL		 192static inline struct pci_cap_saved_state *pci_find_saved_cap(
193 struct pci_dev *pci_dev,char cap)
194{
195 struct pci_cap_saved_state *tmp;
196 struct hlist_node *pos;
197
198 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
199 if (tmp->cap_nr == cap)
200 return tmp;
201 }
202 return NULL;
203}
204
205static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
206 struct pci_cap_saved_state *new_cap)
207{
208 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
209}
210
211static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
212{
213 hlist_del(&cap->next);
214}
215
1da177e4
LT		 216/*
217 * For PCI devices, the region numbers are assigned this way:
218 *
219 * 0-5 standard PCI regions
220 * 6 expansion ROM
221 * 7-10 bridges: address space assigned to buses behind the bridge
222 */
223
4352dfd5
GKH		 224#define PCI_ROM_RESOURCE 6
225#define PCI_BRIDGE_RESOURCES 7
226#define PCI_NUM_RESOURCES 11
1da177e4
LT		 227
228#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 229#define PCI_BUS_NUM_RESOURCES 8
1da177e4 230#endif
4352dfd5
GKH		 231
232#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 233
234struct pci_bus {
235 struct list_head node; /* node in list of buses */
236 struct pci_bus *parent; /* parent bus this bridge is on */
237 struct list_head children; /* list of child buses */
238 struct list_head devices; /* list of devices on this bus */
239 struct pci_dev *self; /* bridge device as seen by parent */
240 struct resource *resource[PCI_BUS_NUM_RESOURCES];
241 /* address space routed to this bus */
242
243 struct pci_ops *ops; /* configuration access functions */
244 void *sysdata; /* hook for sys-specific extension */
245 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
246
247 unsigned char number; /* bus number */
248 unsigned char primary; /* number of primary bridge */
249 unsigned char secondary; /* number of secondary bridge */
250 unsigned char subordinate; /* max number of subordinate buses */
251
252 char name[48];
253
254 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 255 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 256 struct device *bridge;
257 struct class_device class_dev;
258 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
259 struct bin_attribute *legacy_mem; /* legacy mem */
260};
261
262#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
263#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
264
265/*
266 * Error values that may be returned by PCI functions.
267 */
268#define PCIBIOS_SUCCESSFUL 0x00
269#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
270#define PCIBIOS_BAD_VENDOR_ID 0x83
271#define PCIBIOS_DEVICE_NOT_FOUND 0x86
272#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
273#define PCIBIOS_SET_FAILED 0x88
274#define PCIBIOS_BUFFER_TOO_SMALL 0x89
275
276/* Low-level architecture-dependent routines */
277
278struct pci_ops {
279 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
280 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
281};
282
283struct pci_raw_ops {
284 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
285 int reg, int len, u32 *val);
286 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
287 int reg, int len, u32 val);
288};
289
290extern struct pci_raw_ops *raw_pci_ops;
291
292struct pci_bus_region {
293 unsigned long start;
294 unsigned long end;
295};
296
297struct pci_dynids {
298 spinlock_t lock; /* protects list, index */
299 struct list_head list; /* for IDs added at runtime */
300 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
301};
302
392a1ce7 303/* ---------------------------------------------------------------- */
304/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
305 * a set fof callbacks in struct pci_error_handlers, then that device driver
306 * will be notified of PCI bus errors, and will be driven to recovery
307 * when an error occurs.
308 */
309
310typedef unsigned int __bitwise pci_ers_result_t;
311
312enum pci_ers_result {
313 /* no result/none/not supported in device driver */
314 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
315
316 /* Device driver can recover without slot reset */
317 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
318
319 /* Device driver wants slot to be reset. */
320 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
321
322 /* Device has completely failed, is unrecoverable */
323 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
324
325 /* Device driver is fully recovered and operational */
326 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
327};
328
329/* PCI bus error event callbacks */
330struct pci_error_handlers
331{
332 /* PCI bus error detected on this device */
333 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
334 enum pci_channel_state error);
335
336 /* MMIO has been re-enabled, but not DMA */
337 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
338
339 /* PCI Express link has been reset */
340 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
341
342 /* PCI slot has been reset */
343 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
344
345 /* Device driver may resume normal operations */
346 void (*resume)(struct pci_dev *dev);
347};
348
349/* ---------------------------------------------------------------- */
350
1da177e4
LT		 351struct module;
352struct pci_driver {
353 struct list_head node;
354 char *name;
1da177e4
LT		 355 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
356 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
357 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
358 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 359 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
360 int (*resume_early) (struct pci_dev *dev);
1da177e4 361 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 362 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 363 void (*shutdown) (struct pci_dev *dev);
1da177e4 364
392a1ce7 365 struct pci_error_handlers *err_handler;
1da177e4
LT		 366 struct device_driver driver;
367 struct pci_dynids dynids;
50b00755
AC		 368
369 int multithread_probe;
1da177e4
LT		 370};
371
372#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
373
374/**
375 * PCI_DEVICE - macro used to describe a specific pci device
376 * @vend: the 16 bit PCI Vendor ID
377 * @dev: the 16 bit PCI Device ID
378 *
379 * This macro is used to create a struct pci_device_id that matches a
380 * specific device. The subvendor and subdevice fields will be set to
381 * PCI_ANY_ID.
382 */
383#define PCI_DEVICE(vend,dev) \
384 .vendor = (vend), .device = (dev), \
385 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
386
387/**
388 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
389 * @dev_class: the class, subclass, prog-if triple for this device
390 * @dev_class_mask: the class mask for this device
391 *
392 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 393 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 394 * fields will be set to PCI_ANY_ID.
395 */
396#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
397 .class = (dev_class), .class_mask = (dev_class_mask), \
398 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
399 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
400
4352dfd5 401/*
1da177e4
LT		 402 * pci_module_init is obsolete, this stays here till we fix up all usages of it
403 * in the tree.
404 */
405#define pci_module_init pci_register_driver
406
1597cacb
AC		 407/**
408 * PCI_VDEVICE - macro used to describe a specific pci device in short form
409 * @vend: the vendor name
410 * @dev: the 16 bit PCI Device ID
411 *
412 * This macro is used to create a struct pci_device_id that matches a
413 * specific PCI device. The subvendor, and subdevice fields will be set
414 * to PCI_ANY_ID. The macro allows the next field to follow as the device
415 * private data.
416 */
417
418#define PCI_VDEVICE(vendor, device) \
419 PCI_VENDOR_ID_##vendor, (device), \
420 PCI_ANY_ID, PCI_ANY_ID, 0, 0
421
1da177e4
LT		 422/* these external functions are only available when PCI support is enabled */
423#ifdef CONFIG_PCI
424
425extern struct bus_type pci_bus_type;
426
427/* Do NOT directly access these two variables, unless you are arch specific pci
428 * code, or pci core code. */
429extern struct list_head pci_root_buses; /* list of all known PCI buses */
430extern struct list_head pci_devices; /* list of all devices */
431
432void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 433int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 434char *pcibios_setup (char *str);
435
436/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 437void pcibios_align_resource(void *, struct resource *, resource_size_t,
438 resource_size_t);
1da177e4
LT		 439void pcibios_update_irq(struct pci_dev *, int irq);
440
441/* Generic PCI functions used internally */
442
443extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 444void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 445struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
446static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
447{
c431ada4
RS		 448 struct pci_bus *root_bus;
449 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
450 if (root_bus)
451 pci_bus_add_devices(root_bus);
452 return root_bus;
1da177e4 453}
cdb9b9f7
PM		 454struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
455struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 456int pci_scan_slot(struct pci_bus *bus, int devfn);
457struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 458void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 459unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 460int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 461void pci_read_bridge_bases(struct pci_bus *child);
462struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
463int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
464extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
465extern void pci_dev_put(struct pci_dev *dev);
466extern void pci_remove_bus(struct pci_bus *b);
467extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 468extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 469void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 470extern void pci_sort_breadthfirst(void);
1da177e4
LT		 471
472/* Generic PCI functions exported to card drivers */
473
429538ad 474struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
1da177e4
LT		 475struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
476int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 477int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 478int pci_find_ext_capability (struct pci_dev *dev, int cap);
687d5fe3
ME		 479int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
480int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 481struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 482
d42552c3
AM		 483struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
484 struct pci_dev *from);
485struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
486 struct pci_dev *from);
487
1da177e4
LT		 488struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
489 unsigned int ss_vendor, unsigned int ss_device,
490 struct pci_dev *from);
491struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 492struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 493struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
494int pci_dev_present(const struct pci_device_id *ids);
d86f90f9 495const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
1da177e4
LT		 496
497int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
498int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
499int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
500int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
501int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
502int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
503
504static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
505{
506 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
507}
508static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
509{
510 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
511}
512static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
513{
514 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
515}
516static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
517{
518 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
519}
520static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
521{
522 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
523}
524static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
525{
526 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
527}
528
4a7fb636
AM		 529int __must_check pci_enable_device(struct pci_dev *dev);
530int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
1da177e4
LT		 531void pci_disable_device(struct pci_dev *dev);
532void pci_set_master(struct pci_dev *dev);
533#define HAVE_PCI_SET_MWI
4a7fb636 534int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 535void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 536void pci_intx(struct pci_dev *dev, int enable);
9c8550ee
LT		 537int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
538int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 539void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 540int __must_check pci_assign_resource(struct pci_dev *dev, int i);
541int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 542void pci_restore_bars(struct pci_dev *dev);
c87deff7 543int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 544
545/* ROM control related routines */
144a50ea
DJ		 546void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
547void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 548void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
549void pci_remove_rom(struct pci_dev *pdev);
550
551/* Power management related routines */
552int pci_save_state(struct pci_dev *dev);
553int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 554int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
555pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
556int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 557
558/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
559void pci_bus_assign_resources(struct pci_bus *bus);
560void pci_bus_size_bridges(struct pci_bus *bus);
561int pci_claim_resource(struct pci_dev *, int);
562void pci_assign_unassigned_resources(void);
563void pdev_enable_device(struct pci_dev *);
564void pdev_sort_resources(struct pci_dev *, struct resource_list *);
565void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
566 int (*)(struct pci_dev *, u8, u8));
567#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 568int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 569void pci_release_regions(struct pci_dev *);
4a7fb636 570int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 571void pci_release_region(struct pci_dev *, int);
c87deff7
HS		 572int pci_request_selected_regions(struct pci_dev *, int, const char *);
573void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 574
575/* drivers/pci/bus.c */
4a7fb636
AM		 576int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
577 struct resource *res, resource_size_t size,
578 resource_size_t align, resource_size_t min,
579 unsigned int type_mask,
580 void (*alignf)(void *, struct resource *,
581 resource_size_t, resource_size_t),
582 void *alignf_data);
1da177e4
LT		 583void pci_enable_bridges(struct pci_bus *bus);
584
863b18f4 585/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 586int __must_check __pci_register_driver(struct pci_driver *, struct module *,
587 const char *mod_name);
4a7fb636 588static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4 589{
725522b5 590 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
863b18f4
L		 591}
592
1da177e4
LT		 593void pci_unregister_driver(struct pci_driver *);
594void pci_remove_behind_bridge(struct pci_dev *);
595struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 596const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
597const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 598int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
599
cecf4864
PM		 600void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
601 void *userdata);
ac7dc65a 602int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 603unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 604
1da177e4
LT		 605/* kmem_cache style wrapper around pci_alloc_consistent() */
606
607#include <linux/dmapool.h>
608
609#define pci_pool dma_pool
610#define pci_pool_create(name, pdev, size, align, allocation) \
611 dma_pool_create(name, &pdev->dev, size, align, allocation)
612#define pci_pool_destroy(pool) dma_pool_destroy(pool)
613#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
614#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
615
e24c2d96
DM		 616enum pci_dma_burst_strategy {
617 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
618 strategy_parameter is N/A */
619 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
620 byte boundaries */
621 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
622 strategy_parameter byte boundaries */
623};
624
1da177e4
LT		 625struct msix_entry {
626 u16 vector; /* kernel uses to write allocated vector */
627 u16 entry; /* driver uses to specify entry, OS writes */
628};
629
0366f8f7 630
1da177e4 631#ifndef CONFIG_PCI_MSI
1da177e4
LT		 632static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
633static inline void pci_disable_msi(struct pci_dev *dev) {}
634static inline int pci_enable_msix(struct pci_dev* dev,
635 struct msix_entry *entries, int nvec) {return -1;}
636static inline void pci_disable_msix(struct pci_dev *dev) {}
637static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
638#else
1da177e4
LT		 639extern int pci_enable_msi(struct pci_dev *dev);
640extern void pci_disable_msi(struct pci_dev *dev);
641extern int pci_enable_msix(struct pci_dev* dev,
642 struct msix_entry *entries, int nvec);
643extern void pci_disable_msix(struct pci_dev *dev);
644extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
645#endif
646
8b955b0d 647#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 648/* The functions a driver should call */
649int ht_create_irq(struct pci_dev *dev, int idx);
650void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 651#endif /* CONFIG_HT_IRQ */
652
e04b0ea2
BK		 653extern void pci_block_user_cfg_access(struct pci_dev *dev);
654extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
655
4352dfd5
GKH		 656/*
657 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
658 * a PCI domain is defined to be a set of PCI busses which share
659 * configuration space.
660 */
661#ifndef CONFIG_PCI_DOMAINS
662static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
663static inline int pci_proc_domain(struct pci_bus *bus)
664{
665 return 0;
666}
667#endif
1da177e4 668
4352dfd5 669#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 670
671/*
672 * If the system does not have PCI, clearly these return errors. Define
673 * these as simple inline functions to avoid hair in drivers.
674 */
675
1da177e4
LT		 676#define _PCI_NOP(o,s,t) \
677 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
678 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
679#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
680 _PCI_NOP(o,word,u16 x) \
681 _PCI_NOP(o,dword,u32 x)
682_PCI_NOP_ALL(read, *)
683_PCI_NOP_ALL(write,)
684
685static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
686{ return NULL; }
687
688static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
689{ return NULL; }
690
d42552c3
AM		 691static inline struct pci_dev *pci_get_device(unsigned int vendor,
692 unsigned int device, struct pci_dev *from)
693{ return NULL; }
694
695static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
696 unsigned int device, struct pci_dev *from)
1da177e4
LT		 697{ return NULL; }
698
699static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
700unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
701{ return NULL; }
702
703static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
704{ return NULL; }
705
706#define pci_dev_present(ids) (0)
d86f90f9 707#define pci_find_present(ids) (NULL)
1da177e4
LT		 708#define pci_dev_put(dev) do { } while (0)
709
710static inline void pci_set_master(struct pci_dev *dev) { }
711static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
712static inline void pci_disable_device(struct pci_dev *dev) { }
713static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 714static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 715static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 716static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
717static inline void pci_unregister_driver(struct pci_driver *drv) { }
718static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 719static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 720static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 721static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
722
723/* Power management related routines */
724static inline int pci_save_state(struct pci_dev *dev) { return 0; }
725static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
726static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 727static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 728static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
729
a46e8126
KG		 730#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
731
e04b0ea2
BK		 732static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
733static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
734
4352dfd5 735#endif /* CONFIG_PCI */
1da177e4 736
4352dfd5
GKH		 737/* Include architecture-dependent settings and functions */
738
739#include <asm/pci.h>
1da177e4
LT		 740
741/* these helpers provide future and backwards compatibility
742 * for accessing popular PCI BAR info */
743#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
744#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
745#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
746#define pci_resource_len(dev,bar) \
747 ((pci_resource_start((dev),(bar)) == 0 && \
748 pci_resource_end((dev),(bar)) == \
749 pci_resource_start((dev),(bar))) ? 0 : \
750 \
751 (pci_resource_end((dev),(bar)) - \
752 pci_resource_start((dev),(bar)) + 1))
753
754/* Similar to the helpers above, these manipulate per-pci_dev
755 * driver-specific data. They are really just a wrapper around
756 * the generic device structure functions of these calls.
757 */
758static inline void *pci_get_drvdata (struct pci_dev *pdev)
759{
760 return dev_get_drvdata(&pdev->dev);
761}
762
763static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
764{
765 dev_set_drvdata(&pdev->dev, data);
766}
767
768/* If you want to know what to call your pci_dev, ask this function.
769 * Again, it's a wrapper around the generic device.
770 */
771static inline char *pci_name(struct pci_dev *pdev)
772{
773 return pdev->dev.bus_id;
774}
775
2311b1f2
ME		 776
777/* Some archs don't want to expose struct resource to userland as-is
778 * in sysfs and /proc
779 */
780#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
781static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 782 const struct resource *rsrc, resource_size_t *start,
783 resource_size_t *end)
2311b1f2
ME		 784{
785 *start = rsrc->start;
786 *end = rsrc->end;
787}
788#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
789
790
1da177e4
LT		 791/*
792 * The world is not perfect and supplies us with broken PCI devices.
793 * For at least a part of these bugs we need a work-around, so both
794 * generic (drivers/pci/quirks.c) and per-architecture code can define
795 * fixup hooks to be called for particular buggy devices.
796 */
797
798struct pci_fixup {
799 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
800 void (*hook)(struct pci_dev *dev);
801};
802
803enum pci_fixup_pass {
804 pci_fixup_early, /* Before probing BARs */
805 pci_fixup_header, /* After reading configuration header */
806 pci_fixup_final, /* Final phase of device fixups */
807 pci_fixup_enable, /* pci_enable_device() time */
1597cacb 808 pci_fixup_resume, /* pci_enable_device() time */
1da177e4
LT		 809};
810
811/* Anonymous variables would be nice... */
812#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 813 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 814 __attribute__((__section__(#section))) = { vendor, device, hook };
815#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
816 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
817 vendor##device##hook, vendor, device, hook)
818#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
820 vendor##device##hook, vendor, device, hook)
821#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
822 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
823 vendor##device##hook, vendor, device, hook)
824#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
826 vendor##device##hook, vendor, device, hook)
1597cacb
AC		 827#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
828 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
829 resume##vendor##device##hook, vendor, device, hook)
1da177e4
LT		 830
831
832void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
833
834extern int pci_pci_problems;
236561e5 835#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 836#define PCIPCI_TRITON 2
837#define PCIPCI_NATOMA 4
838#define PCIPCI_VIAETBF 8
839#define PCIPCI_VSFX 16
236561e5
AC		 840#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
841#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4
LT		 842
843#endif /* __KERNEL__ */
844#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)