Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * pci.h | |
4 | * | |
5 | * PCI defines and function prototypes | |
6 | * Copyright 1994, Drew Eckhardt | |
7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
8 | * | |
7ce2e76a KW |
9 | * PCI Express ASPM defines and function prototypes |
10 | * Copyright (c) 2007 Intel Corp. | |
11 | * Zhang Yanmin (yanmin.zhang@intel.com) | |
12 | * Shaohua Li (shaohua.li@intel.com) | |
13 | * | |
1da177e4 LT |
14 | * For more information, please consult the following manuals (look at |
15 | * http://www.pcisig.com/ for how to get them): | |
16 | * | |
17 | * PCI BIOS Specification | |
18 | * PCI Local Bus Specification | |
19 | * PCI to PCI Bridge Specification | |
7ce2e76a | 20 | * PCI Express Specification |
1da177e4 LT |
21 | * PCI System Design Guide |
22 | */ | |
1da177e4 LT |
23 | #ifndef LINUX_PCI_H |
24 | #define LINUX_PCI_H | |
25 | ||
b229baa3 | 26 | #include <linux/args.h> |
778382e0 DW |
27 | #include <linux/mod_devicetable.h> |
28 | ||
1da177e4 | 29 | #include <linux/types.h> |
98db6f19 | 30 | #include <linux/init.h> |
1da177e4 LT |
31 | #include <linux/ioport.h> |
32 | #include <linux/list.h> | |
4a7fb636 | 33 | #include <linux/compiler.h> |
1da177e4 | 34 | #include <linux/errno.h> |
f46753c5 | 35 | #include <linux/kobject.h> |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <linux/device.h> |
704e8953 | 38 | #include <linux/interrupt.h> |
1388cc96 | 39 | #include <linux/io.h> |
14d76b68 | 40 | #include <linux/resource_ext.h> |
34026364 | 41 | #include <linux/msi_api.h> |
607ca46e | 42 | #include <uapi/linux/pci.h> |
1da177e4 | 43 | |
7e7a43c3 AB |
44 | #include <linux/pci_ids.h> |
45 | ||
d6e055e8 HK |
46 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
47 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | |
48 | PCI_STATUS_REC_MASTER_ABORT | \ | |
49 | PCI_STATUS_REC_TARGET_ABORT | \ | |
50 | PCI_STATUS_SIG_TARGET_ABORT | \ | |
51 | PCI_STATUS_PARITY) | |
52 | ||
e20afa06 | 53 | /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ |
6937b7dd | 54 | #define PCI_NUM_RESET_METHODS 7 |
e20afa06 | 55 | |
9bdc81ce AN |
56 | #define PCI_RESET_PROBE true |
57 | #define PCI_RESET_DO_RESET false | |
58 | ||
85467136 SK |
59 | /* |
60 | * The PCI interface treats multi-function devices as independent | |
61 | * devices. The slot/function address of each device is encoded | |
62 | * in a single byte as follows: | |
63 | * | |
64 | * 7:3 = slot | |
65 | * 2:0 = function | |
f7625980 BH |
66 | * |
67 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 68 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 69 | * the following kernel-only defines are being added here. |
85467136 | 70 | */ |
0aa0f5d1 | 71 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
72 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
73 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
74 | ||
f46753c5 AC |
75 | /* pci_slot represents a physical slot */ |
76 | struct pci_slot { | |
0aa0f5d1 BH |
77 | struct pci_bus *bus; /* Bus this slot is on */ |
78 | struct list_head list; /* Node in list of slots */ | |
79 | struct hotplug_slot *hotplug; /* Hotplug info (move here) */ | |
80 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
81 | struct kobject kobj; | |
f46753c5 AC |
82 | }; |
83 | ||
0ad772ec AC |
84 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
85 | { | |
86 | return kobject_name(&slot->kobj); | |
87 | } | |
88 | ||
1da177e4 LT |
89 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
90 | enum pci_mmap_state { | |
91 | pci_mmap_io, | |
92 | pci_mmap_mem | |
93 | }; | |
94 | ||
0aa0f5d1 | 95 | /* For PCI devices, the region numbers are assigned this way: */ |
fde09c6d YZ |
96 | enum { |
97 | /* #0-5: standard PCI resources */ | |
98 | PCI_STD_RESOURCES, | |
c9c13ba4 | 99 | PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, |
fde09c6d YZ |
100 | |
101 | /* #6: expansion ROM resource */ | |
102 | PCI_ROM_RESOURCE, | |
103 | ||
0aa0f5d1 | 104 | /* Device-specific resources */ |
d1b054da YZ |
105 | #ifdef CONFIG_PCI_IOV |
106 | PCI_IOV_RESOURCES, | |
107 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
108 | #endif | |
109 | ||
6e0688db KW |
110 | /* PCI-to-PCI (P2P) bridge windows */ |
111 | #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
112 | #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
113 | #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
114 | ||
115 | /* CardBus bridge windows */ | |
116 | #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
117 | #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
118 | #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
119 | #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) | |
120 | ||
121 | /* Total number of bridge resources for P2P and CardBus */ | |
fde09c6d YZ |
122 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
123 | ||
6e0688db | 124 | /* Resources assigned to buses behind the bridge */ |
fde09c6d YZ |
125 | PCI_BRIDGE_RESOURCES, |
126 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
127 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
128 | ||
0aa0f5d1 | 129 | /* Total resources associated with a PCI device */ |
fde09c6d YZ |
130 | PCI_NUM_RESOURCES, |
131 | ||
0aa0f5d1 | 132 | /* Preserve this for compatibility */ |
cda57bf9 | 133 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 134 | }; |
1da177e4 | 135 | |
b352baf1 PB |
136 | /** |
137 | * enum pci_interrupt_pin - PCI INTx interrupt values | |
138 | * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt | |
139 | * @PCI_INTERRUPT_INTA: PCI INTA pin | |
140 | * @PCI_INTERRUPT_INTB: PCI INTB pin | |
141 | * @PCI_INTERRUPT_INTC: PCI INTC pin | |
142 | * @PCI_INTERRUPT_INTD: PCI INTD pin | |
143 | * | |
144 | * Corresponds to values for legacy PCI INTx interrupts, as can be found in the | |
145 | * PCI_INTERRUPT_PIN register. | |
146 | */ | |
147 | enum pci_interrupt_pin { | |
148 | PCI_INTERRUPT_UNKNOWN, | |
149 | PCI_INTERRUPT_INTA, | |
150 | PCI_INTERRUPT_INTB, | |
151 | PCI_INTERRUPT_INTC, | |
152 | PCI_INTERRUPT_INTD, | |
153 | }; | |
154 | ||
155 | /* The number of legacy PCI INTx interrupts */ | |
156 | #define PCI_NUM_INTX 4 | |
157 | ||
57bdeef4 NN |
158 | /* |
159 | * Reading from a device that doesn't respond typically returns ~0. A | |
160 | * successful read from a device may also return ~0, so you need additional | |
161 | * information to reliably identify errors. | |
162 | */ | |
163 | #define PCI_ERROR_RESPONSE (~0ULL) | |
164 | #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) | |
165 | #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) | |
166 | ||
224abb67 BH |
167 | /* |
168 | * pci_power_t values must match the bits in the Capabilities PME_Support | |
169 | * and Control/Status PowerState fields in the Power Management capability. | |
170 | */ | |
1da177e4 LT |
171 | typedef int __bitwise pci_power_t; |
172 | ||
4352dfd5 GKH |
173 | #define PCI_D0 ((pci_power_t __force) 0) |
174 | #define PCI_D1 ((pci_power_t __force) 1) | |
175 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
176 | #define PCI_D3hot ((pci_power_t __force) 3) |
177 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 178 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 179 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 180 | |
00240c38 AS |
181 | /* Remember to update this when the list above changes! */ |
182 | extern const char *pci_power_names[]; | |
183 | ||
184 | static inline const char *pci_power_name(pci_power_t state) | |
185 | { | |
9661e783 | 186 | return pci_power_names[1 + (__force int) state]; |
00240c38 AS |
187 | } |
188 | ||
0aa0f5d1 | 189 | /** |
229b4e07 CD |
190 | * typedef pci_channel_state_t |
191 | * | |
0aa0f5d1 BH |
192 | * The pci_channel state describes connectivity between the CPU and |
193 | * the PCI device. If some PCI bus between here and the PCI device | |
194 | * has crashed or locked up, this info is reflected here. | |
392a1ce7 | 195 | */ |
196 | typedef unsigned int __bitwise pci_channel_state_t; | |
197 | ||
16d79cd4 | 198 | enum { |
392a1ce7 | 199 | /* I/O channel is in normal state */ |
200 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
201 | ||
202 | /* I/O to channel is blocked */ | |
203 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
204 | ||
205 | /* PCI card is dead */ | |
206 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
207 | }; | |
208 | ||
f7bdd12d BK |
209 | typedef unsigned int __bitwise pcie_reset_state_t; |
210 | ||
211 | enum pcie_reset_state { | |
212 | /* Reset is NOT asserted (Use to deassert reset) */ | |
213 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
214 | ||
f7625980 | 215 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
216 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
217 | ||
f7625980 | 218 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
219 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
220 | }; | |
221 | ||
ba698ad4 DM |
222 | typedef unsigned short __bitwise pci_dev_flags_t; |
223 | enum pci_dev_flags { | |
0aa0f5d1 | 224 | /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ |
6b121592 | 225 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 226 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 227 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 228 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 229 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 230 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 231 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
c8fe16e3 AW |
232 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
233 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
234 | /* Do not use bus resets for device */ |
235 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
236 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
237 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
932c435c MR |
238 | /* Get VPD from function 0 VPD */ |
239 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), | |
0aa0f5d1 | 240 | /* A non-root bridge where translation occurs, stop alias search here */ |
ffff8858 | 241 | PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), |
f65fd1aa SN |
242 | /* Do not use FLR even if device advertises PCI_AF_CAP */ |
243 | PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), | |
a99b646a | 244 | /* Don't use Relaxed Ordering for TLPs directed at this device */ |
c2eac4d3 | 245 | PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), |
2226667a MZ |
246 | /* Device does honor MSI masking despite saying otherwise */ |
247 | PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), | |
ba698ad4 DM |
248 | }; |
249 | ||
e1d3a908 SA |
250 | enum pci_irq_reroute_variant { |
251 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
252 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
253 | }; | |
254 | ||
6e325a62 MT |
255 | typedef unsigned short __bitwise pci_bus_flags_t; |
256 | enum pci_bus_flags { | |
032c3d86 JD |
257 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
258 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
259 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, | |
17e8f0d4 | 260 | PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, |
6e325a62 MT |
261 | }; |
262 | ||
0aa0f5d1 | 263 | /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ |
59da381e JK |
264 | enum pcie_link_width { |
265 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
266 | PCIE_LNK_X1 = 0x01, | |
267 | PCIE_LNK_X2 = 0x02, | |
268 | PCIE_LNK_X4 = 0x04, | |
269 | PCIE_LNK_X8 = 0x08, | |
0aa0f5d1 | 270 | PCIE_LNK_X12 = 0x0c, |
59da381e JK |
271 | PCIE_LNK_X16 = 0x10, |
272 | PCIE_LNK_X32 = 0x20, | |
0aa0f5d1 | 273 | PCIE_LNK_WIDTH_UNKNOWN = 0xff, |
59da381e JK |
274 | }; |
275 | ||
e56faff5 | 276 | /* See matching string table in pci_speed_string() */ |
536c8cb4 MW |
277 | enum pci_bus_speed { |
278 | PCI_SPEED_33MHz = 0x00, | |
279 | PCI_SPEED_66MHz = 0x01, | |
280 | PCI_SPEED_66MHz_PCIX = 0x02, | |
281 | PCI_SPEED_100MHz_PCIX = 0x03, | |
282 | PCI_SPEED_133MHz_PCIX = 0x04, | |
283 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
284 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
285 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
286 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
287 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
288 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
289 | AGP_UNKNOWN = 0x0c, |
290 | AGP_1X = 0x0d, | |
291 | AGP_2X = 0x0e, | |
292 | AGP_4X = 0x0f, | |
293 | AGP_8X = 0x10, | |
536c8cb4 MW |
294 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
295 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
296 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
297 | PCIE_SPEED_2_5GT = 0x14, | |
298 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 299 | PCIE_SPEED_8_0GT = 0x16, |
1acfb9b7 | 300 | PCIE_SPEED_16_0GT = 0x17, |
de76cda2 | 301 | PCIE_SPEED_32_0GT = 0x18, |
34191749 | 302 | PCIE_SPEED_64_0GT = 0x19, |
536c8cb4 MW |
303 | PCI_SPEED_UNKNOWN = 0xff, |
304 | }; | |
305 | ||
576c7218 AD |
306 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
307 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); | |
308 | ||
fd00faa3 HK |
309 | struct pci_vpd { |
310 | struct mutex lock; | |
311 | unsigned int len; | |
312 | u8 cap; | |
24a4742f AW |
313 | }; |
314 | ||
402723ad | 315 | struct irq_affinity; |
7d715a6c | 316 | struct pcie_link_state; |
d1b054da | 317 | struct pci_sriov; |
52916982 | 318 | struct pci_p2pdma; |
90655631 | 319 | struct rcec_ea; |
ee69439c | 320 | |
0aa0f5d1 | 321 | /* The pci_dev structure describes PCI devices */ |
1da177e4 | 322 | struct pci_dev { |
0aa0f5d1 BH |
323 | struct list_head bus_list; /* Node in per-bus list */ |
324 | struct pci_bus *bus; /* Bus this device is on */ | |
325 | struct pci_bus *subordinate; /* Bus this device bridges to */ | |
1da177e4 | 326 | |
0aa0f5d1 BH |
327 | void *sysdata; /* Hook for sys-specific extension */ |
328 | struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ | |
f46753c5 | 329 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 | 330 | |
0aa0f5d1 | 331 | unsigned int devfn; /* Encoded device & function index */ |
1da177e4 LT |
332 | unsigned short vendor; |
333 | unsigned short device; | |
334 | unsigned short subsystem_vendor; | |
335 | unsigned short subsystem_device; | |
336 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 337 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 338 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
66b80809 KB |
339 | #ifdef CONFIG_PCIEAER |
340 | u16 aer_cap; /* AER capability offset */ | |
db89ccbe | 341 | struct aer_stats *aer_stats; /* AER stats for this device */ |
90655631 SK |
342 | #endif |
343 | #ifdef CONFIG_PCIEPORTBUS | |
344 | struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ | |
507b460f | 345 | struct pci_dev *rcec; /* Associated RCEC device */ |
66b80809 | 346 | #endif |
69139244 | 347 | u32 devcap; /* PCIe Device Capabilities */ |
f7625980 | 348 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
349 | u8 msi_cap; /* MSI capability offset */ |
350 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 351 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
0aa0f5d1 BH |
352 | u8 rom_base_reg; /* Config register controlling ROM */ |
353 | u8 pin; /* Interrupt pin this device uses */ | |
354 | u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ | |
355 | unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ | |
1da177e4 | 356 | |
68da4e0e | 357 | struct pci_driver *driver; /* Driver bound to this device */ |
1da177e4 LT |
358 | u64 dma_mask; /* Mask of the bits of bus address this |
359 | device implements. Normally this is | |
360 | 0xffffffff. You only need to change | |
361 | this if your device has broken DMA | |
362 | or supports 64-bit transfers. */ | |
363 | ||
4d57cdfa FT |
364 | struct device_dma_parameters dma_parms; |
365 | ||
0aa0f5d1 BH |
366 | pci_power_t current_state; /* Current operating state. In ACPI, |
367 | this is D0-D3, D0 being fully | |
368 | functional, and D3 being off. */ | |
703860ed | 369 | u8 pm_cap; /* PM capability offset */ |
849846c4 | 370 | unsigned int imm_ready:1; /* Supports Immediate Readiness */ |
337001b6 RW |
371 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
372 | can be generated */ | |
379021d5 | 373 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
374 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
375 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
376 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
377 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
9d26d3a8 | 378 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
448bd857 | 379 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
0aa0f5d1 BH |
380 | unsigned int mmio_always_on:1; /* Disallow turning off io/mem |
381 | decoding during BAR sizing */ | |
e80bb09d | 382 | unsigned int wakeup_prepared:1; |
d491f2b7 | 383 | unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ |
b440bde7 | 384 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
576243b3 KB |
385 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
386 | controlled exclusively by | |
387 | user sysfs */ | |
4ec73791 SM |
388 | unsigned int clear_retrain_link:1; /* Need to clear Retrain Link |
389 | bit manually */ | |
3789af9a | 390 | unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ |
448bd857 | 391 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 392 | |
7d715a6c | 393 | #ifdef CONFIG_PCIEASPM |
f7625980 | 394 | struct pcie_link_state *link_state; /* ASPM link state */ |
849846c4 | 395 | u16 l1ss; /* L1SS Capability pointer */ |
c46fd358 BH |
396 | unsigned int ltr_path:1; /* Latency Tolerance Reporting |
397 | supported from root to here */ | |
7d715a6c | 398 | #endif |
8c09e896 | 399 | unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ |
7ce3f912 | 400 | unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ |
7d715a6c | 401 | |
0aa0f5d1 BH |
402 | pci_channel_state_t error_state; /* Current connectivity state */ |
403 | struct device dev; /* Generic device interface */ | |
1da177e4 | 404 | |
0aa0f5d1 | 405 | int cfg_size; /* Size of config space */ |
1da177e4 LT |
406 | |
407 | /* | |
408 | * Instead of touching interrupt line and base address registers | |
409 | * directly, use the values stored here. They might be different! | |
410 | */ | |
411 | unsigned int irq; | |
412 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
27829479 | 413 | struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ |
1da177e4 | 414 | |
0aa0f5d1 BH |
415 | bool match_driver; /* Skip attaching driver */ |
416 | ||
417 | unsigned int transparent:1; /* Subtractive decode bridge */ | |
51c48b31 BH |
418 | unsigned int io_window:1; /* Bridge has I/O window */ |
419 | unsigned int pref_window:1; /* Bridge has pref mem window */ | |
420 | unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ | |
0aa0f5d1 BH |
421 | unsigned int multifunction:1; /* Multi-function device */ |
422 | ||
0aa0f5d1 BH |
423 | unsigned int is_busmaster:1; /* Is busmaster */ |
424 | unsigned int no_msi:1; /* May not use MSI */ | |
f6b6aefe | 425 | unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ |
0aa0f5d1 BH |
426 | unsigned int block_cfg_access:1; /* Config space access blocked */ |
427 | unsigned int broken_parity_status:1; /* Generates false positive parity */ | |
428 | unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ | |
f7625980 | 429 | unsigned int msi_enabled:1; |
99dc804d | 430 | unsigned int msix_enabled:1; |
0aa0f5d1 BH |
431 | unsigned int ari_enabled:1; /* ARI forwarding */ |
432 | unsigned int ats_enabled:1; /* Address Translation Svc */ | |
a4f4fa68 JPB |
433 | unsigned int pasid_enabled:1; /* Process Address Space ID */ |
434 | unsigned int pri_enabled:1; /* Page Request Interface */ | |
3f35d2cf TG |
435 | unsigned int is_managed:1; /* Managed via devres */ |
436 | unsigned int is_msi_managed:1; /* MSI release via devres installed */ | |
0aa0f5d1 | 437 | unsigned int needs_freset:1; /* Requires fundamental reset */ |
aa8c6c93 | 438 | unsigned int state_saved:1; |
d1b054da | 439 | unsigned int is_physfn:1; |
dd7cc44d | 440 | unsigned int is_virtfn:1; |
0aa0f5d1 | 441 | unsigned int is_hotplug_bridge:1; |
b03799b0 | 442 | unsigned int shpc_managed:1; /* SHPC owned by shpchp */ |
0aa0f5d1 | 443 | unsigned int is_thunderbolt:1; /* Thunderbolt controller */ |
617654aa MW |
444 | /* |
445 | * Devices marked being untrusted are the ones that can potentially | |
446 | * execute DMA attacks and similar. They are typically connected | |
447 | * through external ports such as Thunderbolt but not limited to | |
448 | * that. When an IOMMU is enabled they should be getting full | |
449 | * mappings to make sure they cannot access arbitrary memory. | |
450 | */ | |
451 | unsigned int untrusted:1; | |
99b50be9 RJ |
452 | /* |
453 | * Info from the platform, e.g., ACPI or device tree, may mark a | |
454 | * device as "external-facing". An external-facing device is | |
455 | * itself internal but devices downstream from it are external. | |
456 | */ | |
457 | unsigned int external_facing:1; | |
0aa0f5d1 BH |
458 | unsigned int broken_intx_masking:1; /* INTx masking can't be used */ |
459 | unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ | |
cffe0a2b | 460 | unsigned int irq_managed:1; |
0aa0f5d1 BH |
461 | unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ |
462 | unsigned int is_probed:1; /* Device probing in progress */ | |
f0157160 | 463 | unsigned int link_active_reporting:1;/* Device capable of reporting link active */ |
aff68a5a | 464 | unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ |
12856e7a | 465 | unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ |
500b55b0 | 466 | unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ |
091f9f7f | 467 | unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ |
ba698ad4 | 468 | pci_dev_flags_t dev_flags; |
bae94d02 | 469 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 470 | |
5e70d0ac | 471 | spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ |
0aa0f5d1 | 472 | u32 saved_config_space[16]; /* Config space saved at suspend time */ |
41017f0c | 473 | struct hlist_head saved_cap_space; |
1da177e4 | 474 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
45aec1ae | 475 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
9bb04a0c | 476 | |
d22b3621 BH |
477 | #ifdef CONFIG_HOTPLUG_PCI_PCIE |
478 | unsigned int broken_cmd_compl:1; /* No compl for some cmds */ | |
479 | #endif | |
9bb04a0c | 480 | #ifdef CONFIG_PCIE_PTM |
a47126ec | 481 | u16 ptm_cap; /* PTM Capability */ |
9bb04a0c JY |
482 | unsigned int ptm_root:1; |
483 | unsigned int ptm_enabled:1; | |
8b2ec318 | 484 | u8 ptm_granularity; |
9bb04a0c | 485 | #endif |
ded86d8d | 486 | #ifdef CONFIG_PCI_MSI |
85aa607e | 487 | void __iomem *msix_base; |
cd119b09 | 488 | raw_spinlock_t msi_lock; |
ded86d8d | 489 | #endif |
fd00faa3 | 490 | struct pci_vpd vpd; |
be06c1b4 BH |
491 | #ifdef CONFIG_PCIE_DPC |
492 | u16 dpc_cap; | |
493 | unsigned int dpc_rp_extensions:1; | |
494 | u8 dpc_rp_log_size; | |
495 | #endif | |
466b3ddf | 496 | #ifdef CONFIG_PCI_ATS |
dd7cc44d | 497 | union { |
0aa0f5d1 BH |
498 | struct pci_sriov *sriov; /* PF: SR-IOV info */ |
499 | struct pci_dev *physfn; /* VF: related PF */ | |
dd7cc44d | 500 | }; |
67930995 BH |
501 | u16 ats_cap; /* ATS Capability offset */ |
502 | u8 ats_stu; /* ATS Smallest Translation Unit */ | |
4ebeb1ec CT |
503 | #endif |
504 | #ifdef CONFIG_PCI_PRI | |
c065190b | 505 | u16 pri_cap; /* PRI Capability offset */ |
4ebeb1ec | 506 | u32 pri_reqs_alloc; /* Number of PRI requests allocated */ |
e5adf79a | 507 | unsigned int pasid_required:1; /* PRG Response PASID Required */ |
4ebeb1ec CT |
508 | #endif |
509 | #ifdef CONFIG_PCI_PASID | |
751035b8 | 510 | u16 pasid_cap; /* PASID Capability offset */ |
4ebeb1ec | 511 | u16 pasid_features; |
52916982 LG |
512 | #endif |
513 | #ifdef CONFIG_PCI_P2PDMA | |
ae21f835 | 514 | struct pci_p2pdma __rcu *p2pdma; |
ac048403 LW |
515 | #endif |
516 | #ifdef CONFIG_PCI_DOE | |
517 | struct xarray doe_mbs; /* Data Object Exchange mailboxes */ | |
d1b054da | 518 | #endif |
52fbf5bd | 519 | u16 acs_cap; /* ACS Capability offset */ |
0aa0f5d1 BH |
520 | phys_addr_t rom; /* Physical address if not from BAR */ |
521 | size_t romlen; /* Length if not from BAR */ | |
23d99baf KK |
522 | /* |
523 | * Driver name to force a match. Do not set directly, because core | |
524 | * frees it. Use driver_set_override() to set or clear it. | |
525 | */ | |
526 | const char *driver_override; | |
89ee9f76 | 527 | |
0aa0f5d1 | 528 | unsigned long priv_flags; /* Private flags for the PCI driver */ |
e20afa06 AN |
529 | |
530 | /* These methods index pci_reset_fn_methods[] */ | |
531 | u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ | |
1da177e4 LT |
532 | }; |
533 | ||
dda56549 Y |
534 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
535 | { | |
536 | #ifdef CONFIG_PCI_IOV | |
537 | if (dev->is_virtfn) | |
538 | dev = dev->physfn; | |
539 | #endif | |
dda56549 Y |
540 | return dev; |
541 | } | |
542 | ||
3c6e6ae7 | 543 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 544 | |
1da177e4 LT |
545 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
546 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
547 | ||
a7369f1f LV |
548 | static inline int pci_channel_offline(struct pci_dev *pdev) |
549 | { | |
550 | return (pdev->error_state != pci_channel_io_normal); | |
551 | } | |
552 | ||
15d82ca2 BF |
553 | /* |
554 | * Currently in ACPI spec, for each PCI host bridge, PCI Segment | |
555 | * Group number is limited to a 16-bit value, therefore (int)-1 is | |
556 | * not a valid PCI domain number, and can be used as a sentinel | |
557 | * value indicating ->domain_nr is not set by the driver (and | |
558 | * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with | |
559 | * pci_bus_find_domain_nr()). | |
560 | */ | |
561 | #define PCI_DOMAIN_NR_NOT_SET (-1) | |
562 | ||
5a21d70d | 563 | struct pci_host_bridge { |
0aa0f5d1 BH |
564 | struct device dev; |
565 | struct pci_bus *bus; /* Root bus */ | |
566 | struct pci_ops *ops; | |
07e29295 | 567 | struct pci_ops *child_ops; |
0aa0f5d1 BH |
568 | void *sysdata; |
569 | int busnr; | |
15d82ca2 | 570 | int domain_nr; |
14d76b68 | 571 | struct list_head windows; /* resource_entry */ |
e80a91ad | 572 | struct list_head dma_ranges; /* dma ranges resource list */ |
0aa0f5d1 | 573 | u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ |
3aa8a41e | 574 | int (*map_irq)(const struct pci_dev *, u8, u8); |
4fa2649a | 575 | void (*release_fn)(struct pci_host_bridge *); |
0aa0f5d1 | 576 | void *release_data; |
0aa0f5d1 BH |
577 | unsigned int ignore_reset_delay:1; /* For entire hierarchy */ |
578 | unsigned int no_ext_tags:1; /* No Extended Tags */ | |
8b3517f8 | 579 | unsigned int no_inc_mrrs:1; /* No Increase MRRS */ |
02bfeb48 | 580 | unsigned int native_aer:1; /* OS may use PCIe AER */ |
9310f0dc | 581 | unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ |
1df81a6d | 582 | unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ |
02bfeb48 | 583 | unsigned int native_pme:1; /* OS may use PCIe PME */ |
af8bb9f8 | 584 | unsigned int native_ltr:1; /* OS may use PCIe LTR */ |
ac1c8e35 | 585 | unsigned int native_dpc:1; /* OS may use PCIe DPC */ |
589c3357 | 586 | unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ |
a78cf965 | 587 | unsigned int preserve_config:1; /* Preserve FW resource setup */ |
2c8d5a2d | 588 | unsigned int size_windows:1; /* Enable root bus sizing */ |
94e89b14 | 589 | unsigned int msi_domain:1; /* Bridge wants MSI domain */ |
a78cf965 | 590 | |
7c7a0e94 GP |
591 | /* Resource alignment requirements */ |
592 | resource_size_t (*align_resource)(struct pci_dev *dev, | |
593 | const struct resource *res, | |
594 | resource_size_t start, | |
595 | resource_size_t size, | |
596 | resource_size_t align); | |
914a1951 | 597 | unsigned long private[] ____cacheline_aligned; |
5a21d70d | 598 | }; |
41017f0c | 599 | |
7b543663 | 600 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
7c7a0e94 | 601 | |
59094065 TR |
602 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
603 | { | |
604 | return (void *)bridge->private; | |
605 | } | |
606 | ||
607 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) | |
608 | { | |
609 | return container_of(priv, struct pci_host_bridge, private); | |
610 | } | |
611 | ||
a52d1443 | 612 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); |
5c3f18cc LP |
613 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
614 | size_t priv); | |
dff79b91 | 615 | void pci_free_host_bridge(struct pci_host_bridge *bridge); |
7c7a0e94 GP |
616 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
617 | ||
4fa2649a | 618 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
0aa0f5d1 BH |
619 | void (*release_fn)(struct pci_host_bridge *), |
620 | void *release_data); | |
7b543663 | 621 | |
6c0cc950 RW |
622 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
623 | ||
2fe2abf8 BH |
624 | /* |
625 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
626 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
627 | * buses below host bridges or subtractive decode bridges) go in the list. | |
628 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
629 | */ | |
630 | ||
631 | /* | |
632 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
633 | * and there's no way to program the bridge with the details of the window. | |
634 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
635 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
636 | */ | |
637 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
638 | ||
639 | struct pci_bus_resource { | |
0aa0f5d1 BH |
640 | struct list_head list; |
641 | struct resource *res; | |
642 | unsigned int flags; | |
2fe2abf8 | 643 | }; |
4352dfd5 GKH |
644 | |
645 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
646 | |
647 | struct pci_bus { | |
0aa0f5d1 BH |
648 | struct list_head node; /* Node in list of buses */ |
649 | struct pci_bus *parent; /* Parent bus this bridge is on */ | |
650 | struct list_head children; /* List of child buses */ | |
651 | struct list_head devices; /* List of devices on this bus */ | |
652 | struct pci_dev *self; /* Bridge device as seen by parent */ | |
653 | struct list_head slots; /* List of slots on this bus; | |
67546762 | 654 | protected by pci_slot_mutex */ |
2fe2abf8 | 655 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
0aa0f5d1 BH |
656 | struct list_head resources; /* Address space routed to this bus */ |
657 | struct resource busn_res; /* Bus numbers routed to this bus */ | |
1da177e4 | 658 | |
0aa0f5d1 | 659 | struct pci_ops *ops; /* Configuration access functions */ |
0aa0f5d1 BH |
660 | void *sysdata; /* Hook for sys-specific extension */ |
661 | struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ | |
1da177e4 | 662 | |
0aa0f5d1 BH |
663 | unsigned char number; /* Bus number */ |
664 | unsigned char primary; /* Number of primary bridge */ | |
3749c51a MW |
665 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
666 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
667 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
668 | int domain_nr; | |
669 | #endif | |
1da177e4 LT |
670 | |
671 | char name[48]; | |
672 | ||
0aa0f5d1 BH |
673 | unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ |
674 | pci_bus_flags_t bus_flags; /* Inherited by child buses */ | |
1da177e4 | 675 | struct device *bridge; |
fd7d1ced | 676 | struct device dev; |
0aa0f5d1 BH |
677 | struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ |
678 | struct bin_attribute *legacy_mem; /* Legacy mem */ | |
cc74d96f | 679 | unsigned int is_added:1; |
92c45b63 | 680 | unsigned int unsafe_warn:1; /* warned about RW1C config write */ |
1da177e4 LT |
681 | }; |
682 | ||
fd7d1ced | 683 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 684 | |
4e544bac HK |
685 | static inline u16 pci_dev_id(struct pci_dev *dev) |
686 | { | |
687 | return PCI_DEVID(dev->bus->number, dev->devfn); | |
688 | } | |
689 | ||
79af72d7 | 690 | /* |
f7625980 | 691 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 692 | * false otherwise |
77a0dfcd BH |
693 | * |
694 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
695 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
696 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
697 | */ |
698 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
699 | { | |
700 | return !(pbus->parent); | |
701 | } | |
702 | ||
1c86438c YW |
703 | /** |
704 | * pci_is_bridge - check if the PCI device is a bridge | |
705 | * @dev: PCI device | |
706 | * | |
707 | * Return true if the PCI device is bridge whether it has subordinate | |
708 | * or not. | |
709 | */ | |
710 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
711 | { | |
712 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
713 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
714 | } | |
715 | ||
7e845ecb SJ |
716 | /** |
717 | * pci_is_vga - check if the PCI device is a VGA device | |
718 | * | |
719 | * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define | |
720 | * VGA Base Class and Sub-Classes: | |
721 | * | |
722 | * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible | |
723 | * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) | |
724 | * | |
725 | * Return true if the PCI device is a VGA device and uses the legacy VGA | |
726 | * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and | |
727 | * aliases). | |
728 | */ | |
729 | static inline bool pci_is_vga(struct pci_dev *pdev) | |
730 | { | |
731 | if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
732 | return true; | |
733 | ||
734 | if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) | |
735 | return true; | |
736 | ||
737 | return false; | |
738 | } | |
739 | ||
24a0c654 AS |
740 | #define for_each_pci_bridge(dev, bus) \ |
741 | list_for_each_entry(dev, &bus->devices, bus_list) \ | |
742 | if (!pci_is_bridge(dev)) {} else | |
743 | ||
c6bde215 BH |
744 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
745 | { | |
746 | dev = pci_physfn(dev); | |
747 | if (pci_is_root_bus(dev->bus)) | |
748 | return NULL; | |
749 | ||
750 | return dev->bus->self; | |
751 | } | |
752 | ||
16cf0ebc RW |
753 | #ifdef CONFIG_PCI_MSI |
754 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
755 | { | |
756 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
757 | } | |
758 | #else | |
759 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
760 | #endif | |
761 | ||
0aa0f5d1 | 762 | /* Error values that may be returned by PCI functions */ |
1da177e4 LT |
763 | #define PCIBIOS_SUCCESSFUL 0x00 |
764 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
765 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
766 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
767 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
768 | #define PCIBIOS_SET_FAILED 0x88 | |
769 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
770 | ||
0aa0f5d1 | 771 | /* Translate above to generic errno for passing back through non-PCI code */ |
a6961651 AW |
772 | static inline int pcibios_err_to_errno(int err) |
773 | { | |
774 | if (err <= PCIBIOS_SUCCESSFUL) | |
775 | return err; /* Assume already errno */ | |
776 | ||
777 | switch (err) { | |
778 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
779 | return -ENOENT; | |
780 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 781 | return -ENOTTY; |
a6961651 AW |
782 | case PCIBIOS_DEVICE_NOT_FOUND: |
783 | return -ENODEV; | |
784 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
785 | return -EFAULT; | |
786 | case PCIBIOS_SET_FAILED: | |
787 | return -EIO; | |
788 | case PCIBIOS_BUFFER_TOO_SMALL: | |
789 | return -ENOSPC; | |
790 | } | |
791 | ||
d97ffe23 | 792 | return -ERANGE; |
a6961651 AW |
793 | } |
794 | ||
1da177e4 LT |
795 | /* Low-level architecture-dependent routines */ |
796 | ||
797 | struct pci_ops { | |
057bd2e0 TR |
798 | int (*add_bus)(struct pci_bus *bus); |
799 | void (*remove_bus)(struct pci_bus *bus); | |
1f94a94f | 800 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
801 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
802 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
803 | }; | |
804 | ||
b6ce068a MW |
805 | /* |
806 | * ACPI needs to be able to access PCI config space before we've done a | |
807 | * PCI bus scan and created pci_bus structures. | |
808 | */ | |
f39d5b72 BH |
809 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
810 | int reg, int len, u32 *val); | |
811 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
812 | int reg, int len, u32 val); | |
1da177e4 | 813 | |
8e639079 | 814 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
3a9ad0b4 YL |
815 | typedef u64 pci_bus_addr_t; |
816 | #else | |
817 | typedef u32 pci_bus_addr_t; | |
818 | #endif | |
819 | ||
1da177e4 | 820 | struct pci_bus_region { |
0aa0f5d1 BH |
821 | pci_bus_addr_t start; |
822 | pci_bus_addr_t end; | |
1da177e4 LT |
823 | }; |
824 | ||
825 | struct pci_dynids { | |
0aa0f5d1 BH |
826 | spinlock_t lock; /* Protects list, index */ |
827 | struct list_head list; /* For IDs added at runtime */ | |
1da177e4 LT |
828 | }; |
829 | ||
f7625980 BH |
830 | |
831 | /* | |
832 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
833 | * a set of callbacks in struct pci_error_handlers, that device driver | |
834 | * will be notified of PCI bus errors, and will be driven to recovery | |
835 | * when an error occurs. | |
392a1ce7 | 836 | */ |
837 | ||
838 | typedef unsigned int __bitwise pci_ers_result_t; | |
839 | ||
840 | enum pci_ers_result { | |
0aa0f5d1 | 841 | /* No result/none/not supported in device driver */ |
392a1ce7 | 842 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
843 | ||
844 | /* Device driver can recover without slot reset */ | |
845 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
846 | ||
0aa0f5d1 | 847 | /* Device driver wants slot to be reset */ |
392a1ce7 | 848 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
849 | ||
850 | /* Device has completely failed, is unrecoverable */ | |
851 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
852 | ||
853 | /* Device driver is fully recovered and operational */ | |
854 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
855 | |
856 | /* No AER capabilities registered for the driver */ | |
857 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 | 858 | }; |
859 | ||
860 | /* PCI bus error event callbacks */ | |
05cca6e5 | 861 | struct pci_error_handlers { |
392a1ce7 | 862 | /* PCI bus error detected on this device */ |
863 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
16d79cd4 | 864 | pci_channel_state_t error); |
392a1ce7 | 865 | |
866 | /* MMIO has been re-enabled, but not DMA */ | |
867 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
868 | ||
392a1ce7 | 869 | /* PCI slot has been reset */ |
870 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
871 | ||
3ebe7f9f | 872 | /* PCI function reset prepare or completed */ |
775755ed CH |
873 | void (*reset_prepare)(struct pci_dev *dev); |
874 | void (*reset_done)(struct pci_dev *dev); | |
3ebe7f9f | 875 | |
392a1ce7 | 876 | /* Device driver may resume normal operations */ |
877 | void (*resume)(struct pci_dev *dev); | |
361187e0 DJ |
878 | |
879 | /* Allow device driver to record more details of a correctable error */ | |
880 | void (*cor_error_detected)(struct pci_dev *dev); | |
392a1ce7 | 881 | }; |
882 | ||
392a1ce7 | 883 | |
1da177e4 | 884 | struct module; |
229b4e07 CD |
885 | |
886 | /** | |
887 | * struct pci_driver - PCI driver structure | |
888 | * @node: List of driver structures. | |
889 | * @name: Driver name. | |
890 | * @id_table: Pointer to table of device IDs the driver is | |
891 | * interested in. Most drivers should export this | |
892 | * table using MODULE_DEVICE_TABLE(pci,...). | |
893 | * @probe: This probing function gets called (during execution | |
894 | * of pci_register_driver() for already existing | |
895 | * devices or later if a new device gets inserted) for | |
896 | * all PCI devices which match the ID table and are not | |
897 | * "owned" by the other drivers yet. This function gets | |
898 | * passed a "struct pci_dev \*" for each device whose | |
899 | * entry in the ID table matches the device. The probe | |
900 | * function returns zero when the driver chooses to | |
901 | * take "ownership" of the device or an error code | |
902 | * (negative number) otherwise. | |
903 | * The probe function always gets called from process | |
904 | * context, so it can sleep. | |
905 | * @remove: The remove() function gets called whenever a device | |
906 | * being handled by this driver is removed (either during | |
907 | * deregistration of the driver or when it's manually | |
908 | * pulled out of a hot-pluggable slot). | |
909 | * The remove function always gets called from process | |
910 | * context, so it can sleep. | |
911 | * @suspend: Put device into low power state. | |
229b4e07 | 912 | * @resume: Wake device from low power state. |
151f4e2b | 913 | * (Please see Documentation/power/pci.rst for descriptions |
229b4e07 CD |
914 | * of PCI Power Management and the related functions.) |
915 | * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). | |
916 | * Intended to stop any idling DMA operations. | |
917 | * Useful for enabling wake-on-lan (NIC) or changing | |
918 | * the power state of a device before reboot. | |
919 | * e.g. drivers/net/e100.c. | |
920 | * @sriov_configure: Optional driver callback to allow configuration of | |
921 | * number of VFs to enable via sysfs "sriov_numvfs" file. | |
c3d5c2d9 LR |
922 | * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X |
923 | * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". | |
924 | * This will change MSI-X Table Size in the VF Message Control | |
925 | * registers. | |
926 | * @sriov_get_vf_total_msix: PF driver callback to get the total number of | |
927 | * MSI-X vectors available for distribution to the VFs. | |
229b4e07 CD |
928 | * @err_handler: See Documentation/PCI/pci-error-recovery.rst |
929 | * @groups: Sysfs attribute groups. | |
ded13b9c AG |
930 | * @dev_groups: Attributes attached to the device that will be |
931 | * created once it is bound to the driver. | |
229b4e07 CD |
932 | * @driver: Driver model structure. |
933 | * @dynids: List of dynamically added device IDs. | |
512881ea LB |
934 | * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. |
935 | * For most device drivers, no need to care about this flag | |
936 | * as long as all DMAs are handled through the kernel DMA API. | |
937 | * For some special ones, for example VFIO drivers, they know | |
938 | * how to manage the DMA themselves and set this flag so that | |
939 | * the IOMMU layer will allow them to setup and manage their | |
940 | * own I/O address space. | |
229b4e07 | 941 | */ |
1da177e4 | 942 | struct pci_driver { |
0aa0f5d1 BH |
943 | struct list_head node; |
944 | const char *name; | |
945 | const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ | |
946 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
947 | void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
948 | int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
7cb30264 BY |
949 | int (*resume)(struct pci_dev *dev); /* Device woken up */ |
950 | void (*shutdown)(struct pci_dev *dev); | |
951 | int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ | |
c3d5c2d9 LR |
952 | int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ |
953 | u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); | |
49453028 | 954 | const struct pci_error_handlers *err_handler; |
92d50fc1 | 955 | const struct attribute_group **groups; |
ded13b9c | 956 | const struct attribute_group **dev_groups; |
1da177e4 | 957 | struct device_driver driver; |
0aa0f5d1 | 958 | struct pci_dynids dynids; |
512881ea | 959 | bool driver_managed_dma; |
1da177e4 LT |
960 | }; |
961 | ||
8e9028b3 BH |
962 | static inline struct pci_driver *to_pci_driver(struct device_driver *drv) |
963 | { | |
964 | return drv ? container_of(drv, struct pci_driver, driver) : NULL; | |
965 | } | |
1da177e4 LT |
966 | |
967 | /** | |
0aa0f5d1 | 968 | * PCI_DEVICE - macro used to describe a specific PCI device |
1da177e4 LT |
969 | * @vend: the 16 bit PCI Vendor ID |
970 | * @dev: the 16 bit PCI Device ID | |
971 | * | |
972 | * This macro is used to create a struct pci_device_id that matches a | |
973 | * specific device. The subvendor and subdevice fields will be set to | |
974 | * PCI_ANY_ID. | |
975 | */ | |
976 | #define PCI_DEVICE(vend,dev) \ | |
977 | .vendor = (vend), .device = (dev), \ | |
978 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
979 | ||
343b7258 MG |
980 | /** |
981 | * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with | |
982 | * override_only flags. | |
983 | * @vend: the 16 bit PCI Vendor ID | |
984 | * @dev: the 16 bit PCI Device ID | |
985 | * @driver_override: the 32 bit PCI Device override_only | |
986 | * | |
987 | * This macro is used to create a struct pci_device_id that matches only a | |
988 | * driver_override device. The subvendor and subdevice fields will be set to | |
989 | * PCI_ANY_ID. | |
990 | */ | |
991 | #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ | |
992 | .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ | |
993 | .subdevice = PCI_ANY_ID, .override_only = (driver_override) | |
994 | ||
cc6711b0 MG |
995 | /** |
996 | * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO | |
997 | * "driver_override" PCI device. | |
998 | * @vend: the 16 bit PCI Vendor ID | |
999 | * @dev: the 16 bit PCI Device ID | |
1000 | * | |
1001 | * This macro is used to create a struct pci_device_id that matches a | |
1002 | * specific device. The subvendor and subdevice fields will be set to | |
1003 | * PCI_ANY_ID and the driver_override will be set to | |
1004 | * PCI_ID_F_VFIO_DRIVER_OVERRIDE. | |
1005 | */ | |
1006 | #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ | |
1007 | PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) | |
1008 | ||
3d567e0e | 1009 | /** |
0aa0f5d1 | 1010 | * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem |
3d567e0e NNS |
1011 | * @vend: the 16 bit PCI Vendor ID |
1012 | * @dev: the 16 bit PCI Device ID | |
1013 | * @subvend: the 16 bit PCI Subvendor ID | |
1014 | * @subdev: the 16 bit PCI Subdevice ID | |
1015 | * | |
1016 | * This macro is used to create a struct pci_device_id that matches a | |
1017 | * specific device with subsystem information. | |
1018 | */ | |
1019 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
1020 | .vendor = (vend), .device = (dev), \ | |
1021 | .subvendor = (subvend), .subdevice = (subdev) | |
1022 | ||
1da177e4 | 1023 | /** |
0aa0f5d1 | 1024 | * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class |
1da177e4 LT |
1025 | * @dev_class: the class, subclass, prog-if triple for this device |
1026 | * @dev_class_mask: the class mask for this device | |
1027 | * | |
1028 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 1029 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
1030 | * fields will be set to PCI_ANY_ID. |
1031 | */ | |
1032 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
1033 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
1034 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
1035 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
1036 | ||
1597cacb | 1037 | /** |
0aa0f5d1 | 1038 | * PCI_VDEVICE - macro used to describe a specific PCI device in short form |
c1309040 MR |
1039 | * @vend: the vendor name |
1040 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
1041 | * |
1042 | * This macro is used to create a struct pci_device_id that matches a | |
1043 | * specific PCI device. The subvendor, and subdevice fields will be set | |
1044 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
1045 | * private data. | |
1046 | */ | |
c1309040 MR |
1047 | #define PCI_VDEVICE(vend, dev) \ |
1048 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
1049 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 1050 | |
b72ae8ca AS |
1051 | /** |
1052 | * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form | |
1053 | * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) | |
1054 | * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) | |
1055 | * @data: the driver data to be filled | |
1056 | * | |
1057 | * This macro is used to create a struct pci_device_id that matches a | |
1058 | * specific PCI device. The subvendor, and subdevice fields will be set | |
1059 | * to PCI_ANY_ID. | |
1060 | */ | |
1061 | #define PCI_DEVICE_DATA(vend, dev, data) \ | |
1062 | .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ | |
1063 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ | |
1064 | .driver_data = (kernel_ulong_t)(data) | |
1065 | ||
5bbe029f | 1066 | enum { |
0aa0f5d1 BH |
1067 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ |
1068 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ | |
1069 | PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ | |
1070 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ | |
1071 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ | |
5bbe029f | 1072 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
0aa0f5d1 | 1073 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ |
5bbe029f BH |
1074 | }; |
1075 | ||
0d8006dd HX |
1076 | #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ |
1077 | #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ | |
1078 | #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ | |
1079 | #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ | |
1080 | ||
0aa0f5d1 | 1081 | /* These external functions are only available when PCI support is enabled */ |
1da177e4 LT |
1082 | #ifdef CONFIG_PCI |
1083 | ||
5bbe029f BH |
1084 | extern unsigned int pci_flags; |
1085 | ||
1086 | static inline void pci_set_flags(int flags) { pci_flags = flags; } | |
1087 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } | |
1088 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } | |
1089 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } | |
1090 | ||
a58674ff | 1091 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
1092 | |
1093 | enum pcie_bus_config_types { | |
0aa0f5d1 BH |
1094 | PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ |
1095 | PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ | |
1096 | PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ | |
1097 | PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ | |
1098 | PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ | |
b03e7495 JM |
1099 | }; |
1100 | ||
1101 | extern enum pcie_bus_config_types pcie_bus_config; | |
1102 | ||
1da177e4 LT |
1103 | extern struct bus_type pci_bus_type; |
1104 | ||
f7625980 BH |
1105 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
1106 | * code, or PCI core code. */ | |
0aa0f5d1 | 1107 | extern struct list_head pci_root_buses; /* List of all known PCI buses */ |
f7625980 | 1108 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 1109 | int no_pci_devices(void); |
1da177e4 | 1110 | |
3c449ed0 | 1111 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
7b77061f | 1112 | void pcibios_bus_add_device(struct pci_dev *pdev); |
10a95747 JL |
1113 | void pcibios_add_bus(struct pci_bus *bus); |
1114 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 1115 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 1116 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 1117 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 1118 | char *pcibios_setup(char *str); |
1da177e4 LT |
1119 | |
1120 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 1121 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 1122 | resource_size_t, |
e31dd6e4 | 1123 | resource_size_t); |
1da177e4 | 1124 | |
d1bbf38a | 1125 | /* Weak but can be overridden by arch */ |
2d1c8618 BH |
1126 | void pci_fixup_cardbus(struct pci_bus *); |
1127 | ||
1da177e4 LT |
1128 | /* Generic PCI functions used internally */ |
1129 | ||
fc279850 | 1130 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 1131 | struct resource *res); |
fc279850 | 1132 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 1133 | struct pci_bus_region *region); |
d1fd4fb6 | 1134 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 1135 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 1136 | void pci_bus_add_devices(const struct pci_bus *bus); |
de4b2f76 | 1137 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
1138 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1139 | struct pci_ops *ops, void *sysdata, | |
1140 | struct list_head *resources); | |
49b8e3f3 | 1141 | int pci_host_probe(struct pci_host_bridge *bridge); |
98a35831 YL |
1142 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
1143 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
1144 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 1145 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
0aa0f5d1 BH |
1146 | struct pci_ops *ops, void *sysdata, |
1147 | struct list_head *resources); | |
1228c4b6 | 1148 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); |
05cca6e5 GKH |
1149 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
1150 | int busnr); | |
f46753c5 | 1151 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
1152 | const char *name, |
1153 | struct hotplug_slot *hotplug); | |
f46753c5 | 1154 | void pci_destroy_slot(struct pci_slot *slot); |
017ffe64 YW |
1155 | #ifdef CONFIG_SYSFS |
1156 | void pci_dev_assign_slot(struct pci_dev *dev); | |
1157 | #else | |
1158 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } | |
1159 | #endif | |
1da177e4 | 1160 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 1161 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 1162 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 1163 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 1164 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 1165 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
1166 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
1167 | struct resource *res); | |
3df425f3 | 1168 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 1169 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 1170 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
1171 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
1172 | void pci_dev_put(struct pci_dev *dev); | |
1173 | void pci_remove_bus(struct pci_bus *b); | |
1174 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 1175 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
1176 | void pci_stop_root_bus(struct pci_bus *bus); |
1177 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 1178 | void pci_setup_cardbus(struct pci_bus *bus); |
d366d28c | 1179 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
f39d5b72 | 1180 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
1181 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
1182 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
1da177e4 LT |
1183 | |
1184 | /* Generic PCI functions exported to card drivers */ | |
1185 | ||
f646c2a0 PM |
1186 | u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
1187 | u8 pci_find_capability(struct pci_dev *dev, int cap); | |
1188 | u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
1189 | u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
1190 | u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); | |
ee8b1c47 BH |
1191 | u16 pci_find_ext_capability(struct pci_dev *dev, int cap); |
1192 | u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); | |
29f3eb64 | 1193 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
c124fd9a | 1194 | u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); |
ee122037 | 1195 | u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); |
1da177e4 | 1196 | |
70c0923b JK |
1197 | u64 pci_get_dsn(struct pci_dev *dev); |
1198 | ||
d42552c3 | 1199 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
0aa0f5d1 | 1200 | struct pci_dev *from); |
05cca6e5 | 1201 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
0aa0f5d1 BH |
1202 | unsigned int ss_vendor, unsigned int ss_device, |
1203 | struct pci_dev *from); | |
05cca6e5 | 1204 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
1205 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
1206 | unsigned int devfn); | |
05cca6e5 | 1207 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
d427da23 SJ |
1208 | struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); |
1209 | ||
1da177e4 LT |
1210 | int pci_dev_present(const struct pci_device_id *ids); |
1211 | ||
05cca6e5 GKH |
1212 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
1213 | int where, u8 *val); | |
1214 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
1215 | int where, u16 *val); | |
1216 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1217 | int where, u32 *val); | |
1218 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
1219 | int where, u8 val); | |
1220 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
1221 | int where, u16 val); | |
1222 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1223 | int where, u32 val); | |
1f94a94f RH |
1224 | |
1225 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
1226 | int where, int size, u32 *val); | |
1227 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
1228 | int where, int size, u32 val); | |
1229 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
1230 | int where, int size, u32 *val); | |
1231 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
1232 | int where, int size, u32 val); | |
1233 | ||
a72b46c3 | 1234 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 1235 | |
d3881e50 KB |
1236 | int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); |
1237 | int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); | |
1238 | int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); | |
1239 | int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); | |
1240 | int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); | |
1241 | int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); | |
1da177e4 | 1242 | |
8c0d3a02 JL |
1243 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
1244 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
1245 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
1246 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
5e70d0ac IJ |
1247 | int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, |
1248 | u16 clear, u16 set); | |
1249 | int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, | |
1250 | u16 clear, u16 set); | |
8c0d3a02 JL |
1251 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
1252 | u32 clear, u32 set); | |
1253 | ||
5e70d0ac IJ |
1254 | /** |
1255 | * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers | |
1256 | * @dev: PCI device structure of the PCI Express device | |
1257 | * @pos: PCI Express Capability Register | |
1258 | * @clear: Clear bitmask | |
1259 | * @set: Set bitmask | |
1260 | * | |
1261 | * Perform a Read-Modify-Write (RMW) operation using @clear and @set | |
1262 | * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express | |
1263 | * Capability Registers are accessed concurrently in RMW fashion, hence | |
1264 | * require locking which is handled transparently to the caller. | |
1265 | */ | |
1266 | static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, | |
1267 | int pos, | |
1268 | u16 clear, u16 set) | |
1269 | { | |
1270 | switch (pos) { | |
1271 | case PCI_EXP_LNKCTL: | |
1272 | case PCI_EXP_RTCTL: | |
1273 | return pcie_capability_clear_and_set_word_locked(dev, pos, | |
1274 | clear, set); | |
1275 | default: | |
1276 | return pcie_capability_clear_and_set_word_unlocked(dev, pos, | |
1277 | clear, set); | |
1278 | } | |
1279 | } | |
1280 | ||
8c0d3a02 JL |
1281 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, |
1282 | u16 set) | |
1283 | { | |
1284 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
1285 | } | |
1286 | ||
1287 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
1288 | u32 set) | |
1289 | { | |
1290 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
1291 | } | |
1292 | ||
1293 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
1294 | u16 clear) | |
1295 | { | |
1296 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
1297 | } | |
1298 | ||
1299 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
1300 | u32 clear) | |
1301 | { | |
1302 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
1303 | } | |
1304 | ||
0aa0f5d1 | 1305 | /* User-space driven config access */ |
c63587d7 AW |
1306 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
1307 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
1308 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
1309 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
1310 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
1311 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
1312 | ||
4a7fb636 | 1313 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
1314 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
1315 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 1316 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
1317 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
1318 | void pcim_pin_device(struct pci_dev *pdev); | |
1319 | ||
99b3c58f PG |
1320 | static inline bool pci_intx_mask_supported(struct pci_dev *pdev) |
1321 | { | |
1322 | /* | |
1323 | * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is | |
1324 | * writable and no quirk has marked the feature broken. | |
1325 | */ | |
1326 | return !pdev->broken_intx_masking; | |
1327 | } | |
1328 | ||
296ccb08 YS |
1329 | static inline int pci_is_enabled(struct pci_dev *pdev) |
1330 | { | |
1331 | return (atomic_read(&pdev->enable_cnt) > 0); | |
1332 | } | |
1333 | ||
9ac7849e TH |
1334 | static inline int pci_is_managed(struct pci_dev *pdev) |
1335 | { | |
1336 | return pdev->is_managed; | |
1337 | } | |
1338 | ||
1da177e4 | 1339 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
1340 | |
1341 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 1342 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 1343 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 1344 | |
f7bdd12d | 1345 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 1346 | int pci_set_cacheline_size(struct pci_dev *dev); |
4a7fb636 | 1347 | int __must_check pci_set_mwi(struct pci_dev *dev); |
fc0f9f4d | 1348 | int __must_check pcim_set_mwi(struct pci_dev *dev); |
694625c0 | 1349 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 1350 | void pci_clear_mwi(struct pci_dev *dev); |
1fd3dde5 | 1351 | void pci_disable_parity(struct pci_dev *dev); |
a04ce0ff | 1352 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
1353 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
1354 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
157e876f | 1355 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 1356 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
1357 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
1358 | int pcix_get_mmrbc(struct pci_dev *dev); | |
1359 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 1360 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 1361 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
1362 | int pcie_get_mps(struct pci_dev *dev); |
1363 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
6db79a88 TG |
1364 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, |
1365 | enum pci_bus_speed *speed, | |
1366 | enum pcie_link_width *width); | |
9e506a7b | 1367 | void pcie_print_link_status(struct pci_dev *dev); |
9bdc81ce | 1368 | int pcie_reset_flr(struct pci_dev *dev, bool probe); |
91295d79 | 1369 | int pcie_flr(struct pci_dev *dev); |
a96d627a | 1370 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 1371 | int pci_reset_function(struct pci_dev *dev); |
a477b9cd | 1372 | int pci_reset_function_locked(struct pci_dev *dev); |
61cf16d8 | 1373 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 1374 | int pci_probe_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 1375 | int pci_probe_reset_bus(struct pci_bus *bus); |
c6a44ba9 | 1376 | int pci_reset_bus(struct pci_dev *dev); |
9e33002f GS |
1377 | void pci_reset_secondary_bus(struct pci_dev *dev); |
1378 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
14add80b | 1379 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1380 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1381 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
8bb705e3 | 1382 | void pci_release_resource(struct pci_dev *dev, int resno); |
192f1bf7 ND |
1383 | static inline int pci_rebar_bytes_to_size(u64 bytes) |
1384 | { | |
1385 | bytes = roundup_pow_of_two(bytes); | |
1386 | ||
1387 | /* Return BAR size as defined in the resizable BAR specification */ | |
1388 | return max(ilog2(bytes), 20) - 20; | |
1389 | } | |
1390 | ||
8fbdbb66 | 1391 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
8bb705e3 | 1392 | int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); |
c87deff7 | 1393 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1394 | bool pci_device_is_present(struct pci_dev *pdev); |
08249651 | 1395 | void pci_ignore_hotplug(struct pci_dev *dev); |
2856ba60 | 1396 | struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); |
ec5d9e87 | 1397 | int pci_status_get_and_clear_errors(struct pci_dev *pdev); |
1da177e4 | 1398 | |
704e8953 CH |
1399 | int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, |
1400 | irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, | |
1401 | const char *fmt, ...); | |
1402 | void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); | |
1403 | ||
1da177e4 | 1404 | /* ROM control related routines */ |
e416de5e AC |
1405 | int pci_enable_rom(struct pci_dev *pdev); |
1406 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1407 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1408 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
1da177e4 LT |
1409 | |
1410 | /* Power management related routines */ | |
1411 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1412 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1413 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1414 | int pci_load_saved_state(struct pci_dev *dev, |
1415 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1416 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1417 | struct pci_saved_state **state); | |
d6aa37cd | 1418 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1419 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1420 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1421 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1422 | void pci_pme_active(struct pci_dev *dev, bool enable); |
0847684c | 1423 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 1424 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1425 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1426 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1427 | bool pci_dev_run_wake(struct pci_dev *dev); |
9d26d3a8 MW |
1428 | void pci_d3cold_enable(struct pci_dev *dev); |
1429 | void pci_d3cold_disable(struct pci_dev *dev); | |
a99b646a | 1430 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); |
99efde6c | 1431 | void pci_resume_bus(struct pci_bus *bus); |
2a4d2c42 | 1432 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); |
1da177e4 | 1433 | |
bb209c82 BH |
1434 | /* For use by arch with custom probe code */ |
1435 | void set_pcie_port_type(struct pci_dev *pdev); | |
1436 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1437 | ||
ce5ccdef | 1438 | /* Functions for PCI Hotplug drivers to use */ |
2f320521 | 1439 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1440 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1441 | void pci_lock_rescan_remove(void); |
1442 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1443 | |
0aa0f5d1 | 1444 | /* Vital Product Data routines */ |
287d19ce SH |
1445 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1446 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
bf2928c7 HK |
1447 | ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1448 | ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
287d19ce | 1449 | |
1da177e4 | 1450 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1451 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1452 | void pci_bus_assign_resources(const struct pci_bus *bus); |
765bf9b7 | 1453 | void pci_bus_claim_resources(struct pci_bus *bus); |
1da177e4 LT |
1454 | void pci_bus_size_bridges(struct pci_bus *bus); |
1455 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1456 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1457 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1458 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1459 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1460 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
8bb705e3 | 1461 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); |
842de40d | 1462 | int pci_enable_resources(struct pci_dev *, int mask); |
47a650f2 | 1463 | void pci_assign_irq(struct pci_dev *dev); |
afd29f90 | 1464 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
1da177e4 | 1465 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1466 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1467 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1468 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1469 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 1470 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1471 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1472 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1473 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 | 1474 | |
27829479 IW |
1475 | static inline __must_check struct resource * |
1476 | pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, | |
1477 | unsigned int len, const char *name) | |
1478 | { | |
1479 | return __request_region(&pdev->driver_exclusive_resource, offset, len, | |
1480 | name, IORESOURCE_EXCLUSIVE); | |
1481 | } | |
1482 | ||
1483 | static inline void pci_release_config_region(struct pci_dev *pdev, | |
1484 | unsigned int offset, | |
1485 | unsigned int len) | |
1486 | { | |
1487 | __release_region(&pdev->driver_exclusive_resource, offset, len); | |
1488 | } | |
1489 | ||
1da177e4 | 1490 | /* drivers/pci/bus.c */ |
45ca9e97 | 1491 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1492 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1493 | resource_size_t offset); | |
45ca9e97 | 1494 | void pci_free_resource_list(struct list_head *resources); |
950334bc BH |
1495 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
1496 | unsigned int flags); | |
2fe2abf8 BH |
1497 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1498 | void pci_bus_remove_resources(struct pci_bus *bus); | |
ab909509 | 1499 | void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); |
950334bc BH |
1500 | int devm_request_pci_bus_resources(struct device *dev, |
1501 | struct list_head *resources); | |
2fe2abf8 | 1502 | |
bfc45606 DD |
1503 | /* Temporary until new and working PCI SBR API in place */ |
1504 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); | |
1505 | ||
02992064 AS |
1506 | #define __pci_bus_for_each_res0(bus, res, ...) \ |
1507 | for (unsigned int __b = 0; \ | |
1508 | (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ | |
1509 | __b++) | |
1510 | ||
1511 | #define __pci_bus_for_each_res1(bus, res, __b) \ | |
1512 | for (__b = 0; \ | |
1513 | (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ | |
1514 | __b++) | |
1515 | ||
ceb928be AS |
1516 | /** |
1517 | * pci_bus_for_each_resource - iterate over PCI bus resources | |
1518 | * @bus: the PCI bus | |
1519 | * @res: pointer to the current resource | |
02992064 | 1520 | * @...: optional index of the current resource |
ceb928be AS |
1521 | * |
1522 | * Iterate over PCI bus resources. The first part is to go over PCI bus | |
1523 | * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. | |
1524 | * After that continue with the separate list of the additional resources, | |
1525 | * if not empty. That's why the Logical OR is being used. | |
1526 | * | |
1527 | * Possible usage: | |
1528 | * | |
1529 | * struct pci_bus *bus = ...; | |
1530 | * struct resource *res; | |
1531 | * unsigned int i; | |
1532 | * | |
02992064 | 1533 | * // With optional index |
ceb928be AS |
1534 | * pci_bus_for_each_resource(bus, res, i) |
1535 | * pr_info("PCI bus resource[%u]: %pR\n", i, res); | |
02992064 AS |
1536 | * |
1537 | * // Without index | |
1538 | * pci_bus_for_each_resource(bus, res) | |
1539 | * _do_something_(res); | |
ceb928be | 1540 | */ |
02992064 AS |
1541 | #define pci_bus_for_each_resource(bus, res, ...) \ |
1542 | CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ | |
1543 | (bus, res, __VA_ARGS__) | |
89a74ecc | 1544 | |
4a7fb636 AM |
1545 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1546 | struct resource *res, resource_size_t size, | |
1547 | resource_size_t align, resource_size_t min, | |
664c2848 | 1548 | unsigned long type_mask, |
3b7a17fc DB |
1549 | resource_size_t (*alignf)(void *, |
1550 | const struct resource *, | |
b26b2d49 DB |
1551 | resource_size_t, |
1552 | resource_size_t), | |
4a7fb636 | 1553 | void *alignf_data); |
1da177e4 | 1554 | |
8b921acf | 1555 | |
fcfaab30 GP |
1556 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
1557 | resource_size_t size); | |
c5076cfe TN |
1558 | unsigned long pci_address_to_pio(phys_addr_t addr); |
1559 | phys_addr_t pci_pio_to_address(unsigned long pio); | |
8b921acf | 1560 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
a5fb9fb0 SS |
1561 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, |
1562 | phys_addr_t phys_addr); | |
4d3f1384 | 1563 | void pci_unmap_iospace(struct resource *res); |
490cb6dd LP |
1564 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, |
1565 | resource_size_t offset, | |
1566 | resource_size_t size); | |
1567 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
1568 | struct resource *res); | |
8b921acf | 1569 | |
3a9ad0b4 | 1570 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
06cf56e4 BH |
1571 | { |
1572 | struct pci_bus_region region; | |
1573 | ||
1574 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1575 | return region.start; | |
1576 | } | |
1577 | ||
863b18f4 | 1578 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1579 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1580 | const char *mod_name); | |
bba81165 | 1581 | |
0aa0f5d1 | 1582 | /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ |
bba81165 AM |
1583 | #define pci_register_driver(driver) \ |
1584 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1585 | |
05cca6e5 | 1586 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1587 | |
1588 | /** | |
1589 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1590 | * @__pci_driver: pci_driver struct | |
1591 | * | |
1592 | * Helper macro for PCI drivers which do not do anything special in module | |
1593 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1594 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1595 | */ | |
1596 | #define module_pci_driver(__pci_driver) \ | |
0aa0f5d1 | 1597 | module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) |
aad4f400 | 1598 | |
b4eb6cdb PG |
1599 | /** |
1600 | * builtin_pci_driver() - Helper macro for registering a PCI driver | |
1601 | * @__pci_driver: pci_driver struct | |
1602 | * | |
1603 | * Helper macro for PCI drivers which do not do anything special in their | |
1604 | * init code. This eliminates a lot of boilerplate. Each driver may only | |
1605 | * use this macro once, and calling it replaces device_initcall(...) | |
1606 | */ | |
1607 | #define builtin_pci_driver(__pci_driver) \ | |
1608 | builtin_driver(__pci_driver, pci_register_driver) | |
1609 | ||
05cca6e5 | 1610 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1611 | int pci_add_dynid(struct pci_driver *drv, |
1612 | unsigned int vendor, unsigned int device, | |
1613 | unsigned int subvendor, unsigned int subdevice, | |
1614 | unsigned int class, unsigned int class_mask, | |
1615 | unsigned long driver_data); | |
05cca6e5 GKH |
1616 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1617 | struct pci_dev *dev); | |
1618 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1619 | int pass); | |
1da177e4 | 1620 | |
70298c6e | 1621 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1622 | void *userdata); |
ac7dc65a | 1623 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1624 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1625 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1626 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1627 | unsigned long type); | |
cecf4864 | 1628 | |
3448a19d DA |
1629 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1630 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1631 | ||
deb2d2ec | 1632 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1633 | unsigned int command_bits, u32 flags); |
fe537670 | 1634 | |
d7cc609f LG |
1635 | /* |
1636 | * Virtual interrupts allow for more interrupts to be allocated | |
1637 | * than the device has interrupts for. These are not programmed | |
1638 | * into the device's MSI-X table and must be handled by some | |
1639 | * other driver means. | |
1640 | */ | |
1641 | #define PCI_IRQ_VIRTUAL (1 << 4) | |
1642 | ||
4fe0d154 CH |
1643 | #define PCI_IRQ_ALL_TYPES \ |
1644 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) | |
aff17164 | 1645 | |
1da177e4 LT |
1646 | #include <linux/dmapool.h> |
1647 | ||
1da177e4 | 1648 | struct msix_entry { |
0aa0f5d1 BH |
1649 | u32 vector; /* Kernel uses to write allocated vector */ |
1650 | u16 entry; /* Driver uses to specify entry, OS writes */ | |
1da177e4 LT |
1651 | }; |
1652 | ||
41efa431 RC |
1653 | struct msi_domain_template; |
1654 | ||
4c859804 BH |
1655 | #ifdef CONFIG_PCI_MSI |
1656 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 | 1657 | void pci_disable_msi(struct pci_dev *dev); |
4c859804 | 1658 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 | 1659 | void pci_disable_msix(struct pci_dev *dev); |
f39d5b72 BH |
1660 | void pci_restore_msi_state(struct pci_dev *dev); |
1661 | int pci_msi_enabled(void); | |
4fe03955 | 1662 | int pci_enable_msi(struct pci_dev *dev); |
4c859804 BH |
1663 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1664 | int minvec, int maxvec); | |
f7fc32cb AG |
1665 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1666 | struct msix_entry *entries, int nvec) | |
1667 | { | |
1668 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1669 | if (rc < 0) | |
1670 | return rc; | |
1671 | return 0; | |
1672 | } | |
5c0997dc AD |
1673 | int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, |
1674 | unsigned int max_vecs, unsigned int flags); | |
402723ad CH |
1675 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1676 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1677 | struct irq_affinity *affd); |
402723ad | 1678 | |
34026364 TG |
1679 | bool pci_msix_can_alloc_dyn(struct pci_dev *dev); |
1680 | struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, | |
1681 | const struct irq_affinity_desc *affdesc); | |
1682 | void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); | |
1683 | ||
aff17164 CH |
1684 | void pci_free_irq_vectors(struct pci_dev *dev); |
1685 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); | |
ee8d41e5 | 1686 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
41efa431 RC |
1687 | bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, |
1688 | unsigned int hwsize, void *data); | |
1689 | struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie, | |
1690 | const struct irq_affinity_desc *affdesc); | |
1691 | void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map); | |
aff17164 | 1692 | |
4c859804 | 1693 | #else |
2ee546c4 | 1694 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1695 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
1696 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
2ee546c4 | 1697 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
2ee546c4 BH |
1698 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1699 | static inline int pci_msi_enabled(void) { return 0; } | |
4fe03955 | 1700 | static inline int pci_enable_msi(struct pci_dev *dev) |
f7fc32cb | 1701 | { return -ENOSYS; } |
302a2523 | 1702 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
0aa0f5d1 | 1703 | struct msix_entry *entries, int minvec, int maxvec) |
2ee546c4 | 1704 | { return -ENOSYS; } |
f7fc32cb | 1705 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
0aa0f5d1 | 1706 | struct msix_entry *entries, int nvec) |
f7fc32cb | 1707 | { return -ENOSYS; } |
402723ad CH |
1708 | |
1709 | static inline int | |
1710 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1711 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1712 | struct irq_affinity *aff_desc) |
aff17164 | 1713 | { |
83b4605b CH |
1714 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) |
1715 | return 1; | |
1716 | return -ENOSPC; | |
aff17164 | 1717 | } |
5c0997dc AD |
1718 | static inline int |
1719 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1720 | unsigned int max_vecs, unsigned int flags) | |
1721 | { | |
1722 | return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, | |
1723 | flags, NULL); | |
1724 | } | |
402723ad | 1725 | |
195d8e5d RC |
1726 | static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) |
1727 | { return false; } | |
2b129f0b RC |
1728 | static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, |
1729 | const struct irq_affinity_desc *affdesc) | |
1730 | { | |
1731 | struct msi_map map = { .index = -ENOSYS, }; | |
1732 | ||
1733 | return map; | |
1734 | } | |
1735 | ||
1736 | static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) | |
1737 | { | |
1738 | } | |
1739 | ||
aff17164 CH |
1740 | static inline void pci_free_irq_vectors(struct pci_dev *dev) |
1741 | { | |
1742 | } | |
1743 | ||
1744 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1745 | { | |
1746 | if (WARN_ON_ONCE(nr > 0)) | |
1747 | return -EINVAL; | |
1748 | return dev->irq; | |
1749 | } | |
ee8d41e5 TG |
1750 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
1751 | int vec) | |
1752 | { | |
1753 | return cpu_possible_mask; | |
1754 | } | |
41efa431 RC |
1755 | |
1756 | static inline bool pci_create_ims_domain(struct pci_dev *pdev, | |
1757 | const struct msi_domain_template *template, | |
1758 | unsigned int hwsize, void *data) | |
1759 | { return false; } | |
1760 | ||
1761 | static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, | |
1762 | union msi_instance_cookie *icookie, | |
1763 | const struct irq_affinity_desc *affdesc) | |
1764 | { | |
1765 | struct msi_map map = { .index = -ENOSYS, }; | |
1766 | ||
1767 | return map; | |
1768 | } | |
1769 | ||
1770 | static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map) | |
1771 | { | |
1772 | } | |
1773 | ||
1da177e4 LT |
1774 | #endif |
1775 | ||
0d58e6c1 PB |
1776 | /** |
1777 | * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq | |
1778 | * @d: the INTx IRQ domain | |
1779 | * @node: the DT node for the device whose interrupt we're translating | |
1780 | * @intspec: the interrupt specifier data from the DT | |
1781 | * @intsize: the number of entries in @intspec | |
1782 | * @out_hwirq: pointer at which to write the hwirq number | |
1783 | * @out_type: pointer at which to write the interrupt type | |
1784 | * | |
1785 | * Translate a PCI INTx interrupt number from device tree in the range 1-4, as | |
1786 | * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range | |
1787 | * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the | |
1788 | * INTx value to obtain the hwirq number. | |
1789 | * | |
1790 | * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. | |
1791 | */ | |
1792 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, | |
1793 | struct device_node *node, | |
1794 | const u32 *intspec, | |
1795 | unsigned int intsize, | |
1796 | unsigned long *out_hwirq, | |
1797 | unsigned int *out_type) | |
1798 | { | |
1799 | const u32 intx = intspec[0]; | |
1800 | ||
1801 | if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) | |
1802 | return -EINVAL; | |
1803 | ||
1804 | *out_hwirq = intx - PCI_INTERRUPT_INTA; | |
1805 | return 0; | |
1806 | } | |
1807 | ||
ab0724ff | 1808 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 | 1809 | extern bool pcie_ports_disabled; |
5352a44a | 1810 | extern bool pcie_ports_native; |
ab0724ff MT |
1811 | #else |
1812 | #define pcie_ports_disabled true | |
5352a44a | 1813 | #define pcie_ports_native false |
ab0724ff | 1814 | #endif |
415e12b2 | 1815 | |
aff5d055 HK |
1816 | #define PCIE_LINK_STATE_L0S BIT(0) |
1817 | #define PCIE_LINK_STATE_L1 BIT(1) | |
1818 | #define PCIE_LINK_STATE_CLKPM BIT(2) | |
1819 | #define PCIE_LINK_STATE_L1_1 BIT(3) | |
1820 | #define PCIE_LINK_STATE_L1_2 BIT(4) | |
1821 | #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) | |
1822 | #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) | |
de82f60f MB |
1823 | #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\ |
1824 | PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\ | |
1825 | PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\ | |
1826 | PCIE_LINK_STATE_L1_2_PCIPM) | |
7ce2e76a | 1827 | |
4c859804 | 1828 | #ifdef CONFIG_PCIEASPM |
7ce2e76a KW |
1829 | int pci_disable_link_state(struct pci_dev *pdev, int state); |
1830 | int pci_disable_link_state_locked(struct pci_dev *pdev, int state); | |
de82f60f | 1831 | int pci_enable_link_state(struct pci_dev *pdev, int state); |
718ab822 | 1832 | int pci_enable_link_state_locked(struct pci_dev *pdev, int state); |
7ce2e76a | 1833 | void pcie_no_aspm(void); |
f39d5b72 | 1834 | bool pcie_aspm_support_enabled(void); |
accd2dd7 | 1835 | bool pcie_aspm_enabled(struct pci_dev *pdev); |
4c859804 | 1836 | #else |
7ce2e76a KW |
1837 | static inline int pci_disable_link_state(struct pci_dev *pdev, int state) |
1838 | { return 0; } | |
1839 | static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
1840 | { return 0; } | |
de82f60f MB |
1841 | static inline int pci_enable_link_state(struct pci_dev *pdev, int state) |
1842 | { return 0; } | |
718ab822 JH |
1843 | static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) |
1844 | { return 0; } | |
7ce2e76a | 1845 | static inline void pcie_no_aspm(void) { } |
4c859804 | 1846 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
accd2dd7 | 1847 | static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } |
3e1b1600 AP |
1848 | #endif |
1849 | ||
415e12b2 | 1850 | #ifdef CONFIG_PCIEAER |
415e12b2 RW |
1851 | bool pci_aer_available(void); |
1852 | #else | |
415e12b2 RW |
1853 | static inline bool pci_aer_available(void) { return false; } |
1854 | #endif | |
1855 | ||
cef74409 GK |
1856 | bool pci_ats_disabled(void); |
1857 | ||
1d71eb53 VCG |
1858 | #ifdef CONFIG_PCIE_PTM |
1859 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); | |
e8bdc5ea | 1860 | void pci_disable_ptm(struct pci_dev *dev); |
014408cd | 1861 | bool pcie_ptm_enabled(struct pci_dev *dev); |
1d71eb53 VCG |
1862 | #else |
1863 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) | |
1864 | { return -EINVAL; } | |
e8bdc5ea | 1865 | static inline void pci_disable_ptm(struct pci_dev *dev) { } |
014408cd VCG |
1866 | static inline bool pcie_ptm_enabled(struct pci_dev *dev) |
1867 | { return false; } | |
1d71eb53 VCG |
1868 | #endif |
1869 | ||
f39d5b72 BH |
1870 | void pci_cfg_access_lock(struct pci_dev *dev); |
1871 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1872 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1873 | |
dfd5bb23 | 1874 | void pci_dev_lock(struct pci_dev *dev); |
e3a9b121 LC |
1875 | int pci_dev_trylock(struct pci_dev *dev); |
1876 | void pci_dev_unlock(struct pci_dev *dev); | |
1877 | ||
4352dfd5 GKH |
1878 | /* |
1879 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1880 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1881 | * configuration space. |
1882 | */ | |
32a2eea7 JG |
1883 | #ifdef CONFIG_PCI_DOMAINS |
1884 | extern int pci_domains_supported; | |
1885 | #else | |
1886 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1887 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1888 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
32a2eea7 | 1889 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1890 | |
670ba0c8 CM |
1891 | /* |
1892 | * Generic implementation for PCI domain support. If your | |
1893 | * architecture does not need custom management of PCI | |
1894 | * domains then this implementation will be used | |
1895 | */ | |
1896 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1897 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1898 | { | |
1899 | return bus->domain_nr; | |
1900 | } | |
2ab51dde TN |
1901 | #ifdef CONFIG_ACPI |
1902 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); | |
670ba0c8 | 1903 | #else |
2ab51dde TN |
1904 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
1905 | { return 0; } | |
1906 | #endif | |
9c7cb891 | 1907 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
c14f7ccc | 1908 | void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); |
670ba0c8 CM |
1909 | #endif |
1910 | ||
0aa0f5d1 | 1911 | /* Some architectures require additional setup to direct VGA traffic */ |
95a8b6ef | 1912 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
0aa0f5d1 | 1913 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1914 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1915 | |
be9d2e89 JT |
1916 | static inline int |
1917 | pci_request_io_regions(struct pci_dev *pdev, const char *name) | |
1918 | { | |
1919 | return pci_request_selected_regions(pdev, | |
1920 | pci_select_bars(pdev, IORESOURCE_IO), name); | |
1921 | } | |
1922 | ||
1923 | static inline void | |
1924 | pci_release_io_regions(struct pci_dev *pdev) | |
1925 | { | |
1926 | return pci_release_selected_regions(pdev, | |
1927 | pci_select_bars(pdev, IORESOURCE_IO)); | |
1928 | } | |
1929 | ||
1930 | static inline int | |
1931 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) | |
1932 | { | |
1933 | return pci_request_selected_regions(pdev, | |
1934 | pci_select_bars(pdev, IORESOURCE_MEM), name); | |
1935 | } | |
1936 | ||
1937 | static inline void | |
1938 | pci_release_mem_regions(struct pci_dev *pdev) | |
1939 | { | |
1940 | return pci_release_selected_regions(pdev, | |
1941 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1942 | } | |
1943 | ||
4352dfd5 | 1944 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 | 1945 | |
5bbe029f BH |
1946 | static inline void pci_set_flags(int flags) { } |
1947 | static inline void pci_add_flags(int flags) { } | |
1948 | static inline void pci_clear_flags(int flags) { } | |
1949 | static inline int pci_has_flag(int flag) { return 0; } | |
1950 | ||
1da177e4 | 1951 | /* |
0aa0f5d1 BH |
1952 | * If the system does not have PCI, clearly these return errors. Define |
1953 | * these as simple inline functions to avoid hair in drivers. | |
1da177e4 | 1954 | */ |
05cca6e5 GKH |
1955 | #define _PCI_NOP(o, s, t) \ |
1956 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1957 | int where, t val) \ | |
1da177e4 | 1958 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1959 | |
1960 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1961 | _PCI_NOP(o, word, u16 x) \ | |
1962 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1963 | _PCI_NOP_ALL(read, *) |
1964 | _PCI_NOP_ALL(write,) | |
1965 | ||
d42552c3 | 1966 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1967 | unsigned int device, |
1968 | struct pci_dev *from) | |
2ee546c4 | 1969 | { return NULL; } |
d42552c3 | 1970 | |
05cca6e5 GKH |
1971 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1972 | unsigned int device, | |
1973 | unsigned int ss_vendor, | |
1974 | unsigned int ss_device, | |
b08508c4 | 1975 | struct pci_dev *from) |
2ee546c4 | 1976 | { return NULL; } |
1da177e4 | 1977 | |
05cca6e5 GKH |
1978 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1979 | struct pci_dev *from) | |
2ee546c4 | 1980 | { return NULL; } |
1da177e4 | 1981 | |
d427da23 SJ |
1982 | static inline struct pci_dev *pci_get_base_class(unsigned int class, |
1983 | struct pci_dev *from) | |
1984 | { return NULL; } | |
877fee2a HG |
1985 | |
1986 | static inline int pci_dev_present(const struct pci_device_id *ids) | |
1987 | { return 0; } | |
1988 | ||
ed4aaadb | 1989 | #define no_pci_devices() (1) |
1da177e4 LT |
1990 | #define pci_dev_put(dev) do { } while (0) |
1991 | ||
2ee546c4 | 1992 | static inline void pci_set_master(struct pci_dev *dev) { } |
2aa5ac63 | 1993 | static inline void pci_clear_master(struct pci_dev *dev) { } |
2ee546c4 BH |
1994 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } |
1995 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
977da073 | 1996 | static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } |
05cca6e5 | 1997 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1998 | { return -EBUSY; } |
817f9916 AS |
1999 | static inline int __must_check __pci_register_driver(struct pci_driver *drv, |
2000 | struct module *owner, | |
2001 | const char *mod_name) | |
2ee546c4 | 2002 | { return 0; } |
05cca6e5 | 2003 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
2004 | { return 0; } |
2005 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
f646c2a0 | 2006 | static inline u8 pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 2007 | { return 0; } |
05cca6e5 GKH |
2008 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
2009 | int cap) | |
2ee546c4 | 2010 | { return 0; } |
05cca6e5 | 2011 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 2012 | { return 0; } |
05cca6e5 | 2013 | |
70c0923b JK |
2014 | static inline u64 pci_get_dsn(struct pci_dev *dev) |
2015 | { return 0; } | |
2016 | ||
1da177e4 | 2017 | /* Power management related routines */ |
2ee546c4 BH |
2018 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
2019 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 2020 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 2021 | { return 0; } |
3449248c | 2022 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 2023 | { return 0; } |
05cca6e5 GKH |
2024 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
2025 | pm_message_t state) | |
2ee546c4 | 2026 | { return PCI_D0; } |
05cca6e5 GKH |
2027 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
2028 | int enable) | |
2ee546c4 | 2029 | { return 0; } |
48a92a81 | 2030 | |
afd29f90 MW |
2031 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
2032 | struct resource *res) | |
2033 | { return NULL; } | |
05cca6e5 | 2034 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
2035 | { return -EIO; } |
2036 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 2037 | |
00dcc7cf RH |
2038 | static inline int pci_register_io_range(struct fwnode_handle *fwnode, |
2039 | phys_addr_t addr, resource_size_t size) | |
2040 | { return -EINVAL; } | |
2041 | ||
c5076cfe TN |
2042 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
2043 | ||
d80d0217 RD |
2044 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
2045 | { return NULL; } | |
d80d0217 RD |
2046 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
2047 | unsigned int devfn) | |
2048 | { return NULL; } | |
7912af5c RD |
2049 | static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, |
2050 | unsigned int bus, unsigned int devfn) | |
2051 | { return NULL; } | |
d80d0217 | 2052 | |
2ee546c4 BH |
2053 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
2054 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
12ea6cad | 2055 | |
fb8a0d9d WM |
2056 | #define dev_is_pci(d) (false) |
2057 | #define dev_is_pf(d) (false) | |
fe594932 GU |
2058 | static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) |
2059 | { return false; } | |
80db6f08 NC |
2060 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
2061 | struct device_node *node, | |
2062 | const u32 *intspec, | |
2063 | unsigned int intsize, | |
2064 | unsigned long *out_hwirq, | |
2065 | unsigned int *out_type) | |
2066 | { return -EINVAL; } | |
9c212009 LR |
2067 | |
2068 | static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
2069 | struct pci_dev *dev) | |
2070 | { return NULL; } | |
b9ae16d8 | 2071 | static inline bool pci_ats_disabled(void) { return true; } |
0d8006dd HX |
2072 | |
2073 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
2074 | { | |
2075 | return -EINVAL; | |
2076 | } | |
2077 | ||
2078 | static inline int | |
2079 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
2080 | unsigned int max_vecs, unsigned int flags, | |
2081 | struct irq_affinity *aff_desc) | |
2082 | { | |
2083 | return -ENOSPC; | |
2084 | } | |
0d8006dd HX |
2085 | static inline int |
2086 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
2087 | unsigned int max_vecs, unsigned int flags) | |
2088 | { | |
5c0997dc | 2089 | return -ENOSPC; |
0d8006dd | 2090 | } |
5c0997dc | 2091 | #endif /* CONFIG_PCI */ |
0d8006dd | 2092 | |
4352dfd5 GKH |
2093 | /* Include architecture-dependent settings and functions */ |
2094 | ||
2095 | #include <asm/pci.h> | |
1da177e4 | 2096 | |
0ad722f1 | 2097 | /* |
f7195824 DW |
2098 | * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff |
2099 | * is expected to be an offset within that region. | |
2100 | * | |
f7195824 DW |
2101 | */ |
2102 | int pci_mmap_resource_range(struct pci_dev *dev, int bar, | |
2103 | struct vm_area_struct *vma, | |
2104 | enum pci_mmap_state mmap_state, int write_combine); | |
11df1954 | 2105 | |
ae749c7a DW |
2106 | #ifndef arch_can_pci_mmap_wc |
2107 | #define arch_can_pci_mmap_wc() 0 | |
2108 | #endif | |
2bea36fd | 2109 | |
e854d8b2 DW |
2110 | #ifndef arch_can_pci_mmap_io |
2111 | #define arch_can_pci_mmap_io() 0 | |
2bea36fd DW |
2112 | #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) |
2113 | #else | |
2114 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); | |
e854d8b2 | 2115 | #endif |
ae749c7a | 2116 | |
92016ba5 JO |
2117 | #ifndef pci_root_bus_fwnode |
2118 | #define pci_root_bus_fwnode(bus) NULL | |
2119 | #endif | |
2120 | ||
0aa0f5d1 BH |
2121 | /* |
2122 | * These helpers provide future and backwards compatibility | |
2123 | * for accessing popular PCI BAR info | |
2124 | */ | |
144d204d AS |
2125 | #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) |
2126 | #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) | |
2127 | #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) | |
2128 | #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) | |
2129 | #define pci_resource_len(dev,bar) \ | |
2130 | (pci_resource_end((dev), (bar)) ? \ | |
2131 | resource_size(pci_resource_n((dev), (bar))) : 0) | |
1da177e4 | 2132 | |
09cc9006 MW |
2133 | #define __pci_dev_for_each_res0(dev, res, ...) \ |
2134 | for (unsigned int __b = 0; \ | |
2135 | res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \ | |
2136 | __b++) | |
2137 | ||
2138 | #define __pci_dev_for_each_res1(dev, res, __b) \ | |
2139 | for (__b = 0; \ | |
2140 | res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \ | |
2141 | __b++) | |
2142 | ||
2143 | #define pci_dev_for_each_resource(dev, res, ...) \ | |
2144 | CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ | |
2145 | (dev, res, __VA_ARGS__) | |
1da177e4 | 2146 | |
0aa0f5d1 BH |
2147 | /* |
2148 | * Similar to the helpers above, these manipulate per-pci_dev | |
1da177e4 LT |
2149 | * driver-specific data. They are really just a wrapper around |
2150 | * the generic device structure functions of these calls. | |
2151 | */ | |
05cca6e5 | 2152 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
2153 | { |
2154 | return dev_get_drvdata(&pdev->dev); | |
2155 | } | |
2156 | ||
05cca6e5 | 2157 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
2158 | { |
2159 | dev_set_drvdata(&pdev->dev, data); | |
2160 | } | |
2161 | ||
2fc90f61 | 2162 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 2163 | { |
c6c4f070 | 2164 | return dev_name(&pdev->dev); |
1da177e4 LT |
2165 | } |
2166 | ||
8221a013 BH |
2167 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
2168 | const struct resource *rsrc, | |
2169 | resource_size_t *start, resource_size_t *end); | |
2311b1f2 | 2170 | |
1da177e4 | 2171 | /* |
0aa0f5d1 BH |
2172 | * The world is not perfect and supplies us with broken PCI devices. |
2173 | * For at least a part of these bugs we need a work-around, so both | |
2174 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
2175 | * fixup hooks to be called for particular buggy devices. | |
1da177e4 LT |
2176 | */ |
2177 | ||
2178 | struct pci_fixup { | |
0aa0f5d1 BH |
2179 | u16 vendor; /* Or PCI_ANY_ID */ |
2180 | u16 device; /* Or PCI_ANY_ID */ | |
2181 | u32 class; /* Or PCI_ANY_ID */ | |
f4ca5c6a | 2182 | unsigned int class_shift; /* should be 0, 8, 16 */ |
c9d8b55f AB |
2183 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
2184 | int hook_offset; | |
2185 | #else | |
1da177e4 | 2186 | void (*hook)(struct pci_dev *dev); |
c9d8b55f | 2187 | #endif |
1da177e4 LT |
2188 | }; |
2189 | ||
2190 | enum pci_fixup_pass { | |
2191 | pci_fixup_early, /* Before probing BARs */ | |
2192 | pci_fixup_header, /* After reading configuration header */ | |
2193 | pci_fixup_final, /* Final phase of device fixups */ | |
2194 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 2195 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 2196 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 2197 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 2198 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
2199 | }; |
2200 | ||
c9d8b55f | 2201 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
09a4e4d9 | 2202 | #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ |
c9d8b55f AB |
2203 | class_shift, hook) \ |
2204 | __ADDRESSABLE(hook) \ | |
2205 | asm(".section " #sec ", \"a\" \n" \ | |
2206 | ".balign 16 \n" \ | |
2207 | ".short " #vendor ", " #device " \n" \ | |
2208 | ".long " #class ", " #class_shift " \n" \ | |
2209 | ".long " #hook " - . \n" \ | |
2210 | ".previous \n"); | |
09a4e4d9 ST |
2211 | |
2212 | /* | |
2213 | * Clang's LTO may rename static functions in C, but has no way to | |
2214 | * handle such renamings when referenced from inline asm. To work | |
2215 | * around this, create global C stubs for these cases. | |
2216 | */ | |
2217 | #ifdef CONFIG_LTO_CLANG | |
2218 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2219 | class_shift, hook, stub) \ | |
5659b598 ST |
2220 | void stub(struct pci_dev *dev); \ |
2221 | void stub(struct pci_dev *dev) \ | |
09a4e4d9 ST |
2222 | { \ |
2223 | hook(dev); \ | |
2224 | } \ | |
2225 | ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2226 | class_shift, stub) | |
2227 | #else | |
2228 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2229 | class_shift, hook, stub) \ | |
2230 | ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2231 | class_shift, hook) | |
2232 | #endif | |
2233 | ||
c9d8b55f AB |
2234 | #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ |
2235 | class_shift, hook) \ | |
2236 | __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
09a4e4d9 | 2237 | class_shift, hook, __UNIQUE_ID(hook)) |
c9d8b55f | 2238 | #else |
1da177e4 | 2239 | /* Anonymous variables would be nice... */ |
f4ca5c6a YL |
2240 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
2241 | class_shift, hook) \ | |
ecf61c78 | 2242 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
2243 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
2244 | = { vendor, device, class, class_shift, hook }; | |
c9d8b55f | 2245 | #endif |
f4ca5c6a YL |
2246 | |
2247 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
2248 | class_shift, hook) \ | |
2249 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 2250 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2251 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
2252 | class_shift, hook) \ | |
2253 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 2254 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2255 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
2256 | class_shift, hook) \ | |
2257 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 2258 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2259 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
2260 | class_shift, hook) \ | |
2261 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 2262 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2263 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
2264 | class_shift, hook) \ | |
2265 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 2266 | resume##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2267 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
2268 | class_shift, hook) \ | |
2269 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 2270 | resume_early##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2271 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
2272 | class_shift, hook) \ | |
2273 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 2274 | suspend##hook, vendor, device, class, class_shift, hook) |
7d2a01b8 AN |
2275 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
2276 | class_shift, hook) \ | |
2277 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 2278 | suspend_late##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a | 2279 | |
1da177e4 LT |
2280 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
2281 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 2282 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2283 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
2284 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 2285 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2286 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
2287 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 2288 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2289 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
2290 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 2291 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
2292 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
2293 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 2294 | resume##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
2295 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
2296 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 2297 | resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
2298 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
2299 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 2300 | suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
2301 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
2302 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 2303 | suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 | 2304 | |
93177a74 | 2305 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 2306 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
2307 | #else |
2308 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 2309 | struct pci_dev *dev) { } |
93177a74 | 2310 | #endif |
1da177e4 | 2311 | |
05cca6e5 | 2312 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 2313 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 2314 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
2315 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
2316 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 2317 | const char *name); |
fb7ebfe4 | 2318 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 2319 | |
1da177e4 | 2320 | extern int pci_pci_problems; |
236561e5 | 2321 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
2322 | #define PCIPCI_TRITON 2 |
2323 | #define PCIPCI_NATOMA 4 | |
2324 | #define PCIPCI_VIAETBF 8 | |
2325 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
2326 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
2327 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 2328 | |
4516a618 AN |
2329 | extern unsigned long pci_cardbus_io_size; |
2330 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 2331 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 2332 | extern u8 pci_cache_line_size; |
4516a618 | 2333 | |
f7625980 | 2334 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 2335 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 2336 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
2337 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2338 | enum pcie_reset_state state); | |
06dc660e | 2339 | int pcibios_device_add(struct pci_dev *dev); |
6ae32c53 | 2340 | void pcibios_release_device(struct pci_dev *dev); |
5d32a665 | 2341 | #ifdef CONFIG_PCI |
a43ae58c | 2342 | void pcibios_penalize_isa_irq(int irq, int active); |
5d32a665 SK |
2343 | #else |
2344 | static inline void pcibios_penalize_isa_irq(int irq, int active) {} | |
2345 | #endif | |
890e4847 JL |
2346 | int pcibios_alloc_irq(struct pci_dev *dev); |
2347 | void pcibios_free_irq(struct pci_dev *dev); | |
619e6f34 | 2348 | resource_size_t pcibios_default_alignment(void); |
575e3348 | 2349 | |
87382ead AB |
2350 | #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) |
2351 | extern int pci_create_resource_files(struct pci_dev *dev); | |
2352 | extern void pci_remove_resource_files(struct pci_dev *dev); | |
2353 | #endif | |
2354 | ||
935c760e | 2355 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
f39d5b72 BH |
2356 | void __init pci_mmcfg_early_init(void); |
2357 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 2358 | #else |
bb63b421 | 2359 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
2360 | static inline void pci_mmcfg_late_init(void) { } |
2361 | #endif | |
2362 | ||
642c92da | 2363 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 2364 | |
1684f5dd | 2365 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
c43996f4 | 2366 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 2367 | |
dd7cc44d | 2368 | #ifdef CONFIG_PCI_IOV |
b07579c0 WY |
2369 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
2370 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); | |
21ca9fb6 | 2371 | int pci_iov_vf_id(struct pci_dev *dev); |
a7e9f240 | 2372 | void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); |
f39d5b72 BH |
2373 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
2374 | void pci_disable_sriov(struct pci_dev *dev); | |
a1ceea67 NS |
2375 | |
2376 | int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); | |
753f6124 JS |
2377 | int pci_iov_add_virtfn(struct pci_dev *dev, int id); |
2378 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id); | |
f39d5b72 | 2379 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 2380 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
2381 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
2382 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
8effc395 | 2383 | int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); |
0e6c9122 | 2384 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
608c0d88 | 2385 | void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); |
619e6f34 MM |
2386 | |
2387 | /* Arch may override these (weak) */ | |
2388 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); | |
2389 | int pcibios_sriov_disable(struct pci_dev *pdev); | |
2390 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); | |
dd7cc44d | 2391 | #else |
b07579c0 WY |
2392 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
2393 | { | |
2394 | return -ENOSYS; | |
2395 | } | |
2396 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) | |
2397 | { | |
2398 | return -ENOSYS; | |
2399 | } | |
21ca9fb6 JG |
2400 | |
2401 | static inline int pci_iov_vf_id(struct pci_dev *dev) | |
2402 | { | |
2403 | return -ENOSYS; | |
2404 | } | |
2405 | ||
a7e9f240 JG |
2406 | static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, |
2407 | struct pci_driver *pf_driver) | |
2408 | { | |
2409 | return ERR_PTR(-EINVAL); | |
2410 | } | |
2411 | ||
dd7cc44d | 2412 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
2ee546c4 | 2413 | { return -ENODEV; } |
a1ceea67 NS |
2414 | |
2415 | static inline int pci_iov_sysfs_link(struct pci_dev *dev, | |
2416 | struct pci_dev *virtfn, int id) | |
2417 | { | |
2418 | return -ENODEV; | |
2419 | } | |
753f6124 | 2420 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) |
c194f7ea WY |
2421 | { |
2422 | return -ENOSYS; | |
2423 | } | |
2424 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, | |
753f6124 | 2425 | int id) { } |
2ee546c4 | 2426 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
2ee546c4 | 2427 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 2428 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 2429 | { return 0; } |
bff73156 | 2430 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 2431 | { return 0; } |
bff73156 | 2432 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 2433 | { return 0; } |
8effc395 | 2434 | #define pci_sriov_configure_simple NULL |
0e6c9122 WY |
2435 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
2436 | { return 0; } | |
608c0d88 | 2437 | static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } |
dd7cc44d YZ |
2438 | #endif |
2439 | ||
c825bc94 | 2440 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
2441 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
2442 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
2443 | #endif |
2444 | ||
d7b7e605 KK |
2445 | /** |
2446 | * pci_pcie_cap - get the saved PCIe capability offset | |
2447 | * @dev: PCI device | |
2448 | * | |
2449 | * PCIe capability offset is calculated at PCI device initialization | |
2450 | * time and saved in the data structure. This function returns saved | |
2451 | * PCIe capability offset. Using this instead of pci_find_capability() | |
2452 | * reduces unnecessary search in the PCI configuration space. If you | |
2453 | * need to calculate PCIe capability offset from raw device for some | |
2454 | * reasons, please use pci_find_capability() instead. | |
2455 | */ | |
2456 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
2457 | { | |
2458 | return dev->pcie_cap; | |
2459 | } | |
2460 | ||
7eb776c4 KK |
2461 | /** |
2462 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
2463 | * @dev: PCI device | |
2464 | * | |
a895c28a | 2465 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
2466 | */ |
2467 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
2468 | { | |
a895c28a | 2469 | return pci_pcie_cap(dev); |
7eb776c4 KK |
2470 | } |
2471 | ||
7c9c003c MS |
2472 | /** |
2473 | * pcie_caps_reg - get the PCIe Capabilities Register | |
2474 | * @dev: PCI device | |
2475 | */ | |
2476 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
2477 | { | |
2478 | return dev->pcie_flags_reg; | |
2479 | } | |
2480 | ||
786e2288 YW |
2481 | /** |
2482 | * pci_pcie_type - get the PCIe device/port type | |
2483 | * @dev: PCI device | |
2484 | */ | |
2485 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
2486 | { | |
1c531d82 | 2487 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
2488 | } |
2489 | ||
6ae72bfa YY |
2490 | /** |
2491 | * pcie_find_root_port - Get the PCIe root port device | |
2492 | * @dev: PCI device | |
2493 | * | |
2494 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
2495 | * for a given PCI/PCIe Device. | |
2496 | */ | |
e784930b JT |
2497 | static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) |
2498 | { | |
5396956c MW |
2499 | while (dev) { |
2500 | if (pci_is_pcie(dev) && | |
2501 | pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2502 | return dev; | |
2503 | dev = pci_upstream_bridge(dev); | |
e784930b | 2504 | } |
6ae72bfa | 2505 | |
e784930b JT |
2506 | return NULL; |
2507 | } | |
2508 | ||
5d990b62 | 2509 | void pci_request_acs(void); |
ad805758 AW |
2510 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
2511 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2512 | struct pci_dev *end, u16 acs_flags); | |
430a2368 | 2513 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); |
a2ce7662 | 2514 | |
7ad506fa | 2515 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 2516 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
2517 | |
2518 | /* Large Resource Data Type Tag Item Names */ | |
2519 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
2520 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
2521 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
2522 | ||
2523 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
2524 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
2525 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
2526 | ||
4067a854 | 2527 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
16efafa3 | 2528 | #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" |
4067a854 MC |
2529 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
2530 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 2531 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 2532 | |
a2ce7662 | 2533 | /** |
76f3c032 HK |
2534 | * pci_vpd_alloc - Allocate buffer and read VPD into it |
2535 | * @dev: PCI device | |
2536 | * @size: pointer to field where VPD length is returned | |
9eb45d5c | 2537 | * |
76f3c032 | 2538 | * Returns pointer to allocated buffer or an ERR_PTR in case of failure |
9eb45d5c | 2539 | */ |
76f3c032 | 2540 | void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); |
9eb45d5c | 2541 | |
e1d5bdab | 2542 | /** |
acfbb1b8 HK |
2543 | * pci_vpd_find_id_string - Locate id string in VPD |
2544 | * @buf: Pointer to buffered VPD data | |
2545 | * @len: The length of the buffer area in which to search | |
2546 | * @size: Pointer to field where length of id string is returned | |
e1d5bdab | 2547 | * |
acfbb1b8 | 2548 | * Returns the index of the id string or -ENOENT if not found. |
e1d5bdab | 2549 | */ |
acfbb1b8 | 2550 | int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); |
e1d5bdab | 2551 | |
b55ac1b2 | 2552 | /** |
9e515c9f HK |
2553 | * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section |
2554 | * @buf: Pointer to buffered VPD data | |
2555 | * @len: The length of the buffer area in which to search | |
2556 | * @kw: The keyword to search for | |
2557 | * @size: Pointer to field where length of found keyword data is returned | |
b55ac1b2 | 2558 | * |
9e515c9f HK |
2559 | * Returns the index of the information field keyword data or -ENOENT if |
2560 | * not found. | |
b55ac1b2 | 2561 | */ |
9e515c9f HK |
2562 | int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, |
2563 | const char *kw, unsigned int *size); | |
b55ac1b2 | 2564 | |
4067a854 | 2565 | /** |
6107e5cb HK |
2566 | * pci_vpd_check_csum - Check VPD checksum |
2567 | * @buf: Pointer to buffered VPD data | |
2568 | * @len: VPD size | |
4067a854 | 2569 | * |
6107e5cb | 2570 | * Returns 1 if VPD has no checksum, otherwise 0 or an errno |
4067a854 | 2571 | */ |
6107e5cb | 2572 | int pci_vpd_check_csum(const void *buf, unsigned int len); |
4067a854 | 2573 | |
98d9f30c BH |
2574 | /* PCI <-> OF binding helpers */ |
2575 | #ifdef CONFIG_OF | |
2576 | struct device_node; | |
b165e2b6 | 2577 | struct irq_domain; |
b165e2b6 | 2578 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
85aabbd7 | 2579 | bool pci_host_of_has_msi_map(struct device *dev); |
98d9f30c BH |
2580 | |
2581 | /* Arch may override this (weak) */ | |
723ec4d0 | 2582 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 2583 | |
0aa0f5d1 | 2584 | #else /* CONFIG_OF */ |
b165e2b6 MZ |
2585 | static inline struct irq_domain * |
2586 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } | |
85aabbd7 | 2587 | static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } |
98d9f30c BH |
2588 | #endif /* CONFIG_OF */ |
2589 | ||
ad32eb2d BM |
2590 | static inline struct device_node * |
2591 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
2592 | { | |
2593 | return pdev ? pdev->dev.of_node : NULL; | |
2594 | } | |
2595 | ||
2596 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) | |
2597 | { | |
2598 | return bus ? bus->dev.of_node : NULL; | |
2599 | } | |
2600 | ||
471036b2 SS |
2601 | #ifdef CONFIG_ACPI |
2602 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); | |
2603 | ||
2604 | void | |
2605 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); | |
52525b7a | 2606 | bool pci_pr3_present(struct pci_dev *pdev); |
471036b2 SS |
2607 | #else |
2608 | static inline struct irq_domain * | |
2609 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } | |
46b4bff6 | 2610 | static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } |
471036b2 SS |
2611 | #endif |
2612 | ||
eb740b5f GS |
2613 | #ifdef CONFIG_EEH |
2614 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
2615 | { | |
2616 | return pdev->dev.archdata.edev; | |
2617 | } | |
2618 | #endif | |
2619 | ||
09298542 | 2620 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); |
338c3149 | 2621 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
c25dc828 AW |
2622 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
2623 | int (*fn)(struct pci_dev *pdev, | |
2624 | u16 alias, void *data), void *data); | |
2625 | ||
0aa0f5d1 | 2626 | /* Helper functions for operation of device flag */ |
ce052984 EZ |
2627 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
2628 | { | |
2629 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
2630 | } | |
2631 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
2632 | { | |
2633 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
2634 | } | |
2635 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
2636 | { | |
2637 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
2638 | } | |
19bdb6e4 AW |
2639 | |
2640 | /** | |
2641 | * pci_ari_enabled - query ARI forwarding status | |
2642 | * @bus: the PCI bus | |
2643 | * | |
2644 | * Returns true if ARI forwarding is enabled. | |
2645 | */ | |
2646 | static inline bool pci_ari_enabled(struct pci_bus *bus) | |
2647 | { | |
2648 | return bus->self && bus->self->ari_enabled; | |
2649 | } | |
bc4b024a | 2650 | |
8531e283 LW |
2651 | /** |
2652 | * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain | |
2653 | * @pdev: PCI device to check | |
2654 | * | |
2655 | * Walk upwards from @pdev and check for each encountered bridge if it's part | |
2656 | * of a Thunderbolt controller. Reaching the host bridge means @pdev is not | |
2657 | * Thunderbolt-attached. (But rather soldered to the mainboard usually.) | |
2658 | */ | |
2659 | static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) | |
2660 | { | |
2661 | struct pci_dev *parent = pdev; | |
2662 | ||
2663 | if (pdev->is_thunderbolt) | |
2664 | return true; | |
2665 | ||
2666 | while ((parent = pci_upstream_bridge(parent))) | |
2667 | if (parent->is_thunderbolt) | |
2668 | return true; | |
2669 | ||
2670 | return false; | |
2671 | } | |
2672 | ||
2e28bc84 | 2673 | #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) |
3ecac020 ME |
2674 | void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); |
2675 | #endif | |
856e1eb9 | 2676 | |
79687789 | 2677 | #include <linux/dma-mapping.h> |
bc4b024a | 2678 | |
7506dc79 FL |
2679 | #define pci_printk(level, pdev, fmt, arg...) \ |
2680 | dev_printk(level, &(pdev)->dev, fmt, ##arg) | |
2681 | ||
2682 | #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) | |
2683 | #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) | |
2684 | #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) | |
2685 | #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) | |
2686 | #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) | |
27829479 | 2687 | #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) |
7506dc79 FL |
2688 | #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) |
2689 | #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) | |
2690 | #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) | |
2691 | ||
a88a7b3e BH |
2692 | #define pci_notice_ratelimited(pdev, fmt, arg...) \ |
2693 | dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2694 | ||
7f1c62c4 KW |
2695 | #define pci_info_ratelimited(pdev, fmt, arg...) \ |
2696 | dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2697 | ||
12bcae44 BH |
2698 | #define pci_WARN(pdev, condition, fmt, arg...) \ |
2699 | WARN(condition, "%s %s: " fmt, \ | |
2700 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2701 | ||
2702 | #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ | |
2703 | WARN_ONCE(condition, "%s %s: " fmt, \ | |
2704 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2705 | ||
1da177e4 | 2706 | #endif /* LINUX_PCI_H */ |