Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
1da177e4 LT |
16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H | |
18 | ||
1da177e4 | 19 | |
778382e0 DW |
20 | #include <linux/mod_devicetable.h> |
21 | ||
1da177e4 | 22 | #include <linux/types.h> |
98db6f19 | 23 | #include <linux/init.h> |
1da177e4 LT |
24 | #include <linux/ioport.h> |
25 | #include <linux/list.h> | |
4a7fb636 | 26 | #include <linux/compiler.h> |
1da177e4 | 27 | #include <linux/errno.h> |
f46753c5 | 28 | #include <linux/kobject.h> |
60063497 | 29 | #include <linux/atomic.h> |
1da177e4 | 30 | #include <linux/device.h> |
1388cc96 | 31 | #include <linux/io.h> |
14d76b68 | 32 | #include <linux/resource_ext.h> |
607ca46e | 33 | #include <uapi/linux/pci.h> |
1da177e4 | 34 | |
7e7a43c3 AB |
35 | #include <linux/pci_ids.h> |
36 | ||
85467136 SK |
37 | /* |
38 | * The PCI interface treats multi-function devices as independent | |
39 | * devices. The slot/function address of each device is encoded | |
40 | * in a single byte as follows: | |
41 | * | |
42 | * 7:3 = slot | |
43 | * 2:0 = function | |
f7625980 BH |
44 | * |
45 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 46 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 47 | * the following kernel-only defines are being added here. |
85467136 | 48 | */ |
63ddc0b8 | 49 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
50 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
51 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
52 | ||
f46753c5 AC |
53 | /* pci_slot represents a physical slot */ |
54 | struct pci_slot { | |
55 | struct pci_bus *bus; /* The bus this slot is on */ | |
56 | struct list_head list; /* node in list of slots on this bus */ | |
57 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
58 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
59 | struct kobject kobj; | |
60 | }; | |
61 | ||
0ad772ec AC |
62 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
63 | { | |
64 | return kobject_name(&slot->kobj); | |
65 | } | |
66 | ||
1da177e4 LT |
67 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
68 | enum pci_mmap_state { | |
69 | pci_mmap_io, | |
70 | pci_mmap_mem | |
71 | }; | |
72 | ||
fde09c6d YZ |
73 | /* |
74 | * For PCI devices, the region numbers are assigned this way: | |
75 | */ | |
76 | enum { | |
77 | /* #0-5: standard PCI resources */ | |
78 | PCI_STD_RESOURCES, | |
79 | PCI_STD_RESOURCE_END = 5, | |
80 | ||
81 | /* #6: expansion ROM resource */ | |
82 | PCI_ROM_RESOURCE, | |
83 | ||
d1b054da YZ |
84 | /* device specific resources */ |
85 | #ifdef CONFIG_PCI_IOV | |
86 | PCI_IOV_RESOURCES, | |
87 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
88 | #endif | |
89 | ||
fde09c6d YZ |
90 | /* resources assigned to buses behind the bridge */ |
91 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
92 | ||
93 | PCI_BRIDGE_RESOURCES, | |
94 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
95 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
96 | ||
97 | /* total resources associated with a PCI device */ | |
98 | PCI_NUM_RESOURCES, | |
99 | ||
100 | /* preserve this for compatibility */ | |
cda57bf9 | 101 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 102 | }; |
1da177e4 | 103 | |
224abb67 BH |
104 | /* |
105 | * pci_power_t values must match the bits in the Capabilities PME_Support | |
106 | * and Control/Status PowerState fields in the Power Management capability. | |
107 | */ | |
1da177e4 LT |
108 | typedef int __bitwise pci_power_t; |
109 | ||
4352dfd5 GKH |
110 | #define PCI_D0 ((pci_power_t __force) 0) |
111 | #define PCI_D1 ((pci_power_t __force) 1) | |
112 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
113 | #define PCI_D3hot ((pci_power_t __force) 3) |
114 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 115 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 116 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 117 | |
00240c38 AS |
118 | /* Remember to update this when the list above changes! */ |
119 | extern const char *pci_power_names[]; | |
120 | ||
121 | static inline const char *pci_power_name(pci_power_t state) | |
122 | { | |
9661e783 | 123 | return pci_power_names[1 + (__force int) state]; |
00240c38 AS |
124 | } |
125 | ||
448bd857 HY |
126 | #define PCI_PM_D2_DELAY 200 |
127 | #define PCI_PM_D3_WAIT 10 | |
128 | #define PCI_PM_D3COLD_WAIT 100 | |
129 | #define PCI_PM_BUS_WAIT 50 | |
aa8c6c93 | 130 | |
392a1ce7 | 131 | /** The pci_channel state describes connectivity between the CPU and |
132 | * the pci device. If some PCI bus between here and the pci device | |
133 | * has crashed or locked up, this info is reflected here. | |
134 | */ | |
135 | typedef unsigned int __bitwise pci_channel_state_t; | |
136 | ||
137 | enum pci_channel_state { | |
138 | /* I/O channel is in normal state */ | |
139 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
140 | ||
141 | /* I/O to channel is blocked */ | |
142 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
143 | ||
144 | /* PCI card is dead */ | |
145 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
146 | }; | |
147 | ||
f7bdd12d BK |
148 | typedef unsigned int __bitwise pcie_reset_state_t; |
149 | ||
150 | enum pcie_reset_state { | |
151 | /* Reset is NOT asserted (Use to deassert reset) */ | |
152 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
153 | ||
f7625980 | 154 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
155 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
156 | ||
f7625980 | 157 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
158 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
159 | }; | |
160 | ||
ba698ad4 DM |
161 | typedef unsigned short __bitwise pci_dev_flags_t; |
162 | enum pci_dev_flags { | |
163 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
164 | * generation too. | |
165 | */ | |
6b121592 | 166 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 167 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 168 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 169 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 170 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 171 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 172 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
c8fe16e3 AW |
173 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
174 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
175 | /* Do not use bus resets for device */ |
176 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
177 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
178 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
932c435c MR |
179 | /* Get VPD from function 0 VPD */ |
180 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), | |
ba698ad4 DM |
181 | }; |
182 | ||
e1d3a908 SA |
183 | enum pci_irq_reroute_variant { |
184 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
185 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
186 | }; | |
187 | ||
6e325a62 MT |
188 | typedef unsigned short __bitwise pci_bus_flags_t; |
189 | enum pci_bus_flags { | |
032c3d86 JD |
190 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
191 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
192 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, | |
6e325a62 MT |
193 | }; |
194 | ||
59da381e JK |
195 | /* These values come from the PCI Express Spec */ |
196 | enum pcie_link_width { | |
197 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
198 | PCIE_LNK_X1 = 0x01, | |
199 | PCIE_LNK_X2 = 0x02, | |
200 | PCIE_LNK_X4 = 0x04, | |
201 | PCIE_LNK_X8 = 0x08, | |
202 | PCIE_LNK_X12 = 0x0C, | |
203 | PCIE_LNK_X16 = 0x10, | |
204 | PCIE_LNK_X32 = 0x20, | |
205 | PCIE_LNK_WIDTH_UNKNOWN = 0xFF, | |
206 | }; | |
207 | ||
536c8cb4 MW |
208 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
209 | enum pci_bus_speed { | |
210 | PCI_SPEED_33MHz = 0x00, | |
211 | PCI_SPEED_66MHz = 0x01, | |
212 | PCI_SPEED_66MHz_PCIX = 0x02, | |
213 | PCI_SPEED_100MHz_PCIX = 0x03, | |
214 | PCI_SPEED_133MHz_PCIX = 0x04, | |
215 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
216 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
217 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
218 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
219 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
220 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
221 | AGP_UNKNOWN = 0x0c, |
222 | AGP_1X = 0x0d, | |
223 | AGP_2X = 0x0e, | |
224 | AGP_4X = 0x0f, | |
225 | AGP_8X = 0x10, | |
536c8cb4 MW |
226 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
227 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
228 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
229 | PCIE_SPEED_2_5GT = 0x14, | |
230 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 231 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
232 | PCI_SPEED_UNKNOWN = 0xff, |
233 | }; | |
234 | ||
24a4742f | 235 | struct pci_cap_saved_data { |
fd0f7f73 AW |
236 | u16 cap_nr; |
237 | bool cap_extended; | |
24a4742f | 238 | unsigned int size; |
41017f0c SL |
239 | u32 data[0]; |
240 | }; | |
241 | ||
24a4742f AW |
242 | struct pci_cap_saved_state { |
243 | struct hlist_node next; | |
244 | struct pci_cap_saved_data cap; | |
245 | }; | |
246 | ||
7d715a6c | 247 | struct pcie_link_state; |
ee69439c | 248 | struct pci_vpd; |
d1b054da | 249 | struct pci_sriov; |
302b4215 | 250 | struct pci_ats; |
ee69439c | 251 | |
1da177e4 LT |
252 | /* |
253 | * The pci_dev structure is used to describe PCI devices. | |
254 | */ | |
255 | struct pci_dev { | |
1da177e4 LT |
256 | struct list_head bus_list; /* node in per-bus list */ |
257 | struct pci_bus *bus; /* bus this device is on */ | |
258 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
259 | ||
260 | void *sysdata; /* hook for sys-specific extension */ | |
261 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 262 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
263 | |
264 | unsigned int devfn; /* encoded device & function index */ | |
265 | unsigned short vendor; | |
266 | unsigned short device; | |
267 | unsigned short subsystem_vendor; | |
268 | unsigned short subsystem_device; | |
269 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 270 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 271 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
66b80809 KB |
272 | #ifdef CONFIG_PCIEAER |
273 | u16 aer_cap; /* AER capability offset */ | |
274 | #endif | |
f7625980 | 275 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
276 | u8 msi_cap; /* MSI capability offset */ |
277 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 278 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
1da177e4 | 279 | u8 rom_base_reg; /* which config register controls the ROM */ |
f7625980 BH |
280 | u8 pin; /* which interrupt pin this device uses */ |
281 | u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ | |
338c3149 | 282 | unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ |
1da177e4 LT |
283 | |
284 | struct pci_driver *driver; /* which driver has allocated this device */ | |
285 | u64 dma_mask; /* Mask of the bits of bus address this | |
286 | device implements. Normally this is | |
287 | 0xffffffff. You only need to change | |
288 | this if your device has broken DMA | |
289 | or supports 64-bit transfers. */ | |
290 | ||
4d57cdfa FT |
291 | struct device_dma_parameters dma_parms; |
292 | ||
1da177e4 LT |
293 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
294 | this is D0-D3, D0 being fully functional, | |
295 | and D3 being off. */ | |
703860ed | 296 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
297 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
298 | can be generated */ | |
c7f48656 | 299 | unsigned int pme_interrupt:1; |
379021d5 | 300 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
301 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
302 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
303 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
304 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
9d26d3a8 | 305 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
448bd857 | 306 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
253d2e54 JP |
307 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
308 | decoding during bar sizing */ | |
e80bb09d | 309 | unsigned int wakeup_prepared:1; |
448bd857 HY |
310 | unsigned int runtime_d3cold:1; /* whether go through runtime |
311 | D3cold, not set for devices | |
312 | powered on/off by the | |
313 | corresponding bridge */ | |
b440bde7 | 314 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
576243b3 KB |
315 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
316 | controlled exclusively by | |
317 | user sysfs */ | |
1ae861e6 | 318 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
448bd857 | 319 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 320 | |
7d715a6c | 321 | #ifdef CONFIG_PCIEASPM |
f7625980 | 322 | struct pcie_link_state *link_state; /* ASPM link state */ |
7d715a6c SL |
323 | #endif |
324 | ||
392a1ce7 | 325 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
326 | struct device dev; /* Generic device interface */ |
327 | ||
1da177e4 LT |
328 | int cfg_size; /* Size of configuration space */ |
329 | ||
330 | /* | |
331 | * Instead of touching interrupt line and base address registers | |
332 | * directly, use the values stored here. They might be different! | |
333 | */ | |
334 | unsigned int irq; | |
4ef33685 | 335 | struct cpumask *irq_affinity; |
1da177e4 LT |
336 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
337 | ||
58d9a38f | 338 | bool match_driver; /* Skip attaching driver */ |
1da177e4 | 339 | /* These fields are used by common fixups */ |
f7625980 | 340 | unsigned int transparent:1; /* Subtractive decode PCI bridge */ |
1da177e4 LT |
341 | unsigned int multifunction:1;/* Part of multi-function device */ |
342 | /* keep track of device state */ | |
8a1bc901 | 343 | unsigned int is_added:1; |
1da177e4 | 344 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 345 | unsigned int no_msi:1; /* device may not use msi */ |
f144d149 | 346 | unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ |
fb51ccbf | 347 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
bd8481e1 | 348 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 349 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
f7625980 | 350 | unsigned int msi_enabled:1; |
99dc804d | 351 | unsigned int msix_enabled:1; |
58c3a727 | 352 | unsigned int ari_enabled:1; /* ARI forwarding */ |
d544d75a | 353 | unsigned int ats_enabled:1; /* Address Translation Service */ |
9ac7849e | 354 | unsigned int is_managed:1; |
260d703a | 355 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 356 | unsigned int state_saved:1; |
d1b054da | 357 | unsigned int is_physfn:1; |
dd7cc44d | 358 | unsigned int is_virtfn:1; |
711d5779 | 359 | unsigned int reset_fn:1; |
28760489 | 360 | unsigned int is_hotplug_bridge:1; |
affb72c3 HY |
361 | unsigned int __aer_firmware_first_valid:1; |
362 | unsigned int __aer_firmware_first:1; | |
fbebb9fd | 363 | unsigned int broken_intx_masking:1; |
2b28ae19 | 364 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
cffe0a2b | 365 | unsigned int irq_managed:1; |
d0751b98 | 366 | unsigned int has_secondary_link:1; |
b84106b4 | 367 | unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ |
ba698ad4 | 368 | pci_dev_flags_t dev_flags; |
bae94d02 | 369 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 370 | |
1da177e4 | 371 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 372 | struct hlist_head saved_cap_space; |
1da177e4 LT |
373 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
374 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
375 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 376 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
9bb04a0c JY |
377 | |
378 | #ifdef CONFIG_PCIE_PTM | |
379 | unsigned int ptm_root:1; | |
380 | unsigned int ptm_enabled:1; | |
8b2ec318 | 381 | u8 ptm_granularity; |
9bb04a0c | 382 | #endif |
ded86d8d | 383 | #ifdef CONFIG_PCI_MSI |
1c51b50c | 384 | const struct attribute_group **msi_irq_groups; |
ded86d8d | 385 | #endif |
94e61088 | 386 | struct pci_vpd *vpd; |
466b3ddf | 387 | #ifdef CONFIG_PCI_ATS |
dd7cc44d YZ |
388 | union { |
389 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
390 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
391 | }; | |
67930995 BH |
392 | u16 ats_cap; /* ATS Capability offset */ |
393 | u8 ats_stu; /* ATS Smallest Translation Unit */ | |
d544d75a | 394 | atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ |
d1b054da | 395 | #endif |
dbd3fc33 | 396 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
84c1b80e | 397 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
782a985d | 398 | char *driver_override; /* Driver name to force a match */ |
1da177e4 LT |
399 | }; |
400 | ||
dda56549 Y |
401 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
402 | { | |
403 | #ifdef CONFIG_PCI_IOV | |
404 | if (dev->is_virtfn) | |
405 | dev = dev->physfn; | |
406 | #endif | |
dda56549 Y |
407 | return dev; |
408 | } | |
409 | ||
3c6e6ae7 | 410 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 411 | |
1da177e4 LT |
412 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
413 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
414 | ||
a7369f1f LV |
415 | static inline int pci_channel_offline(struct pci_dev *pdev) |
416 | { | |
417 | return (pdev->error_state != pci_channel_io_normal); | |
418 | } | |
419 | ||
5a21d70d | 420 | struct pci_host_bridge { |
7b543663 | 421 | struct device dev; |
5a21d70d | 422 | struct pci_bus *bus; /* root bus */ |
37d6a0a6 AB |
423 | struct pci_ops *ops; |
424 | void *sysdata; | |
425 | int busnr; | |
14d76b68 | 426 | struct list_head windows; /* resource_entry */ |
4fa2649a YL |
427 | void (*release_fn)(struct pci_host_bridge *); |
428 | void *release_data; | |
37d6a0a6 | 429 | struct msi_controller *msi; |
e33caa82 | 430 | unsigned int ignore_reset_delay:1; /* for entire hierarchy */ |
7c7a0e94 GP |
431 | /* Resource alignment requirements */ |
432 | resource_size_t (*align_resource)(struct pci_dev *dev, | |
433 | const struct resource *res, | |
434 | resource_size_t start, | |
435 | resource_size_t size, | |
436 | resource_size_t align); | |
59094065 | 437 | unsigned long private[0] ____cacheline_aligned; |
5a21d70d | 438 | }; |
41017f0c | 439 | |
7b543663 | 440 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
7c7a0e94 | 441 | |
59094065 TR |
442 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
443 | { | |
444 | return (void *)bridge->private; | |
445 | } | |
446 | ||
447 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) | |
448 | { | |
449 | return container_of(priv, struct pci_host_bridge, private); | |
450 | } | |
451 | ||
7c7a0e94 GP |
452 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
453 | ||
4fa2649a YL |
454 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
455 | void (*release_fn)(struct pci_host_bridge *), | |
456 | void *release_data); | |
7b543663 | 457 | |
6c0cc950 RW |
458 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
459 | ||
2fe2abf8 BH |
460 | /* |
461 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
462 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
463 | * buses below host bridges or subtractive decode bridges) go in the list. | |
464 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
465 | */ | |
466 | ||
467 | /* | |
468 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
469 | * and there's no way to program the bridge with the details of the window. | |
470 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
471 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
472 | */ | |
473 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
474 | ||
475 | struct pci_bus_resource { | |
476 | struct list_head list; | |
477 | struct resource *res; | |
478 | unsigned int flags; | |
479 | }; | |
4352dfd5 GKH |
480 | |
481 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
482 | |
483 | struct pci_bus { | |
484 | struct list_head node; /* node in list of buses */ | |
485 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
486 | struct list_head children; /* list of child buses */ | |
487 | struct list_head devices; /* list of devices on this bus */ | |
488 | struct pci_dev *self; /* bridge device as seen by parent */ | |
67546762 YW |
489 | struct list_head slots; /* list of slots on this bus; |
490 | protected by pci_slot_mutex */ | |
2fe2abf8 BH |
491 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
492 | struct list_head resources; /* address space routed to this bus */ | |
92f02430 | 493 | struct resource busn_res; /* bus numbers routed to this bus */ |
1da177e4 LT |
494 | |
495 | struct pci_ops *ops; /* configuration access functions */ | |
c2791b80 | 496 | struct msi_controller *msi; /* MSI controller */ |
1da177e4 LT |
497 | void *sysdata; /* hook for sys-specific extension */ |
498 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
499 | ||
500 | unsigned char number; /* bus number */ | |
501 | unsigned char primary; /* number of primary bridge */ | |
3749c51a MW |
502 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
503 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
504 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
505 | int domain_nr; | |
506 | #endif | |
1da177e4 LT |
507 | |
508 | char name[48]; | |
509 | ||
510 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
f7625980 | 511 | pci_bus_flags_t bus_flags; /* inherited by child buses */ |
1da177e4 | 512 | struct device *bridge; |
fd7d1ced | 513 | struct device dev; |
1da177e4 LT |
514 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
515 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 516 | unsigned int is_added:1; |
1da177e4 LT |
517 | }; |
518 | ||
fd7d1ced | 519 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 520 | |
79af72d7 | 521 | /* |
f7625980 | 522 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 523 | * false otherwise |
77a0dfcd BH |
524 | * |
525 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
526 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
527 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
528 | */ |
529 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
530 | { | |
531 | return !(pbus->parent); | |
532 | } | |
533 | ||
1c86438c YW |
534 | /** |
535 | * pci_is_bridge - check if the PCI device is a bridge | |
536 | * @dev: PCI device | |
537 | * | |
538 | * Return true if the PCI device is bridge whether it has subordinate | |
539 | * or not. | |
540 | */ | |
541 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
542 | { | |
543 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
544 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
545 | } | |
546 | ||
c6bde215 BH |
547 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
548 | { | |
549 | dev = pci_physfn(dev); | |
550 | if (pci_is_root_bus(dev->bus)) | |
551 | return NULL; | |
552 | ||
553 | return dev->bus->self; | |
554 | } | |
555 | ||
6675a601 MK |
556 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
557 | void pci_put_host_bridge_device(struct device *dev); | |
558 | ||
16cf0ebc RW |
559 | #ifdef CONFIG_PCI_MSI |
560 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
561 | { | |
562 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
563 | } | |
564 | #else | |
565 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
566 | #endif | |
567 | ||
1da177e4 LT |
568 | /* |
569 | * Error values that may be returned by PCI functions. | |
570 | */ | |
571 | #define PCIBIOS_SUCCESSFUL 0x00 | |
572 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
573 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
574 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
575 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
576 | #define PCIBIOS_SET_FAILED 0x88 | |
577 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
578 | ||
a6961651 | 579 | /* |
f7625980 | 580 | * Translate above to generic errno for passing back through non-PCI code. |
a6961651 AW |
581 | */ |
582 | static inline int pcibios_err_to_errno(int err) | |
583 | { | |
584 | if (err <= PCIBIOS_SUCCESSFUL) | |
585 | return err; /* Assume already errno */ | |
586 | ||
587 | switch (err) { | |
588 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
589 | return -ENOENT; | |
590 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 591 | return -ENOTTY; |
a6961651 AW |
592 | case PCIBIOS_DEVICE_NOT_FOUND: |
593 | return -ENODEV; | |
594 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
595 | return -EFAULT; | |
596 | case PCIBIOS_SET_FAILED: | |
597 | return -EIO; | |
598 | case PCIBIOS_BUFFER_TOO_SMALL: | |
599 | return -ENOSPC; | |
600 | } | |
601 | ||
d97ffe23 | 602 | return -ERANGE; |
a6961651 AW |
603 | } |
604 | ||
1da177e4 LT |
605 | /* Low-level architecture-dependent routines */ |
606 | ||
607 | struct pci_ops { | |
057bd2e0 TR |
608 | int (*add_bus)(struct pci_bus *bus); |
609 | void (*remove_bus)(struct pci_bus *bus); | |
1f94a94f | 610 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
611 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
612 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
613 | }; | |
614 | ||
b6ce068a MW |
615 | /* |
616 | * ACPI needs to be able to access PCI config space before we've done a | |
617 | * PCI bus scan and created pci_bus structures. | |
618 | */ | |
f39d5b72 BH |
619 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
620 | int reg, int len, u32 *val); | |
621 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
622 | int reg, int len, u32 val); | |
1da177e4 | 623 | |
3a9ad0b4 YL |
624 | #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT |
625 | typedef u64 pci_bus_addr_t; | |
626 | #else | |
627 | typedef u32 pci_bus_addr_t; | |
628 | #endif | |
629 | ||
1da177e4 | 630 | struct pci_bus_region { |
3a9ad0b4 YL |
631 | pci_bus_addr_t start; |
632 | pci_bus_addr_t end; | |
1da177e4 LT |
633 | }; |
634 | ||
635 | struct pci_dynids { | |
636 | spinlock_t lock; /* protects list, index */ | |
637 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
638 | }; |
639 | ||
f7625980 BH |
640 | |
641 | /* | |
642 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
643 | * a set of callbacks in struct pci_error_handlers, that device driver | |
644 | * will be notified of PCI bus errors, and will be driven to recovery | |
645 | * when an error occurs. | |
392a1ce7 | 646 | */ |
647 | ||
648 | typedef unsigned int __bitwise pci_ers_result_t; | |
649 | ||
650 | enum pci_ers_result { | |
651 | /* no result/none/not supported in device driver */ | |
652 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
653 | ||
654 | /* Device driver can recover without slot reset */ | |
655 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
656 | ||
657 | /* Device driver wants slot to be reset. */ | |
658 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
659 | ||
660 | /* Device has completely failed, is unrecoverable */ | |
661 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
662 | ||
663 | /* Device driver is fully recovered and operational */ | |
664 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
665 | |
666 | /* No AER capabilities registered for the driver */ | |
667 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 | 668 | }; |
669 | ||
670 | /* PCI bus error event callbacks */ | |
05cca6e5 | 671 | struct pci_error_handlers { |
392a1ce7 | 672 | /* PCI bus error detected on this device */ |
673 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 674 | enum pci_channel_state error); |
392a1ce7 | 675 | |
676 | /* MMIO has been re-enabled, but not DMA */ | |
677 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
678 | ||
679 | /* PCI Express link has been reset */ | |
680 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
681 | ||
682 | /* PCI slot has been reset */ | |
683 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
684 | ||
3ebe7f9f KB |
685 | /* PCI function reset prepare or completed */ |
686 | void (*reset_notify)(struct pci_dev *dev, bool prepare); | |
687 | ||
392a1ce7 | 688 | /* Device driver may resume normal operations */ |
689 | void (*resume)(struct pci_dev *dev); | |
690 | }; | |
691 | ||
392a1ce7 | 692 | |
1da177e4 LT |
693 | struct module; |
694 | struct pci_driver { | |
695 | struct list_head node; | |
42b21932 | 696 | const char *name; |
1da177e4 LT |
697 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
698 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
699 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
700 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
701 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
702 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 703 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 704 | void (*shutdown) (struct pci_dev *dev); |
1789382a | 705 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
49453028 | 706 | const struct pci_error_handlers *err_handler; |
1da177e4 LT |
707 | struct device_driver driver; |
708 | struct pci_dynids dynids; | |
709 | }; | |
710 | ||
05cca6e5 | 711 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 LT |
712 | |
713 | /** | |
714 | * PCI_DEVICE - macro used to describe a specific pci device | |
715 | * @vend: the 16 bit PCI Vendor ID | |
716 | * @dev: the 16 bit PCI Device ID | |
717 | * | |
718 | * This macro is used to create a struct pci_device_id that matches a | |
719 | * specific device. The subvendor and subdevice fields will be set to | |
720 | * PCI_ANY_ID. | |
721 | */ | |
722 | #define PCI_DEVICE(vend,dev) \ | |
723 | .vendor = (vend), .device = (dev), \ | |
724 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
725 | ||
3d567e0e NNS |
726 | /** |
727 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem | |
728 | * @vend: the 16 bit PCI Vendor ID | |
729 | * @dev: the 16 bit PCI Device ID | |
730 | * @subvend: the 16 bit PCI Subvendor ID | |
731 | * @subdev: the 16 bit PCI Subdevice ID | |
732 | * | |
733 | * This macro is used to create a struct pci_device_id that matches a | |
734 | * specific device with subsystem information. | |
735 | */ | |
736 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
737 | .vendor = (vend), .device = (dev), \ | |
738 | .subvendor = (subvend), .subdevice = (subdev) | |
739 | ||
1da177e4 LT |
740 | /** |
741 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
742 | * @dev_class: the class, subclass, prog-if triple for this device | |
743 | * @dev_class_mask: the class mask for this device | |
744 | * | |
745 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 746 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
747 | * fields will be set to PCI_ANY_ID. |
748 | */ | |
749 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
750 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
751 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
752 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
753 | ||
1597cacb AC |
754 | /** |
755 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c1309040 MR |
756 | * @vend: the vendor name |
757 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
758 | * |
759 | * This macro is used to create a struct pci_device_id that matches a | |
760 | * specific PCI device. The subvendor, and subdevice fields will be set | |
761 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
762 | * private data. | |
763 | */ | |
764 | ||
c1309040 MR |
765 | #define PCI_VDEVICE(vend, dev) \ |
766 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
767 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 768 | |
5bbe029f BH |
769 | enum { |
770 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ | |
771 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ | |
772 | PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ | |
773 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ | |
774 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ | |
775 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ | |
776 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ | |
777 | }; | |
778 | ||
1da177e4 LT |
779 | /* these external functions are only available when PCI support is enabled */ |
780 | #ifdef CONFIG_PCI | |
781 | ||
5bbe029f BH |
782 | extern unsigned int pci_flags; |
783 | ||
784 | static inline void pci_set_flags(int flags) { pci_flags = flags; } | |
785 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } | |
786 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } | |
787 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } | |
788 | ||
a58674ff | 789 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
790 | |
791 | enum pcie_bus_config_types { | |
27d868b5 KB |
792 | PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ |
793 | PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ | |
794 | PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ | |
795 | PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ | |
796 | PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ | |
b03e7495 JM |
797 | }; |
798 | ||
799 | extern enum pcie_bus_config_types pcie_bus_config; | |
800 | ||
1da177e4 LT |
801 | extern struct bus_type pci_bus_type; |
802 | ||
f7625980 BH |
803 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
804 | * code, or PCI core code. */ | |
1da177e4 | 805 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
f7625980 | 806 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 807 | int no_pci_devices(void); |
1da177e4 | 808 | |
3c449ed0 | 809 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
7b77061f | 810 | void pcibios_bus_add_device(struct pci_dev *pdev); |
10a95747 JL |
811 | void pcibios_add_bus(struct pci_bus *bus); |
812 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 813 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 814 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 815 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 816 | char *pcibios_setup(char *str); |
1da177e4 LT |
817 | |
818 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 819 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 820 | resource_size_t, |
e31dd6e4 | 821 | resource_size_t); |
1da177e4 LT |
822 | void pcibios_update_irq(struct pci_dev *, int irq); |
823 | ||
2d1c8618 BH |
824 | /* Weak but can be overriden by arch */ |
825 | void pci_fixup_cardbus(struct pci_bus *); | |
826 | ||
1da177e4 LT |
827 | /* Generic PCI functions used internally */ |
828 | ||
fc279850 | 829 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 830 | struct resource *res); |
fc279850 | 831 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 832 | struct pci_bus_region *region); |
d1fd4fb6 | 833 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 834 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 835 | void pci_bus_add_devices(const struct pci_bus *bus); |
de4b2f76 | 836 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
837 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
838 | struct pci_ops *ops, void *sysdata, | |
839 | struct list_head *resources); | |
98a35831 YL |
840 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
841 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
842 | void pci_bus_release_busn_res(struct pci_bus *b); | |
d2a7926d LP |
843 | struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, |
844 | struct pci_ops *ops, void *sysdata, | |
845 | struct list_head *resources, | |
846 | struct msi_controller *msi); | |
15856ad5 | 847 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
a2ebb827 BH |
848 | struct pci_ops *ops, void *sysdata, |
849 | struct list_head *resources); | |
05cca6e5 GKH |
850 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
851 | int busnr); | |
3749c51a | 852 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 853 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
854 | const char *name, |
855 | struct hotplug_slot *hotplug); | |
f46753c5 | 856 | void pci_destroy_slot(struct pci_slot *slot); |
017ffe64 YW |
857 | #ifdef CONFIG_SYSFS |
858 | void pci_dev_assign_slot(struct pci_dev *dev); | |
859 | #else | |
860 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } | |
861 | #endif | |
1da177e4 | 862 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 863 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 864 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 865 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 866 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 867 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
868 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
869 | struct resource *res); | |
c56d4450 | 870 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
3df425f3 | 871 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 872 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 873 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
874 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
875 | void pci_dev_put(struct pci_dev *dev); | |
876 | void pci_remove_bus(struct pci_bus *b); | |
877 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 878 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
879 | void pci_stop_root_bus(struct pci_bus *bus); |
880 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 881 | void pci_setup_cardbus(struct pci_bus *bus); |
d366d28c | 882 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
f39d5b72 | 883 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
884 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
885 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
886 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) | |
1da177e4 LT |
887 | |
888 | /* Generic PCI functions exported to card drivers */ | |
889 | ||
388c8c16 JB |
890 | enum pci_lost_interrupt_reason { |
891 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
892 | PCI_LOST_IRQ_DISABLE_MSI, | |
893 | PCI_LOST_IRQ_DISABLE_MSIX, | |
894 | PCI_LOST_IRQ_DISABLE_ACPI, | |
895 | }; | |
896 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
897 | int pci_find_capability(struct pci_dev *dev, int cap); |
898 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
899 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
44a9a36f | 900 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
05cca6e5 GKH |
901 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
902 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 903 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 904 | |
d42552c3 AM |
905 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
906 | struct pci_dev *from); | |
05cca6e5 | 907 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 908 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 909 | struct pci_dev *from); |
05cca6e5 | 910 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
911 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
912 | unsigned int devfn); | |
913 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
914 | unsigned int devfn) | |
915 | { | |
916 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
917 | } | |
05cca6e5 | 918 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
919 | int pci_dev_present(const struct pci_device_id *ids); |
920 | ||
05cca6e5 GKH |
921 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
922 | int where, u8 *val); | |
923 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
924 | int where, u16 *val); | |
925 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
926 | int where, u32 *val); | |
927 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
928 | int where, u8 val); | |
929 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
930 | int where, u16 val); | |
931 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
932 | int where, u32 val); | |
1f94a94f RH |
933 | |
934 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
935 | int where, int size, u32 *val); | |
936 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
937 | int where, int size, u32 val); | |
938 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
939 | int where, int size, u32 *val); | |
940 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
941 | int where, int size, u32 val); | |
942 | ||
a72b46c3 | 943 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 944 | |
bf362f75 | 945 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
1da177e4 | 946 | { |
05cca6e5 | 947 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 948 | } |
bf362f75 | 949 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
1da177e4 | 950 | { |
05cca6e5 | 951 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 952 | } |
bf362f75 | 953 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 954 | u32 *val) |
1da177e4 | 955 | { |
05cca6e5 | 956 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 | 957 | } |
bf362f75 | 958 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
1da177e4 | 959 | { |
05cca6e5 | 960 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 961 | } |
bf362f75 | 962 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
1da177e4 | 963 | { |
05cca6e5 | 964 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 965 | } |
bf362f75 | 966 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 967 | u32 val) |
1da177e4 | 968 | { |
05cca6e5 | 969 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
970 | } |
971 | ||
8c0d3a02 JL |
972 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
973 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
974 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
975 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
976 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
977 | u16 clear, u16 set); | |
978 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
979 | u32 clear, u32 set); | |
980 | ||
981 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
982 | u16 set) | |
983 | { | |
984 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
985 | } | |
986 | ||
987 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
988 | u32 set) | |
989 | { | |
990 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
991 | } | |
992 | ||
993 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
994 | u16 clear) | |
995 | { | |
996 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
997 | } | |
998 | ||
999 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
1000 | u32 clear) | |
1001 | { | |
1002 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
1003 | } | |
1004 | ||
c63587d7 AW |
1005 | /* user-space driven config access */ |
1006 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); | |
1007 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
1008 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
1009 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
1010 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
1011 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
1012 | ||
4a7fb636 | 1013 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
1014 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
1015 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 1016 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
1017 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
1018 | void pcim_pin_device(struct pci_dev *pdev); | |
1019 | ||
296ccb08 YS |
1020 | static inline int pci_is_enabled(struct pci_dev *pdev) |
1021 | { | |
1022 | return (atomic_read(&pdev->enable_cnt) > 0); | |
1023 | } | |
1024 | ||
9ac7849e TH |
1025 | static inline int pci_is_managed(struct pci_dev *pdev) |
1026 | { | |
1027 | return pdev->is_managed; | |
1028 | } | |
1029 | ||
1da177e4 | 1030 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
1031 | |
1032 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 1033 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 1034 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 1035 | |
f7bdd12d | 1036 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 1037 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 1038 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 1039 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 1040 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 1041 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 1042 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
1043 | bool pci_intx_mask_supported(struct pci_dev *dev); |
1044 | bool pci_check_and_mask_intx(struct pci_dev *dev); | |
1045 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
157e876f | 1046 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 1047 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
1048 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
1049 | int pcix_get_mmrbc(struct pci_dev *dev); | |
1050 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 1051 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 1052 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
1053 | int pcie_get_mps(struct pci_dev *dev); |
1054 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
81377c8d JK |
1055 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
1056 | enum pcie_link_width *width); | |
8c1c699f | 1057 | int __pci_reset_function(struct pci_dev *dev); |
a96d627a | 1058 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 1059 | int pci_reset_function(struct pci_dev *dev); |
61cf16d8 | 1060 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 1061 | int pci_probe_reset_slot(struct pci_slot *slot); |
090a3c53 | 1062 | int pci_reset_slot(struct pci_slot *slot); |
61cf16d8 | 1063 | int pci_try_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 1064 | int pci_probe_reset_bus(struct pci_bus *bus); |
090a3c53 | 1065 | int pci_reset_bus(struct pci_bus *bus); |
61cf16d8 | 1066 | int pci_try_reset_bus(struct pci_bus *bus); |
9e33002f GS |
1067 | void pci_reset_secondary_bus(struct pci_dev *dev); |
1068 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
64e8674f | 1069 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
14add80b | 1070 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1071 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1072 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
c87deff7 | 1073 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1074 | bool pci_device_is_present(struct pci_dev *pdev); |
08249651 | 1075 | void pci_ignore_hotplug(struct pci_dev *dev); |
1da177e4 LT |
1076 | |
1077 | /* ROM control related routines */ | |
e416de5e AC |
1078 | int pci_enable_rom(struct pci_dev *pdev); |
1079 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1080 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1081 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 1082 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
fffe01f7 | 1083 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 LT |
1084 | |
1085 | /* Power management related routines */ | |
1086 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1087 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1088 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1089 | int pci_load_saved_state(struct pci_dev *dev, |
1090 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1091 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1092 | struct pci_saved_state **state); | |
fd0f7f73 AW |
1093 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
1094 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, | |
1095 | u16 cap); | |
1096 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); | |
1097 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, | |
1098 | u16 cap, unsigned int size); | |
0e5dd46b | 1099 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1100 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1101 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1102 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1103 | void pci_pme_active(struct pci_dev *dev, bool enable); |
6cbf8214 RW |
1104 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1105 | bool runtime, bool enable); | |
0235c4fc | 1106 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1107 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1108 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1109 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 1110 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 1111 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
9d26d3a8 MW |
1112 | void pci_d3cold_enable(struct pci_dev *dev); |
1113 | void pci_d3cold_disable(struct pci_dev *dev); | |
1da177e4 | 1114 | |
6cbf8214 RW |
1115 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1116 | bool enable) | |
1117 | { | |
1118 | return __pci_enable_wake(dev, state, false, enable); | |
1119 | } | |
1da177e4 | 1120 | |
425c1b22 AW |
1121 | /* PCI Virtual Channel */ |
1122 | int pci_save_vc_state(struct pci_dev *dev); | |
1123 | void pci_restore_vc_state(struct pci_dev *dev); | |
1124 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
51c2e0a7 | 1125 | |
bb209c82 BH |
1126 | /* For use by arch with custom probe code */ |
1127 | void set_pcie_port_type(struct pci_dev *pdev); | |
1128 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1129 | ||
ce5ccdef | 1130 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 1131 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
2f320521 | 1132 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1133 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1134 | void pci_lock_rescan_remove(void); |
1135 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1136 | |
287d19ce SH |
1137 | /* Vital product data routines */ |
1138 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
1139 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
cb92148b | 1140 | int pci_set_vpd_size(struct pci_dev *dev, size_t len); |
287d19ce | 1141 | |
1da177e4 | 1142 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1143 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1144 | void pci_bus_assign_resources(const struct pci_bus *bus); |
765bf9b7 | 1145 | void pci_bus_claim_resources(struct pci_bus *bus); |
1da177e4 LT |
1146 | void pci_bus_size_bridges(struct pci_bus *bus); |
1147 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1148 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1149 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1150 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1151 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1152 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
1da177e4 | 1153 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1154 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 | 1155 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
d5341942 | 1156 | int (*)(const struct pci_dev *, u8, u8)); |
afd29f90 | 1157 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
1da177e4 | 1158 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1159 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1160 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1161 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1162 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 1163 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 1164 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1165 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1166 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1167 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1168 | |
1169 | /* drivers/pci/bus.c */ | |
fe830ef6 JL |
1170 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
1171 | void pci_bus_put(struct pci_bus *bus); | |
45ca9e97 | 1172 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1173 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1174 | resource_size_t offset); | |
45ca9e97 | 1175 | void pci_free_resource_list(struct list_head *resources); |
950334bc BH |
1176 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
1177 | unsigned int flags); | |
2fe2abf8 BH |
1178 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1179 | void pci_bus_remove_resources(struct pci_bus *bus); | |
950334bc BH |
1180 | int devm_request_pci_bus_resources(struct device *dev, |
1181 | struct list_head *resources); | |
2fe2abf8 | 1182 | |
89a74ecc | 1183 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1184 | for (i = 0; \ |
1185 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1186 | i++) | |
89a74ecc | 1187 | |
4a7fb636 AM |
1188 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1189 | struct resource *res, resource_size_t size, | |
1190 | resource_size_t align, resource_size_t min, | |
664c2848 | 1191 | unsigned long type_mask, |
3b7a17fc DB |
1192 | resource_size_t (*alignf)(void *, |
1193 | const struct resource *, | |
b26b2d49 DB |
1194 | resource_size_t, |
1195 | resource_size_t), | |
4a7fb636 | 1196 | void *alignf_data); |
1da177e4 | 1197 | |
8b921acf | 1198 | |
c5076cfe TN |
1199 | int pci_register_io_range(phys_addr_t addr, resource_size_t size); |
1200 | unsigned long pci_address_to_pio(phys_addr_t addr); | |
1201 | phys_addr_t pci_pio_to_address(unsigned long pio); | |
8b921acf | 1202 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
4d3f1384 | 1203 | void pci_unmap_iospace(struct resource *res); |
8b921acf | 1204 | |
3a9ad0b4 | 1205 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
06cf56e4 BH |
1206 | { |
1207 | struct pci_bus_region region; | |
1208 | ||
1209 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1210 | return region.start; | |
1211 | } | |
1212 | ||
863b18f4 | 1213 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1214 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1215 | const char *mod_name); | |
bba81165 AM |
1216 | |
1217 | /* | |
1218 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
1219 | */ | |
1220 | #define pci_register_driver(driver) \ | |
1221 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1222 | |
05cca6e5 | 1223 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1224 | |
1225 | /** | |
1226 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1227 | * @__pci_driver: pci_driver struct | |
1228 | * | |
1229 | * Helper macro for PCI drivers which do not do anything special in module | |
1230 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1231 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1232 | */ | |
1233 | #define module_pci_driver(__pci_driver) \ | |
1234 | module_driver(__pci_driver, pci_register_driver, \ | |
1235 | pci_unregister_driver) | |
1236 | ||
b4eb6cdb PG |
1237 | /** |
1238 | * builtin_pci_driver() - Helper macro for registering a PCI driver | |
1239 | * @__pci_driver: pci_driver struct | |
1240 | * | |
1241 | * Helper macro for PCI drivers which do not do anything special in their | |
1242 | * init code. This eliminates a lot of boilerplate. Each driver may only | |
1243 | * use this macro once, and calling it replaces device_initcall(...) | |
1244 | */ | |
1245 | #define builtin_pci_driver(__pci_driver) \ | |
1246 | builtin_driver(__pci_driver, pci_register_driver) | |
1247 | ||
05cca6e5 | 1248 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1249 | int pci_add_dynid(struct pci_driver *drv, |
1250 | unsigned int vendor, unsigned int device, | |
1251 | unsigned int subvendor, unsigned int subdevice, | |
1252 | unsigned int class, unsigned int class_mask, | |
1253 | unsigned long driver_data); | |
05cca6e5 GKH |
1254 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1255 | struct pci_dev *dev); | |
1256 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1257 | int pass); | |
1da177e4 | 1258 | |
70298c6e | 1259 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1260 | void *userdata); |
ac7dc65a | 1261 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1262 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1263 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1264 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1265 | unsigned long type); | |
978d2d68 | 1266 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); |
cecf4864 | 1267 | |
3448a19d DA |
1268 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1269 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1270 | ||
deb2d2ec | 1271 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1272 | unsigned int command_bits, u32 flags); |
fe537670 | 1273 | |
4fe0d154 CH |
1274 | #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ |
1275 | #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ | |
1276 | #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ | |
1277 | #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ | |
1278 | #define PCI_IRQ_ALL_TYPES \ | |
1279 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) | |
aff17164 | 1280 | |
1da177e4 LT |
1281 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1282 | ||
f41b1771 | 1283 | #include <linux/pci-dma.h> |
1da177e4 LT |
1284 | #include <linux/dmapool.h> |
1285 | ||
1286 | #define pci_pool dma_pool | |
1287 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
1288 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
1289 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
1290 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
01a7fd33 SS |
1291 | #define pci_pool_zalloc(pool, flags, handle) \ |
1292 | dma_pool_zalloc(pool, flags, handle) | |
1da177e4 LT |
1293 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
1294 | ||
1da177e4 | 1295 | struct msix_entry { |
16dbef4a | 1296 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
1297 | u16 entry; /* driver uses to specify entry, OS writes */ |
1298 | }; | |
1299 | ||
4c859804 BH |
1300 | #ifdef CONFIG_PCI_MSI |
1301 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 BH |
1302 | void pci_msi_shutdown(struct pci_dev *dev); |
1303 | void pci_disable_msi(struct pci_dev *dev); | |
4c859804 | 1304 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 BH |
1305 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); |
1306 | void pci_msix_shutdown(struct pci_dev *dev); | |
1307 | void pci_disable_msix(struct pci_dev *dev); | |
f39d5b72 BH |
1308 | void pci_restore_msi_state(struct pci_dev *dev); |
1309 | int pci_msi_enabled(void); | |
4c859804 | 1310 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); |
f7fc32cb AG |
1311 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
1312 | { | |
1313 | int rc = pci_enable_msi_range(dev, nvec, nvec); | |
1314 | if (rc < 0) | |
1315 | return rc; | |
1316 | return 0; | |
1317 | } | |
4c859804 BH |
1318 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1319 | int minvec, int maxvec); | |
f7fc32cb AG |
1320 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1321 | struct msix_entry *entries, int nvec) | |
1322 | { | |
1323 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1324 | if (rc < 0) | |
1325 | return rc; | |
1326 | return 0; | |
1327 | } | |
aff17164 CH |
1328 | int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, |
1329 | unsigned int max_vecs, unsigned int flags); | |
1330 | void pci_free_irq_vectors(struct pci_dev *dev); | |
1331 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); | |
ee8d41e5 | 1332 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
aff17164 | 1333 | |
4c859804 | 1334 | #else |
2ee546c4 | 1335 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1336 | static inline void pci_msi_shutdown(struct pci_dev *dev) { } |
1337 | static inline void pci_disable_msi(struct pci_dev *dev) { } | |
1338 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
05cca6e5 GKH |
1339 | static inline int pci_enable_msix(struct pci_dev *dev, |
1340 | struct msix_entry *entries, int nvec) | |
2ee546c4 BH |
1341 | { return -ENOSYS; } |
1342 | static inline void pci_msix_shutdown(struct pci_dev *dev) { } | |
1343 | static inline void pci_disable_msix(struct pci_dev *dev) { } | |
2ee546c4 BH |
1344 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1345 | static inline int pci_msi_enabled(void) { return 0; } | |
302a2523 AG |
1346 | static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, |
1347 | int maxvec) | |
2ee546c4 | 1348 | { return -ENOSYS; } |
f7fc32cb AG |
1349 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
1350 | { return -ENOSYS; } | |
302a2523 AG |
1351 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
1352 | struct msix_entry *entries, int minvec, int maxvec) | |
2ee546c4 | 1353 | { return -ENOSYS; } |
f7fc32cb AG |
1354 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1355 | struct msix_entry *entries, int nvec) | |
1356 | { return -ENOSYS; } | |
aff17164 CH |
1357 | static inline int pci_alloc_irq_vectors(struct pci_dev *dev, |
1358 | unsigned int min_vecs, unsigned int max_vecs, | |
1359 | unsigned int flags) | |
1360 | { | |
1361 | if (min_vecs > 1) | |
1362 | return -EINVAL; | |
1363 | return 1; | |
1364 | } | |
1365 | static inline void pci_free_irq_vectors(struct pci_dev *dev) | |
1366 | { | |
1367 | } | |
1368 | ||
1369 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1370 | { | |
1371 | if (WARN_ON_ONCE(nr > 0)) | |
1372 | return -EINVAL; | |
1373 | return dev->irq; | |
1374 | } | |
ee8d41e5 TG |
1375 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
1376 | int vec) | |
1377 | { | |
1378 | return cpu_possible_mask; | |
1379 | } | |
1da177e4 LT |
1380 | #endif |
1381 | ||
ab0724ff | 1382 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 RW |
1383 | extern bool pcie_ports_disabled; |
1384 | extern bool pcie_ports_auto; | |
ab0724ff MT |
1385 | #else |
1386 | #define pcie_ports_disabled true | |
1387 | #define pcie_ports_auto false | |
1388 | #endif | |
415e12b2 | 1389 | |
4c859804 | 1390 | #ifdef CONFIG_PCIEASPM |
f39d5b72 | 1391 | bool pcie_aspm_support_enabled(void); |
4c859804 BH |
1392 | #else |
1393 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 AP |
1394 | #endif |
1395 | ||
415e12b2 RW |
1396 | #ifdef CONFIG_PCIEAER |
1397 | void pci_no_aer(void); | |
1398 | bool pci_aer_available(void); | |
66b80809 | 1399 | int pci_aer_init(struct pci_dev *dev); |
415e12b2 RW |
1400 | #else |
1401 | static inline void pci_no_aer(void) { } | |
1402 | static inline bool pci_aer_available(void) { return false; } | |
66b80809 | 1403 | static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } |
415e12b2 RW |
1404 | #endif |
1405 | ||
4c859804 | 1406 | #ifdef CONFIG_PCIE_ECRC |
f39d5b72 BH |
1407 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
1408 | void pcie_ecrc_get_policy(char *str); | |
4c859804 | 1409 | #else |
2ee546c4 BH |
1410 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
1411 | static inline void pcie_ecrc_get_policy(char *str) { } | |
43c16408 AP |
1412 | #endif |
1413 | ||
034cd97e | 1414 | #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) |
1c8d7b0a | 1415 | |
8b955b0d | 1416 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
1417 | /* The functions a driver should call */ |
1418 | int ht_create_irq(struct pci_dev *dev, int idx); | |
1419 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
1420 | #endif /* CONFIG_HT_IRQ */ |
1421 | ||
edc90fee BH |
1422 | #ifdef CONFIG_PCI_ATS |
1423 | /* Address Translation Service */ | |
1424 | void pci_ats_init(struct pci_dev *dev); | |
ff9bee89 BH |
1425 | int pci_enable_ats(struct pci_dev *dev, int ps); |
1426 | void pci_disable_ats(struct pci_dev *dev); | |
1427 | int pci_ats_queue_depth(struct pci_dev *dev); | |
edc90fee | 1428 | #else |
ff9bee89 BH |
1429 | static inline void pci_ats_init(struct pci_dev *d) { } |
1430 | static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } | |
1431 | static inline void pci_disable_ats(struct pci_dev *d) { } | |
1432 | static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } | |
edc90fee BH |
1433 | #endif |
1434 | ||
eec097d4 BH |
1435 | #ifdef CONFIG_PCIE_PTM |
1436 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); | |
1437 | #else | |
1438 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) | |
1439 | { return -EINVAL; } | |
1440 | #endif | |
1441 | ||
f39d5b72 BH |
1442 | void pci_cfg_access_lock(struct pci_dev *dev); |
1443 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1444 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1445 | |
4352dfd5 GKH |
1446 | /* |
1447 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1448 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1449 | * configuration space. |
1450 | */ | |
32a2eea7 JG |
1451 | #ifdef CONFIG_PCI_DOMAINS |
1452 | extern int pci_domains_supported; | |
41e5c0f8 | 1453 | int pci_get_new_domain_nr(void); |
32a2eea7 JG |
1454 | #else |
1455 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1456 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1457 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
41e5c0f8 | 1458 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
32a2eea7 | 1459 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1460 | |
670ba0c8 CM |
1461 | /* |
1462 | * Generic implementation for PCI domain support. If your | |
1463 | * architecture does not need custom management of PCI | |
1464 | * domains then this implementation will be used | |
1465 | */ | |
1466 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1467 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1468 | { | |
1469 | return bus->domain_nr; | |
1470 | } | |
2ab51dde TN |
1471 | #ifdef CONFIG_ACPI |
1472 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); | |
670ba0c8 | 1473 | #else |
2ab51dde TN |
1474 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
1475 | { return 0; } | |
1476 | #endif | |
9c7cb891 | 1477 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
670ba0c8 CM |
1478 | #endif |
1479 | ||
95a8b6ef MT |
1480 | /* some architectures require additional setup to direct VGA traffic */ |
1481 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, | |
3448a19d | 1482 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1483 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1484 | |
be9d2e89 JT |
1485 | static inline int |
1486 | pci_request_io_regions(struct pci_dev *pdev, const char *name) | |
1487 | { | |
1488 | return pci_request_selected_regions(pdev, | |
1489 | pci_select_bars(pdev, IORESOURCE_IO), name); | |
1490 | } | |
1491 | ||
1492 | static inline void | |
1493 | pci_release_io_regions(struct pci_dev *pdev) | |
1494 | { | |
1495 | return pci_release_selected_regions(pdev, | |
1496 | pci_select_bars(pdev, IORESOURCE_IO)); | |
1497 | } | |
1498 | ||
1499 | static inline int | |
1500 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) | |
1501 | { | |
1502 | return pci_request_selected_regions(pdev, | |
1503 | pci_select_bars(pdev, IORESOURCE_MEM), name); | |
1504 | } | |
1505 | ||
1506 | static inline void | |
1507 | pci_release_mem_regions(struct pci_dev *pdev) | |
1508 | { | |
1509 | return pci_release_selected_regions(pdev, | |
1510 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1511 | } | |
1512 | ||
4352dfd5 | 1513 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 | 1514 | |
5bbe029f BH |
1515 | static inline void pci_set_flags(int flags) { } |
1516 | static inline void pci_add_flags(int flags) { } | |
1517 | static inline void pci_clear_flags(int flags) { } | |
1518 | static inline int pci_has_flag(int flag) { return 0; } | |
1519 | ||
1da177e4 LT |
1520 | /* |
1521 | * If the system does not have PCI, clearly these return errors. Define | |
1522 | * these as simple inline functions to avoid hair in drivers. | |
1523 | */ | |
1524 | ||
05cca6e5 GKH |
1525 | #define _PCI_NOP(o, s, t) \ |
1526 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1527 | int where, t val) \ | |
1da177e4 | 1528 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1529 | |
1530 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1531 | _PCI_NOP(o, word, u16 x) \ | |
1532 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1533 | _PCI_NOP_ALL(read, *) |
1534 | _PCI_NOP_ALL(write,) | |
1535 | ||
d42552c3 | 1536 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1537 | unsigned int device, |
1538 | struct pci_dev *from) | |
2ee546c4 | 1539 | { return NULL; } |
d42552c3 | 1540 | |
05cca6e5 GKH |
1541 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1542 | unsigned int device, | |
1543 | unsigned int ss_vendor, | |
1544 | unsigned int ss_device, | |
b08508c4 | 1545 | struct pci_dev *from) |
2ee546c4 | 1546 | { return NULL; } |
1da177e4 | 1547 | |
05cca6e5 GKH |
1548 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1549 | struct pci_dev *from) | |
2ee546c4 | 1550 | { return NULL; } |
1da177e4 LT |
1551 | |
1552 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1553 | #define no_pci_devices() (1) |
1da177e4 LT |
1554 | #define pci_dev_put(dev) do { } while (0) |
1555 | ||
2ee546c4 BH |
1556 | static inline void pci_set_master(struct pci_dev *dev) { } |
1557 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
1558 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
05cca6e5 | 1559 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1560 | { return -EBUSY; } |
05cca6e5 GKH |
1561 | static inline int __pci_register_driver(struct pci_driver *drv, |
1562 | struct module *owner) | |
2ee546c4 | 1563 | { return 0; } |
05cca6e5 | 1564 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
1565 | { return 0; } |
1566 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
05cca6e5 | 1567 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1568 | { return 0; } |
05cca6e5 GKH |
1569 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1570 | int cap) | |
2ee546c4 | 1571 | { return 0; } |
05cca6e5 | 1572 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1573 | { return 0; } |
05cca6e5 | 1574 | |
1da177e4 | 1575 | /* Power management related routines */ |
2ee546c4 BH |
1576 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
1577 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 1578 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 1579 | { return 0; } |
3449248c | 1580 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 1581 | { return 0; } |
05cca6e5 GKH |
1582 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1583 | pm_message_t state) | |
2ee546c4 | 1584 | { return PCI_D0; } |
05cca6e5 GKH |
1585 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1586 | int enable) | |
2ee546c4 | 1587 | { return 0; } |
48a92a81 | 1588 | |
afd29f90 MW |
1589 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
1590 | struct resource *res) | |
1591 | { return NULL; } | |
05cca6e5 | 1592 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
1593 | { return -EIO; } |
1594 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 1595 | |
c5076cfe TN |
1596 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
1597 | ||
2ee546c4 | 1598 | static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
fb51ccbf JK |
1599 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
1600 | { return 0; } | |
2ee546c4 | 1601 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
e04b0ea2 | 1602 | |
d80d0217 RD |
1603 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1604 | { return NULL; } | |
d80d0217 RD |
1605 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1606 | unsigned int devfn) | |
1607 | { return NULL; } | |
d80d0217 RD |
1608 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
1609 | unsigned int devfn) | |
1610 | { return NULL; } | |
1611 | ||
2ee546c4 BH |
1612 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1613 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
41e5c0f8 | 1614 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
12ea6cad | 1615 | |
fb8a0d9d WM |
1616 | #define dev_is_pci(d) (false) |
1617 | #define dev_is_pf(d) (false) | |
1618 | #define dev_num_vf(d) (0) | |
4352dfd5 | 1619 | #endif /* CONFIG_PCI */ |
1da177e4 | 1620 | |
4352dfd5 GKH |
1621 | /* Include architecture-dependent settings and functions */ |
1622 | ||
1623 | #include <asm/pci.h> | |
1da177e4 | 1624 | |
92016ba5 JO |
1625 | #ifndef pci_root_bus_fwnode |
1626 | #define pci_root_bus_fwnode(bus) NULL | |
1627 | #endif | |
1628 | ||
1da177e4 LT |
1629 | /* these helpers provide future and backwards compatibility |
1630 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1631 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1632 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1633 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1634 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1635 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1636 | pci_resource_end((dev), (bar)) == \ | |
1637 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1638 | \ | |
1639 | (pci_resource_end((dev), (bar)) - \ | |
1640 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1641 | |
1642 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1643 | * driver-specific data. They are really just a wrapper around | |
1644 | * the generic device structure functions of these calls. | |
1645 | */ | |
05cca6e5 | 1646 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1647 | { |
1648 | return dev_get_drvdata(&pdev->dev); | |
1649 | } | |
1650 | ||
05cca6e5 | 1651 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1652 | { |
1653 | dev_set_drvdata(&pdev->dev, data); | |
1654 | } | |
1655 | ||
1656 | /* If you want to know what to call your pci_dev, ask this function. | |
1657 | * Again, it's a wrapper around the generic device. | |
1658 | */ | |
2fc90f61 | 1659 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1660 | { |
c6c4f070 | 1661 | return dev_name(&pdev->dev); |
1da177e4 LT |
1662 | } |
1663 | ||
2311b1f2 ME |
1664 | |
1665 | /* Some archs don't want to expose struct resource to userland as-is | |
1666 | * in sysfs and /proc | |
1667 | */ | |
8221a013 BH |
1668 | #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER |
1669 | void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
1670 | const struct resource *rsrc, | |
1671 | resource_size_t *start, resource_size_t *end); | |
1672 | #else | |
2311b1f2 | 1673 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
05cca6e5 | 1674 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1675 | resource_size_t *end) |
2311b1f2 ME |
1676 | { |
1677 | *start = rsrc->start; | |
1678 | *end = rsrc->end; | |
1679 | } | |
1680 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1681 | ||
1682 | ||
1da177e4 LT |
1683 | /* |
1684 | * The world is not perfect and supplies us with broken PCI devices. | |
1685 | * For at least a part of these bugs we need a work-around, so both | |
1686 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1687 | * fixup hooks to be called for particular buggy devices. | |
1688 | */ | |
1689 | ||
1690 | struct pci_fixup { | |
f4ca5c6a YL |
1691 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
1692 | u16 device; /* You can use PCI_ANY_ID here of course */ | |
1693 | u32 class; /* You can use PCI_ANY_ID here too */ | |
1694 | unsigned int class_shift; /* should be 0, 8, 16 */ | |
1da177e4 LT |
1695 | void (*hook)(struct pci_dev *dev); |
1696 | }; | |
1697 | ||
1698 | enum pci_fixup_pass { | |
1699 | pci_fixup_early, /* Before probing BARs */ | |
1700 | pci_fixup_header, /* After reading configuration header */ | |
1701 | pci_fixup_final, /* Final phase of device fixups */ | |
1702 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 1703 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 1704 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 1705 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 1706 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
1707 | }; |
1708 | ||
1709 | /* Anonymous variables would be nice... */ | |
f4ca5c6a YL |
1710 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1711 | class_shift, hook) \ | |
ecf61c78 | 1712 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
1713 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1714 | = { vendor, device, class, class_shift, hook }; | |
1715 | ||
1716 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
1717 | class_shift, hook) \ | |
1718 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1719 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1720 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
1721 | class_shift, hook) \ | |
1722 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1723 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1724 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
1725 | class_shift, hook) \ | |
1726 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1727 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1728 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
1729 | class_shift, hook) \ | |
1730 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1731 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1732 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
1733 | class_shift, hook) \ | |
1734 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
ecf61c78 | 1735 | resume##hook, vendor, device, class, \ |
f4ca5c6a YL |
1736 | class_shift, hook) |
1737 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ | |
1738 | class_shift, hook) \ | |
1739 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
ecf61c78 | 1740 | resume_early##hook, vendor, device, \ |
f4ca5c6a YL |
1741 | class, class_shift, hook) |
1742 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ | |
1743 | class_shift, hook) \ | |
1744 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
ecf61c78 | 1745 | suspend##hook, vendor, device, class, \ |
f4ca5c6a | 1746 | class_shift, hook) |
7d2a01b8 AN |
1747 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
1748 | class_shift, hook) \ | |
1749 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
1750 | suspend_late##hook, vendor, device, \ | |
1751 | class, class_shift, hook) | |
f4ca5c6a | 1752 | |
1da177e4 LT |
1753 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1754 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1755 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1756 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1757 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1758 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1759 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1760 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1761 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1762 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1763 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1764 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
1765 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1766 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
ecf61c78 | 1767 | resume##hook, vendor, device, \ |
f4ca5c6a | 1768 | PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1769 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1770 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
ecf61c78 | 1771 | resume_early##hook, vendor, device, \ |
f4ca5c6a | 1772 | PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1773 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1774 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
ecf61c78 | 1775 | suspend##hook, vendor, device, \ |
f4ca5c6a | 1776 | PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
1777 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
1778 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
1779 | suspend_late##hook, vendor, device, \ | |
1780 | PCI_ANY_ID, 0, hook) | |
1da177e4 | 1781 | |
93177a74 | 1782 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1783 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
ad805758 | 1784 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
c1d61c9b | 1785 | int pci_dev_specific_enable_acs(struct pci_dev *dev); |
93177a74 RW |
1786 | #else |
1787 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 1788 | struct pci_dev *dev) { } |
ad805758 AW |
1789 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
1790 | u16 acs_flags) | |
1791 | { | |
1792 | return -ENOTTY; | |
1793 | } | |
c1d61c9b AW |
1794 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) |
1795 | { | |
1796 | return -ENOTTY; | |
1797 | } | |
93177a74 | 1798 | #endif |
1da177e4 | 1799 | |
05cca6e5 | 1800 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1801 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1802 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
1803 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
1804 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 1805 | const char *name); |
fb7ebfe4 | 1806 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 1807 | |
1da177e4 | 1808 | extern int pci_pci_problems; |
236561e5 | 1809 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1810 | #define PCIPCI_TRITON 2 |
1811 | #define PCIPCI_NATOMA 4 | |
1812 | #define PCIPCI_VIAETBF 8 | |
1813 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1814 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1815 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1816 | |
4516a618 AN |
1817 | extern unsigned long pci_cardbus_io_size; |
1818 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 1819 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 1820 | extern u8 pci_cache_line_size; |
4516a618 | 1821 | |
28760489 EB |
1822 | extern unsigned long pci_hotplug_io_size; |
1823 | extern unsigned long pci_hotplug_mem_size; | |
e16b4660 | 1824 | extern unsigned long pci_hotplug_bus_size; |
28760489 | 1825 | |
f7625980 | 1826 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 1827 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 1828 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
1829 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1830 | enum pcie_reset_state state); | |
eca0d467 | 1831 | int pcibios_add_device(struct pci_dev *dev); |
6ae32c53 | 1832 | void pcibios_release_device(struct pci_dev *dev); |
a43ae58c | 1833 | void pcibios_penalize_isa_irq(int irq, int active); |
890e4847 JL |
1834 | int pcibios_alloc_irq(struct pci_dev *dev); |
1835 | void pcibios_free_irq(struct pci_dev *dev); | |
575e3348 | 1836 | |
699c1985 SO |
1837 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
1838 | extern struct dev_pm_ops pcibios_pm_ops; | |
1839 | #endif | |
1840 | ||
935c760e | 1841 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
f39d5b72 BH |
1842 | void __init pci_mmcfg_early_init(void); |
1843 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 1844 | #else |
bb63b421 | 1845 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1846 | static inline void pci_mmcfg_late_init(void) { } |
1847 | #endif | |
1848 | ||
642c92da | 1849 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 1850 | |
1684f5dd | 1851 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
c43996f4 | 1852 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1853 | |
dd7cc44d | 1854 | #ifdef CONFIG_PCI_IOV |
b07579c0 WY |
1855 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
1856 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); | |
1857 | ||
f39d5b72 BH |
1858 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
1859 | void pci_disable_sriov(struct pci_dev *dev); | |
c194f7ea WY |
1860 | int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); |
1861 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); | |
f39d5b72 | 1862 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 1863 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
1864 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
1865 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
0e6c9122 | 1866 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
dd7cc44d | 1867 | #else |
b07579c0 WY |
1868 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
1869 | { | |
1870 | return -ENOSYS; | |
1871 | } | |
1872 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) | |
1873 | { | |
1874 | return -ENOSYS; | |
1875 | } | |
dd7cc44d | 1876 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
2ee546c4 | 1877 | { return -ENODEV; } |
c194f7ea WY |
1878 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) |
1879 | { | |
1880 | return -ENOSYS; | |
1881 | } | |
1882 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, | |
1883 | int id, int reset) { } | |
2ee546c4 | 1884 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
2ee546c4 | 1885 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 1886 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 1887 | { return 0; } |
bff73156 | 1888 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 1889 | { return 0; } |
bff73156 | 1890 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 1891 | { return 0; } |
0e6c9122 WY |
1892 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
1893 | { return 0; } | |
dd7cc44d YZ |
1894 | #endif |
1895 | ||
c825bc94 | 1896 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
1897 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
1898 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
1899 | #endif |
1900 | ||
d7b7e605 KK |
1901 | /** |
1902 | * pci_pcie_cap - get the saved PCIe capability offset | |
1903 | * @dev: PCI device | |
1904 | * | |
1905 | * PCIe capability offset is calculated at PCI device initialization | |
1906 | * time and saved in the data structure. This function returns saved | |
1907 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1908 | * reduces unnecessary search in the PCI configuration space. If you | |
1909 | * need to calculate PCIe capability offset from raw device for some | |
1910 | * reasons, please use pci_find_capability() instead. | |
1911 | */ | |
1912 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1913 | { | |
1914 | return dev->pcie_cap; | |
1915 | } | |
1916 | ||
7eb776c4 KK |
1917 | /** |
1918 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1919 | * @dev: PCI device | |
1920 | * | |
a895c28a | 1921 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
1922 | */ |
1923 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1924 | { | |
a895c28a | 1925 | return pci_pcie_cap(dev); |
7eb776c4 KK |
1926 | } |
1927 | ||
7c9c003c MS |
1928 | /** |
1929 | * pcie_caps_reg - get the PCIe Capabilities Register | |
1930 | * @dev: PCI device | |
1931 | */ | |
1932 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
1933 | { | |
1934 | return dev->pcie_flags_reg; | |
1935 | } | |
1936 | ||
786e2288 YW |
1937 | /** |
1938 | * pci_pcie_type - get the PCIe device/port type | |
1939 | * @dev: PCI device | |
1940 | */ | |
1941 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
1942 | { | |
1c531d82 | 1943 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
1944 | } |
1945 | ||
5d990b62 | 1946 | void pci_request_acs(void); |
ad805758 AW |
1947 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
1948 | bool pci_acs_path_enabled(struct pci_dev *start, | |
1949 | struct pci_dev *end, u16 acs_flags); | |
a2ce7662 | 1950 | |
7ad506fa | 1951 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 1952 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
1953 | |
1954 | /* Large Resource Data Type Tag Item Names */ | |
1955 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
1956 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
1957 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
1958 | ||
1959 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
1960 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
1961 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
1962 | ||
1963 | /* Small Resource Data Type Tag Item Names */ | |
9eb45d5c | 1964 | #define PCI_VPD_STIN_END 0x0f /* End */ |
7ad506fa | 1965 | |
9eb45d5c | 1966 | #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) |
7ad506fa MC |
1967 | |
1968 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
1969 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
9eb45d5c | 1970 | #define PCI_VPD_LRDT_TIN_MASK 0x7f |
7ad506fa MC |
1971 | |
1972 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
1973 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 1974 | |
e1d5bdab MC |
1975 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1976 | ||
4067a854 MC |
1977 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1978 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
1979 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 1980 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 1981 | |
a2ce7662 MC |
1982 | /** |
1983 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
1984 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1985 | * | |
1986 | * Returns the extracted Large Resource Data Type length. | |
1987 | */ | |
1988 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
1989 | { | |
1990 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
1991 | } | |
1992 | ||
9eb45d5c HR |
1993 | /** |
1994 | * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item | |
1995 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1996 | * | |
1997 | * Returns the extracted Large Resource Data Type Tag item. | |
1998 | */ | |
1999 | static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) | |
2000 | { | |
2001 | return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); | |
2002 | } | |
2003 | ||
7ad506fa MC |
2004 | /** |
2005 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
2006 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
2007 | * | |
2008 | * Returns the extracted Small Resource Data Type length. | |
2009 | */ | |
2010 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
2011 | { | |
2012 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
2013 | } | |
2014 | ||
9eb45d5c HR |
2015 | /** |
2016 | * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item | |
2017 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
2018 | * | |
2019 | * Returns the extracted Small Resource Data Type Tag Item. | |
2020 | */ | |
2021 | static inline u8 pci_vpd_srdt_tag(const u8 *srdt) | |
2022 | { | |
2023 | return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; | |
2024 | } | |
2025 | ||
e1d5bdab MC |
2026 | /** |
2027 | * pci_vpd_info_field_size - Extracts the information field length | |
2028 | * @lrdt: Pointer to the beginning of an information field header | |
2029 | * | |
2030 | * Returns the extracted information field length. | |
2031 | */ | |
2032 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
2033 | { | |
2034 | return info_field[2]; | |
2035 | } | |
2036 | ||
b55ac1b2 MC |
2037 | /** |
2038 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
2039 | * @buf: Pointer to buffered vpd data | |
2040 | * @off: The offset into the buffer at which to begin the search | |
2041 | * @len: The length of the vpd buffer | |
2042 | * @rdt: The Resource Data Type to search for | |
2043 | * | |
2044 | * Returns the index where the Resource Data Type was found or | |
2045 | * -ENOENT otherwise. | |
2046 | */ | |
2047 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
2048 | ||
4067a854 MC |
2049 | /** |
2050 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
2051 | * @buf: Pointer to buffered vpd data | |
2052 | * @off: The offset into the buffer at which to begin the search | |
2053 | * @len: The length of the buffer area, relative to off, in which to search | |
2054 | * @kw: The keyword to search for | |
2055 | * | |
2056 | * Returns the index where the information field keyword was found or | |
2057 | * -ENOENT otherwise. | |
2058 | */ | |
2059 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
2060 | unsigned int len, const char *kw); | |
2061 | ||
98d9f30c BH |
2062 | /* PCI <-> OF binding helpers */ |
2063 | #ifdef CONFIG_OF | |
2064 | struct device_node; | |
b165e2b6 | 2065 | struct irq_domain; |
f39d5b72 BH |
2066 | void pci_set_of_node(struct pci_dev *dev); |
2067 | void pci_release_of_node(struct pci_dev *dev); | |
2068 | void pci_set_bus_of_node(struct pci_bus *bus); | |
2069 | void pci_release_bus_of_node(struct pci_bus *bus); | |
b165e2b6 | 2070 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
98d9f30c BH |
2071 | |
2072 | /* Arch may override this (weak) */ | |
723ec4d0 | 2073 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 2074 | |
3df425f3 JC |
2075 | static inline struct device_node * |
2076 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
64099d98 BH |
2077 | { |
2078 | return pdev ? pdev->dev.of_node : NULL; | |
2079 | } | |
2080 | ||
ef3b4f8c BH |
2081 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
2082 | { | |
2083 | return bus ? bus->dev.of_node : NULL; | |
2084 | } | |
2085 | ||
98d9f30c BH |
2086 | #else /* CONFIG_OF */ |
2087 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
2088 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
2089 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
2090 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
f0b66a2c KH |
2091 | static inline struct device_node * |
2092 | pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } | |
b165e2b6 MZ |
2093 | static inline struct irq_domain * |
2094 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } | |
98d9f30c BH |
2095 | #endif /* CONFIG_OF */ |
2096 | ||
471036b2 SS |
2097 | #ifdef CONFIG_ACPI |
2098 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); | |
2099 | ||
2100 | void | |
2101 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); | |
2102 | #else | |
2103 | static inline struct irq_domain * | |
2104 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } | |
2105 | #endif | |
2106 | ||
eb740b5f GS |
2107 | #ifdef CONFIG_EEH |
2108 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
2109 | { | |
2110 | return pdev->dev.archdata.edev; | |
2111 | } | |
2112 | #endif | |
2113 | ||
f0af9593 | 2114 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); |
338c3149 | 2115 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
c25dc828 AW |
2116 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
2117 | int (*fn)(struct pci_dev *pdev, | |
2118 | u16 alias, void *data), void *data); | |
2119 | ||
ce052984 EZ |
2120 | /* helper functions for operation of device flag */ |
2121 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) | |
2122 | { | |
2123 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
2124 | } | |
2125 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
2126 | { | |
2127 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
2128 | } | |
2129 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
2130 | { | |
2131 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
2132 | } | |
19bdb6e4 AW |
2133 | |
2134 | /** | |
2135 | * pci_ari_enabled - query ARI forwarding status | |
2136 | * @bus: the PCI bus | |
2137 | * | |
2138 | * Returns true if ARI forwarding is enabled. | |
2139 | */ | |
2140 | static inline bool pci_ari_enabled(struct pci_bus *bus) | |
2141 | { | |
2142 | return bus->self && bus->self->ari_enabled; | |
2143 | } | |
bc4b024a CH |
2144 | |
2145 | /* provide the legacy pci_dma_* API */ | |
2146 | #include <linux/pci-dma-compat.h> | |
2147 | ||
1da177e4 | 2148 | #endif /* LINUX_PCI_H */ |