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PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
7ce2e76a
KW		 9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
1da177e4
LT		 14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
7ce2e76a 20 * PCI Express Specification
1da177e4
LT		 21 * PCI System Design Guide
22 */
1da177e4
LT		 23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
b229baa3 26#include <linux/args.h>
778382e0
DW		 27#include <linux/mod_devicetable.h>
28
1da177e4 29#include <linux/types.h>
98db6f19 30#include <linux/init.h>
1da177e4
LT		 31#include <linux/ioport.h>
32#include <linux/list.h>
4a7fb636 33#include <linux/compiler.h>
1da177e4 34#include <linux/errno.h>
f46753c5 35#include <linux/kobject.h>
60063497 36#include <linux/atomic.h>
1da177e4 37#include <linux/device.h>
704e8953 38#include <linux/interrupt.h>
1388cc96 39#include <linux/io.h>
14d76b68 40#include <linux/resource_ext.h>
34026364 41#include <linux/msi_api.h>
607ca46e 42#include <uapi/linux/pci.h>
1da177e4 43
7e7a43c3
AB		 44#include <linux/pci_ids.h>
45
d6e055e8
HK		 46#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
e20afa06 53/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
6937b7dd 54#define PCI_NUM_RESET_METHODS 7
e20afa06 55
9bdc81ce
AN		 56#define PCI_RESET_PROBE true
57#define PCI_RESET_DO_RESET false
58
85467136
SK		 59/*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
f7625980
BH		 66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 68 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 69 * the following kernel-only defines are being added here.
85467136 70 */
0aa0f5d1 71#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 72/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
f46753c5
AC		 75/* pci_slot represents a physical slot */
76struct pci_slot {
0aa0f5d1
BH		 77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
f46753c5
AC		 82};
83
0ad772ec
AC		 84static inline const char *pci_slot_name(const struct pci_slot *slot)
85{
86 return kobject_name(&slot->kobj);
87}
88
1da177e4
LT		 89/* File state for mmap()s on /proc/bus/pci/X/Y */
90enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93};
94
0aa0f5d1 95/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 96enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
c9c13ba4 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
fde09c6d
YZ		 100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
0aa0f5d1 104 /* Device-specific resources */
d1b054da
YZ		 105#ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108#endif
109
6e0688db
KW		 110/* PCI-to-PCI (P2P) bridge windows */
111#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115/* CardBus bridge windows */
116#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121/* Total number of bridge resources for P2P and CardBus */
fde09c6d
YZ		 122#define PCI_BRIDGE_RESOURCE_NUM 4
123
6e0688db 124 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
0aa0f5d1 129 /* Total resources associated with a PCI device */
fde09c6d
YZ		 130 PCI_NUM_RESOURCES,
131
0aa0f5d1 132 /* Preserve this for compatibility */
cda57bf9 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 134};
1da177e4 135
b352baf1
PB		 136/**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153};
154
155/* The number of legacy PCI INTx interrupts */
156#define PCI_NUM_INTX 4
157
57bdeef4
NN		 158/*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163#define PCI_ERROR_RESPONSE (~0ULL)
164#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
224abb67
BH		 167/*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
1da177e4
LT		 171typedef int __bitwise pci_power_t;
172
4352dfd5
GKH		 173#define PCI_D0 ((pci_power_t __force) 0)
174#define PCI_D1 ((pci_power_t __force) 1)
175#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 176#define PCI_D3hot ((pci_power_t __force) 3)
177#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 178#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 179#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 180
00240c38
AS		 181/* Remember to update this when the list above changes! */
182extern const char *pci_power_names[];
183
184static inline const char *pci_power_name(pci_power_t state)
185{
9661e783 186 return pci_power_names[1 + (__force int) state];
00240c38
AS		 187}
188
0aa0f5d1 189/**
229b4e07
CD		 190 * typedef pci_channel_state_t
191 *
0aa0f5d1
BH		 192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
392a1ce7 195 */
196typedef unsigned int __bitwise pci_channel_state_t;
197
16d79cd4 198enum {
392a1ce7 199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207};
208
f7bdd12d
BK		 209typedef unsigned int __bitwise pcie_reset_state_t;
210
211enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
f7625980 215 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
f7625980 218 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220};
221
ba698ad4
DM		 222typedef unsigned short __bitwise pci_dev_flags_t;
223enum pci_dev_flags {
0aa0f5d1 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 226 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 228 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 240 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 244 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
2226667a
MZ		 246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
ba698ad4
DM		 248};
249
e1d3a908
SA		 250enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253};
254
6e325a62
MT		 255typedef unsigned short __bitwise pci_bus_flags_t;
256enum pci_bus_flags {
032c3d86
JD		 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 261};
262
0aa0f5d1 263/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 264enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
0aa0f5d1 270 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
0aa0f5d1 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 274};
275
e56faff5 276/* See matching string table in pci_speed_string() */
536c8cb4
MW		 277enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
536c8cb4
MW		 294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 299 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 300 PCIE_SPEED_16_0GT = 0x17,
de76cda2 301 PCIE_SPEED_32_0GT = 0x18,
34191749 302 PCIE_SPEED_64_0GT = 0x19,
536c8cb4
MW		 303 PCI_SPEED_UNKNOWN = 0xff,
304};
305
576c7218
AD		 306enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
fd00faa3
HK		 309struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
24a4742f
AW		 313};
314
402723ad 315struct irq_affinity;
7d715a6c 316struct pcie_link_state;
d1b054da 317struct pci_sriov;
52916982 318struct pci_p2pdma;
90655631 319struct rcec_ea;
ee69439c 320
0aa0f5d1 321/* The pci_dev structure describes PCI devices */
1da177e4 322struct pci_dev {
0aa0f5d1
BH		 323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 326
0aa0f5d1
BH		 327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 329 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 330
0aa0f5d1 331 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 337 u8 revision; /* PCI revision, low byte of class word */
1da177e4 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 339#ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
db89ccbe 341 struct aer_stats *aer_stats; /* AER stats for this device */
90655631
SK		 342#endif
343#ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
507b460f 345 struct pci_dev *rcec; /* Associated RCEC device */
66b80809 346#endif
69139244 347 u32 devcap; /* PCIe Device Capabilities */
f7625980 348 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
f7625980 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 356
68da4e0e 357 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
4d57cdfa
FT		 364 struct device_dma_parameters dma_parms;
365
0aa0f5d1
BH		 366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
703860ed 369 u8 pm_cap; /* PM capability offset */
849846c4 370 unsigned int imm_ready:1; /* Supports Immediate Readiness */
337001b6
RW		 371 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 can be generated */
379021d5 373 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
e80bb09d 382 unsigned int wakeup_prepared:1;
d491f2b7 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
387 user sysfs */
4ec73791
SM		 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 bit manually */
3789af9a 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
448bd857 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 392
7d715a6c 393#ifdef CONFIG_PCIEASPM
f7625980 394 struct pcie_link_state *link_state; /* ASPM link state */
849846c4 395 u16 l1ss; /* L1SS Capability pointer */
c46fd358
BH		 396 unsigned int ltr_path:1; /* Latency Tolerance Reporting
397 supported from root to here */
7d715a6c 398#endif
8c09e896 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
7ce3f912 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 401
0aa0f5d1
BH		 402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
1da177e4 404
0aa0f5d1 405 int cfg_size; /* Size of config space */
1da177e4
LT		 406
407 /*
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
410 */
411 unsigned int irq;
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
27829479 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
1da177e4 414
0aa0f5d1
BH		 415 bool match_driver; /* Skip attaching driver */
416
417 unsigned int transparent:1; /* Subtractive decode bridge */
51c48b31
BH		 418 unsigned int io_window:1; /* Bridge has I/O window */
419 unsigned int pref_window:1; /* Bridge has pref mem window */
420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
0aa0f5d1
BH		 421 unsigned int multifunction:1; /* Multi-function device */
422
0aa0f5d1
BH		 423 unsigned int is_busmaster:1; /* Is busmaster */
424 unsigned int no_msi:1; /* May not use MSI */
f6b6aefe 425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
0aa0f5d1
BH		 426 unsigned int block_cfg_access:1; /* Config space access blocked */
427 unsigned int broken_parity_status:1; /* Generates false positive parity */
428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 429 unsigned int msi_enabled:1;
99dc804d 430 unsigned int msix_enabled:1;
0aa0f5d1
BH		 431 unsigned int ari_enabled:1; /* ARI forwarding */
432 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 433 unsigned int pasid_enabled:1; /* Process Address Space ID */
434 unsigned int pri_enabled:1; /* Page Request Interface */
3f35d2cf
TG		 435 unsigned int is_managed:1; /* Managed via devres */
436 unsigned int is_msi_managed:1; /* MSI release via devres installed */
0aa0f5d1 437 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 438 unsigned int state_saved:1;
d1b054da 439 unsigned int is_physfn:1;
dd7cc44d 440 unsigned int is_virtfn:1;
0aa0f5d1 441 unsigned int is_hotplug_bridge:1;
b03799b0 442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
0aa0f5d1 443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
617654aa
MW		 444 /*
445 * Devices marked being untrusted are the ones that can potentially
446 * execute DMA attacks and similar. They are typically connected
447 * through external ports such as Thunderbolt but not limited to
448 * that. When an IOMMU is enabled they should be getting full
449 * mappings to make sure they cannot access arbitrary memory.
450 */
451 unsigned int untrusted:1;
99b50be9
RJ		 452 /*
453 * Info from the platform, e.g., ACPI or device tree, may mark a
454 * device as "external-facing". An external-facing device is
455 * itself internal but devices downstream from it are external.
456 */
457 unsigned int external_facing:1;
0aa0f5d1
BH		 458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 460 unsigned int irq_managed:1;
0aa0f5d1
BH		 461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
462 unsigned int is_probed:1; /* Device probing in progress */
f0157160 463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
aff68a5a 464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
12856e7a 465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
500b55b0 466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
091f9f7f 467 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
ba698ad4 468 pci_dev_flags_t dev_flags;
bae94d02 469 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 470
5e70d0ac 471 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
0aa0f5d1 472 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 473 struct hlist_head saved_cap_space;
1da177e4 474 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 475 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 476
d22b3621
BH		 477#ifdef CONFIG_HOTPLUG_PCI_PCIE
478 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
479#endif
9bb04a0c 480#ifdef CONFIG_PCIE_PTM
a47126ec 481 u16 ptm_cap; /* PTM Capability */
9bb04a0c
JY		 482 unsigned int ptm_root:1;
483 unsigned int ptm_enabled:1;
8b2ec318 484 u8 ptm_granularity;
9bb04a0c 485#endif
ded86d8d 486#ifdef CONFIG_PCI_MSI
85aa607e 487 void __iomem *msix_base;
cd119b09 488 raw_spinlock_t msi_lock;
ded86d8d 489#endif
fd00faa3 490 struct pci_vpd vpd;
be06c1b4
BH		 491#ifdef CONFIG_PCIE_DPC
492 u16 dpc_cap;
493 unsigned int dpc_rp_extensions:1;
494 u8 dpc_rp_log_size;
495#endif
466b3ddf 496#ifdef CONFIG_PCI_ATS
dd7cc44d 497 union {
0aa0f5d1
BH		 498 struct pci_sriov *sriov; /* PF: SR-IOV info */
499 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 500 };
67930995
BH		 501 u16 ats_cap; /* ATS Capability offset */
502 u8 ats_stu; /* ATS Smallest Translation Unit */
4ebeb1ec
CT		 503#endif
504#ifdef CONFIG_PCI_PRI
c065190b 505 u16 pri_cap; /* PRI Capability offset */
4ebeb1ec 506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
e5adf79a 507 unsigned int pasid_required:1; /* PRG Response PASID Required */
4ebeb1ec
CT		 508#endif
509#ifdef CONFIG_PCI_PASID
751035b8 510 u16 pasid_cap; /* PASID Capability offset */
4ebeb1ec 511 u16 pasid_features;
52916982
LG		 512#endif
513#ifdef CONFIG_PCI_P2PDMA
ae21f835 514 struct pci_p2pdma __rcu *p2pdma;
ac048403
LW		 515#endif
516#ifdef CONFIG_PCI_DOE
517 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
d1b054da 518#endif
52fbf5bd 519 u16 acs_cap; /* ACS Capability offset */
0aa0f5d1
BH		 520 phys_addr_t rom; /* Physical address if not from BAR */
521 size_t romlen; /* Length if not from BAR */
23d99baf
KK		 522 /*
523 * Driver name to force a match. Do not set directly, because core
524 * frees it. Use driver_set_override() to set or clear it.
525 */
526 const char *driver_override;
89ee9f76 527
0aa0f5d1 528 unsigned long priv_flags; /* Private flags for the PCI driver */
e20afa06
AN		 529
530 /* These methods index pci_reset_fn_methods[] */
531 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
1da177e4
LT		 532};
533
dda56549
Y		 534static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
535{
536#ifdef CONFIG_PCI_IOV
537 if (dev->is_virtfn)
538 dev = dev->physfn;
539#endif
dda56549
Y		 540 return dev;
541}
542
3c6e6ae7 543struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 544
1da177e4
LT		 545#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
546#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
547
a7369f1f
LV		 548static inline int pci_channel_offline(struct pci_dev *pdev)
549{
550 return (pdev->error_state != pci_channel_io_normal);
551}
552
15d82ca2
BF		 553/*
554 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
555 * Group number is limited to a 16-bit value, therefore (int)-1 is
556 * not a valid PCI domain number, and can be used as a sentinel
557 * value indicating ->domain_nr is not set by the driver (and
558 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
559 * pci_bus_find_domain_nr()).
560 */
561#define PCI_DOMAIN_NR_NOT_SET (-1)
562
5a21d70d 563struct pci_host_bridge {
0aa0f5d1
BH		 564 struct device dev;
565 struct pci_bus *bus; /* Root bus */
566 struct pci_ops *ops;
07e29295 567 struct pci_ops *child_ops;
0aa0f5d1
BH		 568 void *sysdata;
569 int busnr;
15d82ca2 570 int domain_nr;
14d76b68 571 struct list_head windows; /* resource_entry */
e80a91ad 572 struct list_head dma_ranges; /* dma ranges resource list */
0aa0f5d1 573 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 574 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 575 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 576 void *release_data;
0aa0f5d1
BH		 577 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
578 unsigned int no_ext_tags:1; /* No Extended Tags */
8b3517f8 579 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
02bfeb48 580 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 581 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 582 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 583 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 584 unsigned int native_ltr:1; /* OS may use PCIe LTR */
ac1c8e35 585 unsigned int native_dpc:1; /* OS may use PCIe DPC */
589c3357 586 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
a78cf965 587 unsigned int preserve_config:1; /* Preserve FW resource setup */
2c8d5a2d 588 unsigned int size_windows:1; /* Enable root bus sizing */
94e89b14 589 unsigned int msi_domain:1; /* Bridge wants MSI domain */
a78cf965 590
7c7a0e94
GP		 591 /* Resource alignment requirements */
592 resource_size_t (*align_resource)(struct pci_dev *dev,
593 const struct resource *res,
594 resource_size_t start,
595 resource_size_t size,
596 resource_size_t align);
914a1951 597 unsigned long private[] ____cacheline_aligned;
5a21d70d 598};
41017f0c 599
7b543663 600#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 601
59094065
TR		 602static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
603{
604 return (void *)bridge->private;
605}
606
607static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
608{
609 return container_of(priv, struct pci_host_bridge, private);
610}
611
a52d1443 612struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 613struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
614 size_t priv);
dff79b91 615void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 616struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
617
4fa2649a 618void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 619 void (*release_fn)(struct pci_host_bridge *),
620 void *release_data);
7b543663 621
6c0cc950
RW		 622int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
623
2fe2abf8
BH		 624/*
625 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
626 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
627 * buses below host bridges or subtractive decode bridges) go in the list.
628 * Use pci_bus_for_each_resource() to iterate through all the resources.
629 */
630
631/*
632 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
633 * and there's no way to program the bridge with the details of the window.
634 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
635 * decode bit set, because they are explicit and can be programmed with _SRS.
636 */
637#define PCI_SUBTRACTIVE_DECODE 0x1
638
639struct pci_bus_resource {
0aa0f5d1
BH		 640 struct list_head list;
641 struct resource *res;
642 unsigned int flags;
2fe2abf8 643};
4352dfd5
GKH		 644
645#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 646
647struct pci_bus {
0aa0f5d1
BH		 648 struct list_head node; /* Node in list of buses */
649 struct pci_bus *parent; /* Parent bus this bridge is on */
650 struct list_head children; /* List of child buses */
651 struct list_head devices; /* List of devices on this bus */
652 struct pci_dev *self; /* Bridge device as seen by parent */
653 struct list_head slots; /* List of slots on this bus;
67546762 654 protected by pci_slot_mutex */
2fe2abf8 655 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 656 struct list_head resources; /* Address space routed to this bus */
657 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 658
0aa0f5d1 659 struct pci_ops *ops; /* Configuration access functions */
0aa0f5d1
BH		 660 void *sysdata; /* Hook for sys-specific extension */
661 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 662
0aa0f5d1
BH		 663 unsigned char number; /* Bus number */
664 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 665 unsigned char max_bus_speed; /* enum pci_bus_speed */
666 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 667#ifdef CONFIG_PCI_DOMAINS_GENERIC
668 int domain_nr;
669#endif
1da177e4
LT		 670
671 char name[48];
672
0aa0f5d1
BH		 673 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
674 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 675 struct device *bridge;
fd7d1ced 676 struct device dev;
0aa0f5d1
BH		 677 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
678 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 679 unsigned int is_added:1;
92c45b63 680 unsigned int unsafe_warn:1; /* warned about RW1C config write */
1da177e4
LT		 681};
682
fd7d1ced 683#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 684
4e544bac
HK		 685static inline u16 pci_dev_id(struct pci_dev *dev)
686{
687 return PCI_DEVID(dev->bus->number, dev->devfn);
688}
689
79af72d7 690/*
f7625980 691 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 692 * false otherwise
77a0dfcd
BH		 693 *
694 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
695 * This is incorrect because "virtual" buses added for SR-IOV (via
696 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 697 */
698static inline bool pci_is_root_bus(struct pci_bus *pbus)
699{
700 return !(pbus->parent);
701}
702
1c86438c
YW		 703/**
704 * pci_is_bridge - check if the PCI device is a bridge
705 * @dev: PCI device
706 *
707 * Return true if the PCI device is bridge whether it has subordinate
708 * or not.
709 */
710static inline bool pci_is_bridge(struct pci_dev *dev)
711{
712 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
713 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
714}
715
7e845ecb
SJ		 716/**
717 * pci_is_vga - check if the PCI device is a VGA device
718 *
719 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
720 * VGA Base Class and Sub-Classes:
721 *
722 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
723 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
724 *
725 * Return true if the PCI device is a VGA device and uses the legacy VGA
726 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
727 * aliases).
728 */
729static inline bool pci_is_vga(struct pci_dev *pdev)
730{
731 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
732 return true;
733
734 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
735 return true;
736
737 return false;
738}
739
24a0c654
AS		 740#define for_each_pci_bridge(dev, bus) \
741 list_for_each_entry(dev, &bus->devices, bus_list) \
742 if (!pci_is_bridge(dev)) {} else
743
c6bde215
BH		 744static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
745{
746 dev = pci_physfn(dev);
747 if (pci_is_root_bus(dev->bus))
748 return NULL;
749
750 return dev->bus->self;
751}
752
16cf0ebc
RW		 753#ifdef CONFIG_PCI_MSI
754static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
755{
756 return pci_dev->msi_enabled || pci_dev->msix_enabled;
757}
758#else
759static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
760#endif
761
0aa0f5d1 762/* Error values that may be returned by PCI functions */
1da177e4
LT		 763#define PCIBIOS_SUCCESSFUL 0x00
764#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
765#define PCIBIOS_BAD_VENDOR_ID 0x83
766#define PCIBIOS_DEVICE_NOT_FOUND 0x86
767#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
768#define PCIBIOS_SET_FAILED 0x88
769#define PCIBIOS_BUFFER_TOO_SMALL 0x89
770
0aa0f5d1 771/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 772static inline int pcibios_err_to_errno(int err)
773{
774 if (err <= PCIBIOS_SUCCESSFUL)
775 return err; /* Assume already errno */
776
777 switch (err) {
778 case PCIBIOS_FUNC_NOT_SUPPORTED:
779 return -ENOENT;
780 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 781 return -ENOTTY;
a6961651
AW		 782 case PCIBIOS_DEVICE_NOT_FOUND:
783 return -ENODEV;
784 case PCIBIOS_BAD_REGISTER_NUMBER:
785 return -EFAULT;
786 case PCIBIOS_SET_FAILED:
787 return -EIO;
788 case PCIBIOS_BUFFER_TOO_SMALL:
789 return -ENOSPC;
790 }
791
d97ffe23 792 return -ERANGE;
a6961651
AW		 793}
794
1da177e4
LT		 795/* Low-level architecture-dependent routines */
796
797struct pci_ops {
057bd2e0
TR		 798 int (*add_bus)(struct pci_bus *bus);
799 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 800 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 801 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
802 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
803};
804
b6ce068a
MW		 805/*
806 * ACPI needs to be able to access PCI config space before we've done a
807 * PCI bus scan and created pci_bus structures.
808 */
f39d5b72
BH		 809int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
810 int reg, int len, u32 *val);
811int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
812 int reg, int len, u32 val);
1da177e4 813
8e639079 814#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 815typedef u64 pci_bus_addr_t;
816#else
817typedef u32 pci_bus_addr_t;
818#endif
819
1da177e4 820struct pci_bus_region {
0aa0f5d1
BH		 821 pci_bus_addr_t start;
822 pci_bus_addr_t end;
1da177e4
LT		 823};
824
825struct pci_dynids {
0aa0f5d1
BH		 826 spinlock_t lock; /* Protects list, index */
827 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 828};
829
f7625980
BH		 830
831/*
832 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
833 * a set of callbacks in struct pci_error_handlers, that device driver
834 * will be notified of PCI bus errors, and will be driven to recovery
835 * when an error occurs.
392a1ce7 836 */
837
838typedef unsigned int __bitwise pci_ers_result_t;
839
840enum pci_ers_result {
0aa0f5d1 841 /* No result/none/not supported in device driver */
392a1ce7 842 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
843
844 /* Device driver can recover without slot reset */
845 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
846
0aa0f5d1 847 /* Device driver wants slot to be reset */
392a1ce7 848 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
849
850 /* Device has completely failed, is unrecoverable */
851 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
852
853 /* Device driver is fully recovered and operational */
854 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 855
856 /* No AER capabilities registered for the driver */
857 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 858};
859
860/* PCI bus error event callbacks */
05cca6e5 861struct pci_error_handlers {
392a1ce7 862 /* PCI bus error detected on this device */
863 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
16d79cd4 864 pci_channel_state_t error);
392a1ce7 865
866 /* MMIO has been re-enabled, but not DMA */
867 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
868
392a1ce7 869 /* PCI slot has been reset */
870 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
871
3ebe7f9f 872 /* PCI function reset prepare or completed */
775755ed
CH		 873 void (*reset_prepare)(struct pci_dev *dev);
874 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 875
392a1ce7 876 /* Device driver may resume normal operations */
877 void (*resume)(struct pci_dev *dev);
361187e0
DJ		 878
879 /* Allow device driver to record more details of a correctable error */
880 void (*cor_error_detected)(struct pci_dev *dev);
392a1ce7 881};
882
392a1ce7 883
1da177e4 884struct module;
229b4e07
CD		 885
886/**
887 * struct pci_driver - PCI driver structure
888 * @node: List of driver structures.
889 * @name: Driver name.
890 * @id_table: Pointer to table of device IDs the driver is
891 * interested in. Most drivers should export this
892 * table using MODULE_DEVICE_TABLE(pci,...).
893 * @probe: This probing function gets called (during execution
894 * of pci_register_driver() for already existing
895 * devices or later if a new device gets inserted) for
896 * all PCI devices which match the ID table and are not
897 * "owned" by the other drivers yet. This function gets
898 * passed a "struct pci_dev \*" for each device whose
899 * entry in the ID table matches the device. The probe
900 * function returns zero when the driver chooses to
901 * take "ownership" of the device or an error code
902 * (negative number) otherwise.
903 * The probe function always gets called from process
904 * context, so it can sleep.
905 * @remove: The remove() function gets called whenever a device
906 * being handled by this driver is removed (either during
907 * deregistration of the driver or when it's manually
908 * pulled out of a hot-pluggable slot).
909 * The remove function always gets called from process
910 * context, so it can sleep.
911 * @suspend: Put device into low power state.
229b4e07 912 * @resume: Wake device from low power state.
151f4e2b 913 * (Please see Documentation/power/pci.rst for descriptions
229b4e07
CD		 914 * of PCI Power Management and the related functions.)
915 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
916 * Intended to stop any idling DMA operations.
917 * Useful for enabling wake-on-lan (NIC) or changing
918 * the power state of a device before reboot.
919 * e.g. drivers/net/e100.c.
920 * @sriov_configure: Optional driver callback to allow configuration of
921 * number of VFs to enable via sysfs "sriov_numvfs" file.
c3d5c2d9
LR		 922 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
923 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
924 * This will change MSI-X Table Size in the VF Message Control
925 * registers.
926 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
927 * MSI-X vectors available for distribution to the VFs.
229b4e07
CD		 928 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
929 * @groups: Sysfs attribute groups.
ded13b9c
AG		 930 * @dev_groups: Attributes attached to the device that will be
931 * created once it is bound to the driver.
229b4e07
CD		 932 * @driver: Driver model structure.
933 * @dynids: List of dynamically added device IDs.
512881ea
LB		 934 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
935 * For most device drivers, no need to care about this flag
936 * as long as all DMAs are handled through the kernel DMA API.
937 * For some special ones, for example VFIO drivers, they know
938 * how to manage the DMA themselves and set this flag so that
939 * the IOMMU layer will allow them to setup and manage their
940 * own I/O address space.
229b4e07 941 */
1da177e4 942struct pci_driver {
0aa0f5d1
BH		 943 struct list_head node;
944 const char *name;
945 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
946 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
947 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
948 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
7cb30264
BY		 949 int (*resume)(struct pci_dev *dev); /* Device woken up */
950 void (*shutdown)(struct pci_dev *dev);
951 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
c3d5c2d9
LR		 952 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
953 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
49453028 954 const struct pci_error_handlers *err_handler;
92d50fc1 955 const struct attribute_group **groups;
ded13b9c 956 const struct attribute_group **dev_groups;
1da177e4 957 struct device_driver driver;
0aa0f5d1 958 struct pci_dynids dynids;
512881ea 959 bool driver_managed_dma;
1da177e4
LT		 960};
961
8e9028b3
BH		 962static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
963{
964 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
965}
1da177e4
LT		 966
967/**
0aa0f5d1 968 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 969 * @vend: the 16 bit PCI Vendor ID
970 * @dev: the 16 bit PCI Device ID
971 *
972 * This macro is used to create a struct pci_device_id that matches a
973 * specific device. The subvendor and subdevice fields will be set to
974 * PCI_ANY_ID.
975 */
976#define PCI_DEVICE(vend,dev) \
977 .vendor = (vend), .device = (dev), \
978 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
979
343b7258
MG		 980/**
981 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
982 * override_only flags.
983 * @vend: the 16 bit PCI Vendor ID
984 * @dev: the 16 bit PCI Device ID
985 * @driver_override: the 32 bit PCI Device override_only
986 *
987 * This macro is used to create a struct pci_device_id that matches only a
988 * driver_override device. The subvendor and subdevice fields will be set to
989 * PCI_ANY_ID.
990 */
991#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
992 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
993 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
994
cc6711b0
MG		 995/**
996 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
997 * "driver_override" PCI device.
998 * @vend: the 16 bit PCI Vendor ID
999 * @dev: the 16 bit PCI Device ID
1000 *
1001 * This macro is used to create a struct pci_device_id that matches a
1002 * specific device. The subvendor and subdevice fields will be set to
1003 * PCI_ANY_ID and the driver_override will be set to
1004 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1005 */
1006#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1007 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1008
3d567e0e 1009/**
0aa0f5d1 1010 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 1011 * @vend: the 16 bit PCI Vendor ID
1012 * @dev: the 16 bit PCI Device ID
1013 * @subvend: the 16 bit PCI Subvendor ID
1014 * @subdev: the 16 bit PCI Subdevice ID
1015 *
1016 * This macro is used to create a struct pci_device_id that matches a
1017 * specific device with subsystem information.
1018 */
1019#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1020 .vendor = (vend), .device = (dev), \
1021 .subvendor = (subvend), .subdevice = (subdev)
1022
1da177e4 1023/**
0aa0f5d1 1024 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 1025 * @dev_class: the class, subclass, prog-if triple for this device
1026 * @dev_class_mask: the class mask for this device
1027 *
1028 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 1029 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 1030 * fields will be set to PCI_ANY_ID.
1031 */
1032#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1033 .class = (dev_class), .class_mask = (dev_class_mask), \
1034 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1035 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1036
1597cacb 1037/**
0aa0f5d1 1038 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 1039 * @vend: the vendor name
1040 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 1041 *
1042 * This macro is used to create a struct pci_device_id that matches a
1043 * specific PCI device. The subvendor, and subdevice fields will be set
1044 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1045 * private data.
1046 */
c1309040
MR		 1047#define PCI_VDEVICE(vend, dev) \
1048 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1049 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 1050
b72ae8ca
AS		 1051/**
1052 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1053 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1054 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1055 * @data: the driver data to be filled
1056 *
1057 * This macro is used to create a struct pci_device_id that matches a
1058 * specific PCI device. The subvendor, and subdevice fields will be set
1059 * to PCI_ANY_ID.
1060 */
1061#define PCI_DEVICE_DATA(vend, dev, data) \
1062 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1063 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1064 .driver_data = (kernel_ulong_t)(data)
1065
5bbe029f 1066enum {
0aa0f5d1
BH		 1067 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1068 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1069 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1070 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1071 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 1072 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 1073 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 1074};
1075
58ff9c5a 1076#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
0d8006dd
HX		 1077#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1078#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1079#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1080
58ff9c5a
BH		 1081#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* Deprecated! Use PCI_IRQ_INTX */
1082
0aa0f5d1 1083/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 1084#ifdef CONFIG_PCI
1085
5bbe029f
BH		 1086extern unsigned int pci_flags;
1087
1088static inline void pci_set_flags(int flags) { pci_flags = flags; }
1089static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1090static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1091static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1092
a58674ff 1093void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 1094
1095enum pcie_bus_config_types {
0aa0f5d1
BH		 1096 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1097 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1098 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1099 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1100 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 1101};
1102
1103extern enum pcie_bus_config_types pcie_bus_config;
1104
1da177e4
LT		 1105extern struct bus_type pci_bus_type;
1106
f7625980
BH		 1107/* Do NOT directly access these two variables, unless you are arch-specific PCI
1108 * code, or PCI core code. */
0aa0f5d1 1109extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 1110/* Some device drivers need know if PCI is initiated */
f39d5b72 1111int no_pci_devices(void);
1da177e4 1112
3c449ed0 1113void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 1114void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 1115void pcibios_add_bus(struct pci_bus *bus);
1116void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 1117void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 1118int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 1119/* Architecture-specific versions may override this (weak) */
05cca6e5 1120char *pcibios_setup(char *str);
1da177e4
LT		 1121
1122/* Used only when drivers/pci/setup.c is used */
3b7a17fc 1123resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 1124 resource_size_t,
e31dd6e4 1125 resource_size_t);
1da177e4 1126
d1bbf38a 1127/* Weak but can be overridden by arch */
2d1c8618
BH		 1128void pci_fixup_cardbus(struct pci_bus *);
1129
1da177e4
LT		 1130/* Generic PCI functions used internally */
1131
fc279850 1132void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 1133 struct resource *res);
fc279850 1134void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 1135 struct pci_bus_region *region);
d1fd4fb6 1136void pcibios_scan_specific_bus(int busn);
f39d5b72 1137struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 1138void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 1139struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 1140struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1141 struct pci_ops *ops, void *sysdata,
1142 struct list_head *resources);
49b8e3f3 1143int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 1144int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1145int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1146void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 1147struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 1148 struct pci_ops *ops, void *sysdata,
1149 struct list_head *resources);
1228c4b6 1150int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 1151struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1152 int busnr);
f46753c5 1153struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 1154 const char *name,
1155 struct hotplug_slot *hotplug);
f46753c5 1156void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 1157#ifdef CONFIG_SYSFS
1158void pci_dev_assign_slot(struct pci_dev *dev);
1159#else
1160static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1161#endif
1da177e4 1162int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 1163struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 1164void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 1165unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 1166void pci_bus_add_device(struct pci_dev *dev);
1da177e4 1167void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 1168struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1169 struct resource *res);
3df425f3 1170u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 1171int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 1172u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 1173struct pci_dev *pci_dev_get(struct pci_dev *dev);
1174void pci_dev_put(struct pci_dev *dev);
1175void pci_remove_bus(struct pci_bus *b);
1176void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 1177void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 1178void pci_stop_root_bus(struct pci_bus *bus);
1179void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 1180void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 1181void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 1182void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 1183#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1184#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 1185
1186/* Generic PCI functions exported to card drivers */
1187
f646c2a0
PM		 1188u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1189u8 pci_find_capability(struct pci_dev *dev, int cap);
1190u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1191u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1192u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
ee8b1c47
BH		 1193u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1194u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
29f3eb64 1195struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
c124fd9a 1196u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
ee122037 1197u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1da177e4 1198
70c0923b
JK		 1199u64 pci_get_dsn(struct pci_dev *dev);
1200
d42552c3 1201struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 1202 struct pci_dev *from);
05cca6e5 1203struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 1204 unsigned int ss_vendor, unsigned int ss_device,
1205 struct pci_dev *from);
05cca6e5 1206struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 1207struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1208 unsigned int devfn);
05cca6e5 1209struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
d427da23
SJ		 1210struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1211
1da177e4
LT		 1212int pci_dev_present(const struct pci_device_id *ids);
1213
05cca6e5
GKH		 1214int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1215 int where, u8 *val);
1216int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1217 int where, u16 *val);
1218int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1219 int where, u32 *val);
1220int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1221 int where, u8 val);
1222int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1223 int where, u16 val);
1224int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1225 int where, u32 val);
1f94a94f
RH		 1226
1227int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1228 int where, int size, u32 *val);
1229int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1230 int where, int size, u32 val);
1231int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1232 int where, int size, u32 *val);
1233int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1234 int where, int size, u32 val);
1235
a72b46c3 1236struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1237
d3881e50
KB		 1238int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1239int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1240int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1241int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1242int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1243int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 1244
8c0d3a02
JL		 1245int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1246int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1247int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1248int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
5e70d0ac
IJ		 1249int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1250 u16 clear, u16 set);
1251int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1252 u16 clear, u16 set);
8c0d3a02
JL		 1253int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1254 u32 clear, u32 set);
1255
5e70d0ac
IJ		 1256/**
1257 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1258 * @dev: PCI device structure of the PCI Express device
1259 * @pos: PCI Express Capability Register
1260 * @clear: Clear bitmask
1261 * @set: Set bitmask
1262 *
1263 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1264 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1265 * Capability Registers are accessed concurrently in RMW fashion, hence
1266 * require locking which is handled transparently to the caller.
1267 */
1268static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1269 int pos,
1270 u16 clear, u16 set)
1271{
1272 switch (pos) {
1273 case PCI_EXP_LNKCTL:
1274 case PCI_EXP_RTCTL:
1275 return pcie_capability_clear_and_set_word_locked(dev, pos,
1276 clear, set);
1277 default:
1278 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1279 clear, set);
1280 }
1281}
1282
8c0d3a02
JL		 1283static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1284 u16 set)
1285{
1286 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1287}
1288
1289static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1290 u32 set)
1291{
1292 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1293}
1294
1295static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1296 u16 clear)
1297{
1298 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1299}
1300
1301static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1302 u32 clear)
1303{
1304 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1305}
1306
0aa0f5d1 1307/* User-space driven config access */
c63587d7
AW		 1308int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1309int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1310int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1311int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1312int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1313int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1314
4a7fb636 1315int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1316int __must_check pci_enable_device_io(struct pci_dev *dev);
1317int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1318int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1319int __must_check pcim_enable_device(struct pci_dev *pdev);
1320void pcim_pin_device(struct pci_dev *pdev);
1321
99b3c58f
PG		 1322static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1323{
1324 /*
1325 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1326 * writable and no quirk has marked the feature broken.
1327 */
1328 return !pdev->broken_intx_masking;
1329}
1330
296ccb08
YS		 1331static inline int pci_is_enabled(struct pci_dev *pdev)
1332{
1333 return (atomic_read(&pdev->enable_cnt) > 0);
1334}
1335
9ac7849e
TH		 1336static inline int pci_is_managed(struct pci_dev *pdev)
1337{
1338 return pdev->is_managed;
1339}
1340
1da177e4 1341void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1342
1343extern unsigned int pcibios_max_latency;
1da177e4 1344void pci_set_master(struct pci_dev *dev);
6a479079 1345void pci_clear_master(struct pci_dev *dev);
96c55900 1346
f7bdd12d 1347int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1348int pci_set_cacheline_size(struct pci_dev *dev);
4a7fb636 1349int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1350int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1351int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1352void pci_clear_mwi(struct pci_dev *dev);
1fd3dde5 1353void pci_disable_parity(struct pci_dev *dev);
a04ce0ff 1354void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1355bool pci_check_and_mask_intx(struct pci_dev *dev);
1356bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1357int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1358int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1359int pcix_get_max_mmrbc(struct pci_dev *dev);
1360int pcix_get_mmrbc(struct pci_dev *dev);
1361int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1362int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1363int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1364int pcie_get_mps(struct pci_dev *dev);
1365int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1366u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1367 enum pci_bus_speed *speed,
1368 enum pcie_link_width *width);
9e506a7b 1369void pcie_print_link_status(struct pci_dev *dev);
9bdc81ce 1370int pcie_reset_flr(struct pci_dev *dev, bool probe);
91295d79 1371int pcie_flr(struct pci_dev *dev);
a96d627a 1372int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1373int pci_reset_function(struct pci_dev *dev);
a477b9cd 1374int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1375int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1376int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1377int pci_probe_reset_bus(struct pci_bus *bus);
c6a44ba9 1378int pci_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1379void pci_reset_secondary_bus(struct pci_dev *dev);
1380void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1381void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1382int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1383int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3 1384void pci_release_resource(struct pci_dev *dev, int resno);
192f1bf7
ND		 1385static inline int pci_rebar_bytes_to_size(u64 bytes)
1386{
1387 bytes = roundup_pow_of_two(bytes);
1388
1389 /* Return BAR size as defined in the resizable BAR specification */
1390 return max(ilog2(bytes), 20) - 20;
1391}
1392
8fbdbb66 1393u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
8bb705e3 1394int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1395int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1396bool pci_device_is_present(struct pci_dev *pdev);
08249651 1397void pci_ignore_hotplug(struct pci_dev *dev);
2856ba60 1398struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
ec5d9e87 1399int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1da177e4 1400
704e8953
CH		 1401int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1402 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1403 const char *fmt, ...);
1404void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1405
1da177e4 1406/* ROM control related routines */
e416de5e
AC		 1407int pci_enable_rom(struct pci_dev *pdev);
1408void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1409void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1410void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1da177e4
LT		 1411
1412/* Power management related routines */
1413int pci_save_state(struct pci_dev *dev);
1d3c16a8 1414void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1415struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1416int pci_load_saved_state(struct pci_dev *dev,
1417 struct pci_saved_state *state);
ffbdd3f7
AW		 1418int pci_load_and_free_saved_state(struct pci_dev *dev,
1419 struct pci_saved_state **state);
d6aa37cd 1420int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1421int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1422pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1423bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1424void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1425int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1426int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1427int pci_prepare_to_sleep(struct pci_dev *dev);
1428int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1429bool pci_dev_run_wake(struct pci_dev *dev);
9d26d3a8
MW		 1430void pci_d3cold_enable(struct pci_dev *dev);
1431void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1432bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
99efde6c 1433void pci_resume_bus(struct pci_bus *bus);
2a4d2c42 1434void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1435
bb209c82
BH		 1436/* For use by arch with custom probe code */
1437void set_pcie_port_type(struct pci_dev *pdev);
1438void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1439
ce5ccdef 1440/* Functions for PCI Hotplug drivers to use */
2f320521 1441unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1442unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1443void pci_lock_rescan_remove(void);
1444void pci_unlock_rescan_remove(void);
ce5ccdef 1445
0aa0f5d1 1446/* Vital Product Data routines */
287d19ce
SH		 1447ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1448ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
bf2928c7
HK		 1449ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1450ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
287d19ce 1451
1da177e4 1452/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1453resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1454void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1455void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1456void pci_bus_size_bridges(struct pci_bus *bus);
1457int pci_claim_resource(struct pci_dev *, int);
8505e729 1458int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1459void pci_assign_unassigned_resources(void);
6841ec68 1460void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1461void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1462void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1463int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
842de40d 1464int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1465void pci_assign_irq(struct pci_dev *dev);
afd29f90 1466struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1467#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1468int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1469int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1470void pci_release_regions(struct pci_dev *);
4a7fb636 1471int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 1472void pci_release_region(struct pci_dev *, int);
c87deff7 1473int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1474int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1475void pci_release_selected_regions(struct pci_dev *, int);
1da177e4 1476
27829479
IW		 1477static inline __must_check struct resource *
1478pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1479 unsigned int len, const char *name)
1480{
1481 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1482 name, IORESOURCE_EXCLUSIVE);
1483}
1484
1485static inline void pci_release_config_region(struct pci_dev *pdev,
1486 unsigned int offset,
1487 unsigned int len)
1488{
1489 __release_region(&pdev->driver_exclusive_resource, offset, len);
1490}
1491
1da177e4 1492/* drivers/pci/bus.c */
45ca9e97 1493void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1494void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1495 resource_size_t offset);
45ca9e97 1496void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1497void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1498 unsigned int flags);
2fe2abf8
BH		 1499struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1500void pci_bus_remove_resources(struct pci_bus *bus);
ab909509 1501void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
950334bc
BH		 1502int devm_request_pci_bus_resources(struct device *dev,
1503 struct list_head *resources);
2fe2abf8 1504
bfc45606
DD		 1505/* Temporary until new and working PCI SBR API in place */
1506int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1507
02992064
AS		 1508#define __pci_bus_for_each_res0(bus, res, ...) \
1509 for (unsigned int __b = 0; \
1510 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1511 __b++)
1512
1513#define __pci_bus_for_each_res1(bus, res, __b) \
1514 for (__b = 0; \
1515 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1516 __b++)
1517
ceb928be
AS		 1518/**
1519 * pci_bus_for_each_resource - iterate over PCI bus resources
1520 * @bus: the PCI bus
1521 * @res: pointer to the current resource
02992064 1522 * @...: optional index of the current resource
ceb928be
AS		 1523 *
1524 * Iterate over PCI bus resources. The first part is to go over PCI bus
1525 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1526 * After that continue with the separate list of the additional resources,
1527 * if not empty. That's why the Logical OR is being used.
1528 *
1529 * Possible usage:
1530 *
1531 * struct pci_bus *bus = ...;
1532 * struct resource *res;
1533 * unsigned int i;
1534 *
02992064 1535 * // With optional index
ceb928be
AS		 1536 * pci_bus_for_each_resource(bus, res, i)
1537 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
02992064
AS		 1538 *
1539 * // Without index
1540 * pci_bus_for_each_resource(bus, res)
1541 * _do_something_(res);
ceb928be 1542 */
02992064
AS		 1543#define pci_bus_for_each_resource(bus, res, ...) \
1544 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1545 (bus, res, __VA_ARGS__)
89a74ecc 1546
4a7fb636
AM		 1547int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1548 struct resource *res, resource_size_t size,
1549 resource_size_t align, resource_size_t min,
664c2848 1550 unsigned long type_mask,
3b7a17fc
DB		 1551 resource_size_t (*alignf)(void *,
1552 const struct resource *,
b26b2d49
DB		 1553 resource_size_t,
1554 resource_size_t),
4a7fb636 1555 void *alignf_data);
1da177e4 1556
8b921acf 1557
fcfaab30
GP		 1558int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1559 resource_size_t size);
c5076cfe
TN		 1560unsigned long pci_address_to_pio(phys_addr_t addr);
1561phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1562int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
a5fb9fb0
SS		 1563int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1564 phys_addr_t phys_addr);
4d3f1384 1565void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1566void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1567 resource_size_t offset,
1568 resource_size_t size);
1569void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1570 struct resource *res);
8b921acf 1571
3a9ad0b4 1572static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1573{
1574 struct pci_bus_region region;
1575
1576 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1577 return region.start;
1578}
1579
863b18f4 1580/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1581int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1582 const char *mod_name);
bba81165 1583
0aa0f5d1 1584/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1585#define pci_register_driver(driver) \
1586 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1587
05cca6e5 1588void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1589
1590/**
1591 * module_pci_driver() - Helper macro for registering a PCI driver
1592 * @__pci_driver: pci_driver struct
1593 *
1594 * Helper macro for PCI drivers which do not do anything special in module
1595 * init/exit. This eliminates a lot of boilerplate. Each module may only
1596 * use this macro once, and calling it replaces module_init() and module_exit()
1597 */
1598#define module_pci_driver(__pci_driver) \
0aa0f5d1 1599 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1600
b4eb6cdb
PG		 1601/**
1602 * builtin_pci_driver() - Helper macro for registering a PCI driver
1603 * @__pci_driver: pci_driver struct
1604 *
1605 * Helper macro for PCI drivers which do not do anything special in their
1606 * init code. This eliminates a lot of boilerplate. Each driver may only
1607 * use this macro once, and calling it replaces device_initcall(...)
1608 */
1609#define builtin_pci_driver(__pci_driver) \
1610 builtin_driver(__pci_driver, pci_register_driver)
1611
05cca6e5 1612struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1613int pci_add_dynid(struct pci_driver *drv,
1614 unsigned int vendor, unsigned int device,
1615 unsigned int subvendor, unsigned int subdevice,
1616 unsigned int class, unsigned int class_mask,
1617 unsigned long driver_data);
05cca6e5
GKH		 1618const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1619 struct pci_dev *dev);
1620int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1621 int pass);
1da177e4 1622
70298c6e 1623void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1624 void *userdata);
ac7dc65a 1625int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1626unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1627void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1628resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1629 unsigned long type);
cecf4864 1630
3448a19d
DA		 1631#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1632#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1633
deb2d2ec 1634int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1635 unsigned int command_bits, u32 flags);
fe537670 1636
d7cc609f
LG		 1637/*
1638 * Virtual interrupts allow for more interrupts to be allocated
1639 * than the device has interrupts for. These are not programmed
1640 * into the device's MSI-X table and must be handled by some
1641 * other driver means.
1642 */
1643#define PCI_IRQ_VIRTUAL (1 << 4)
1644
4fe0d154
CH		 1645#define PCI_IRQ_ALL_TYPES \
1646 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1647
1da177e4
LT		 1648#include <linux/dmapool.h>
1649
1da177e4 1650struct msix_entry {
0aa0f5d1
BH		 1651 u32 vector; /* Kernel uses to write allocated vector */
1652 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1653};
1654
41efa431
RC		 1655struct msi_domain_template;
1656
4c859804
BH		 1657#ifdef CONFIG_PCI_MSI
1658int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1659void pci_disable_msi(struct pci_dev *dev);
4c859804 1660int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1661void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1662void pci_restore_msi_state(struct pci_dev *dev);
1663int pci_msi_enabled(void);
4fe03955 1664int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1665int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1666 int minvec, int maxvec);
f7fc32cb
AG		 1667static inline int pci_enable_msix_exact(struct pci_dev *dev,
1668 struct msix_entry *entries, int nvec)
1669{
1670 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1671 if (rc < 0)
1672 return rc;
1673 return 0;
1674}
5c0997dc
AD		 1675int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1676 unsigned int max_vecs, unsigned int flags);
402723ad
CH		 1677int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1678 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1679 struct irq_affinity *affd);
402723ad 1680
34026364
TG		 1681bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1682struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1683 const struct irq_affinity_desc *affdesc);
1684void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1685
aff17164
CH		 1686void pci_free_irq_vectors(struct pci_dev *dev);
1687int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1688const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
41efa431
RC		 1689bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
1690 unsigned int hwsize, void *data);
1691struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
1692 const struct irq_affinity_desc *affdesc);
1693void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
aff17164 1694
4c859804 1695#else
2ee546c4 1696static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1697static inline void pci_disable_msi(struct pci_dev *dev) { }
1698static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1699static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1700static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1701static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1702static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1703{ return -ENOSYS; }
302a2523 1704static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1705 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1706{ return -ENOSYS; }
f7fc32cb 1707static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1708 struct msix_entry *entries, int nvec)
f7fc32cb 1709{ return -ENOSYS; }
402723ad
CH		 1710
1711static inline int
1712pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1713 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1714 struct irq_affinity *aff_desc)
aff17164 1715{
83b4605b
CH		 1716 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1717 return 1;
1718 return -ENOSPC;
aff17164 1719}
5c0997dc
AD		 1720static inline int
1721pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1722 unsigned int max_vecs, unsigned int flags)
1723{
1724 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1725 flags, NULL);
1726}
402723ad 1727
195d8e5d
RC		 1728static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1729{ return false; }
2b129f0b
RC		 1730static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1731 const struct irq_affinity_desc *affdesc)
1732{
1733 struct msi_map map = { .index = -ENOSYS, };
1734
1735 return map;
1736}
1737
1738static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1739{
1740}
1741
aff17164
CH		 1742static inline void pci_free_irq_vectors(struct pci_dev *dev)
1743{
1744}
1745
1746static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1747{
1748 if (WARN_ON_ONCE(nr > 0))
1749 return -EINVAL;
1750 return dev->irq;
1751}
ee8d41e5
TG		 1752static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1753 int vec)
1754{
1755 return cpu_possible_mask;
1756}
41efa431
RC		 1757
1758static inline bool pci_create_ims_domain(struct pci_dev *pdev,
1759 const struct msi_domain_template *template,
1760 unsigned int hwsize, void *data)
1761{ return false; }
1762
1763static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev,
1764 union msi_instance_cookie *icookie,
1765 const struct irq_affinity_desc *affdesc)
1766{
1767 struct msi_map map = { .index = -ENOSYS, };
1768
1769 return map;
1770}
1771
1772static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map)
1773{
1774}
1775
1da177e4
LT		 1776#endif
1777
0d58e6c1
PB		 1778/**
1779 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1780 * @d: the INTx IRQ domain
1781 * @node: the DT node for the device whose interrupt we're translating
1782 * @intspec: the interrupt specifier data from the DT
1783 * @intsize: the number of entries in @intspec
1784 * @out_hwirq: pointer at which to write the hwirq number
1785 * @out_type: pointer at which to write the interrupt type
1786 *
1787 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1788 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1789 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1790 * INTx value to obtain the hwirq number.
1791 *
1792 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1793 */
1794static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1795 struct device_node *node,
1796 const u32 *intspec,
1797 unsigned int intsize,
1798 unsigned long *out_hwirq,
1799 unsigned int *out_type)
1800{
1801 const u32 intx = intspec[0];
1802
1803 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1804 return -EINVAL;
1805
1806 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1807 return 0;
1808}
1809
ab0724ff 1810#ifdef CONFIG_PCIEPORTBUS
415e12b2 1811extern bool pcie_ports_disabled;
5352a44a 1812extern bool pcie_ports_native;
ab0724ff
MT		 1813#else
1814#define pcie_ports_disabled true
5352a44a 1815#define pcie_ports_native false
ab0724ff 1816#endif
415e12b2 1817
aff5d055
HK		 1818#define PCIE_LINK_STATE_L0S BIT(0)
1819#define PCIE_LINK_STATE_L1 BIT(1)
1820#define PCIE_LINK_STATE_CLKPM BIT(2)
1821#define PCIE_LINK_STATE_L1_1 BIT(3)
1822#define PCIE_LINK_STATE_L1_2 BIT(4)
1823#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1824#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
de82f60f
MB		 1825#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
1826 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
1827 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
1828 PCIE_LINK_STATE_L1_2_PCIPM)
7ce2e76a 1829
4c859804 1830#ifdef CONFIG_PCIEASPM
7ce2e76a
KW		 1831int pci_disable_link_state(struct pci_dev *pdev, int state);
1832int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
de82f60f 1833int pci_enable_link_state(struct pci_dev *pdev, int state);
7ce2e76a 1834void pcie_no_aspm(void);
f39d5b72 1835bool pcie_aspm_support_enabled(void);
accd2dd7 1836bool pcie_aspm_enabled(struct pci_dev *pdev);
4c859804 1837#else
7ce2e76a
KW		 1838static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1839{ return 0; }
1840static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1841{ return 0; }
de82f60f
MB		 1842static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1843{ return 0; }
7ce2e76a 1844static inline void pcie_no_aspm(void) { }
4c859804 1845static inline bool pcie_aspm_support_enabled(void) { return false; }
accd2dd7 1846static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
3e1b1600
AP		 1847#endif
1848
415e12b2 1849#ifdef CONFIG_PCIEAER
415e12b2
RW		 1850bool pci_aer_available(void);
1851#else
415e12b2
RW		 1852static inline bool pci_aer_available(void) { return false; }
1853#endif
1854
cef74409
GK		 1855bool pci_ats_disabled(void);
1856
1d71eb53
VCG		 1857#ifdef CONFIG_PCIE_PTM
1858int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
e8bdc5ea 1859void pci_disable_ptm(struct pci_dev *dev);
014408cd 1860bool pcie_ptm_enabled(struct pci_dev *dev);
1d71eb53
VCG		 1861#else
1862static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1863{ return -EINVAL; }
e8bdc5ea 1864static inline void pci_disable_ptm(struct pci_dev *dev) { }
014408cd
VCG		 1865static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1866{ return false; }
1d71eb53
VCG		 1867#endif
1868
f39d5b72
BH		 1869void pci_cfg_access_lock(struct pci_dev *dev);
1870bool pci_cfg_access_trylock(struct pci_dev *dev);
1871void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1872
dfd5bb23 1873void pci_dev_lock(struct pci_dev *dev);
e3a9b121
LC		 1874int pci_dev_trylock(struct pci_dev *dev);
1875void pci_dev_unlock(struct pci_dev *dev);
1876
4352dfd5
GKH		 1877/*
1878 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1879 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1880 * configuration space.
1881 */
32a2eea7
JG		 1882#ifdef CONFIG_PCI_DOMAINS
1883extern int pci_domains_supported;
1884#else
1885enum { pci_domains_supported = 0 };
2ee546c4
BH		 1886static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1887static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1888#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1889
670ba0c8
CM		 1890/*
1891 * Generic implementation for PCI domain support. If your
1892 * architecture does not need custom management of PCI
1893 * domains then this implementation will be used
1894 */
1895#ifdef CONFIG_PCI_DOMAINS_GENERIC
1896static inline int pci_domain_nr(struct pci_bus *bus)
1897{
1898 return bus->domain_nr;
1899}
2ab51dde
TN		 1900#ifdef CONFIG_ACPI
1901int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1902#else
2ab51dde
TN		 1903static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1904{ return 0; }
1905#endif
9c7cb891 1906int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
c14f7ccc 1907void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1908#endif
1909
0aa0f5d1 1910/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1911typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1912 unsigned int command_bits, u32 flags);
f39d5b72 1913void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1914
be9d2e89
JT		 1915static inline int
1916pci_request_io_regions(struct pci_dev *pdev, const char *name)
1917{
1918 return pci_request_selected_regions(pdev,
1919 pci_select_bars(pdev, IORESOURCE_IO), name);
1920}
1921
1922static inline void
1923pci_release_io_regions(struct pci_dev *pdev)
1924{
1925 return pci_release_selected_regions(pdev,
1926 pci_select_bars(pdev, IORESOURCE_IO));
1927}
1928
1929static inline int
1930pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1931{
1932 return pci_request_selected_regions(pdev,
1933 pci_select_bars(pdev, IORESOURCE_MEM), name);
1934}
1935
1936static inline void
1937pci_release_mem_regions(struct pci_dev *pdev)
1938{
1939 return pci_release_selected_regions(pdev,
1940 pci_select_bars(pdev, IORESOURCE_MEM));
1941}
1942
4352dfd5 1943#else /* CONFIG_PCI is not enabled */
1da177e4 1944
5bbe029f
BH		 1945static inline void pci_set_flags(int flags) { }
1946static inline void pci_add_flags(int flags) { }
1947static inline void pci_clear_flags(int flags) { }
1948static inline int pci_has_flag(int flag) { return 0; }
1949
1da177e4 1950/*
0aa0f5d1
BH		 1951 * If the system does not have PCI, clearly these return errors. Define
1952 * these as simple inline functions to avoid hair in drivers.
1da177e4 1953 */
05cca6e5
GKH		 1954#define _PCI_NOP(o, s, t) \
1955 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1956 int where, t val) \
1da177e4 1957 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1958
1959#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1960 _PCI_NOP(o, word, u16 x) \
1961 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1962_PCI_NOP_ALL(read, *)
1963_PCI_NOP_ALL(write,)
1964
d42552c3 1965static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1966 unsigned int device,
1967 struct pci_dev *from)
2ee546c4 1968{ return NULL; }
d42552c3 1969
05cca6e5
GKH		 1970static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1971 unsigned int device,
1972 unsigned int ss_vendor,
1973 unsigned int ss_device,
b08508c4 1974 struct pci_dev *from)
2ee546c4 1975{ return NULL; }
1da177e4 1976
05cca6e5
GKH		 1977static inline struct pci_dev *pci_get_class(unsigned int class,
1978 struct pci_dev *from)
2ee546c4 1979{ return NULL; }
1da177e4 1980
d427da23
SJ		 1981static inline struct pci_dev *pci_get_base_class(unsigned int class,
1982 struct pci_dev *from)
1983{ return NULL; }
877fee2a
HG		 1984
1985static inline int pci_dev_present(const struct pci_device_id *ids)
1986{ return 0; }
1987
ed4aaadb 1988#define no_pci_devices() (1)
1da177e4
LT		 1989#define pci_dev_put(dev) do { } while (0)
1990
2ee546c4 1991static inline void pci_set_master(struct pci_dev *dev) { }
2aa5ac63 1992static inline void pci_clear_master(struct pci_dev *dev) { }
2ee546c4
BH		 1993static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1994static inline void pci_disable_device(struct pci_dev *dev) { }
977da073 1995static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
05cca6e5 1996static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1997{ return -EBUSY; }
817f9916
AS		 1998static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1999 struct module *owner,
2000 const char *mod_name)
2ee546c4 2001{ return 0; }
05cca6e5 2002static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 2003{ return 0; }
2004static inline void pci_unregister_driver(struct pci_driver *drv) { }
f646c2a0 2005static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 2006{ return 0; }
05cca6e5
GKH		 2007static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
2008 int cap)
2ee546c4 2009{ return 0; }
05cca6e5 2010static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 2011{ return 0; }
05cca6e5 2012
70c0923b
JK		 2013static inline u64 pci_get_dsn(struct pci_dev *dev)
2014{ return 0; }
2015
1da177e4 2016/* Power management related routines */
2ee546c4
BH		 2017static inline int pci_save_state(struct pci_dev *dev) { return 0; }
2018static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 2019static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 2020{ return 0; }
3449248c 2021static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 2022{ return 0; }
05cca6e5
GKH		 2023static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2024 pm_message_t state)
2ee546c4 2025{ return PCI_D0; }
05cca6e5
GKH		 2026static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2027 int enable)
2ee546c4 2028{ return 0; }
48a92a81 2029
afd29f90
MW		 2030static inline struct resource *pci_find_resource(struct pci_dev *dev,
2031 struct resource *res)
2032{ return NULL; }
05cca6e5 2033static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 2034{ return -EIO; }
2035static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 2036
00dcc7cf
RH		 2037static inline int pci_register_io_range(struct fwnode_handle *fwnode,
2038 phys_addr_t addr, resource_size_t size)
2039{ return -EINVAL; }
2040
c5076cfe
TN		 2041static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2042
d80d0217
RD		 2043static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2044{ return NULL; }
d80d0217
RD		 2045static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2046 unsigned int devfn)
2047{ return NULL; }
7912af5c
RD		 2048static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2049 unsigned int bus, unsigned int devfn)
2050{ return NULL; }
d80d0217 2051
2ee546c4
BH		 2052static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
2053static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 2054
fb8a0d9d
WM		 2055#define dev_is_pci(d) (false)
2056#define dev_is_pf(d) (false)
fe594932
GU		 2057static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2058{ return false; }
80db6f08
NC		 2059static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2060 struct device_node *node,
2061 const u32 *intspec,
2062 unsigned int intsize,
2063 unsigned long *out_hwirq,
2064 unsigned int *out_type)
2065{ return -EINVAL; }
9c212009
LR		 2066
2067static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2068 struct pci_dev *dev)
2069{ return NULL; }
b9ae16d8 2070static inline bool pci_ats_disabled(void) { return true; }
0d8006dd
HX		 2071
2072static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2073{
2074 return -EINVAL;
2075}
2076
2077static inline int
2078pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2079 unsigned int max_vecs, unsigned int flags,
2080 struct irq_affinity *aff_desc)
2081{
2082 return -ENOSPC;
2083}
0d8006dd
HX		 2084static inline int
2085pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2086 unsigned int max_vecs, unsigned int flags)
2087{
5c0997dc 2088 return -ENOSPC;
0d8006dd 2089}
5c0997dc 2090#endif /* CONFIG_PCI */
0d8006dd 2091
4352dfd5
GKH		 2092/* Include architecture-dependent settings and functions */
2093
2094#include <asm/pci.h>
1da177e4 2095
0ad722f1 2096/*
f7195824
DW		 2097 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2098 * is expected to be an offset within that region.
2099 *
f7195824
DW		 2100 */
2101int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2102 struct vm_area_struct *vma,
2103 enum pci_mmap_state mmap_state, int write_combine);
11df1954 2104
ae749c7a
DW		 2105#ifndef arch_can_pci_mmap_wc
2106#define arch_can_pci_mmap_wc() 0
2107#endif
2bea36fd 2108
e854d8b2
DW		 2109#ifndef arch_can_pci_mmap_io
2110#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 2111#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2112#else
2113int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 2114#endif
ae749c7a 2115
92016ba5
JO		 2116#ifndef pci_root_bus_fwnode
2117#define pci_root_bus_fwnode(bus) NULL
2118#endif
2119
0aa0f5d1
BH		 2120/*
2121 * These helpers provide future and backwards compatibility
2122 * for accessing popular PCI BAR info
2123 */
144d204d
AS		 2124#define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2125#define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2126#define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2127#define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2128#define pci_resource_len(dev,bar) \
2129 (pci_resource_end((dev), (bar)) ? \
2130 resource_size(pci_resource_n((dev), (bar))) : 0)
1da177e4 2131
09cc9006
MW		 2132#define __pci_dev_for_each_res0(dev, res, ...) \
2133 for (unsigned int __b = 0; \
2134 res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2135 __b++)
2136
2137#define __pci_dev_for_each_res1(dev, res, __b) \
2138 for (__b = 0; \
2139 res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2140 __b++)
2141
2142#define pci_dev_for_each_resource(dev, res, ...) \
2143 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2144 (dev, res, __VA_ARGS__)
1da177e4 2145
0aa0f5d1
BH		 2146/*
2147 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 2148 * driver-specific data. They are really just a wrapper around
2149 * the generic device structure functions of these calls.
2150 */
05cca6e5 2151static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 2152{
2153 return dev_get_drvdata(&pdev->dev);
2154}
2155
05cca6e5 2156static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 2157{
2158 dev_set_drvdata(&pdev->dev, data);
2159}
2160
2fc90f61 2161static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 2162{
c6c4f070 2163 return dev_name(&pdev->dev);
1da177e4
LT		 2164}
2165
8221a013
BH		 2166void pci_resource_to_user(const struct pci_dev *dev, int bar,
2167 const struct resource *rsrc,
2168 resource_size_t *start, resource_size_t *end);
2311b1f2 2169
1da177e4 2170/*
0aa0f5d1
BH		 2171 * The world is not perfect and supplies us with broken PCI devices.
2172 * For at least a part of these bugs we need a work-around, so both
2173 * generic (drivers/pci/quirks.c) and per-architecture code can define
2174 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 2175 */
2176
2177struct pci_fixup {
0aa0f5d1
BH		 2178 u16 vendor; /* Or PCI_ANY_ID */
2179 u16 device; /* Or PCI_ANY_ID */
2180 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 2181 unsigned int class_shift; /* should be 0, 8, 16 */
c9d8b55f
AB		 2182#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2183 int hook_offset;
2184#else
1da177e4 2185 void (*hook)(struct pci_dev *dev);
c9d8b55f 2186#endif
1da177e4
LT		 2187};
2188
2189enum pci_fixup_pass {
2190 pci_fixup_early, /* Before probing BARs */
2191 pci_fixup_header, /* After reading configuration header */
2192 pci_fixup_final, /* Final phase of device fixups */
2193 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 2194 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 2195 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 2196 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 2197 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 2198};
2199
c9d8b55f 2200#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
09a4e4d9 2201#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
c9d8b55f
AB		 2202 class_shift, hook) \
2203 __ADDRESSABLE(hook) \
2204 asm(".section " #sec ", \"a\" \n" \
2205 ".balign 16 \n" \
2206 ".short " #vendor ", " #device " \n" \
2207 ".long " #class ", " #class_shift " \n" \
2208 ".long " #hook " - . \n" \
2209 ".previous \n");
09a4e4d9
ST		 2210
2211/*
2212 * Clang's LTO may rename static functions in C, but has no way to
2213 * handle such renamings when referenced from inline asm. To work
2214 * around this, create global C stubs for these cases.
2215 */
2216#ifdef CONFIG_LTO_CLANG
2217#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2218 class_shift, hook, stub) \
5659b598
ST		 2219 void stub(struct pci_dev *dev); \
2220 void stub(struct pci_dev *dev) \
09a4e4d9
ST		 2221 { \
2222 hook(dev); \
2223 } \
2224 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2225 class_shift, stub)
2226#else
2227#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2228 class_shift, hook, stub) \
2229 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2230 class_shift, hook)
2231#endif
2232
c9d8b55f
AB		 2233#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2234 class_shift, hook) \
2235 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
09a4e4d9 2236 class_shift, hook, __UNIQUE_ID(hook))
c9d8b55f 2237#else
1da177e4 2238/* Anonymous variables would be nice... */
f4ca5c6a
YL		 2239#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2240 class_shift, hook) \
ecf61c78 2241 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 2242 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2243 = { vendor, device, class, class_shift, hook };
c9d8b55f 2244#endif
f4ca5c6a
YL		 2245
2246#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2247 class_shift, hook) \
2248 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2249 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2250#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2251 class_shift, hook) \
2252 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2253 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2254#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2255 class_shift, hook) \
2256 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2257 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2258#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2259 class_shift, hook) \
2260 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2261 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2262#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2263 class_shift, hook) \
2264 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2265 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2266#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2267 class_shift, hook) \
2268 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2269 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2270#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2271 class_shift, hook) \
2272 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2273 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 2274#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2275 class_shift, hook) \
2276 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2277 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 2278
1da177e4
LT		 2279#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2280 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2281 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2282#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2283 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2284 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2285#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2286 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2287 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2288#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2289 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2290 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 2291#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2292 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2293 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2294#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2295 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2296 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2297#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2298 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2299 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 2300#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2301 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2302 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 2303
93177a74 2304#ifdef CONFIG_PCI_QUIRKS
1da177e4 2305void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 2306#else
2307static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 2308 struct pci_dev *dev) { }
93177a74 2309#endif
1da177e4 2310
05cca6e5 2311void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 2312void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 2313void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 2314int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2315int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 2316 const char *name);
fb7ebfe4 2317void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 2318
1da177e4 2319extern int pci_pci_problems;
236561e5 2320#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 2321#define PCIPCI_TRITON 2
2322#define PCIPCI_NATOMA 4
2323#define PCIPCI_VIAETBF 8
2324#define PCIPCI_VSFX 16
236561e5
AC		 2325#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2326#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 2327
4516a618
AN		 2328extern unsigned long pci_cardbus_io_size;
2329extern unsigned long pci_cardbus_mem_size;
15856ad5 2330extern u8 pci_dfl_cache_line_size;
ac1aa47b 2331extern u8 pci_cache_line_size;
4516a618 2332
f7625980 2333/* Architecture-specific versions may override these (weak) */
19792a08 2334void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 2335void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 2336int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2337 enum pcie_reset_state state);
06dc660e 2338int pcibios_device_add(struct pci_dev *dev);
6ae32c53 2339void pcibios_release_device(struct pci_dev *dev);
5d32a665 2340#ifdef CONFIG_PCI
a43ae58c 2341void pcibios_penalize_isa_irq(int irq, int active);
5d32a665
SK		 2342#else
2343static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2344#endif
890e4847
JL		 2345int pcibios_alloc_irq(struct pci_dev *dev);
2346void pcibios_free_irq(struct pci_dev *dev);
619e6f34 2347resource_size_t pcibios_default_alignment(void);
575e3348 2348
87382ead
AB		 2349#if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2350extern int pci_create_resource_files(struct pci_dev *dev);
2351extern void pci_remove_resource_files(struct pci_dev *dev);
2352#endif
2353
935c760e 2354#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 2355void __init pci_mmcfg_early_init(void);
2356void __init pci_mmcfg_late_init(void);
7752d5cf 2357#else
bb63b421 2358static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 2359static inline void pci_mmcfg_late_init(void) { }
2360#endif
2361
642c92da 2362int pci_ext_cfg_avail(void);
0ef5f8f6 2363
1684f5dd 2364void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 2365void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 2366
dd7cc44d 2367#ifdef CONFIG_PCI_IOV
b07579c0
WY		 2368int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2369int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
21ca9fb6 2370int pci_iov_vf_id(struct pci_dev *dev);
a7e9f240 2371void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
f39d5b72
BH		 2372int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2373void pci_disable_sriov(struct pci_dev *dev);
a1ceea67
NS		 2374
2375int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
753f6124
JS		 2376int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2377void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 2378int pci_num_vf(struct pci_dev *dev);
5a8eb242 2379int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 2380int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2381int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 2382int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 2383resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 2384void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 2385
2386/* Arch may override these (weak) */
2387int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2388int pcibios_sriov_disable(struct pci_dev *pdev);
2389resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 2390#else
b07579c0
WY		 2391static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2392{
2393 return -ENOSYS;
2394}
2395static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2396{
2397 return -ENOSYS;
2398}
21ca9fb6
JG		 2399
2400static inline int pci_iov_vf_id(struct pci_dev *dev)
2401{
2402 return -ENOSYS;
2403}
2404
a7e9f240
JG		 2405static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2406 struct pci_driver *pf_driver)
2407{
2408 return ERR_PTR(-EINVAL);
2409}
2410
dd7cc44d 2411static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2412{ return -ENODEV; }
a1ceea67
NS		 2413
2414static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2415 struct pci_dev *virtfn, int id)
2416{
2417 return -ENODEV;
2418}
753f6124 2419static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2420{
2421 return -ENOSYS;
2422}
2423static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2424 int id) { }
2ee546c4 2425static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2426static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2427static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2428{ return 0; }
bff73156 2429static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2430{ return 0; }
bff73156 2431static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2432{ return 0; }
8effc395 2433#define pci_sriov_configure_simple NULL
0e6c9122
WY		 2434static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2435{ return 0; }
608c0d88 2436static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 2437#endif
2438
c825bc94 2439#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2440void pci_hp_create_module_link(struct pci_slot *pci_slot);
2441void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2442#endif
2443
d7b7e605
KK		 2444/**
2445 * pci_pcie_cap - get the saved PCIe capability offset
2446 * @dev: PCI device
2447 *
2448 * PCIe capability offset is calculated at PCI device initialization
2449 * time and saved in the data structure. This function returns saved
2450 * PCIe capability offset. Using this instead of pci_find_capability()
2451 * reduces unnecessary search in the PCI configuration space. If you
2452 * need to calculate PCIe capability offset from raw device for some
2453 * reasons, please use pci_find_capability() instead.
2454 */
2455static inline int pci_pcie_cap(struct pci_dev *dev)
2456{
2457 return dev->pcie_cap;
2458}
2459
7eb776c4
KK		 2460/**
2461 * pci_is_pcie - check if the PCI device is PCI Express capable
2462 * @dev: PCI device
2463 *
a895c28a 2464 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2465 */
2466static inline bool pci_is_pcie(struct pci_dev *dev)
2467{
a895c28a 2468 return pci_pcie_cap(dev);
7eb776c4
KK		 2469}
2470
7c9c003c
MS		 2471/**
2472 * pcie_caps_reg - get the PCIe Capabilities Register
2473 * @dev: PCI device
2474 */
2475static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2476{
2477 return dev->pcie_flags_reg;
2478}
2479
786e2288
YW		 2480/**
2481 * pci_pcie_type - get the PCIe device/port type
2482 * @dev: PCI device
2483 */
2484static inline int pci_pcie_type(const struct pci_dev *dev)
2485{
1c531d82 2486 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2487}
2488
6ae72bfa
YY		 2489/**
2490 * pcie_find_root_port - Get the PCIe root port device
2491 * @dev: PCI device
2492 *
2493 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2494 * for a given PCI/PCIe Device.
2495 */
e784930b
JT		 2496static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2497{
5396956c
MW		 2498 while (dev) {
2499 if (pci_is_pcie(dev) &&
2500 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2501 return dev;
2502 dev = pci_upstream_bridge(dev);
e784930b 2503 }
6ae72bfa 2504
e784930b
JT		 2505 return NULL;
2506}
2507
5d990b62 2508void pci_request_acs(void);
ad805758
AW		 2509bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2510bool pci_acs_path_enabled(struct pci_dev *start,
2511 struct pci_dev *end, u16 acs_flags);
430a2368 2512int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2513
7ad506fa 2514#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2515#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2516
2517/* Large Resource Data Type Tag Item Names */
2518#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2519#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2520#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2521
2522#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2523#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2524#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2525
4067a854 2526#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
16efafa3 2527#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
4067a854
MC		 2528#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2529#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2530#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2531
a2ce7662 2532/**
76f3c032
HK		 2533 * pci_vpd_alloc - Allocate buffer and read VPD into it
2534 * @dev: PCI device
2535 * @size: pointer to field where VPD length is returned
9eb45d5c 2536 *
76f3c032 2537 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
9eb45d5c 2538 */
76f3c032 2539void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
9eb45d5c 2540
e1d5bdab 2541/**
acfbb1b8
HK		 2542 * pci_vpd_find_id_string - Locate id string in VPD
2543 * @buf: Pointer to buffered VPD data
2544 * @len: The length of the buffer area in which to search
2545 * @size: Pointer to field where length of id string is returned
e1d5bdab 2546 *
acfbb1b8 2547 * Returns the index of the id string or -ENOENT if not found.
e1d5bdab 2548 */
acfbb1b8 2549int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
e1d5bdab 2550
b55ac1b2 2551/**
9e515c9f
HK		 2552 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2553 * @buf: Pointer to buffered VPD data
2554 * @len: The length of the buffer area in which to search
2555 * @kw: The keyword to search for
2556 * @size: Pointer to field where length of found keyword data is returned
b55ac1b2 2557 *
9e515c9f
HK		 2558 * Returns the index of the information field keyword data or -ENOENT if
2559 * not found.
b55ac1b2 2560 */
9e515c9f
HK		 2561int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2562 const char *kw, unsigned int *size);
b55ac1b2 2563
4067a854 2564/**
6107e5cb
HK		 2565 * pci_vpd_check_csum - Check VPD checksum
2566 * @buf: Pointer to buffered VPD data
2567 * @len: VPD size
4067a854 2568 *
6107e5cb 2569 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
4067a854 2570 */
6107e5cb 2571int pci_vpd_check_csum(const void *buf, unsigned int len);
4067a854 2572
98d9f30c
BH		 2573/* PCI <-> OF binding helpers */
2574#ifdef CONFIG_OF
2575struct device_node;
b165e2b6 2576struct irq_domain;
b165e2b6 2577struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
85aabbd7 2578bool pci_host_of_has_msi_map(struct device *dev);
98d9f30c
BH		 2579
2580/* Arch may override this (weak) */
723ec4d0 2581struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2582
0aa0f5d1 2583#else /* CONFIG_OF */
b165e2b6
MZ		 2584static inline struct irq_domain *
2585pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
85aabbd7 2586static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
98d9f30c
BH		 2587#endif /* CONFIG_OF */
2588
ad32eb2d
BM		 2589static inline struct device_node *
2590pci_device_to_OF_node(const struct pci_dev *pdev)
2591{
2592 return pdev ? pdev->dev.of_node : NULL;
2593}
2594
2595static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2596{
2597 return bus ? bus->dev.of_node : NULL;
2598}
2599
471036b2
SS		 2600#ifdef CONFIG_ACPI
2601struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2602
2603void
2604pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
52525b7a 2605bool pci_pr3_present(struct pci_dev *pdev);
471036b2
SS		 2606#else
2607static inline struct irq_domain *
2608pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
46b4bff6 2609static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
471036b2
SS		 2610#endif
2611
eb740b5f
GS		 2612#ifdef CONFIG_EEH
2613static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2614{
2615 return pdev->dev.archdata.edev;
2616}
2617#endif
2618
09298542 2619void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
338c3149 2620bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2621int pci_for_each_dma_alias(struct pci_dev *pdev,
2622 int (*fn)(struct pci_dev *pdev,
2623 u16 alias, void *data), void *data);
2624
0aa0f5d1 2625/* Helper functions for operation of device flag */
ce052984
EZ		 2626static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2627{
2628 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2629}
2630static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2631{
2632 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2633}
2634static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2635{
2636 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2637}
19bdb6e4
AW		 2638
2639/**
2640 * pci_ari_enabled - query ARI forwarding status
2641 * @bus: the PCI bus
2642 *
2643 * Returns true if ARI forwarding is enabled.
2644 */
2645static inline bool pci_ari_enabled(struct pci_bus *bus)
2646{
2647 return bus->self && bus->self->ari_enabled;
2648}
bc4b024a 2649
8531e283
LW		 2650/**
2651 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2652 * @pdev: PCI device to check
2653 *
2654 * Walk upwards from @pdev and check for each encountered bridge if it's part
2655 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2656 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2657 */
2658static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2659{
2660 struct pci_dev *parent = pdev;
2661
2662 if (pdev->is_thunderbolt)
2663 return true;
2664
2665 while ((parent = pci_upstream_bridge(parent)))
2666 if (parent->is_thunderbolt)
2667 return true;
2668
2669 return false;
2670}
2671
2e28bc84 2672#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2673void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2674#endif
856e1eb9 2675
79687789 2676#include <linux/dma-mapping.h>
bc4b024a 2677
7506dc79
FL		 2678#define pci_printk(level, pdev, fmt, arg...) \
2679 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2680
2681#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2682#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2683#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2684#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2685#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
27829479 2686#define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
7506dc79
FL		 2687#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2688#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2689#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2690
a88a7b3e
BH		 2691#define pci_notice_ratelimited(pdev, fmt, arg...) \
2692 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2693
7f1c62c4
KW		 2694#define pci_info_ratelimited(pdev, fmt, arg...) \
2695 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2696
12bcae44
BH		 2697#define pci_WARN(pdev, condition, fmt, arg...) \
2698 WARN(condition, "%s %s: " fmt, \
2699 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2700
2701#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2702 WARN_ONCE(condition, "%s %s: " fmt, \
2703 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2704
1da177e4 2705#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)