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PCI: Unify PCI and normal DMA direction definitions
[linux-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
1da177e4
LT		 17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
1da177e4 20
778382e0
DW		 21#include <linux/mod_devicetable.h>
22
1da177e4 23#include <linux/types.h>
98db6f19 24#include <linux/init.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/list.h>
4a7fb636 27#include <linux/compiler.h>
1da177e4 28#include <linux/errno.h>
f46753c5 29#include <linux/kobject.h>
60063497 30#include <linux/atomic.h>
1da177e4 31#include <linux/device.h>
704e8953 32#include <linux/interrupt.h>
1388cc96 33#include <linux/io.h>
14d76b68 34#include <linux/resource_ext.h>
607ca46e 35#include <uapi/linux/pci.h>
1da177e4 36
7e7a43c3
AB		 37#include <linux/pci_ids.h>
38
85467136
SK		 39/*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
f7625980
BH		 46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 48 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 49 * the following kernel-only defines are being added here.
85467136 50 */
0aa0f5d1 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
f46753c5
AC		 55/* pci_slot represents a physical slot */
56struct pci_slot {
0aa0f5d1
BH		 57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
f46753c5
AC		 62};
63
0ad772ec
AC		 64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
1da177e4
LT		 69/* File state for mmap()s on /proc/bus/pci/X/Y */
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
0aa0f5d1 75/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 76enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
0aa0f5d1 84 /* Device-specific resources */
d1b054da
YZ		 85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
0aa0f5d1 90 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
0aa0f5d1 97 /* Total resources associated with a PCI device */
fde09c6d
YZ		 98 PCI_NUM_RESOURCES,
99
0aa0f5d1 100 /* Preserve this for compatibility */
cda57bf9 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 102};
1da177e4 103
b352baf1
PB		 104/**
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
111 *
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
114 */
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123/* The number of legacy PCI INTx interrupts */
124#define PCI_NUM_INTX 4
125
224abb67
BH		 126/*
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
129 */
1da177e4
LT		 130typedef int __bitwise pci_power_t;
131
4352dfd5
GKH		 132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 137#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 139
00240c38
AS		 140/* Remember to update this when the list above changes! */
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
9661e783 145 return pci_power_names[1 + (__force int) state];
00240c38
AS		 146}
147
448bd857
HY		 148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
aa8c6c93 152
0aa0f5d1
BH		 153/**
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
392a1ce7 157 */
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
f7bdd12d
BK		 171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
f7625980 177 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
f7625980 180 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
ba698ad4
DM		 184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
0aa0f5d1 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 188 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 190 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 202 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 206 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 208};
209
e1d3a908
SA		 210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
6e325a62
MT		 215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
032c3d86
JD		 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 221};
222
0aa0f5d1 223/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
0aa0f5d1 230 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
0aa0f5d1 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 234};
235
536c8cb4
MW		 236/* Based on the PCI Hotplug Spec, but some values are made up by us */
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
536c8cb4
MW		 254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 259 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 260 PCIE_SPEED_16_0GT = 0x17,
536c8cb4
MW		 261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
24a4742f 264struct pci_cap_saved_data {
0aa0f5d1
BH		 265 u16 cap_nr;
266 bool cap_extended;
267 unsigned int size;
268 u32 data[0];
41017f0c
SL		 269};
270
24a4742f 271struct pci_cap_saved_state {
0aa0f5d1
BH		 272 struct hlist_node next;
273 struct pci_cap_saved_data cap;
24a4742f
AW		 274};
275
402723ad 276struct irq_affinity;
7d715a6c 277struct pcie_link_state;
ee69439c 278struct pci_vpd;
d1b054da 279struct pci_sriov;
302b4215 280struct pci_ats;
ee69439c 281
0aa0f5d1 282/* The pci_dev structure describes PCI devices */
1da177e4 283struct pci_dev {
0aa0f5d1
BH		 284 struct list_head bus_list; /* Node in per-bus list */
285 struct pci_bus *bus; /* Bus this device is on */
286 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 287
0aa0f5d1
BH		 288 void *sysdata; /* Hook for sys-specific extension */
289 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 290 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 291
0aa0f5d1 292 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 293 unsigned short vendor;
294 unsigned short device;
295 unsigned short subsystem_vendor;
296 unsigned short subsystem_device;
297 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 298 u8 revision; /* PCI revision, low byte of class word */
1da177e4 299 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 300#ifdef CONFIG_PCIEAER
301 u16 aer_cap; /* AER capability offset */
302#endif
f7625980 303 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 304 u8 msi_cap; /* MSI capability offset */
305 u8 msix_cap; /* MSI-X capability offset */
f7625980 306 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 307 u8 rom_base_reg; /* Config register controlling ROM */
308 u8 pin; /* Interrupt pin this device uses */
309 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
310 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 311
0aa0f5d1 312 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 313 u64 dma_mask; /* Mask of the bits of bus address this
314 device implements. Normally this is
315 0xffffffff. You only need to change
316 this if your device has broken DMA
317 or supports 64-bit transfers. */
318
4d57cdfa
FT		 319 struct device_dma_parameters dma_parms;
320
0aa0f5d1
BH		 321 pci_power_t current_state; /* Current operating state. In ACPI,
322 this is D0-D3, D0 being fully
323 functional, and D3 being off. */
703860ed 324 u8 pm_cap; /* PM capability offset */
337001b6
RW		 325 unsigned int pme_support:5; /* Bitmask of states from which PME#
326 can be generated */
379021d5 327 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 328 unsigned int d1_support:1; /* Low power state D1 is supported */
329 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 330 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
331 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 332 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 333 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 334 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
335 decoding during BAR sizing */
e80bb09d 336 unsigned int wakeup_prepared:1;
0aa0f5d1 337 unsigned int runtime_d3cold:1; /* Whether go through runtime
448bd857
HY		 338 D3cold, not set for devices
339 powered on/off by the
340 corresponding bridge */
b440bde7 341 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 342 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
343 controlled exclusively by
344 user sysfs */
1ae861e6 345 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 346 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 347
7d715a6c 348#ifdef CONFIG_PCIEASPM
f7625980 349 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 350 unsigned int ltr_path:1; /* Latency Tolerance Reporting
351 supported from root to here */
7d715a6c
SL		 352#endif
353
0aa0f5d1
BH		 354 pci_channel_state_t error_state; /* Current connectivity state */
355 struct device dev; /* Generic device interface */
1da177e4 356
0aa0f5d1 357 int cfg_size; /* Size of config space */
1da177e4
LT		 358
359 /*
360 * Instead of touching interrupt line and base address registers
361 * directly, use the values stored here. They might be different!
362 */
363 unsigned int irq;
364 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
365
0aa0f5d1
BH		 366 bool match_driver; /* Skip attaching driver */
367
368 unsigned int transparent:1; /* Subtractive decode bridge */
369 unsigned int multifunction:1; /* Multi-function device */
370
8a1bc901 371 unsigned int is_added:1;
0aa0f5d1
BH		 372 unsigned int is_busmaster:1; /* Is busmaster */
373 unsigned int no_msi:1; /* May not use MSI */
374 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
375 unsigned int block_cfg_access:1; /* Config space access blocked */
376 unsigned int broken_parity_status:1; /* Generates false positive parity */
377 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 378 unsigned int msi_enabled:1;
99dc804d 379 unsigned int msix_enabled:1;
0aa0f5d1
BH		 380 unsigned int ari_enabled:1; /* ARI forwarding */
381 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 382 unsigned int pasid_enabled:1; /* Process Address Space ID */
383 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 384 unsigned int is_managed:1;
0aa0f5d1 385 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 386 unsigned int state_saved:1;
d1b054da 387 unsigned int is_physfn:1;
dd7cc44d 388 unsigned int is_virtfn:1;
711d5779 389 unsigned int reset_fn:1;
0aa0f5d1
BH		 390 unsigned int is_hotplug_bridge:1;
391 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
392 unsigned int __aer_firmware_first_valid:1;
affb72c3 393 unsigned int __aer_firmware_first:1;
0aa0f5d1
BH		 394 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
395 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 396 unsigned int irq_managed:1;
d0751b98 397 unsigned int has_secondary_link:1;
0aa0f5d1
BH		 398 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
399 unsigned int is_probed:1; /* Device probing in progress */
ba698ad4 400 pci_dev_flags_t dev_flags;
bae94d02 401 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 402
0aa0f5d1 403 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 404 struct hlist_head saved_cap_space;
0aa0f5d1
BH		 405 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
406 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 407 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 408 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 409
d22b3621
BH		 410#ifdef CONFIG_HOTPLUG_PCI_PCIE
411 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
412#endif
9bb04a0c
JY		 413#ifdef CONFIG_PCIE_PTM
414 unsigned int ptm_root:1;
415 unsigned int ptm_enabled:1;
8b2ec318 416 u8 ptm_granularity;
9bb04a0c 417#endif
ded86d8d 418#ifdef CONFIG_PCI_MSI
1c51b50c 419 const struct attribute_group **msi_irq_groups;
ded86d8d 420#endif
94e61088 421 struct pci_vpd *vpd;
466b3ddf 422#ifdef CONFIG_PCI_ATS
dd7cc44d 423 union {
0aa0f5d1
BH		 424 struct pci_sriov *sriov; /* PF: SR-IOV info */
425 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 426 };
67930995
BH		 427 u16 ats_cap; /* ATS Capability offset */
428 u8 ats_stu; /* ATS Smallest Translation Unit */
0aa0f5d1 429 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
4ebeb1ec
CT		 430#endif
431#ifdef CONFIG_PCI_PRI
432 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
433#endif
434#ifdef CONFIG_PCI_PASID
435 u16 pasid_features;
d1b054da 436#endif
0aa0f5d1
BH		 437 phys_addr_t rom; /* Physical address if not from BAR */
438 size_t romlen; /* Length if not from BAR */
439 char *driver_override; /* Driver name to force a match */
89ee9f76 440
0aa0f5d1 441 unsigned long priv_flags; /* Private flags for the PCI driver */
1da177e4
LT		 442};
443
dda56549
Y		 444static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
445{
446#ifdef CONFIG_PCI_IOV
447 if (dev->is_virtfn)
448 dev = dev->physfn;
449#endif
dda56549
Y		 450 return dev;
451}
452
3c6e6ae7 453struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 454
1da177e4
LT		 455#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
456#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
457
a7369f1f
LV		 458static inline int pci_channel_offline(struct pci_dev *pdev)
459{
460 return (pdev->error_state != pci_channel_io_normal);
461}
462
5a21d70d 463struct pci_host_bridge {
0aa0f5d1
BH		 464 struct device dev;
465 struct pci_bus *bus; /* Root bus */
466 struct pci_ops *ops;
467 void *sysdata;
468 int busnr;
14d76b68 469 struct list_head windows; /* resource_entry */
0aa0f5d1 470 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 471 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 472 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 473 void *release_data;
37d6a0a6 474 struct msi_controller *msi;
0aa0f5d1
BH		 475 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
476 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48 477 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 478 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 479 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 480 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 481 unsigned int native_ltr:1; /* OS may use PCIe LTR */
7c7a0e94
GP		 482 /* Resource alignment requirements */
483 resource_size_t (*align_resource)(struct pci_dev *dev,
484 const struct resource *res,
485 resource_size_t start,
486 resource_size_t size,
487 resource_size_t align);
0aa0f5d1 488 unsigned long private[0] ____cacheline_aligned;
5a21d70d 489};
41017f0c 490
7b543663 491#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 492
59094065
TR		 493static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
494{
495 return (void *)bridge->private;
496}
497
498static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
499{
500 return container_of(priv, struct pci_host_bridge, private);
501}
502
a52d1443 503struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 504struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
505 size_t priv);
dff79b91 506void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 507struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
508
4fa2649a 509void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 510 void (*release_fn)(struct pci_host_bridge *),
511 void *release_data);
7b543663 512
6c0cc950
RW		 513int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
514
2fe2abf8
BH		 515/*
516 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
517 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
518 * buses below host bridges or subtractive decode bridges) go in the list.
519 * Use pci_bus_for_each_resource() to iterate through all the resources.
520 */
521
522/*
523 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
524 * and there's no way to program the bridge with the details of the window.
525 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
526 * decode bit set, because they are explicit and can be programmed with _SRS.
527 */
528#define PCI_SUBTRACTIVE_DECODE 0x1
529
530struct pci_bus_resource {
0aa0f5d1
BH		 531 struct list_head list;
532 struct resource *res;
533 unsigned int flags;
2fe2abf8 534};
4352dfd5
GKH		 535
536#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 537
538struct pci_bus {
0aa0f5d1
BH		 539 struct list_head node; /* Node in list of buses */
540 struct pci_bus *parent; /* Parent bus this bridge is on */
541 struct list_head children; /* List of child buses */
542 struct list_head devices; /* List of devices on this bus */
543 struct pci_dev *self; /* Bridge device as seen by parent */
544 struct list_head slots; /* List of slots on this bus;
67546762 545 protected by pci_slot_mutex */
2fe2abf8 546 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 547 struct list_head resources; /* Address space routed to this bus */
548 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 549
0aa0f5d1 550 struct pci_ops *ops; /* Configuration access functions */
c2791b80 551 struct msi_controller *msi; /* MSI controller */
0aa0f5d1
BH		 552 void *sysdata; /* Hook for sys-specific extension */
553 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 554
0aa0f5d1
BH		 555 unsigned char number; /* Bus number */
556 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 557 unsigned char max_bus_speed; /* enum pci_bus_speed */
558 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 559#ifdef CONFIG_PCI_DOMAINS_GENERIC
560 int domain_nr;
561#endif
1da177e4
LT		 562
563 char name[48];
564
0aa0f5d1
BH		 565 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
566 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 567 struct device *bridge;
fd7d1ced 568 struct device dev;
0aa0f5d1
BH		 569 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
570 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 571 unsigned int is_added:1;
1da177e4
LT		 572};
573
fd7d1ced 574#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 575
79af72d7 576/*
f7625980 577 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 578 * false otherwise
77a0dfcd
BH		 579 *
580 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
581 * This is incorrect because "virtual" buses added for SR-IOV (via
582 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 583 */
584static inline bool pci_is_root_bus(struct pci_bus *pbus)
585{
586 return !(pbus->parent);
587}
588
1c86438c
YW		 589/**
590 * pci_is_bridge - check if the PCI device is a bridge
591 * @dev: PCI device
592 *
593 * Return true if the PCI device is bridge whether it has subordinate
594 * or not.
595 */
596static inline bool pci_is_bridge(struct pci_dev *dev)
597{
598 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
599 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
600}
601
24a0c654
AS		 602#define for_each_pci_bridge(dev, bus) \
603 list_for_each_entry(dev, &bus->devices, bus_list) \
604 if (!pci_is_bridge(dev)) {} else
605
c6bde215
BH		 606static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
607{
608 dev = pci_physfn(dev);
609 if (pci_is_root_bus(dev->bus))
610 return NULL;
611
612 return dev->bus->self;
613}
614
6675a601
MK		 615struct device *pci_get_host_bridge_device(struct pci_dev *dev);
616void pci_put_host_bridge_device(struct device *dev);
617
16cf0ebc
RW		 618#ifdef CONFIG_PCI_MSI
619static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
620{
621 return pci_dev->msi_enabled || pci_dev->msix_enabled;
622}
623#else
624static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
625#endif
626
0aa0f5d1 627/* Error values that may be returned by PCI functions */
1da177e4
LT		 628#define PCIBIOS_SUCCESSFUL 0x00
629#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
630#define PCIBIOS_BAD_VENDOR_ID 0x83
631#define PCIBIOS_DEVICE_NOT_FOUND 0x86
632#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
633#define PCIBIOS_SET_FAILED 0x88
634#define PCIBIOS_BUFFER_TOO_SMALL 0x89
635
0aa0f5d1 636/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 637static inline int pcibios_err_to_errno(int err)
638{
639 if (err <= PCIBIOS_SUCCESSFUL)
640 return err; /* Assume already errno */
641
642 switch (err) {
643 case PCIBIOS_FUNC_NOT_SUPPORTED:
644 return -ENOENT;
645 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 646 return -ENOTTY;
a6961651
AW		 647 case PCIBIOS_DEVICE_NOT_FOUND:
648 return -ENODEV;
649 case PCIBIOS_BAD_REGISTER_NUMBER:
650 return -EFAULT;
651 case PCIBIOS_SET_FAILED:
652 return -EIO;
653 case PCIBIOS_BUFFER_TOO_SMALL:
654 return -ENOSPC;
655 }
656
d97ffe23 657 return -ERANGE;
a6961651
AW		 658}
659
1da177e4
LT		 660/* Low-level architecture-dependent routines */
661
662struct pci_ops {
057bd2e0
TR		 663 int (*add_bus)(struct pci_bus *bus);
664 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 665 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 666 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
667 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
668};
669
b6ce068a
MW		 670/*
671 * ACPI needs to be able to access PCI config space before we've done a
672 * PCI bus scan and created pci_bus structures.
673 */
f39d5b72
BH		 674int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
675 int reg, int len, u32 *val);
676int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
677 int reg, int len, u32 val);
1da177e4 678
8e639079 679#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 680typedef u64 pci_bus_addr_t;
681#else
682typedef u32 pci_bus_addr_t;
683#endif
684
1da177e4 685struct pci_bus_region {
0aa0f5d1
BH		 686 pci_bus_addr_t start;
687 pci_bus_addr_t end;
1da177e4
LT		 688};
689
690struct pci_dynids {
0aa0f5d1
BH		 691 spinlock_t lock; /* Protects list, index */
692 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 693};
694
f7625980
BH		 695
696/*
697 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
698 * a set of callbacks in struct pci_error_handlers, that device driver
699 * will be notified of PCI bus errors, and will be driven to recovery
700 * when an error occurs.
392a1ce7 701 */
702
703typedef unsigned int __bitwise pci_ers_result_t;
704
705enum pci_ers_result {
0aa0f5d1 706 /* No result/none/not supported in device driver */
392a1ce7 707 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
708
709 /* Device driver can recover without slot reset */
710 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
711
0aa0f5d1 712 /* Device driver wants slot to be reset */
392a1ce7 713 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
714
715 /* Device has completely failed, is unrecoverable */
716 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
717
718 /* Device driver is fully recovered and operational */
719 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 720
721 /* No AER capabilities registered for the driver */
722 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 723};
724
725/* PCI bus error event callbacks */
05cca6e5 726struct pci_error_handlers {
392a1ce7 727 /* PCI bus error detected on this device */
728 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 729 enum pci_channel_state error);
392a1ce7 730
731 /* MMIO has been re-enabled, but not DMA */
732 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
733
392a1ce7 734 /* PCI slot has been reset */
735 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
736
3ebe7f9f 737 /* PCI function reset prepare or completed */
775755ed
CH		 738 void (*reset_prepare)(struct pci_dev *dev);
739 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 740
392a1ce7 741 /* Device driver may resume normal operations */
742 void (*resume)(struct pci_dev *dev);
743};
744
392a1ce7 745
1da177e4
LT		 746struct module;
747struct pci_driver {
0aa0f5d1
BH		 748 struct list_head node;
749 const char *name;
750 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
751 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
752 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
753 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
754 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
755 int (*resume_early)(struct pci_dev *dev);
756 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 757 void (*shutdown) (struct pci_dev *dev);
0aa0f5d1 758 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
49453028 759 const struct pci_error_handlers *err_handler;
92d50fc1 760 const struct attribute_group **groups;
1da177e4 761 struct device_driver driver;
0aa0f5d1 762 struct pci_dynids dynids;
1da177e4
LT		 763};
764
05cca6e5 765#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 766
767/**
0aa0f5d1 768 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 769 * @vend: the 16 bit PCI Vendor ID
770 * @dev: the 16 bit PCI Device ID
771 *
772 * This macro is used to create a struct pci_device_id that matches a
773 * specific device. The subvendor and subdevice fields will be set to
774 * PCI_ANY_ID.
775 */
776#define PCI_DEVICE(vend,dev) \
777 .vendor = (vend), .device = (dev), \
778 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
779
3d567e0e 780/**
0aa0f5d1 781 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 782 * @vend: the 16 bit PCI Vendor ID
783 * @dev: the 16 bit PCI Device ID
784 * @subvend: the 16 bit PCI Subvendor ID
785 * @subdev: the 16 bit PCI Subdevice ID
786 *
787 * This macro is used to create a struct pci_device_id that matches a
788 * specific device with subsystem information.
789 */
790#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
791 .vendor = (vend), .device = (dev), \
792 .subvendor = (subvend), .subdevice = (subdev)
793
1da177e4 794/**
0aa0f5d1 795 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 796 * @dev_class: the class, subclass, prog-if triple for this device
797 * @dev_class_mask: the class mask for this device
798 *
799 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 800 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 801 * fields will be set to PCI_ANY_ID.
802 */
803#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
804 .class = (dev_class), .class_mask = (dev_class_mask), \
805 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
806 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
807
1597cacb 808/**
0aa0f5d1 809 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 810 * @vend: the vendor name
811 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 812 *
813 * This macro is used to create a struct pci_device_id that matches a
814 * specific PCI device. The subvendor, and subdevice fields will be set
815 * to PCI_ANY_ID. The macro allows the next field to follow as the device
816 * private data.
817 */
c1309040
MR		 818#define PCI_VDEVICE(vend, dev) \
819 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 821
5bbe029f 822enum {
0aa0f5d1
BH		 823 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
824 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
825 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
826 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
827 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 828 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 829 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 830};
831
0aa0f5d1 832/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 833#ifdef CONFIG_PCI
834
5bbe029f
BH		 835extern unsigned int pci_flags;
836
837static inline void pci_set_flags(int flags) { pci_flags = flags; }
838static inline void pci_add_flags(int flags) { pci_flags |= flags; }
839static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
840static inline int pci_has_flag(int flag) { return pci_flags & flag; }
841
a58674ff 842void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 843
844enum pcie_bus_config_types {
0aa0f5d1
BH		 845 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
846 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
847 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
848 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
849 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 850};
851
852extern enum pcie_bus_config_types pcie_bus_config;
853
1da177e4
LT		 854extern struct bus_type pci_bus_type;
855
f7625980
BH		 856/* Do NOT directly access these two variables, unless you are arch-specific PCI
857 * code, or PCI core code. */
0aa0f5d1 858extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 859/* Some device drivers need know if PCI is initiated */
f39d5b72 860int no_pci_devices(void);
1da177e4 861
3c449ed0 862void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 863void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 864void pcibios_add_bus(struct pci_bus *bus);
865void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 866void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 867int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 868/* Architecture-specific versions may override this (weak) */
05cca6e5 869char *pcibios_setup(char *str);
1da177e4
LT		 870
871/* Used only when drivers/pci/setup.c is used */
3b7a17fc 872resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 873 resource_size_t,
e31dd6e4 874 resource_size_t);
1da177e4 875
2d1c8618
BH		 876/* Weak but can be overriden by arch */
877void pci_fixup_cardbus(struct pci_bus *);
878
1da177e4
LT		 879/* Generic PCI functions used internally */
880
fc279850 881void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 882 struct resource *res);
fc279850 883void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 884 struct pci_bus_region *region);
d1fd4fb6 885void pcibios_scan_specific_bus(int busn);
f39d5b72 886struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 887void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 888struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 889struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
890 struct pci_ops *ops, void *sysdata,
891 struct list_head *resources);
49b8e3f3 892int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 893int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
894int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
895void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 896struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 897 struct pci_ops *ops, void *sysdata,
898 struct list_head *resources);
1228c4b6 899int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 900struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
901 int busnr);
3749c51a 902void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 903struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 904 const char *name,
905 struct hotplug_slot *hotplug);
f46753c5 906void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 907#ifdef CONFIG_SYSFS
908void pci_dev_assign_slot(struct pci_dev *dev);
909#else
910static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
911#endif
1da177e4 912int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 913struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 914void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 915unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 916void pci_bus_add_device(struct pci_dev *dev);
1da177e4 917void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 918struct resource *pci_find_parent_resource(const struct pci_dev *dev,
919 struct resource *res);
c56d4450 920struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 921u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 922int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 923u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 924struct pci_dev *pci_dev_get(struct pci_dev *dev);
925void pci_dev_put(struct pci_dev *dev);
926void pci_remove_bus(struct pci_bus *b);
927void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 928void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 929void pci_stop_root_bus(struct pci_bus *bus);
930void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 931void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 932void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 933void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 934#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
935#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 936
937/* Generic PCI functions exported to card drivers */
938
388c8c16
JB		 939enum pci_lost_interrupt_reason {
940 PCI_LOST_IRQ_NO_INFORMATION = 0,
941 PCI_LOST_IRQ_DISABLE_MSI,
942 PCI_LOST_IRQ_DISABLE_MSIX,
943 PCI_LOST_IRQ_DISABLE_ACPI,
944};
945enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 946int pci_find_capability(struct pci_dev *dev, int cap);
947int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
948int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 949int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 950int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
951int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 952struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 953
d42552c3 954struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 955 struct pci_dev *from);
05cca6e5 956struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 957 unsigned int ss_vendor, unsigned int ss_device,
958 struct pci_dev *from);
05cca6e5 959struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 960struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
961 unsigned int devfn);
05cca6e5 962struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 963int pci_dev_present(const struct pci_device_id *ids);
964
05cca6e5
GKH		 965int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
966 int where, u8 *val);
967int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
968 int where, u16 *val);
969int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
970 int where, u32 *val);
971int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
972 int where, u8 val);
973int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
974 int where, u16 val);
975int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
976 int where, u32 val);
1f94a94f
RH		 977
978int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
979 int where, int size, u32 *val);
980int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
981 int where, int size, u32 val);
982int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
983 int where, int size, u32 *val);
984int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
985 int where, int size, u32 val);
986
a72b46c3 987struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 988
d3881e50
KB		 989int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
990int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
991int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
992int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
993int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
994int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 995
8c0d3a02
JL		 996int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
997int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
998int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
999int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1000int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1001 u16 clear, u16 set);
1002int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1003 u32 clear, u32 set);
1004
1005static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1006 u16 set)
1007{
1008 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1009}
1010
1011static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1012 u32 set)
1013{
1014 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1015}
1016
1017static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1018 u16 clear)
1019{
1020 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1021}
1022
1023static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1024 u32 clear)
1025{
1026 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1027}
1028
0aa0f5d1 1029/* User-space driven config access */
c63587d7
AW		 1030int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1031int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1032int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1033int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1034int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1035int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1036
4a7fb636 1037int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1038int __must_check pci_enable_device_io(struct pci_dev *dev);
1039int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1040int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1041int __must_check pcim_enable_device(struct pci_dev *pdev);
1042void pcim_pin_device(struct pci_dev *pdev);
1043
99b3c58f
PG		 1044static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1045{
1046 /*
1047 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1048 * writable and no quirk has marked the feature broken.
1049 */
1050 return !pdev->broken_intx_masking;
1051}
1052
296ccb08
YS		 1053static inline int pci_is_enabled(struct pci_dev *pdev)
1054{
1055 return (atomic_read(&pdev->enable_cnt) > 0);
1056}
1057
9ac7849e
TH		 1058static inline int pci_is_managed(struct pci_dev *pdev)
1059{
1060 return pdev->is_managed;
1061}
1062
1da177e4 1063void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1064
1065extern unsigned int pcibios_max_latency;
1da177e4 1066void pci_set_master(struct pci_dev *dev);
6a479079 1067void pci_clear_master(struct pci_dev *dev);
96c55900 1068
f7bdd12d 1069int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1070int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1071#define HAVE_PCI_SET_MWI
4a7fb636 1072int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1073int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1074int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1075void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1076void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1077bool pci_check_and_mask_intx(struct pci_dev *dev);
1078bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1079int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1080int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1081int pcix_get_max_mmrbc(struct pci_dev *dev);
1082int pcix_get_mmrbc(struct pci_dev *dev);
1083int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1084int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1085int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1086int pcie_get_mps(struct pci_dev *dev);
1087int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1088u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1089 enum pci_bus_speed *speed,
1090 enum pcie_link_width *width);
9e506a7b 1091void pcie_print_link_status(struct pci_dev *dev);
91295d79 1092int pcie_flr(struct pci_dev *dev);
a96d627a 1093int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1094int pci_reset_function(struct pci_dev *dev);
a477b9cd 1095int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1096int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1097int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1098int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1099int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1100int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1101int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1102int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1103void pci_reset_secondary_bus(struct pci_dev *dev);
1104void pcibios_reset_secondary_bus(struct pci_dev *dev);
01fd61c0 1105int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1106void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1107int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1108int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1109void pci_release_resource(struct pci_dev *dev, int resno);
1110int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1111int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1112bool pci_device_is_present(struct pci_dev *pdev);
08249651 1113void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1114
704e8953
CH		 1115int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1116 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1117 const char *fmt, ...);
1118void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1119
1da177e4 1120/* ROM control related routines */
e416de5e
AC		 1121int pci_enable_rom(struct pci_dev *pdev);
1122void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1123void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1124void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1125size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1126void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1127
1128/* Power management related routines */
1129int pci_save_state(struct pci_dev *dev);
1d3c16a8 1130void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1131struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1132int pci_load_saved_state(struct pci_dev *dev,
1133 struct pci_saved_state *state);
ffbdd3f7
AW		 1134int pci_load_and_free_saved_state(struct pci_dev *dev,
1135 struct pci_saved_state **state);
fd0f7f73
AW		 1136struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1137struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1138 u16 cap);
1139int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1140int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1141 u16 cap, unsigned int size);
0e5dd46b 1142int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1143int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1144pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1145bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1146void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1147int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1148int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1149int pci_prepare_to_sleep(struct pci_dev *dev);
1150int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1151bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1152bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1153void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1154void pci_d3cold_enable(struct pci_dev *dev);
1155void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1156bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
2a4d2c42
LW		 1157void pci_wakeup_bus(struct pci_bus *bus);
1158void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1159
425c1b22
AW		 1160/* PCI Virtual Channel */
1161int pci_save_vc_state(struct pci_dev *dev);
1162void pci_restore_vc_state(struct pci_dev *dev);
1163void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1164
bb209c82
BH		 1165/* For use by arch with custom probe code */
1166void set_pcie_port_type(struct pci_dev *pdev);
1167void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1168
ce5ccdef 1169/* Functions for PCI Hotplug drivers to use */
05cca6e5 1170int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1171unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1172unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1173void pci_lock_rescan_remove(void);
1174void pci_unlock_rescan_remove(void);
ce5ccdef 1175
0aa0f5d1 1176/* Vital Product Data routines */
287d19ce
SH		 1177ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1178ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1179int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1180
1da177e4 1181/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1182resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1183void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1184void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1185void pci_bus_size_bridges(struct pci_bus *bus);
1186int pci_claim_resource(struct pci_dev *, int);
8505e729 1187int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1188void pci_assign_unassigned_resources(void);
6841ec68 1189void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1190void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1191void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1192int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1193void pdev_enable_device(struct pci_dev *);
842de40d 1194int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1195void pci_assign_irq(struct pci_dev *dev);
afd29f90 1196struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1197#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1198int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1199int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1200void pci_release_regions(struct pci_dev *);
4a7fb636 1201int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1202int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1203void pci_release_region(struct pci_dev *, int);
c87deff7 1204int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1205int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1206void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1207
1208/* drivers/pci/bus.c */
fe830ef6
JL		 1209struct pci_bus *pci_bus_get(struct pci_bus *bus);
1210void pci_bus_put(struct pci_bus *bus);
45ca9e97 1211void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1212void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1213 resource_size_t offset);
45ca9e97 1214void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1215void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1216 unsigned int flags);
2fe2abf8
BH		 1217struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1218void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1219int devm_request_pci_bus_resources(struct device *dev,
1220 struct list_head *resources);
2fe2abf8 1221
89a74ecc 1222#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1223 for (i = 0; \
1224 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1225 i++)
89a74ecc 1226
4a7fb636
AM		 1227int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1228 struct resource *res, resource_size_t size,
1229 resource_size_t align, resource_size_t min,
664c2848 1230 unsigned long type_mask,
3b7a17fc
DB		 1231 resource_size_t (*alignf)(void *,
1232 const struct resource *,
b26b2d49
DB		 1233 resource_size_t,
1234 resource_size_t),
4a7fb636 1235 void *alignf_data);
1da177e4 1236
8b921acf 1237
fcfaab30
GP		 1238int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1239 resource_size_t size);
c5076cfe
TN		 1240unsigned long pci_address_to_pio(phys_addr_t addr);
1241phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1242int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
4d3f1384 1243void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1244void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1245 resource_size_t offset,
1246 resource_size_t size);
1247void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1248 struct resource *res);
8b921acf 1249
3a9ad0b4 1250static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1251{
1252 struct pci_bus_region region;
1253
1254 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1255 return region.start;
1256}
1257
863b18f4 1258/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1259int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1260 const char *mod_name);
bba81165 1261
0aa0f5d1 1262/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1263#define pci_register_driver(driver) \
1264 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1265
05cca6e5 1266void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1267
1268/**
1269 * module_pci_driver() - Helper macro for registering a PCI driver
1270 * @__pci_driver: pci_driver struct
1271 *
1272 * Helper macro for PCI drivers which do not do anything special in module
1273 * init/exit. This eliminates a lot of boilerplate. Each module may only
1274 * use this macro once, and calling it replaces module_init() and module_exit()
1275 */
1276#define module_pci_driver(__pci_driver) \
0aa0f5d1 1277 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1278
b4eb6cdb
PG		 1279/**
1280 * builtin_pci_driver() - Helper macro for registering a PCI driver
1281 * @__pci_driver: pci_driver struct
1282 *
1283 * Helper macro for PCI drivers which do not do anything special in their
1284 * init code. This eliminates a lot of boilerplate. Each driver may only
1285 * use this macro once, and calling it replaces device_initcall(...)
1286 */
1287#define builtin_pci_driver(__pci_driver) \
1288 builtin_driver(__pci_driver, pci_register_driver)
1289
05cca6e5 1290struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1291int pci_add_dynid(struct pci_driver *drv,
1292 unsigned int vendor, unsigned int device,
1293 unsigned int subvendor, unsigned int subdevice,
1294 unsigned int class, unsigned int class_mask,
1295 unsigned long driver_data);
05cca6e5
GKH		 1296const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1297 struct pci_dev *dev);
1298int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1299 int pass);
1da177e4 1300
70298c6e 1301void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1302 void *userdata);
ac7dc65a 1303int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1304unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1305void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1306resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1307 unsigned long type);
cecf4864 1308
3448a19d
DA		 1309#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1310#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1311
deb2d2ec 1312int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1313 unsigned int command_bits, u32 flags);
fe537670 1314
0aa0f5d1
BH		 1315#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1316#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1317#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1318#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
4fe0d154
CH		 1319#define PCI_IRQ_ALL_TYPES \
1320 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1321
1da177e4
LT		 1322/* kmem_cache style wrapper around pci_alloc_consistent() */
1323
f41b1771 1324#include <linux/pci-dma.h>
1da177e4
LT		 1325#include <linux/dmapool.h>
1326
1327#define pci_pool dma_pool
1328#define pci_pool_create(name, pdev, size, align, allocation) \
1329 dma_pool_create(name, &pdev->dev, size, align, allocation)
1330#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1331#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1332#define pci_pool_zalloc(pool, flags, handle) \
1333 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1334#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1335
1da177e4 1336struct msix_entry {
0aa0f5d1
BH		 1337 u32 vector; /* Kernel uses to write allocated vector */
1338 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1339};
1340
4c859804
BH		 1341#ifdef CONFIG_PCI_MSI
1342int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1343void pci_disable_msi(struct pci_dev *dev);
4c859804 1344int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1345void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1346void pci_restore_msi_state(struct pci_dev *dev);
1347int pci_msi_enabled(void);
4fe03955 1348int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1349int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1350 int minvec, int maxvec);
f7fc32cb
AG		 1351static inline int pci_enable_msix_exact(struct pci_dev *dev,
1352 struct msix_entry *entries, int nvec)
1353{
1354 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1355 if (rc < 0)
1356 return rc;
1357 return 0;
1358}
402723ad
CH		 1359int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1360 unsigned int max_vecs, unsigned int flags,
1361 const struct irq_affinity *affd);
1362
aff17164
CH		 1363void pci_free_irq_vectors(struct pci_dev *dev);
1364int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1365const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1366int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1367
4c859804 1368#else
2ee546c4 1369static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1370static inline void pci_disable_msi(struct pci_dev *dev) { }
1371static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1372static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1373static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1374static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1375static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1376{ return -ENOSYS; }
302a2523 1377static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1378 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1379{ return -ENOSYS; }
f7fc32cb 1380static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1381 struct msix_entry *entries, int nvec)
f7fc32cb 1382{ return -ENOSYS; }
402723ad
CH		 1383
1384static inline int
1385pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1386 unsigned int max_vecs, unsigned int flags,
1387 const struct irq_affinity *aff_desc)
aff17164 1388{
83b4605b
CH		 1389 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1390 return 1;
1391 return -ENOSPC;
aff17164 1392}
402723ad 1393
aff17164
CH		 1394static inline void pci_free_irq_vectors(struct pci_dev *dev)
1395{
1396}
1397
1398static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1399{
1400 if (WARN_ON_ONCE(nr > 0))
1401 return -EINVAL;
1402 return dev->irq;
1403}
ee8d41e5
TG		 1404static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1405 int vec)
1406{
1407 return cpu_possible_mask;
1408}
27ddb689
SL		 1409
1410static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1411{
1412 return first_online_node;
1413}
1da177e4
LT		 1414#endif
1415
402723ad
CH		 1416static inline int
1417pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1418 unsigned int max_vecs, unsigned int flags)
1419{
1420 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1421 NULL);
1422}
1423
0d58e6c1
PB		 1424/**
1425 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1426 * @d: the INTx IRQ domain
1427 * @node: the DT node for the device whose interrupt we're translating
1428 * @intspec: the interrupt specifier data from the DT
1429 * @intsize: the number of entries in @intspec
1430 * @out_hwirq: pointer at which to write the hwirq number
1431 * @out_type: pointer at which to write the interrupt type
1432 *
1433 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1434 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1435 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1436 * INTx value to obtain the hwirq number.
1437 *
1438 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1439 */
1440static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1441 struct device_node *node,
1442 const u32 *intspec,
1443 unsigned int intsize,
1444 unsigned long *out_hwirq,
1445 unsigned int *out_type)
1446{
1447 const u32 intx = intspec[0];
1448
1449 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1450 return -EINVAL;
1451
1452 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1453 return 0;
1454}
1455
ab0724ff 1456#ifdef CONFIG_PCIEPORTBUS
415e12b2 1457extern bool pcie_ports_disabled;
5352a44a 1458extern bool pcie_ports_native;
ab0724ff
MT		 1459#else
1460#define pcie_ports_disabled true
5352a44a 1461#define pcie_ports_native false
ab0724ff 1462#endif
415e12b2 1463
4c859804 1464#ifdef CONFIG_PCIEASPM
f39d5b72 1465bool pcie_aspm_support_enabled(void);
4c859804
BH		 1466#else
1467static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1468#endif
1469
415e12b2
RW		 1470#ifdef CONFIG_PCIEAER
1471void pci_no_aer(void);
1472bool pci_aer_available(void);
66b80809 1473int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1474#else
1475static inline void pci_no_aer(void) { }
1476static inline bool pci_aer_available(void) { return false; }
66b80809 1477static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1478#endif
1479
4c859804 1480#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1481void pcie_set_ecrc_checking(struct pci_dev *dev);
1482void pcie_ecrc_get_policy(char *str);
4c859804 1483#else
2ee546c4
BH		 1484static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1485static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1486#endif
1487
cef74409
GK		 1488bool pci_ats_disabled(void);
1489
edc90fee
BH		 1490#ifdef CONFIG_PCI_ATS
1491/* Address Translation Service */
1492void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1493int pci_enable_ats(struct pci_dev *dev, int ps);
1494void pci_disable_ats(struct pci_dev *dev);
1495int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1496#else
ff9bee89
BH		 1497static inline void pci_ats_init(struct pci_dev *d) { }
1498static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1499static inline void pci_disable_ats(struct pci_dev *d) { }
1500static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1501#endif
1502
eec097d4
BH		 1503#ifdef CONFIG_PCIE_PTM
1504int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1505#else
1506static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1507{ return -EINVAL; }
1508#endif
1509
f39d5b72
BH		 1510void pci_cfg_access_lock(struct pci_dev *dev);
1511bool pci_cfg_access_trylock(struct pci_dev *dev);
1512void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1513
4352dfd5
GKH		 1514/*
1515 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1516 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1517 * configuration space.
1518 */
32a2eea7
JG		 1519#ifdef CONFIG_PCI_DOMAINS
1520extern int pci_domains_supported;
1521#else
1522enum { pci_domains_supported = 0 };
2ee546c4
BH		 1523static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1524static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1525#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1526
670ba0c8
CM		 1527/*
1528 * Generic implementation for PCI domain support. If your
1529 * architecture does not need custom management of PCI
1530 * domains then this implementation will be used
1531 */
1532#ifdef CONFIG_PCI_DOMAINS_GENERIC
1533static inline int pci_domain_nr(struct pci_bus *bus)
1534{
1535 return bus->domain_nr;
1536}
2ab51dde
TN		 1537#ifdef CONFIG_ACPI
1538int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1539#else
2ab51dde
TN		 1540static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1541{ return 0; }
1542#endif
9c7cb891 1543int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1544#endif
1545
0aa0f5d1 1546/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1547typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1548 unsigned int command_bits, u32 flags);
f39d5b72 1549void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1550
be9d2e89
JT		 1551static inline int
1552pci_request_io_regions(struct pci_dev *pdev, const char *name)
1553{
1554 return pci_request_selected_regions(pdev,
1555 pci_select_bars(pdev, IORESOURCE_IO), name);
1556}
1557
1558static inline void
1559pci_release_io_regions(struct pci_dev *pdev)
1560{
1561 return pci_release_selected_regions(pdev,
1562 pci_select_bars(pdev, IORESOURCE_IO));
1563}
1564
1565static inline int
1566pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1567{
1568 return pci_request_selected_regions(pdev,
1569 pci_select_bars(pdev, IORESOURCE_MEM), name);
1570}
1571
1572static inline void
1573pci_release_mem_regions(struct pci_dev *pdev)
1574{
1575 return pci_release_selected_regions(pdev,
1576 pci_select_bars(pdev, IORESOURCE_MEM));
1577}
1578
4352dfd5 1579#else /* CONFIG_PCI is not enabled */
1da177e4 1580
5bbe029f
BH		 1581static inline void pci_set_flags(int flags) { }
1582static inline void pci_add_flags(int flags) { }
1583static inline void pci_clear_flags(int flags) { }
1584static inline int pci_has_flag(int flag) { return 0; }
1585
1da177e4 1586/*
0aa0f5d1
BH		 1587 * If the system does not have PCI, clearly these return errors. Define
1588 * these as simple inline functions to avoid hair in drivers.
1da177e4 1589 */
05cca6e5
GKH		 1590#define _PCI_NOP(o, s, t) \
1591 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1592 int where, t val) \
1da177e4 1593 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1594
1595#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1596 _PCI_NOP(o, word, u16 x) \
1597 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1598_PCI_NOP_ALL(read, *)
1599_PCI_NOP_ALL(write,)
1600
d42552c3 1601static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1602 unsigned int device,
1603 struct pci_dev *from)
2ee546c4 1604{ return NULL; }
d42552c3 1605
05cca6e5
GKH		 1606static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1607 unsigned int device,
1608 unsigned int ss_vendor,
1609 unsigned int ss_device,
b08508c4 1610 struct pci_dev *from)
2ee546c4 1611{ return NULL; }
1da177e4 1612
05cca6e5
GKH		 1613static inline struct pci_dev *pci_get_class(unsigned int class,
1614 struct pci_dev *from)
2ee546c4 1615{ return NULL; }
1da177e4
LT		 1616
1617#define pci_dev_present(ids) (0)
ed4aaadb 1618#define no_pci_devices() (1)
1da177e4
LT		 1619#define pci_dev_put(dev) do { } while (0)
1620
2ee546c4
BH		 1621static inline void pci_set_master(struct pci_dev *dev) { }
1622static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1623static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1624static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1625{ return -EBUSY; }
05cca6e5
GKH		 1626static inline int __pci_register_driver(struct pci_driver *drv,
1627 struct module *owner)
2ee546c4 1628{ return 0; }
05cca6e5 1629static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1630{ return 0; }
1631static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1632static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1633{ return 0; }
05cca6e5
GKH		 1634static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1635 int cap)
2ee546c4 1636{ return 0; }
05cca6e5 1637static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1638{ return 0; }
05cca6e5 1639
1da177e4 1640/* Power management related routines */
2ee546c4
BH		 1641static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1642static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1643static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1644{ return 0; }
3449248c 1645static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1646{ return 0; }
05cca6e5
GKH		 1647static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1648 pm_message_t state)
2ee546c4 1649{ return PCI_D0; }
05cca6e5
GKH		 1650static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1651 int enable)
2ee546c4 1652{ return 0; }
48a92a81 1653
afd29f90
MW		 1654static inline struct resource *pci_find_resource(struct pci_dev *dev,
1655 struct resource *res)
1656{ return NULL; }
05cca6e5 1657static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1658{ return -EIO; }
1659static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1660
c5076cfe
TN		 1661static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1662
2ee546c4 1663static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1664static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1665{ return 0; }
2ee546c4 1666static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1667
d80d0217
RD		 1668static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1669{ return NULL; }
d80d0217
RD		 1670static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1671 unsigned int devfn)
1672{ return NULL; }
7912af5c
RD		 1673static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1674 unsigned int bus, unsigned int devfn)
1675{ return NULL; }
d80d0217 1676
2ee546c4
BH		 1677static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1678static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 1679
fb8a0d9d
WM		 1680#define dev_is_pci(d) (false)
1681#define dev_is_pf(d) (false)
fe594932
GU		 1682static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1683{ return false; }
80db6f08
NC		 1684static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1685 struct device_node *node,
1686 const u32 *intspec,
1687 unsigned int intsize,
1688 unsigned long *out_hwirq,
1689 unsigned int *out_type)
1690{ return -EINVAL; }
4352dfd5 1691#endif /* CONFIG_PCI */
1da177e4 1692
4352dfd5
GKH		 1693/* Include architecture-dependent settings and functions */
1694
1695#include <asm/pci.h>
1da177e4 1696
f7195824
DW		 1697/* These two functions provide almost identical functionality. Depennding
1698 * on the architecture, one will be implemented as a wrapper around the
1699 * other (in drivers/pci/mmap.c).
1700 *
1701 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1702 * is expected to be an offset within that region.
1703 *
1704 * pci_mmap_page_range() is the legacy architecture-specific interface,
1705 * which accepts a "user visible" resource address converted by
1706 * pci_resource_to_user(), as used in the legacy mmap() interface in
1707 * /proc/bus/pci/.
1708 */
1709int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1710 struct vm_area_struct *vma,
1711 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1712int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1713 struct vm_area_struct *vma,
11df1954
DW		 1714 enum pci_mmap_state mmap_state, int write_combine);
1715
ae749c7a
DW		 1716#ifndef arch_can_pci_mmap_wc
1717#define arch_can_pci_mmap_wc() 0
1718#endif
2bea36fd 1719
e854d8b2
DW		 1720#ifndef arch_can_pci_mmap_io
1721#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1722#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1723#else
1724int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1725#endif
ae749c7a 1726
92016ba5
JO		 1727#ifndef pci_root_bus_fwnode
1728#define pci_root_bus_fwnode(bus) NULL
1729#endif
1730
0aa0f5d1
BH		 1731/*
1732 * These helpers provide future and backwards compatibility
1733 * for accessing popular PCI BAR info
1734 */
05cca6e5
GKH		 1735#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1736#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1737#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1738#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1739 ((pci_resource_start((dev), (bar)) == 0 && \
1740 pci_resource_end((dev), (bar)) == \
1741 pci_resource_start((dev), (bar))) ? 0 : \
1742 \
1743 (pci_resource_end((dev), (bar)) - \
1744 pci_resource_start((dev), (bar)) + 1))
1da177e4 1745
0aa0f5d1
BH		 1746/*
1747 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1748 * driver-specific data. They are really just a wrapper around
1749 * the generic device structure functions of these calls.
1750 */
05cca6e5 1751static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1752{
1753 return dev_get_drvdata(&pdev->dev);
1754}
1755
05cca6e5 1756static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1757{
1758 dev_set_drvdata(&pdev->dev, data);
1759}
1760
2fc90f61 1761static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1762{
c6c4f070 1763 return dev_name(&pdev->dev);
1da177e4
LT		 1764}
1765
2311b1f2 1766
0aa0f5d1
BH		 1767/*
1768 * Some archs don't want to expose struct resource to userland as-is
2311b1f2
ME		 1769 * in sysfs and /proc
1770 */
8221a013
BH		 1771#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1772void pci_resource_to_user(const struct pci_dev *dev, int bar,
1773 const struct resource *rsrc,
1774 resource_size_t *start, resource_size_t *end);
1775#else
2311b1f2 1776static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1777 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1778 resource_size_t *end)
2311b1f2
ME		 1779{
1780 *start = rsrc->start;
1781 *end = rsrc->end;
1782}
1783#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1784
1785
1da177e4 1786/*
0aa0f5d1
BH		 1787 * The world is not perfect and supplies us with broken PCI devices.
1788 * For at least a part of these bugs we need a work-around, so both
1789 * generic (drivers/pci/quirks.c) and per-architecture code can define
1790 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1791 */
1792
1793struct pci_fixup {
0aa0f5d1
BH		 1794 u16 vendor; /* Or PCI_ANY_ID */
1795 u16 device; /* Or PCI_ANY_ID */
1796 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 1797 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1798 void (*hook)(struct pci_dev *dev);
1799};
1800
1801enum pci_fixup_pass {
1802 pci_fixup_early, /* Before probing BARs */
1803 pci_fixup_header, /* After reading configuration header */
1804 pci_fixup_final, /* Final phase of device fixups */
1805 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1806 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1807 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1808 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1809 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1810};
1811
1812/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1813#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1814 class_shift, hook) \
ecf61c78 1815 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1816 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1817 = { vendor, device, class, class_shift, hook };
1818
1819#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1820 class_shift, hook) \
1821 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1822 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1823#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1824 class_shift, hook) \
1825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1826 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1827#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1828 class_shift, hook) \
1829 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1830 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1831#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1832 class_shift, hook) \
1833 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1834 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1835#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1836 class_shift, hook) \
1837 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1838 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1839#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1840 class_shift, hook) \
1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1842 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1843#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1844 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1846 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 1847#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1848 class_shift, hook) \
1849 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1850 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 1851
1da177e4
LT		 1852#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1854 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1855#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1857 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1858#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1860 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1861#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1863 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1864#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1866 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1867#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1869 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1870#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1872 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1873#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1874 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1875 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 1876
93177a74 1877#ifdef CONFIG_PCI_QUIRKS
1da177e4 1878void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1879int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1880int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1881#else
1882static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1883 struct pci_dev *dev) { }
ad805758
AW		 1884static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1885 u16 acs_flags)
1886{
1887 return -ENOTTY;
1888}
c1d61c9b
AW		 1889static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1890{
1891 return -ENOTTY;
1892}
93177a74 1893#endif
1da177e4 1894
05cca6e5 1895void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1896void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1897void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1898int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1899int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1900 const char *name);
fb7ebfe4 1901void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1902
1da177e4 1903extern int pci_pci_problems;
236561e5 1904#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1905#define PCIPCI_TRITON 2
1906#define PCIPCI_NATOMA 4
1907#define PCIPCI_VIAETBF 8
1908#define PCIPCI_VSFX 16
236561e5
AC		 1909#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1910#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1911
4516a618
AN		 1912extern unsigned long pci_cardbus_io_size;
1913extern unsigned long pci_cardbus_mem_size;
15856ad5 1914extern u8 pci_dfl_cache_line_size;
ac1aa47b 1915extern u8 pci_cache_line_size;
4516a618 1916
28760489
EB		 1917extern unsigned long pci_hotplug_io_size;
1918extern unsigned long pci_hotplug_mem_size;
e16b4660 1919extern unsigned long pci_hotplug_bus_size;
28760489 1920
f7625980 1921/* Architecture-specific versions may override these (weak) */
19792a08 1922void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1923void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1924int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1925 enum pcie_reset_state state);
eca0d467 1926int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1927void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1928void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1929int pcibios_alloc_irq(struct pci_dev *dev);
1930void pcibios_free_irq(struct pci_dev *dev);
619e6f34 1931resource_size_t pcibios_default_alignment(void);
575e3348 1932
699c1985
SO		 1933#ifdef CONFIG_HIBERNATE_CALLBACKS
1934extern struct dev_pm_ops pcibios_pm_ops;
1935#endif
1936
935c760e 1937#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1938void __init pci_mmcfg_early_init(void);
1939void __init pci_mmcfg_late_init(void);
7752d5cf 1940#else
bb63b421 1941static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1942static inline void pci_mmcfg_late_init(void) { }
1943#endif
1944
642c92da 1945int pci_ext_cfg_avail(void);
0ef5f8f6 1946
1684f5dd 1947void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1948void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1949
dd7cc44d 1950#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1951int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1952int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1953
f39d5b72
BH		 1954int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1955void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 1956int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1957void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 1958int pci_num_vf(struct pci_dev *dev);
5a8eb242 1959int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1960int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1961int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 1962int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 1963resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 1964void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 1965
1966/* Arch may override these (weak) */
1967int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1968int pcibios_sriov_disable(struct pci_dev *pdev);
1969resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 1970#else
b07579c0
WY		 1971static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1972{
1973 return -ENOSYS;
1974}
1975static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1976{
1977 return -ENOSYS;
1978}
dd7cc44d 1979static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1980{ return -ENODEV; }
753f6124 1981static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 1982{
1983 return -ENOSYS;
1984}
1985static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 1986 int id) { }
2ee546c4 1987static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1988static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1989static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1990{ return 0; }
bff73156 1991static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1992{ return 0; }
bff73156 1993static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1994{ return 0; }
8effc395 1995#define pci_sriov_configure_simple NULL
0e6c9122
WY		 1996static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1997{ return 0; }
608c0d88 1998static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 1999#endif
2000
c825bc94 2001#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2002void pci_hp_create_module_link(struct pci_slot *pci_slot);
2003void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2004#endif
2005
d7b7e605
KK		 2006/**
2007 * pci_pcie_cap - get the saved PCIe capability offset
2008 * @dev: PCI device
2009 *
2010 * PCIe capability offset is calculated at PCI device initialization
2011 * time and saved in the data structure. This function returns saved
2012 * PCIe capability offset. Using this instead of pci_find_capability()
2013 * reduces unnecessary search in the PCI configuration space. If you
2014 * need to calculate PCIe capability offset from raw device for some
2015 * reasons, please use pci_find_capability() instead.
2016 */
2017static inline int pci_pcie_cap(struct pci_dev *dev)
2018{
2019 return dev->pcie_cap;
2020}
2021
7eb776c4
KK		 2022/**
2023 * pci_is_pcie - check if the PCI device is PCI Express capable
2024 * @dev: PCI device
2025 *
a895c28a 2026 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2027 */
2028static inline bool pci_is_pcie(struct pci_dev *dev)
2029{
a895c28a 2030 return pci_pcie_cap(dev);
7eb776c4
KK		 2031}
2032
7c9c003c
MS		 2033/**
2034 * pcie_caps_reg - get the PCIe Capabilities Register
2035 * @dev: PCI device
2036 */
2037static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2038{
2039 return dev->pcie_flags_reg;
2040}
2041
786e2288
YW		 2042/**
2043 * pci_pcie_type - get the PCIe device/port type
2044 * @dev: PCI device
2045 */
2046static inline int pci_pcie_type(const struct pci_dev *dev)
2047{
1c531d82 2048 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2049}
2050
e784930b
JT		 2051static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2052{
2053 while (1) {
2054 if (!pci_is_pcie(dev))
2055 break;
2056 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2057 return dev;
2058 if (!dev->bus->self)
2059 break;
2060 dev = dev->bus->self;
2061 }
2062 return NULL;
2063}
2064
5d990b62 2065void pci_request_acs(void);
ad805758
AW		 2066bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2067bool pci_acs_path_enabled(struct pci_dev *start,
2068 struct pci_dev *end, u16 acs_flags);
430a2368 2069int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2070
7ad506fa 2071#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2072#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2073
2074/* Large Resource Data Type Tag Item Names */
2075#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2076#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2077#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2078
2079#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2080#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2081#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2082
2083/* Small Resource Data Type Tag Item Names */
9eb45d5c 2084#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2085
9eb45d5c 2086#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2087
2088#define PCI_VPD_SRDT_TIN_MASK 0x78
2089#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2090#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2091
2092#define PCI_VPD_LRDT_TAG_SIZE 3
2093#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2094
e1d5bdab
MC		 2095#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2096
4067a854
MC		 2097#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2098#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2099#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2100#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2101
a2ce7662
MC		 2102/**
2103 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2104 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2105 *
2106 * Returns the extracted Large Resource Data Type length.
2107 */
2108static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2109{
2110 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2111}
2112
9eb45d5c
HR		 2113/**
2114 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2115 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2116 *
2117 * Returns the extracted Large Resource Data Type Tag item.
2118 */
2119static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2120{
0aa0f5d1 2121 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
9eb45d5c
HR		 2122}
2123
7ad506fa
MC		 2124/**
2125 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2126 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2127 *
2128 * Returns the extracted Small Resource Data Type length.
2129 */
2130static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2131{
2132 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2133}
2134
9eb45d5c
HR		 2135/**
2136 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2137 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2138 *
2139 * Returns the extracted Small Resource Data Type Tag Item.
2140 */
2141static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2142{
2143 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2144}
2145
e1d5bdab
MC		 2146/**
2147 * pci_vpd_info_field_size - Extracts the information field length
2148 * @lrdt: Pointer to the beginning of an information field header
2149 *
2150 * Returns the extracted information field length.
2151 */
2152static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2153{
2154 return info_field[2];
2155}
2156
b55ac1b2
MC		 2157/**
2158 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2159 * @buf: Pointer to buffered vpd data
2160 * @off: The offset into the buffer at which to begin the search
2161 * @len: The length of the vpd buffer
2162 * @rdt: The Resource Data Type to search for
2163 *
2164 * Returns the index where the Resource Data Type was found or
2165 * -ENOENT otherwise.
2166 */
2167int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2168
4067a854
MC		 2169/**
2170 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2171 * @buf: Pointer to buffered vpd data
2172 * @off: The offset into the buffer at which to begin the search
2173 * @len: The length of the buffer area, relative to off, in which to search
2174 * @kw: The keyword to search for
2175 *
2176 * Returns the index where the information field keyword was found or
2177 * -ENOENT otherwise.
2178 */
2179int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2180 unsigned int len, const char *kw);
2181
98d9f30c
BH		 2182/* PCI <-> OF binding helpers */
2183#ifdef CONFIG_OF
2184struct device_node;
b165e2b6 2185struct irq_domain;
f39d5b72
BH		 2186void pci_set_of_node(struct pci_dev *dev);
2187void pci_release_of_node(struct pci_dev *dev);
2188void pci_set_bus_of_node(struct pci_bus *bus);
2189void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2190struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
3a8f77e4
CP		 2191int pci_parse_request_of_pci_ranges(struct device *dev,
2192 struct list_head *resources,
2193 struct resource **bus_range);
98d9f30c
BH		 2194
2195/* Arch may override this (weak) */
723ec4d0 2196struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2197
0aa0f5d1 2198#else /* CONFIG_OF */
98d9f30c
BH		 2199static inline void pci_set_of_node(struct pci_dev *dev) { }
2200static inline void pci_release_of_node(struct pci_dev *dev) { }
2201static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2202static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
b165e2b6
MZ		 2203static inline struct irq_domain *
2204pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
3a8f77e4
CP		 2205static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2206 struct list_head *resources,
2207 struct resource **bus_range)
2208{
2209 return -EINVAL;
2210}
98d9f30c
BH		 2211#endif /* CONFIG_OF */
2212
ad32eb2d
BM		 2213static inline struct device_node *
2214pci_device_to_OF_node(const struct pci_dev *pdev)
2215{
2216 return pdev ? pdev->dev.of_node : NULL;
2217}
2218
2219static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2220{
2221 return bus ? bus->dev.of_node : NULL;
2222}
2223
471036b2
SS		 2224#ifdef CONFIG_ACPI
2225struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2226
2227void
2228pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2229#else
2230static inline struct irq_domain *
2231pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2232#endif
2233
eb740b5f
GS		 2234#ifdef CONFIG_EEH
2235static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2236{
2237 return pdev->dev.archdata.edev;
2238}
2239#endif
2240
f0af9593 2241void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2242bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2243int pci_for_each_dma_alias(struct pci_dev *pdev,
2244 int (*fn)(struct pci_dev *pdev,
2245 u16 alias, void *data), void *data);
2246
0aa0f5d1 2247/* Helper functions for operation of device flag */
ce052984
EZ		 2248static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2249{
2250 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2251}
2252static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2253{
2254 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2255}
2256static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2257{
2258 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2259}
19bdb6e4
AW		 2260
2261/**
2262 * pci_ari_enabled - query ARI forwarding status
2263 * @bus: the PCI bus
2264 *
2265 * Returns true if ARI forwarding is enabled.
2266 */
2267static inline bool pci_ari_enabled(struct pci_bus *bus)
2268{
2269 return bus->self && bus->self->ari_enabled;
2270}
bc4b024a 2271
8531e283
LW		 2272/**
2273 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2274 * @pdev: PCI device to check
2275 *
2276 * Walk upwards from @pdev and check for each encountered bridge if it's part
2277 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2278 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2279 */
2280static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2281{
2282 struct pci_dev *parent = pdev;
2283
2284 if (pdev->is_thunderbolt)
2285 return true;
2286
2287 while ((parent = pci_upstream_bridge(parent)))
2288 if (parent->is_thunderbolt)
2289 return true;
2290
2291 return false;
2292}
2293
2e28bc84 2294#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2295void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2296#endif
856e1eb9 2297
0aa0f5d1 2298/* Provide the legacy pci_dma_* API */
bc4b024a
CH		 2299#include <linux/pci-dma-compat.h>
2300
7506dc79
FL		 2301#define pci_printk(level, pdev, fmt, arg...) \
2302 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2303
2304#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2305#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2306#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2307#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2308#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2309#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2310#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2311#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2312
1da177e4 2313#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)