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PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
7ce2e76a
KW		 9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
1da177e4
LT		 14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
7ce2e76a 20 * PCI Express Specification
1da177e4
LT		 21 * PCI System Design Guide
22 */
1da177e4
LT		 23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
b229baa3 26#include <linux/args.h>
778382e0
DW		 27#include <linux/mod_devicetable.h>
28
1da177e4 29#include <linux/types.h>
98db6f19 30#include <linux/init.h>
1da177e4
LT		 31#include <linux/ioport.h>
32#include <linux/list.h>
4a7fb636 33#include <linux/compiler.h>
1da177e4 34#include <linux/errno.h>
f46753c5 35#include <linux/kobject.h>
60063497 36#include <linux/atomic.h>
1da177e4 37#include <linux/device.h>
704e8953 38#include <linux/interrupt.h>
1388cc96 39#include <linux/io.h>
14d76b68 40#include <linux/resource_ext.h>
34026364 41#include <linux/msi_api.h>
607ca46e 42#include <uapi/linux/pci.h>
1da177e4 43
7e7a43c3
AB		 44#include <linux/pci_ids.h>
45
d6e055e8
HK		 46#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
e20afa06 53/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53c49b6e 54#define PCI_NUM_RESET_METHODS 8
e20afa06 55
9bdc81ce
AN		 56#define PCI_RESET_PROBE true
57#define PCI_RESET_DO_RESET false
58
85467136
SK		 59/*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
f7625980
BH		 66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 68 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 69 * the following kernel-only defines are being added here.
85467136 70 */
0aa0f5d1 71#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 72/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
f46753c5
AC		 75/* pci_slot represents a physical slot */
76struct pci_slot {
0aa0f5d1
BH		 77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
f46753c5
AC		 82};
83
0ad772ec
AC		 84static inline const char *pci_slot_name(const struct pci_slot *slot)
85{
86 return kobject_name(&slot->kobj);
87}
88
1da177e4
LT		 89/* File state for mmap()s on /proc/bus/pci/X/Y */
90enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93};
94
0aa0f5d1 95/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 96enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
c9c13ba4 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
fde09c6d
YZ		 100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
0aa0f5d1 104 /* Device-specific resources */
d1b054da
YZ		 105#ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108#endif
109
6e0688db
KW		 110/* PCI-to-PCI (P2P) bridge windows */
111#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115/* CardBus bridge windows */
116#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121/* Total number of bridge resources for P2P and CardBus */
fde09c6d
YZ		 122#define PCI_BRIDGE_RESOURCE_NUM 4
123
6e0688db 124 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
0aa0f5d1 129 /* Total resources associated with a PCI device */
fde09c6d
YZ		 130 PCI_NUM_RESOURCES,
131
0aa0f5d1 132 /* Preserve this for compatibility */
cda57bf9 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 134};
1da177e4 135
b352baf1
PB		 136/**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153};
154
155/* The number of legacy PCI INTx interrupts */
156#define PCI_NUM_INTX 4
157
57bdeef4
NN		 158/*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163#define PCI_ERROR_RESPONSE (~0ULL)
164#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
224abb67
BH		 167/*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
1da177e4
LT		 171typedef int __bitwise pci_power_t;
172
4352dfd5
GKH		 173#define PCI_D0 ((pci_power_t __force) 0)
174#define PCI_D1 ((pci_power_t __force) 1)
175#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 176#define PCI_D3hot ((pci_power_t __force) 3)
177#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 178#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 179#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 180
00240c38
AS		 181/* Remember to update this when the list above changes! */
182extern const char *pci_power_names[];
183
184static inline const char *pci_power_name(pci_power_t state)
185{
9661e783 186 return pci_power_names[1 + (__force int) state];
00240c38
AS		 187}
188
0aa0f5d1 189/**
229b4e07
CD		 190 * typedef pci_channel_state_t
191 *
0aa0f5d1
BH		 192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
392a1ce7 195 */
196typedef unsigned int __bitwise pci_channel_state_t;
197
16d79cd4 198enum {
392a1ce7 199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207};
208
f7bdd12d
BK		 209typedef unsigned int __bitwise pcie_reset_state_t;
210
211enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
f7625980 215 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
f7625980 218 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220};
221
ba698ad4
DM		 222typedef unsigned short __bitwise pci_dev_flags_t;
223enum pci_dev_flags {
0aa0f5d1 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 226 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 228 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 240 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 244 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
2226667a
MZ		 246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
ba698ad4
DM		 248};
249
e1d3a908
SA		 250enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253};
254
6e325a62
MT		 255typedef unsigned short __bitwise pci_bus_flags_t;
256enum pci_bus_flags {
032c3d86
JD		 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 261};
262
0aa0f5d1 263/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 264enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
0aa0f5d1 270 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
0aa0f5d1 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 274};
275
e56faff5 276/* See matching string table in pci_speed_string() */
536c8cb4
MW		 277enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
536c8cb4
MW		 294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 299 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 300 PCIE_SPEED_16_0GT = 0x17,
de76cda2 301 PCIE_SPEED_32_0GT = 0x18,
34191749 302 PCIE_SPEED_64_0GT = 0x19,
536c8cb4
MW		 303 PCI_SPEED_UNKNOWN = 0xff,
304};
305
576c7218
AD		 306enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
fd00faa3
HK		 309struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
24a4742f
AW		 313};
314
402723ad 315struct irq_affinity;
7d715a6c 316struct pcie_link_state;
d1b054da 317struct pci_sriov;
52916982 318struct pci_p2pdma;
90655631 319struct rcec_ea;
ee69439c 320
0aa0f5d1 321/* The pci_dev structure describes PCI devices */
1da177e4 322struct pci_dev {
0aa0f5d1
BH		 323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 326
0aa0f5d1
BH		 327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 329 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 330
0aa0f5d1 331 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 337 u8 revision; /* PCI revision, low byte of class word */
1da177e4 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 339#ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
db89ccbe 341 struct aer_stats *aer_stats; /* AER stats for this device */
90655631
SK		 342#endif
343#ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
507b460f 345 struct pci_dev *rcec; /* Associated RCEC device */
66b80809 346#endif
69139244 347 u32 devcap; /* PCIe Device Capabilities */
f7625980 348 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
f7625980 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 356
68da4e0e 357 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
4d57cdfa
FT		 364 struct device_dma_parameters dma_parms;
365
0aa0f5d1
BH		 366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
703860ed 369 u8 pm_cap; /* PM capability offset */
849846c4 370 unsigned int imm_ready:1; /* Supports Immediate Readiness */
337001b6
RW		 371 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 can be generated */
379021d5 373 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
e80bb09d 382 unsigned int wakeup_prepared:1;
d491f2b7 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
387 user sysfs */
4ec73791
SM		 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 bit manually */
3789af9a 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
448bd857 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 392
17423360 393 u16 l1ss; /* L1SS Capability pointer */
7d715a6c 394#ifdef CONFIG_PCIEASPM
f7625980 395 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 396 unsigned int ltr_path:1; /* Latency Tolerance Reporting
397 supported from root to here */
7d715a6c 398#endif
8c09e896 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
7ce3f912 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 401
0aa0f5d1
BH		 402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
1da177e4 404
0aa0f5d1 405 int cfg_size; /* Size of config space */
1da177e4
LT		 406
407 /*
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
410 */
411 unsigned int irq;
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
27829479 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
1da177e4 414
0aa0f5d1 415 bool match_driver; /* Skip attaching driver */
7e89efc6
DJ		 416 struct lock_class_key cfg_access_key;
417 struct lockdep_map cfg_access_lock;
0aa0f5d1
BH		 418
419 unsigned int transparent:1; /* Subtractive decode bridge */
51c48b31
BH		 420 unsigned int io_window:1; /* Bridge has I/O window */
421 unsigned int pref_window:1; /* Bridge has pref mem window */
422 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
0aa0f5d1
BH		 423 unsigned int multifunction:1; /* Multi-function device */
424
0aa0f5d1
BH		 425 unsigned int is_busmaster:1; /* Is busmaster */
426 unsigned int no_msi:1; /* May not use MSI */
f6b6aefe 427 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
0aa0f5d1
BH		 428 unsigned int block_cfg_access:1; /* Config space access blocked */
429 unsigned int broken_parity_status:1; /* Generates false positive parity */
430 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 431 unsigned int msi_enabled:1;
99dc804d 432 unsigned int msix_enabled:1;
0aa0f5d1
BH		 433 unsigned int ari_enabled:1; /* ARI forwarding */
434 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 435 unsigned int pasid_enabled:1; /* Process Address Space ID */
436 unsigned int pri_enabled:1; /* Page Request Interface */
3f35d2cf
TG		 437 unsigned int is_managed:1; /* Managed via devres */
438 unsigned int is_msi_managed:1; /* MSI release via devres installed */
0aa0f5d1 439 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 440 unsigned int state_saved:1;
d1b054da 441 unsigned int is_physfn:1;
dd7cc44d 442 unsigned int is_virtfn:1;
0aa0f5d1 443 unsigned int is_hotplug_bridge:1;
b03799b0 444 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
0aa0f5d1 445 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
617654aa
MW		 446 /*
447 * Devices marked being untrusted are the ones that can potentially
448 * execute DMA attacks and similar. They are typically connected
449 * through external ports such as Thunderbolt but not limited to
450 * that. When an IOMMU is enabled they should be getting full
451 * mappings to make sure they cannot access arbitrary memory.
452 */
453 unsigned int untrusted:1;
99b50be9
RJ		 454 /*
455 * Info from the platform, e.g., ACPI or device tree, may mark a
456 * device as "external-facing". An external-facing device is
457 * itself internal but devices downstream from it are external.
458 */
459 unsigned int external_facing:1;
0aa0f5d1
BH		 460 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
461 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 462 unsigned int irq_managed:1;
0aa0f5d1
BH		 463 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
464 unsigned int is_probed:1; /* Device probing in progress */
f0157160 465 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
aff68a5a 466 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
12856e7a 467 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
500b55b0 468 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
091f9f7f 469 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
ba698ad4 470 pci_dev_flags_t dev_flags;
bae94d02 471 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 472
5e70d0ac 473 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
0aa0f5d1 474 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 475 struct hlist_head saved_cap_space;
1da177e4 476 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 477 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 478
d22b3621
BH		 479#ifdef CONFIG_HOTPLUG_PCI_PCIE
480 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
481#endif
9bb04a0c 482#ifdef CONFIG_PCIE_PTM
a47126ec 483 u16 ptm_cap; /* PTM Capability */
9bb04a0c
JY		 484 unsigned int ptm_root:1;
485 unsigned int ptm_enabled:1;
8b2ec318 486 u8 ptm_granularity;
9bb04a0c 487#endif
ded86d8d 488#ifdef CONFIG_PCI_MSI
85aa607e 489 void __iomem *msix_base;
cd119b09 490 raw_spinlock_t msi_lock;
ded86d8d 491#endif
fd00faa3 492 struct pci_vpd vpd;
be06c1b4
BH		 493#ifdef CONFIG_PCIE_DPC
494 u16 dpc_cap;
495 unsigned int dpc_rp_extensions:1;
496 u8 dpc_rp_log_size;
497#endif
466b3ddf 498#ifdef CONFIG_PCI_ATS
dd7cc44d 499 union {
0aa0f5d1
BH		 500 struct pci_sriov *sriov; /* PF: SR-IOV info */
501 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 502 };
67930995
BH		 503 u16 ats_cap; /* ATS Capability offset */
504 u8 ats_stu; /* ATS Smallest Translation Unit */
4ebeb1ec
CT		 505#endif
506#ifdef CONFIG_PCI_PRI
c065190b 507 u16 pri_cap; /* PRI Capability offset */
4ebeb1ec 508 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
e5adf79a 509 unsigned int pasid_required:1; /* PRG Response PASID Required */
4ebeb1ec
CT		 510#endif
511#ifdef CONFIG_PCI_PASID
751035b8 512 u16 pasid_cap; /* PASID Capability offset */
4ebeb1ec 513 u16 pasid_features;
52916982
LG		 514#endif
515#ifdef CONFIG_PCI_P2PDMA
ae21f835 516 struct pci_p2pdma __rcu *p2pdma;
ac048403
LW		 517#endif
518#ifdef CONFIG_PCI_DOE
519 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
d1b054da 520#endif
52fbf5bd 521 u16 acs_cap; /* ACS Capability offset */
0aa0f5d1
BH		 522 phys_addr_t rom; /* Physical address if not from BAR */
523 size_t romlen; /* Length if not from BAR */
23d99baf
KK		 524 /*
525 * Driver name to force a match. Do not set directly, because core
526 * frees it. Use driver_set_override() to set or clear it.
527 */
528 const char *driver_override;
89ee9f76 529
0aa0f5d1 530 unsigned long priv_flags; /* Private flags for the PCI driver */
e20afa06
AN		 531
532 /* These methods index pci_reset_fn_methods[] */
533 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
1da177e4
LT		 534};
535
dda56549
Y		 536static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
537{
538#ifdef CONFIG_PCI_IOV
539 if (dev->is_virtfn)
540 dev = dev->physfn;
541#endif
dda56549
Y		 542 return dev;
543}
544
3c6e6ae7 545struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 546
1da177e4
LT		 547#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
548#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
549
a7369f1f
LV		 550static inline int pci_channel_offline(struct pci_dev *pdev)
551{
552 return (pdev->error_state != pci_channel_io_normal);
553}
554
15d82ca2
BF		 555/*
556 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
557 * Group number is limited to a 16-bit value, therefore (int)-1 is
558 * not a valid PCI domain number, and can be used as a sentinel
559 * value indicating ->domain_nr is not set by the driver (and
560 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
561 * pci_bus_find_domain_nr()).
562 */
563#define PCI_DOMAIN_NR_NOT_SET (-1)
564
5a21d70d 565struct pci_host_bridge {
0aa0f5d1
BH		 566 struct device dev;
567 struct pci_bus *bus; /* Root bus */
568 struct pci_ops *ops;
07e29295 569 struct pci_ops *child_ops;
0aa0f5d1
BH		 570 void *sysdata;
571 int busnr;
15d82ca2 572 int domain_nr;
14d76b68 573 struct list_head windows; /* resource_entry */
e80a91ad 574 struct list_head dma_ranges; /* dma ranges resource list */
0aa0f5d1 575 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 576 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 577 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 578 void *release_data;
0aa0f5d1
BH		 579 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
580 unsigned int no_ext_tags:1; /* No Extended Tags */
8b3517f8 581 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
02bfeb48 582 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 583 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 584 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 585 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 586 unsigned int native_ltr:1; /* OS may use PCIe LTR */
ac1c8e35 587 unsigned int native_dpc:1; /* OS may use PCIe DPC */
589c3357 588 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
a78cf965 589 unsigned int preserve_config:1; /* Preserve FW resource setup */
2c8d5a2d 590 unsigned int size_windows:1; /* Enable root bus sizing */
94e89b14 591 unsigned int msi_domain:1; /* Bridge wants MSI domain */
a78cf965 592
7c7a0e94
GP		 593 /* Resource alignment requirements */
594 resource_size_t (*align_resource)(struct pci_dev *dev,
595 const struct resource *res,
596 resource_size_t start,
597 resource_size_t size,
598 resource_size_t align);
914a1951 599 unsigned long private[] ____cacheline_aligned;
5a21d70d 600};
41017f0c 601
7b543663 602#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 603
59094065
TR		 604static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
605{
606 return (void *)bridge->private;
607}
608
609static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
610{
611 return container_of(priv, struct pci_host_bridge, private);
612}
613
a52d1443 614struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 615struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
616 size_t priv);
dff79b91 617void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 618struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
619
4fa2649a 620void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 621 void (*release_fn)(struct pci_host_bridge *),
622 void *release_data);
7b543663 623
6c0cc950
RW		 624int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
625
2fe2abf8
BH		 626/*
627 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
628 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
629 * buses below host bridges or subtractive decode bridges) go in the list.
630 * Use pci_bus_for_each_resource() to iterate through all the resources.
631 */
632
633/*
634 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
635 * and there's no way to program the bridge with the details of the window.
636 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
637 * decode bit set, because they are explicit and can be programmed with _SRS.
638 */
639#define PCI_SUBTRACTIVE_DECODE 0x1
640
641struct pci_bus_resource {
0aa0f5d1
BH		 642 struct list_head list;
643 struct resource *res;
644 unsigned int flags;
2fe2abf8 645};
4352dfd5
GKH		 646
647#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 648
649struct pci_bus {
0aa0f5d1
BH		 650 struct list_head node; /* Node in list of buses */
651 struct pci_bus *parent; /* Parent bus this bridge is on */
652 struct list_head children; /* List of child buses */
653 struct list_head devices; /* List of devices on this bus */
654 struct pci_dev *self; /* Bridge device as seen by parent */
655 struct list_head slots; /* List of slots on this bus;
67546762 656 protected by pci_slot_mutex */
2fe2abf8 657 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 658 struct list_head resources; /* Address space routed to this bus */
659 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 660
0aa0f5d1 661 struct pci_ops *ops; /* Configuration access functions */
0aa0f5d1
BH		 662 void *sysdata; /* Hook for sys-specific extension */
663 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 664
0aa0f5d1
BH		 665 unsigned char number; /* Bus number */
666 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 667 unsigned char max_bus_speed; /* enum pci_bus_speed */
668 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 669#ifdef CONFIG_PCI_DOMAINS_GENERIC
670 int domain_nr;
671#endif
1da177e4
LT		 672
673 char name[48];
674
0aa0f5d1
BH		 675 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
676 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 677 struct device *bridge;
fd7d1ced 678 struct device dev;
0aa0f5d1
BH		 679 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
680 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 681 unsigned int is_added:1;
92c45b63 682 unsigned int unsafe_warn:1; /* warned about RW1C config write */
1da177e4
LT		 683};
684
fd7d1ced 685#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 686
4e544bac
HK		 687static inline u16 pci_dev_id(struct pci_dev *dev)
688{
689 return PCI_DEVID(dev->bus->number, dev->devfn);
690}
691
79af72d7 692/*
f7625980 693 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 694 * false otherwise
77a0dfcd
BH		 695 *
696 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
697 * This is incorrect because "virtual" buses added for SR-IOV (via
698 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 699 */
700static inline bool pci_is_root_bus(struct pci_bus *pbus)
701{
702 return !(pbus->parent);
703}
704
1c86438c
YW		 705/**
706 * pci_is_bridge - check if the PCI device is a bridge
707 * @dev: PCI device
708 *
709 * Return true if the PCI device is bridge whether it has subordinate
710 * or not.
711 */
712static inline bool pci_is_bridge(struct pci_dev *dev)
713{
714 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
715 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
716}
717
7e845ecb
SJ		 718/**
719 * pci_is_vga - check if the PCI device is a VGA device
2db6b72c 720 * @pdev: PCI device
7e845ecb
SJ		 721 *
722 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
723 * VGA Base Class and Sub-Classes:
724 *
725 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
726 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
727 *
728 * Return true if the PCI device is a VGA device and uses the legacy VGA
729 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
730 * aliases).
731 */
732static inline bool pci_is_vga(struct pci_dev *pdev)
733{
734 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
735 return true;
736
737 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
738 return true;
739
740 return false;
741}
742
24a0c654
AS		 743#define for_each_pci_bridge(dev, bus) \
744 list_for_each_entry(dev, &bus->devices, bus_list) \
745 if (!pci_is_bridge(dev)) {} else
746
c6bde215
BH		 747static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
748{
749 dev = pci_physfn(dev);
750 if (pci_is_root_bus(dev->bus))
751 return NULL;
752
753 return dev->bus->self;
754}
755
16cf0ebc
RW		 756#ifdef CONFIG_PCI_MSI
757static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
758{
759 return pci_dev->msi_enabled || pci_dev->msix_enabled;
760}
761#else
762static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
763#endif
764
0aa0f5d1 765/* Error values that may be returned by PCI functions */
1da177e4
LT		 766#define PCIBIOS_SUCCESSFUL 0x00
767#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
768#define PCIBIOS_BAD_VENDOR_ID 0x83
769#define PCIBIOS_DEVICE_NOT_FOUND 0x86
770#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
771#define PCIBIOS_SET_FAILED 0x88
772#define PCIBIOS_BUFFER_TOO_SMALL 0x89
773
0aa0f5d1 774/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 775static inline int pcibios_err_to_errno(int err)
776{
777 if (err <= PCIBIOS_SUCCESSFUL)
778 return err; /* Assume already errno */
779
780 switch (err) {
781 case PCIBIOS_FUNC_NOT_SUPPORTED:
782 return -ENOENT;
783 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 784 return -ENOTTY;
a6961651
AW		 785 case PCIBIOS_DEVICE_NOT_FOUND:
786 return -ENODEV;
787 case PCIBIOS_BAD_REGISTER_NUMBER:
788 return -EFAULT;
789 case PCIBIOS_SET_FAILED:
790 return -EIO;
791 case PCIBIOS_BUFFER_TOO_SMALL:
792 return -ENOSPC;
793 }
794
d97ffe23 795 return -ERANGE;
a6961651
AW		 796}
797
1da177e4
LT		 798/* Low-level architecture-dependent routines */
799
800struct pci_ops {
057bd2e0
TR		 801 int (*add_bus)(struct pci_bus *bus);
802 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 803 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 804 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
805 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
806};
807
b6ce068a
MW		 808/*
809 * ACPI needs to be able to access PCI config space before we've done a
810 * PCI bus scan and created pci_bus structures.
811 */
f39d5b72
BH		 812int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
813 int reg, int len, u32 *val);
814int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
815 int reg, int len, u32 val);
1da177e4 816
8e639079 817#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 818typedef u64 pci_bus_addr_t;
819#else
820typedef u32 pci_bus_addr_t;
821#endif
822
1da177e4 823struct pci_bus_region {
0aa0f5d1
BH		 824 pci_bus_addr_t start;
825 pci_bus_addr_t end;
1da177e4
LT		 826};
827
828struct pci_dynids {
0aa0f5d1
BH		 829 spinlock_t lock; /* Protects list, index */
830 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 831};
832
f7625980
BH		 833
834/*
835 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
836 * a set of callbacks in struct pci_error_handlers, that device driver
837 * will be notified of PCI bus errors, and will be driven to recovery
838 * when an error occurs.
392a1ce7 839 */
840
841typedef unsigned int __bitwise pci_ers_result_t;
842
843enum pci_ers_result {
0aa0f5d1 844 /* No result/none/not supported in device driver */
392a1ce7 845 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
846
847 /* Device driver can recover without slot reset */
848 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
849
0aa0f5d1 850 /* Device driver wants slot to be reset */
392a1ce7 851 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
852
853 /* Device has completely failed, is unrecoverable */
854 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
855
856 /* Device driver is fully recovered and operational */
857 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 858
859 /* No AER capabilities registered for the driver */
860 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 861};
862
863/* PCI bus error event callbacks */
05cca6e5 864struct pci_error_handlers {
392a1ce7 865 /* PCI bus error detected on this device */
866 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
16d79cd4 867 pci_channel_state_t error);
392a1ce7 868
869 /* MMIO has been re-enabled, but not DMA */
870 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
871
392a1ce7 872 /* PCI slot has been reset */
873 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
874
3ebe7f9f 875 /* PCI function reset prepare or completed */
775755ed
CH		 876 void (*reset_prepare)(struct pci_dev *dev);
877 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 878
392a1ce7 879 /* Device driver may resume normal operations */
880 void (*resume)(struct pci_dev *dev);
361187e0
DJ		 881
882 /* Allow device driver to record more details of a correctable error */
883 void (*cor_error_detected)(struct pci_dev *dev);
392a1ce7 884};
885
392a1ce7 886
1da177e4 887struct module;
229b4e07
CD		 888
889/**
890 * struct pci_driver - PCI driver structure
229b4e07
CD		 891 * @name: Driver name.
892 * @id_table: Pointer to table of device IDs the driver is
893 * interested in. Most drivers should export this
894 * table using MODULE_DEVICE_TABLE(pci,...).
895 * @probe: This probing function gets called (during execution
896 * of pci_register_driver() for already existing
897 * devices or later if a new device gets inserted) for
898 * all PCI devices which match the ID table and are not
899 * "owned" by the other drivers yet. This function gets
900 * passed a "struct pci_dev \*" for each device whose
901 * entry in the ID table matches the device. The probe
902 * function returns zero when the driver chooses to
903 * take "ownership" of the device or an error code
904 * (negative number) otherwise.
905 * The probe function always gets called from process
906 * context, so it can sleep.
907 * @remove: The remove() function gets called whenever a device
908 * being handled by this driver is removed (either during
909 * deregistration of the driver or when it's manually
910 * pulled out of a hot-pluggable slot).
911 * The remove function always gets called from process
912 * context, so it can sleep.
913 * @suspend: Put device into low power state.
229b4e07 914 * @resume: Wake device from low power state.
151f4e2b 915 * (Please see Documentation/power/pci.rst for descriptions
229b4e07
CD		 916 * of PCI Power Management and the related functions.)
917 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
918 * Intended to stop any idling DMA operations.
919 * Useful for enabling wake-on-lan (NIC) or changing
920 * the power state of a device before reboot.
921 * e.g. drivers/net/e100.c.
922 * @sriov_configure: Optional driver callback to allow configuration of
923 * number of VFs to enable via sysfs "sriov_numvfs" file.
c3d5c2d9
LR		 924 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
925 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
926 * This will change MSI-X Table Size in the VF Message Control
927 * registers.
928 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
929 * MSI-X vectors available for distribution to the VFs.
229b4e07
CD		 930 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
931 * @groups: Sysfs attribute groups.
ded13b9c
AG		 932 * @dev_groups: Attributes attached to the device that will be
933 * created once it is bound to the driver.
229b4e07
CD		 934 * @driver: Driver model structure.
935 * @dynids: List of dynamically added device IDs.
512881ea
LB		 936 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
937 * For most device drivers, no need to care about this flag
938 * as long as all DMAs are handled through the kernel DMA API.
939 * For some special ones, for example VFIO drivers, they know
940 * how to manage the DMA themselves and set this flag so that
941 * the IOMMU layer will allow them to setup and manage their
942 * own I/O address space.
229b4e07 943 */
1da177e4 944struct pci_driver {
0aa0f5d1
BH		 945 const char *name;
946 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
947 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
948 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
949 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
7cb30264
BY		 950 int (*resume)(struct pci_dev *dev); /* Device woken up */
951 void (*shutdown)(struct pci_dev *dev);
952 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
c3d5c2d9
LR		 953 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
954 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
49453028 955 const struct pci_error_handlers *err_handler;
92d50fc1 956 const struct attribute_group **groups;
ded13b9c 957 const struct attribute_group **dev_groups;
1da177e4 958 struct device_driver driver;
0aa0f5d1 959 struct pci_dynids dynids;
512881ea 960 bool driver_managed_dma;
1da177e4
LT		 961};
962
8e9028b3
BH		 963static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
964{
965 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
966}
1da177e4
LT		 967
968/**
0aa0f5d1 969 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 970 * @vend: the 16 bit PCI Vendor ID
971 * @dev: the 16 bit PCI Device ID
972 *
973 * This macro is used to create a struct pci_device_id that matches a
974 * specific device. The subvendor and subdevice fields will be set to
975 * PCI_ANY_ID.
976 */
977#define PCI_DEVICE(vend,dev) \
978 .vendor = (vend), .device = (dev), \
979 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
980
343b7258
MG		 981/**
982 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
983 * override_only flags.
984 * @vend: the 16 bit PCI Vendor ID
985 * @dev: the 16 bit PCI Device ID
986 * @driver_override: the 32 bit PCI Device override_only
987 *
988 * This macro is used to create a struct pci_device_id that matches only a
989 * driver_override device. The subvendor and subdevice fields will be set to
990 * PCI_ANY_ID.
991 */
992#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
993 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
994 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
995
cc6711b0
MG		 996/**
997 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
998 * "driver_override" PCI device.
999 * @vend: the 16 bit PCI Vendor ID
1000 * @dev: the 16 bit PCI Device ID
1001 *
1002 * This macro is used to create a struct pci_device_id that matches a
1003 * specific device. The subvendor and subdevice fields will be set to
1004 * PCI_ANY_ID and the driver_override will be set to
1005 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1006 */
1007#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1008 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1009
3d567e0e 1010/**
0aa0f5d1 1011 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 1012 * @vend: the 16 bit PCI Vendor ID
1013 * @dev: the 16 bit PCI Device ID
1014 * @subvend: the 16 bit PCI Subvendor ID
1015 * @subdev: the 16 bit PCI Subdevice ID
1016 *
1017 * This macro is used to create a struct pci_device_id that matches a
1018 * specific device with subsystem information.
1019 */
1020#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1021 .vendor = (vend), .device = (dev), \
1022 .subvendor = (subvend), .subdevice = (subdev)
1023
1da177e4 1024/**
0aa0f5d1 1025 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 1026 * @dev_class: the class, subclass, prog-if triple for this device
1027 * @dev_class_mask: the class mask for this device
1028 *
1029 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 1030 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 1031 * fields will be set to PCI_ANY_ID.
1032 */
1033#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1034 .class = (dev_class), .class_mask = (dev_class_mask), \
1035 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1036 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1037
1597cacb 1038/**
0aa0f5d1 1039 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 1040 * @vend: the vendor name
1041 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 1042 *
1043 * This macro is used to create a struct pci_device_id that matches a
1044 * specific PCI device. The subvendor, and subdevice fields will be set
1045 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1046 * private data.
1047 */
c1309040
MR		 1048#define PCI_VDEVICE(vend, dev) \
1049 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1050 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 1051
b72ae8ca
AS		 1052/**
1053 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1054 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1055 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1056 * @data: the driver data to be filled
1057 *
1058 * This macro is used to create a struct pci_device_id that matches a
1059 * specific PCI device. The subvendor, and subdevice fields will be set
1060 * to PCI_ANY_ID.
1061 */
1062#define PCI_DEVICE_DATA(vend, dev, data) \
1063 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1064 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1065 .driver_data = (kernel_ulong_t)(data)
1066
5bbe029f 1067enum {
0aa0f5d1
BH		 1068 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1069 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1070 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1071 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1072 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 1073 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 1074 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 1075};
1076
58ff9c5a 1077#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
0d8006dd
HX		 1078#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1079#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1080#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1081
58ff9c5a
BH		 1082#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* Deprecated! Use PCI_IRQ_INTX */
1083
0aa0f5d1 1084/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 1085#ifdef CONFIG_PCI
1086
5bbe029f
BH		 1087extern unsigned int pci_flags;
1088
1089static inline void pci_set_flags(int flags) { pci_flags = flags; }
1090static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1091static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1092static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1093
a58674ff 1094void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 1095
1096enum pcie_bus_config_types {
0aa0f5d1
BH		 1097 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1098 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1099 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1100 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1101 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 1102};
1103
1104extern enum pcie_bus_config_types pcie_bus_config;
1105
1da177e4
LT		 1106extern struct bus_type pci_bus_type;
1107
f7625980
BH		 1108/* Do NOT directly access these two variables, unless you are arch-specific PCI
1109 * code, or PCI core code. */
0aa0f5d1 1110extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 1111/* Some device drivers need know if PCI is initiated */
f39d5b72 1112int no_pci_devices(void);
1da177e4 1113
3c449ed0 1114void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 1115void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 1116void pcibios_add_bus(struct pci_bus *bus);
1117void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 1118void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 1119int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 1120/* Architecture-specific versions may override this (weak) */
05cca6e5 1121char *pcibios_setup(char *str);
1da177e4
LT		 1122
1123/* Used only when drivers/pci/setup.c is used */
3b7a17fc 1124resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 1125 resource_size_t,
e31dd6e4 1126 resource_size_t);
1da177e4 1127
d1bbf38a 1128/* Weak but can be overridden by arch */
2d1c8618
BH		 1129void pci_fixup_cardbus(struct pci_bus *);
1130
1da177e4
LT		 1131/* Generic PCI functions used internally */
1132
fc279850 1133void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 1134 struct resource *res);
fc279850 1135void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 1136 struct pci_bus_region *region);
d1fd4fb6 1137void pcibios_scan_specific_bus(int busn);
f39d5b72 1138struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 1139void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 1140struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 1141struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1142 struct pci_ops *ops, void *sysdata,
1143 struct list_head *resources);
49b8e3f3 1144int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 1145int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1146int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1147void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 1148struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 1149 struct pci_ops *ops, void *sysdata,
1150 struct list_head *resources);
1228c4b6 1151int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 1152struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1153 int busnr);
f46753c5 1154struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 1155 const char *name,
1156 struct hotplug_slot *hotplug);
f46753c5 1157void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 1158#ifdef CONFIG_SYSFS
1159void pci_dev_assign_slot(struct pci_dev *dev);
1160#else
1161static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1162#endif
1da177e4 1163int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 1164struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 1165void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 1166unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 1167void pci_bus_add_device(struct pci_dev *dev);
1da177e4 1168void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 1169struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1170 struct resource *res);
3df425f3 1171u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 1172int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 1173u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 1174struct pci_dev *pci_dev_get(struct pci_dev *dev);
1175void pci_dev_put(struct pci_dev *dev);
ced085ef 1176DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T))
f39d5b72
BH		 1177void pci_remove_bus(struct pci_bus *b);
1178void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 1179void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 1180void pci_stop_root_bus(struct pci_bus *bus);
1181void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 1182void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 1183void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 1184void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 1185#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1186#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 1187
1188/* Generic PCI functions exported to card drivers */
1189
f646c2a0
PM		 1190u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1191u8 pci_find_capability(struct pci_dev *dev, int cap);
1192u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1193u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1194u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
ee8b1c47
BH		 1195u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1196u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
29f3eb64 1197struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
c124fd9a 1198u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
ee122037 1199u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1da177e4 1200
70c0923b
JK		 1201u64 pci_get_dsn(struct pci_dev *dev);
1202
d42552c3 1203struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 1204 struct pci_dev *from);
05cca6e5 1205struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 1206 unsigned int ss_vendor, unsigned int ss_device,
1207 struct pci_dev *from);
05cca6e5 1208struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 1209struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1210 unsigned int devfn);
05cca6e5 1211struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
d427da23
SJ		 1212struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1213
1da177e4
LT		 1214int pci_dev_present(const struct pci_device_id *ids);
1215
05cca6e5
GKH		 1216int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1217 int where, u8 *val);
1218int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1219 int where, u16 *val);
1220int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1221 int where, u32 *val);
1222int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1223 int where, u8 val);
1224int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1225 int where, u16 val);
1226int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1227 int where, u32 val);
1f94a94f
RH		 1228
1229int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1230 int where, int size, u32 *val);
1231int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1232 int where, int size, u32 val);
1233int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1234 int where, int size, u32 *val);
1235int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1236 int where, int size, u32 val);
1237
a72b46c3 1238struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1239
d3881e50
KB		 1240int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1241int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1242int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1243int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1244int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1245int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
ac160871
SX		 1246void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1247 u32 clear, u32 set);
1da177e4 1248
8c0d3a02
JL		 1249int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1250int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1251int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1252int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
5e70d0ac
IJ		 1253int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1254 u16 clear, u16 set);
1255int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1256 u16 clear, u16 set);
8c0d3a02
JL		 1257int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1258 u32 clear, u32 set);
1259
5e70d0ac
IJ		 1260/**
1261 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1262 * @dev: PCI device structure of the PCI Express device
1263 * @pos: PCI Express Capability Register
1264 * @clear: Clear bitmask
1265 * @set: Set bitmask
1266 *
1267 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1268 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1269 * Capability Registers are accessed concurrently in RMW fashion, hence
1270 * require locking which is handled transparently to the caller.
1271 */
1272static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1273 int pos,
1274 u16 clear, u16 set)
1275{
1276 switch (pos) {
1277 case PCI_EXP_LNKCTL:
1278 case PCI_EXP_RTCTL:
1279 return pcie_capability_clear_and_set_word_locked(dev, pos,
1280 clear, set);
1281 default:
1282 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1283 clear, set);
1284 }
1285}
1286
8c0d3a02
JL		 1287static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1288 u16 set)
1289{
1290 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1291}
1292
1293static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1294 u32 set)
1295{
1296 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1297}
1298
1299static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1300 u16 clear)
1301{
1302 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1303}
1304
1305static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1306 u32 clear)
1307{
1308 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1309}
1310
0aa0f5d1 1311/* User-space driven config access */
c63587d7
AW		 1312int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1313int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1314int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1315int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1316int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1317int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1318
4a7fb636 1319int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1320int __must_check pci_enable_device_io(struct pci_dev *dev);
1321int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1322int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1323int __must_check pcim_enable_device(struct pci_dev *pdev);
1324void pcim_pin_device(struct pci_dev *pdev);
1325
99b3c58f
PG		 1326static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1327{
1328 /*
1329 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1330 * writable and no quirk has marked the feature broken.
1331 */
1332 return !pdev->broken_intx_masking;
1333}
1334
296ccb08
YS		 1335static inline int pci_is_enabled(struct pci_dev *pdev)
1336{
1337 return (atomic_read(&pdev->enable_cnt) > 0);
1338}
1339
9ac7849e
TH		 1340static inline int pci_is_managed(struct pci_dev *pdev)
1341{
1342 return pdev->is_managed;
1343}
1344
1da177e4 1345void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1346
1347extern unsigned int pcibios_max_latency;
1da177e4 1348void pci_set_master(struct pci_dev *dev);
6a479079 1349void pci_clear_master(struct pci_dev *dev);
96c55900 1350
f7bdd12d 1351int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1352int pci_set_cacheline_size(struct pci_dev *dev);
4a7fb636 1353int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1354int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1355int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1356void pci_clear_mwi(struct pci_dev *dev);
1fd3dde5 1357void pci_disable_parity(struct pci_dev *dev);
a04ce0ff 1358void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1359bool pci_check_and_mask_intx(struct pci_dev *dev);
1360bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1361int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1362int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1363int pcix_get_max_mmrbc(struct pci_dev *dev);
1364int pcix_get_mmrbc(struct pci_dev *dev);
1365int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1366int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1367int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1368int pcie_get_mps(struct pci_dev *dev);
1369int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1370u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1371 enum pci_bus_speed *speed,
1372 enum pcie_link_width *width);
4d07a053 1373int pcie_link_speed_mbps(struct pci_dev *pdev);
9e506a7b 1374void pcie_print_link_status(struct pci_dev *dev);
9bdc81ce 1375int pcie_reset_flr(struct pci_dev *dev, bool probe);
91295d79 1376int pcie_flr(struct pci_dev *dev);
a96d627a 1377int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1378int pci_reset_function(struct pci_dev *dev);
a477b9cd 1379int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1380int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1381int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1382int pci_probe_reset_bus(struct pci_bus *bus);
c6a44ba9 1383int pci_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1384void pci_reset_secondary_bus(struct pci_dev *dev);
1385void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1386void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1387int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1388int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3 1389void pci_release_resource(struct pci_dev *dev, int resno);
192f1bf7
ND		 1390static inline int pci_rebar_bytes_to_size(u64 bytes)
1391{
1392 bytes = roundup_pow_of_two(bytes);
1393
1394 /* Return BAR size as defined in the resizable BAR specification */
1395 return max(ilog2(bytes), 20) - 20;
1396}
1397
8fbdbb66 1398u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
8bb705e3 1399int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1400int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1401bool pci_device_is_present(struct pci_dev *pdev);
08249651 1402void pci_ignore_hotplug(struct pci_dev *dev);
2856ba60 1403struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
ec5d9e87 1404int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1da177e4 1405
704e8953
CH		 1406int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1407 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1408 const char *fmt, ...);
1409void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1410
1da177e4 1411/* ROM control related routines */
e416de5e
AC		 1412int pci_enable_rom(struct pci_dev *pdev);
1413void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1414void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1415void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1da177e4
LT		 1416
1417/* Power management related routines */
1418int pci_save_state(struct pci_dev *dev);
1d3c16a8 1419void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1420struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1421int pci_load_saved_state(struct pci_dev *dev,
1422 struct pci_saved_state *state);
ffbdd3f7
AW		 1423int pci_load_and_free_saved_state(struct pci_dev *dev,
1424 struct pci_saved_state **state);
d6aa37cd 1425int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee 1426int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1e560864 1427int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state);
9c8550ee 1428pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1429bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1430void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1431int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1432int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1433int pci_prepare_to_sleep(struct pci_dev *dev);
1434int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1435bool pci_dev_run_wake(struct pci_dev *dev);
9d26d3a8
MW		 1436void pci_d3cold_enable(struct pci_dev *dev);
1437void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1438bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
99efde6c 1439void pci_resume_bus(struct pci_bus *bus);
2a4d2c42 1440void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1441
bb209c82
BH		 1442/* For use by arch with custom probe code */
1443void set_pcie_port_type(struct pci_dev *pdev);
1444void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1445
ce5ccdef 1446/* Functions for PCI Hotplug drivers to use */
2f320521 1447unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1448unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1449void pci_lock_rescan_remove(void);
1450void pci_unlock_rescan_remove(void);
ce5ccdef 1451
0aa0f5d1 1452/* Vital Product Data routines */
287d19ce
SH		 1453ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1454ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
bf2928c7
HK		 1455ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1456ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
287d19ce 1457
1da177e4 1458/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1459resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1460void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1461void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1462void pci_bus_size_bridges(struct pci_bus *bus);
1463int pci_claim_resource(struct pci_dev *, int);
8505e729 1464int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1465void pci_assign_unassigned_resources(void);
6841ec68 1466void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1467void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1468void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1469int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
842de40d 1470int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1471void pci_assign_irq(struct pci_dev *dev);
afd29f90 1472struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1473#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1474int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1475int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1476void pci_release_regions(struct pci_dev *);
4a7fb636 1477int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 1478void pci_release_region(struct pci_dev *, int);
c87deff7 1479int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1480int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1481void pci_release_selected_regions(struct pci_dev *, int);
1da177e4 1482
27829479
IW		 1483static inline __must_check struct resource *
1484pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1485 unsigned int len, const char *name)
1486{
1487 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1488 name, IORESOURCE_EXCLUSIVE);
1489}
1490
1491static inline void pci_release_config_region(struct pci_dev *pdev,
1492 unsigned int offset,
1493 unsigned int len)
1494{
1495 __release_region(&pdev->driver_exclusive_resource, offset, len);
1496}
1497
1da177e4 1498/* drivers/pci/bus.c */
45ca9e97 1499void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1500void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1501 resource_size_t offset);
45ca9e97 1502void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1503void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1504 unsigned int flags);
2fe2abf8
BH		 1505struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1506void pci_bus_remove_resources(struct pci_bus *bus);
ab909509 1507void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
950334bc
BH		 1508int devm_request_pci_bus_resources(struct device *dev,
1509 struct list_head *resources);
2fe2abf8 1510
bfc45606
DD		 1511/* Temporary until new and working PCI SBR API in place */
1512int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1513
02992064
AS		 1514#define __pci_bus_for_each_res0(bus, res, ...) \
1515 for (unsigned int __b = 0; \
1516 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1517 __b++)
1518
1519#define __pci_bus_for_each_res1(bus, res, __b) \
1520 for (__b = 0; \
1521 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1522 __b++)
1523
ceb928be
AS		 1524/**
1525 * pci_bus_for_each_resource - iterate over PCI bus resources
1526 * @bus: the PCI bus
1527 * @res: pointer to the current resource
02992064 1528 * @...: optional index of the current resource
ceb928be
AS		 1529 *
1530 * Iterate over PCI bus resources. The first part is to go over PCI bus
1531 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1532 * After that continue with the separate list of the additional resources,
1533 * if not empty. That's why the Logical OR is being used.
1534 *
1535 * Possible usage:
1536 *
1537 * struct pci_bus *bus = ...;
1538 * struct resource *res;
1539 * unsigned int i;
1540 *
02992064 1541 * // With optional index
ceb928be
AS		 1542 * pci_bus_for_each_resource(bus, res, i)
1543 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
02992064
AS		 1544 *
1545 * // Without index
1546 * pci_bus_for_each_resource(bus, res)
1547 * _do_something_(res);
ceb928be 1548 */
02992064
AS		 1549#define pci_bus_for_each_resource(bus, res, ...) \
1550 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1551 (bus, res, __VA_ARGS__)
89a74ecc 1552
4a7fb636
AM		 1553int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1554 struct resource *res, resource_size_t size,
1555 resource_size_t align, resource_size_t min,
664c2848 1556 unsigned long type_mask,
3b7a17fc
DB		 1557 resource_size_t (*alignf)(void *,
1558 const struct resource *,
b26b2d49
DB		 1559 resource_size_t,
1560 resource_size_t),
4a7fb636 1561 void *alignf_data);
1da177e4 1562
8b921acf 1563
fcfaab30
GP		 1564int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1565 resource_size_t size);
c5076cfe
TN		 1566unsigned long pci_address_to_pio(phys_addr_t addr);
1567phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1568int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
a5fb9fb0
SS		 1569int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1570 phys_addr_t phys_addr);
4d3f1384 1571void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1572void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1573 resource_size_t offset,
1574 resource_size_t size);
1575void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1576 struct resource *res);
8b921acf 1577
3a9ad0b4 1578static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1579{
1580 struct pci_bus_region region;
1581
1582 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1583 return region.start;
1584}
1585
863b18f4 1586/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1587int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1588 const char *mod_name);
bba81165 1589
0aa0f5d1 1590/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1591#define pci_register_driver(driver) \
1592 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1593
05cca6e5 1594void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1595
1596/**
1597 * module_pci_driver() - Helper macro for registering a PCI driver
1598 * @__pci_driver: pci_driver struct
1599 *
1600 * Helper macro for PCI drivers which do not do anything special in module
1601 * init/exit. This eliminates a lot of boilerplate. Each module may only
1602 * use this macro once, and calling it replaces module_init() and module_exit()
1603 */
1604#define module_pci_driver(__pci_driver) \
0aa0f5d1 1605 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1606
b4eb6cdb
PG		 1607/**
1608 * builtin_pci_driver() - Helper macro for registering a PCI driver
1609 * @__pci_driver: pci_driver struct
1610 *
1611 * Helper macro for PCI drivers which do not do anything special in their
1612 * init code. This eliminates a lot of boilerplate. Each driver may only
1613 * use this macro once, and calling it replaces device_initcall(...)
1614 */
1615#define builtin_pci_driver(__pci_driver) \
1616 builtin_driver(__pci_driver, pci_register_driver)
1617
05cca6e5 1618struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1619int pci_add_dynid(struct pci_driver *drv,
1620 unsigned int vendor, unsigned int device,
1621 unsigned int subvendor, unsigned int subdevice,
1622 unsigned int class, unsigned int class_mask,
1623 unsigned long driver_data);
05cca6e5
GKH		 1624const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1625 struct pci_dev *dev);
1626int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1627 int pass);
1da177e4 1628
70298c6e 1629void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1630 void *userdata);
1e560864
JH		 1631void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1632 void *userdata);
ac7dc65a 1633int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1634unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1635void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1636resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1637 unsigned long type);
cecf4864 1638
3448a19d
DA		 1639#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1640#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1641
deb2d2ec 1642int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1643 unsigned int command_bits, u32 flags);
fe537670 1644
d7cc609f
LG		 1645/*
1646 * Virtual interrupts allow for more interrupts to be allocated
1647 * than the device has interrupts for. These are not programmed
1648 * into the device's MSI-X table and must be handled by some
1649 * other driver means.
1650 */
1651#define PCI_IRQ_VIRTUAL (1 << 4)
1652
4fe0d154
CH		 1653#define PCI_IRQ_ALL_TYPES \
1654 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1655
1da177e4
LT		 1656#include <linux/dmapool.h>
1657
1da177e4 1658struct msix_entry {
0aa0f5d1
BH		 1659 u32 vector; /* Kernel uses to write allocated vector */
1660 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1661};
1662
41efa431
RC		 1663struct msi_domain_template;
1664
4c859804
BH		 1665#ifdef CONFIG_PCI_MSI
1666int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1667void pci_disable_msi(struct pci_dev *dev);
4c859804 1668int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1669void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1670void pci_restore_msi_state(struct pci_dev *dev);
1671int pci_msi_enabled(void);
4fe03955 1672int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1673int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1674 int minvec, int maxvec);
f7fc32cb
AG		 1675static inline int pci_enable_msix_exact(struct pci_dev *dev,
1676 struct msix_entry *entries, int nvec)
1677{
1678 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1679 if (rc < 0)
1680 return rc;
1681 return 0;
1682}
5c0997dc
AD		 1683int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1684 unsigned int max_vecs, unsigned int flags);
402723ad
CH		 1685int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1686 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1687 struct irq_affinity *affd);
402723ad 1688
34026364
TG		 1689bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1690struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1691 const struct irq_affinity_desc *affdesc);
1692void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1693
aff17164
CH		 1694void pci_free_irq_vectors(struct pci_dev *dev);
1695int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1696const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
41efa431
RC		 1697bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
1698 unsigned int hwsize, void *data);
1699struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
1700 const struct irq_affinity_desc *affdesc);
1701void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
aff17164 1702
4c859804 1703#else
2ee546c4 1704static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1705static inline void pci_disable_msi(struct pci_dev *dev) { }
1706static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1707static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1708static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1709static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1710static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1711{ return -ENOSYS; }
302a2523 1712static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1713 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1714{ return -ENOSYS; }
f7fc32cb 1715static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1716 struct msix_entry *entries, int nvec)
f7fc32cb 1717{ return -ENOSYS; }
402723ad
CH		 1718
1719static inline int
1720pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1721 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1722 struct irq_affinity *aff_desc)
aff17164 1723{
83b4605b
CH		 1724 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1725 return 1;
1726 return -ENOSPC;
aff17164 1727}
5c0997dc
AD		 1728static inline int
1729pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1730 unsigned int max_vecs, unsigned int flags)
1731{
1732 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1733 flags, NULL);
1734}
402723ad 1735
195d8e5d
RC		 1736static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1737{ return false; }
2b129f0b
RC		 1738static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1739 const struct irq_affinity_desc *affdesc)
1740{
1741 struct msi_map map = { .index = -ENOSYS, };
1742
1743 return map;
1744}
1745
1746static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1747{
1748}
1749
aff17164
CH		 1750static inline void pci_free_irq_vectors(struct pci_dev *dev)
1751{
1752}
1753
1754static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1755{
1756 if (WARN_ON_ONCE(nr > 0))
1757 return -EINVAL;
1758 return dev->irq;
1759}
ee8d41e5
TG		 1760static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1761 int vec)
1762{
1763 return cpu_possible_mask;
1764}
41efa431
RC		 1765
1766static inline bool pci_create_ims_domain(struct pci_dev *pdev,
1767 const struct msi_domain_template *template,
1768 unsigned int hwsize, void *data)
1769{ return false; }
1770
1771static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev,
1772 union msi_instance_cookie *icookie,
1773 const struct irq_affinity_desc *affdesc)
1774{
1775 struct msi_map map = { .index = -ENOSYS, };
1776
1777 return map;
1778}
1779
1780static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map)
1781{
1782}
1783
1da177e4
LT		 1784#endif
1785
0d58e6c1
PB		 1786/**
1787 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1788 * @d: the INTx IRQ domain
1789 * @node: the DT node for the device whose interrupt we're translating
1790 * @intspec: the interrupt specifier data from the DT
1791 * @intsize: the number of entries in @intspec
1792 * @out_hwirq: pointer at which to write the hwirq number
1793 * @out_type: pointer at which to write the interrupt type
1794 *
1795 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1796 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1797 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1798 * INTx value to obtain the hwirq number.
1799 *
1800 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1801 */
1802static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1803 struct device_node *node,
1804 const u32 *intspec,
1805 unsigned int intsize,
1806 unsigned long *out_hwirq,
1807 unsigned int *out_type)
1808{
1809 const u32 intx = intspec[0];
1810
1811 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1812 return -EINVAL;
1813
1814 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1815 return 0;
1816}
1817
ab0724ff 1818#ifdef CONFIG_PCIEPORTBUS
415e12b2 1819extern bool pcie_ports_disabled;
5352a44a 1820extern bool pcie_ports_native;
ab0724ff
MT		 1821#else
1822#define pcie_ports_disabled true
5352a44a 1823#define pcie_ports_native false
ab0724ff 1824#endif
415e12b2 1825
aff5d055
HK		 1826#define PCIE_LINK_STATE_L0S BIT(0)
1827#define PCIE_LINK_STATE_L1 BIT(1)
1828#define PCIE_LINK_STATE_CLKPM BIT(2)
1829#define PCIE_LINK_STATE_L1_1 BIT(3)
1830#define PCIE_LINK_STATE_L1_2 BIT(4)
1831#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1832#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
de82f60f
MB		 1833#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
1834 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
1835 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
1836 PCIE_LINK_STATE_L1_2_PCIPM)
7ce2e76a 1837
4c859804 1838#ifdef CONFIG_PCIEASPM
7ce2e76a
KW		 1839int pci_disable_link_state(struct pci_dev *pdev, int state);
1840int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
de82f60f 1841int pci_enable_link_state(struct pci_dev *pdev, int state);
718ab822 1842int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
7ce2e76a 1843void pcie_no_aspm(void);
f39d5b72 1844bool pcie_aspm_support_enabled(void);
accd2dd7 1845bool pcie_aspm_enabled(struct pci_dev *pdev);
4c859804 1846#else
7ce2e76a
KW		 1847static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1848{ return 0; }
1849static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1850{ return 0; }
de82f60f
MB		 1851static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1852{ return 0; }
718ab822
JH		 1853static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1854{ return 0; }
7ce2e76a 1855static inline void pcie_no_aspm(void) { }
4c859804 1856static inline bool pcie_aspm_support_enabled(void) { return false; }
accd2dd7 1857static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
3e1b1600
AP		 1858#endif
1859
415e12b2 1860#ifdef CONFIG_PCIEAER
415e12b2
RW		 1861bool pci_aer_available(void);
1862#else
415e12b2
RW		 1863static inline bool pci_aer_available(void) { return false; }
1864#endif
1865
cef74409
GK		 1866bool pci_ats_disabled(void);
1867
1d71eb53
VCG		 1868#ifdef CONFIG_PCIE_PTM
1869int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
e8bdc5ea 1870void pci_disable_ptm(struct pci_dev *dev);
014408cd 1871bool pcie_ptm_enabled(struct pci_dev *dev);
1d71eb53
VCG		 1872#else
1873static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1874{ return -EINVAL; }
e8bdc5ea 1875static inline void pci_disable_ptm(struct pci_dev *dev) { }
014408cd
VCG		 1876static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1877{ return false; }
1d71eb53
VCG		 1878#endif
1879
f39d5b72
BH		 1880void pci_cfg_access_lock(struct pci_dev *dev);
1881bool pci_cfg_access_trylock(struct pci_dev *dev);
1882void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1883
dfd5bb23 1884void pci_dev_lock(struct pci_dev *dev);
e3a9b121
LC		 1885int pci_dev_trylock(struct pci_dev *dev);
1886void pci_dev_unlock(struct pci_dev *dev);
ced085ef 1887DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T))
e3a9b121 1888
4352dfd5
GKH		 1889/*
1890 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1891 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1892 * configuration space.
1893 */
32a2eea7
JG		 1894#ifdef CONFIG_PCI_DOMAINS
1895extern int pci_domains_supported;
1896#else
1897enum { pci_domains_supported = 0 };
2ee546c4
BH		 1898static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1899static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1900#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1901
670ba0c8
CM		 1902/*
1903 * Generic implementation for PCI domain support. If your
1904 * architecture does not need custom management of PCI
1905 * domains then this implementation will be used
1906 */
1907#ifdef CONFIG_PCI_DOMAINS_GENERIC
1908static inline int pci_domain_nr(struct pci_bus *bus)
1909{
1910 return bus->domain_nr;
1911}
2ab51dde
TN		 1912#ifdef CONFIG_ACPI
1913int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1914#else
2ab51dde
TN		 1915static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1916{ return 0; }
1917#endif
9c7cb891 1918int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
c14f7ccc 1919void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1920#endif
1921
0aa0f5d1 1922/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1923typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1924 unsigned int command_bits, u32 flags);
f39d5b72 1925void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1926
be9d2e89
JT		 1927static inline int
1928pci_request_io_regions(struct pci_dev *pdev, const char *name)
1929{
1930 return pci_request_selected_regions(pdev,
1931 pci_select_bars(pdev, IORESOURCE_IO), name);
1932}
1933
1934static inline void
1935pci_release_io_regions(struct pci_dev *pdev)
1936{
1937 return pci_release_selected_regions(pdev,
1938 pci_select_bars(pdev, IORESOURCE_IO));
1939}
1940
1941static inline int
1942pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1943{
1944 return pci_request_selected_regions(pdev,
1945 pci_select_bars(pdev, IORESOURCE_MEM), name);
1946}
1947
1948static inline void
1949pci_release_mem_regions(struct pci_dev *pdev)
1950{
1951 return pci_release_selected_regions(pdev,
1952 pci_select_bars(pdev, IORESOURCE_MEM));
1953}
1954
4352dfd5 1955#else /* CONFIG_PCI is not enabled */
1da177e4 1956
5bbe029f
BH		 1957static inline void pci_set_flags(int flags) { }
1958static inline void pci_add_flags(int flags) { }
1959static inline void pci_clear_flags(int flags) { }
1960static inline int pci_has_flag(int flag) { return 0; }
1961
1da177e4 1962/*
0aa0f5d1
BH		 1963 * If the system does not have PCI, clearly these return errors. Define
1964 * these as simple inline functions to avoid hair in drivers.
1da177e4 1965 */
05cca6e5
GKH		 1966#define _PCI_NOP(o, s, t) \
1967 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1968 int where, t val) \
1da177e4 1969 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1970
1971#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1972 _PCI_NOP(o, word, u16 x) \
1973 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1974_PCI_NOP_ALL(read, *)
1975_PCI_NOP_ALL(write,)
1976
d42552c3 1977static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1978 unsigned int device,
1979 struct pci_dev *from)
2ee546c4 1980{ return NULL; }
d42552c3 1981
05cca6e5
GKH		 1982static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1983 unsigned int device,
1984 unsigned int ss_vendor,
1985 unsigned int ss_device,
b08508c4 1986 struct pci_dev *from)
2ee546c4 1987{ return NULL; }
1da177e4 1988
05cca6e5
GKH		 1989static inline struct pci_dev *pci_get_class(unsigned int class,
1990 struct pci_dev *from)
2ee546c4 1991{ return NULL; }
1da177e4 1992
d427da23
SJ		 1993static inline struct pci_dev *pci_get_base_class(unsigned int class,
1994 struct pci_dev *from)
1995{ return NULL; }
877fee2a
HG		 1996
1997static inline int pci_dev_present(const struct pci_device_id *ids)
1998{ return 0; }
1999
ed4aaadb 2000#define no_pci_devices() (1)
1da177e4
LT		 2001#define pci_dev_put(dev) do { } while (0)
2002
2ee546c4 2003static inline void pci_set_master(struct pci_dev *dev) { }
2aa5ac63 2004static inline void pci_clear_master(struct pci_dev *dev) { }
2ee546c4
BH		 2005static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
2006static inline void pci_disable_device(struct pci_dev *dev) { }
977da073 2007static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
05cca6e5 2008static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 2009{ return -EBUSY; }
817f9916
AS		 2010static inline int __must_check __pci_register_driver(struct pci_driver *drv,
2011 struct module *owner,
2012 const char *mod_name)
2ee546c4 2013{ return 0; }
05cca6e5 2014static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 2015{ return 0; }
2016static inline void pci_unregister_driver(struct pci_driver *drv) { }
f646c2a0 2017static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 2018{ return 0; }
05cca6e5
GKH		 2019static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
2020 int cap)
2ee546c4 2021{ return 0; }
05cca6e5 2022static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 2023{ return 0; }
05cca6e5 2024
70c0923b
JK		 2025static inline u64 pci_get_dsn(struct pci_dev *dev)
2026{ return 0; }
2027
1da177e4 2028/* Power management related routines */
2ee546c4
BH		 2029static inline int pci_save_state(struct pci_dev *dev) { return 0; }
2030static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 2031static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 2032{ return 0; }
1e560864
JH		 2033static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
2034{ return 0; }
3449248c 2035static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 2036{ return 0; }
05cca6e5
GKH		 2037static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2038 pm_message_t state)
2ee546c4 2039{ return PCI_D0; }
05cca6e5
GKH		 2040static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2041 int enable)
2ee546c4 2042{ return 0; }
48a92a81 2043
afd29f90
MW		 2044static inline struct resource *pci_find_resource(struct pci_dev *dev,
2045 struct resource *res)
2046{ return NULL; }
05cca6e5 2047static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 2048{ return -EIO; }
2049static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 2050
00dcc7cf
RH		 2051static inline int pci_register_io_range(struct fwnode_handle *fwnode,
2052 phys_addr_t addr, resource_size_t size)
2053{ return -EINVAL; }
2054
c5076cfe
TN		 2055static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2056
d80d0217
RD		 2057static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2058{ return NULL; }
d80d0217
RD		 2059static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2060 unsigned int devfn)
2061{ return NULL; }
7912af5c
RD		 2062static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2063 unsigned int bus, unsigned int devfn)
2064{ return NULL; }
d80d0217 2065
2ee546c4
BH		 2066static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
2067static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 2068
fb8a0d9d
WM		 2069#define dev_is_pci(d) (false)
2070#define dev_is_pf(d) (false)
fe594932
GU		 2071static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2072{ return false; }
80db6f08
NC		 2073static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2074 struct device_node *node,
2075 const u32 *intspec,
2076 unsigned int intsize,
2077 unsigned long *out_hwirq,
2078 unsigned int *out_type)
2079{ return -EINVAL; }
9c212009
LR		 2080
2081static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2082 struct pci_dev *dev)
2083{ return NULL; }
b9ae16d8 2084static inline bool pci_ats_disabled(void) { return true; }
0d8006dd
HX		 2085
2086static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2087{
2088 return -EINVAL;
2089}
2090
2091static inline int
2092pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2093 unsigned int max_vecs, unsigned int flags,
2094 struct irq_affinity *aff_desc)
2095{
2096 return -ENOSPC;
2097}
0d8006dd
HX		 2098static inline int
2099pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2100 unsigned int max_vecs, unsigned int flags)
2101{
5c0997dc 2102 return -ENOSPC;
0d8006dd 2103}
5c0997dc 2104#endif /* CONFIG_PCI */
0d8006dd 2105
4352dfd5
GKH		 2106/* Include architecture-dependent settings and functions */
2107
2108#include <asm/pci.h>
1da177e4 2109
0ad722f1 2110/*
f7195824
DW		 2111 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2112 * is expected to be an offset within that region.
2113 *
f7195824
DW		 2114 */
2115int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2116 struct vm_area_struct *vma,
2117 enum pci_mmap_state mmap_state, int write_combine);
11df1954 2118
ae749c7a
DW		 2119#ifndef arch_can_pci_mmap_wc
2120#define arch_can_pci_mmap_wc() 0
2121#endif
2bea36fd 2122
e854d8b2
DW		 2123#ifndef arch_can_pci_mmap_io
2124#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 2125#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2126#else
2127int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 2128#endif
ae749c7a 2129
92016ba5
JO		 2130#ifndef pci_root_bus_fwnode
2131#define pci_root_bus_fwnode(bus) NULL
2132#endif
2133
0aa0f5d1
BH		 2134/*
2135 * These helpers provide future and backwards compatibility
2136 * for accessing popular PCI BAR info
2137 */
144d204d
AS		 2138#define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2139#define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2140#define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2141#define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2142#define pci_resource_len(dev,bar) \
2143 (pci_resource_end((dev), (bar)) ? \
2144 resource_size(pci_resource_n((dev), (bar))) : 0)
1da177e4 2145
3171e46d
AS		 2146#define __pci_dev_for_each_res0(dev, res, ...) \
2147 for (unsigned int __b = 0; \
2148 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
09cc9006
MW		 2149 __b++)
2150
3171e46d
AS		 2151#define __pci_dev_for_each_res1(dev, res, __b) \
2152 for (__b = 0; \
2153 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
09cc9006
MW		 2154 __b++)
2155
2156#define pci_dev_for_each_resource(dev, res, ...) \
2157 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2158 (dev, res, __VA_ARGS__)
1da177e4 2159
0aa0f5d1
BH		 2160/*
2161 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 2162 * driver-specific data. They are really just a wrapper around
2163 * the generic device structure functions of these calls.
2164 */
05cca6e5 2165static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 2166{
2167 return dev_get_drvdata(&pdev->dev);
2168}
2169
05cca6e5 2170static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 2171{
2172 dev_set_drvdata(&pdev->dev, data);
2173}
2174
2fc90f61 2175static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 2176{
c6c4f070 2177 return dev_name(&pdev->dev);
1da177e4
LT		 2178}
2179
8221a013
BH		 2180void pci_resource_to_user(const struct pci_dev *dev, int bar,
2181 const struct resource *rsrc,
2182 resource_size_t *start, resource_size_t *end);
2311b1f2 2183
1da177e4 2184/*
0aa0f5d1
BH		 2185 * The world is not perfect and supplies us with broken PCI devices.
2186 * For at least a part of these bugs we need a work-around, so both
2187 * generic (drivers/pci/quirks.c) and per-architecture code can define
2188 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 2189 */
2190
2191struct pci_fixup {
0aa0f5d1
BH		 2192 u16 vendor; /* Or PCI_ANY_ID */
2193 u16 device; /* Or PCI_ANY_ID */
2194 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 2195 unsigned int class_shift; /* should be 0, 8, 16 */
c9d8b55f
AB		 2196#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2197 int hook_offset;
2198#else
1da177e4 2199 void (*hook)(struct pci_dev *dev);
c9d8b55f 2200#endif
1da177e4
LT		 2201};
2202
2203enum pci_fixup_pass {
2204 pci_fixup_early, /* Before probing BARs */
2205 pci_fixup_header, /* After reading configuration header */
2206 pci_fixup_final, /* Final phase of device fixups */
2207 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 2208 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 2209 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 2210 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 2211 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 2212};
2213
c9d8b55f 2214#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
09a4e4d9 2215#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
c9d8b55f
AB		 2216 class_shift, hook) \
2217 __ADDRESSABLE(hook) \
2218 asm(".section " #sec ", \"a\" \n" \
2219 ".balign 16 \n" \
2220 ".short " #vendor ", " #device " \n" \
2221 ".long " #class ", " #class_shift " \n" \
2222 ".long " #hook " - . \n" \
2223 ".previous \n");
09a4e4d9
ST		 2224
2225/*
2226 * Clang's LTO may rename static functions in C, but has no way to
2227 * handle such renamings when referenced from inline asm. To work
2228 * around this, create global C stubs for these cases.
2229 */
2230#ifdef CONFIG_LTO_CLANG
2231#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2232 class_shift, hook, stub) \
5659b598
ST		 2233 void stub(struct pci_dev *dev); \
2234 void stub(struct pci_dev *dev) \
09a4e4d9
ST		 2235 { \
2236 hook(dev); \
2237 } \
2238 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2239 class_shift, stub)
2240#else
2241#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2242 class_shift, hook, stub) \
2243 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2244 class_shift, hook)
2245#endif
2246
c9d8b55f
AB		 2247#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2248 class_shift, hook) \
2249 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
09a4e4d9 2250 class_shift, hook, __UNIQUE_ID(hook))
c9d8b55f 2251#else
1da177e4 2252/* Anonymous variables would be nice... */
f4ca5c6a
YL		 2253#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2254 class_shift, hook) \
ecf61c78 2255 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 2256 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2257 = { vendor, device, class, class_shift, hook };
c9d8b55f 2258#endif
f4ca5c6a
YL		 2259
2260#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2261 class_shift, hook) \
2262 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2263 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2264#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2265 class_shift, hook) \
2266 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2267 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2268#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2269 class_shift, hook) \
2270 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2271 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2272#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2273 class_shift, hook) \
2274 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2275 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2276#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2277 class_shift, hook) \
2278 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2279 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2280#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2281 class_shift, hook) \
2282 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2283 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2284#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2285 class_shift, hook) \
2286 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2287 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 2288#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2289 class_shift, hook) \
2290 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2291 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 2292
1da177e4
LT		 2293#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2294 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2295 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2296#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2297 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2298 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2299#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2300 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2301 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2302#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2303 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2304 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 2305#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2306 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2307 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2308#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2309 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2310 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2311#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2312 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2313 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 2314#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2315 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2316 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 2317
93177a74 2318#ifdef CONFIG_PCI_QUIRKS
1da177e4 2319void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 2320#else
2321static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 2322 struct pci_dev *dev) { }
93177a74 2323#endif
1da177e4 2324
05cca6e5 2325void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 2326void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 2327void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 2328int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2329int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 2330 const char *name);
fb7ebfe4 2331void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 2332
1da177e4 2333extern int pci_pci_problems;
236561e5 2334#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 2335#define PCIPCI_TRITON 2
2336#define PCIPCI_NATOMA 4
2337#define PCIPCI_VIAETBF 8
2338#define PCIPCI_VSFX 16
236561e5
AC		 2339#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2340#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 2341
4516a618
AN		 2342extern unsigned long pci_cardbus_io_size;
2343extern unsigned long pci_cardbus_mem_size;
15856ad5 2344extern u8 pci_dfl_cache_line_size;
ac1aa47b 2345extern u8 pci_cache_line_size;
4516a618 2346
f7625980 2347/* Architecture-specific versions may override these (weak) */
19792a08 2348void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 2349void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 2350int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2351 enum pcie_reset_state state);
06dc660e 2352int pcibios_device_add(struct pci_dev *dev);
6ae32c53 2353void pcibios_release_device(struct pci_dev *dev);
5d32a665 2354#ifdef CONFIG_PCI
a43ae58c 2355void pcibios_penalize_isa_irq(int irq, int active);
5d32a665
SK		 2356#else
2357static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2358#endif
890e4847
JL		 2359int pcibios_alloc_irq(struct pci_dev *dev);
2360void pcibios_free_irq(struct pci_dev *dev);
619e6f34 2361resource_size_t pcibios_default_alignment(void);
575e3348 2362
87382ead
AB		 2363#if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2364extern int pci_create_resource_files(struct pci_dev *dev);
2365extern void pci_remove_resource_files(struct pci_dev *dev);
2366#endif
2367
935c760e 2368#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 2369void __init pci_mmcfg_early_init(void);
2370void __init pci_mmcfg_late_init(void);
7752d5cf 2371#else
bb63b421 2372static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 2373static inline void pci_mmcfg_late_init(void) { }
2374#endif
2375
642c92da 2376int pci_ext_cfg_avail(void);
0ef5f8f6 2377
1684f5dd 2378void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 2379void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 2380
dd7cc44d 2381#ifdef CONFIG_PCI_IOV
b07579c0
WY		 2382int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2383int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
21ca9fb6 2384int pci_iov_vf_id(struct pci_dev *dev);
a7e9f240 2385void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
f39d5b72
BH		 2386int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2387void pci_disable_sriov(struct pci_dev *dev);
a1ceea67
NS		 2388
2389int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
753f6124
JS		 2390int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2391void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 2392int pci_num_vf(struct pci_dev *dev);
5a8eb242 2393int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 2394int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2395int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 2396int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 2397resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 2398void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 2399
2400/* Arch may override these (weak) */
2401int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2402int pcibios_sriov_disable(struct pci_dev *pdev);
2403resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 2404#else
b07579c0
WY		 2405static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2406{
2407 return -ENOSYS;
2408}
2409static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2410{
2411 return -ENOSYS;
2412}
21ca9fb6
JG		 2413
2414static inline int pci_iov_vf_id(struct pci_dev *dev)
2415{
2416 return -ENOSYS;
2417}
2418
a7e9f240
JG		 2419static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2420 struct pci_driver *pf_driver)
2421{
2422 return ERR_PTR(-EINVAL);
2423}
2424
dd7cc44d 2425static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2426{ return -ENODEV; }
a1ceea67
NS		 2427
2428static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2429 struct pci_dev *virtfn, int id)
2430{
2431 return -ENODEV;
2432}
753f6124 2433static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2434{
2435 return -ENOSYS;
2436}
2437static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2438 int id) { }
2ee546c4 2439static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2440static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2441static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2442{ return 0; }
bff73156 2443static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2444{ return 0; }
bff73156 2445static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2446{ return 0; }
8effc395 2447#define pci_sriov_configure_simple NULL
0e6c9122
WY		 2448static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2449{ return 0; }
608c0d88 2450static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 2451#endif
2452
c825bc94 2453#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2454void pci_hp_create_module_link(struct pci_slot *pci_slot);
2455void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2456#endif
2457
d7b7e605
KK		 2458/**
2459 * pci_pcie_cap - get the saved PCIe capability offset
2460 * @dev: PCI device
2461 *
2462 * PCIe capability offset is calculated at PCI device initialization
2463 * time and saved in the data structure. This function returns saved
2464 * PCIe capability offset. Using this instead of pci_find_capability()
2465 * reduces unnecessary search in the PCI configuration space. If you
2466 * need to calculate PCIe capability offset from raw device for some
2467 * reasons, please use pci_find_capability() instead.
2468 */
2469static inline int pci_pcie_cap(struct pci_dev *dev)
2470{
2471 return dev->pcie_cap;
2472}
2473
7eb776c4
KK		 2474/**
2475 * pci_is_pcie - check if the PCI device is PCI Express capable
2476 * @dev: PCI device
2477 *
a895c28a 2478 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2479 */
2480static inline bool pci_is_pcie(struct pci_dev *dev)
2481{
a895c28a 2482 return pci_pcie_cap(dev);
7eb776c4
KK		 2483}
2484
7c9c003c
MS		 2485/**
2486 * pcie_caps_reg - get the PCIe Capabilities Register
2487 * @dev: PCI device
2488 */
2489static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2490{
2491 return dev->pcie_flags_reg;
2492}
2493
786e2288
YW		 2494/**
2495 * pci_pcie_type - get the PCIe device/port type
2496 * @dev: PCI device
2497 */
2498static inline int pci_pcie_type(const struct pci_dev *dev)
2499{
1c531d82 2500 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2501}
2502
6ae72bfa
YY		 2503/**
2504 * pcie_find_root_port - Get the PCIe root port device
2505 * @dev: PCI device
2506 *
2507 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2508 * for a given PCI/PCIe Device.
2509 */
e784930b
JT		 2510static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2511{
5396956c
MW		 2512 while (dev) {
2513 if (pci_is_pcie(dev) &&
2514 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2515 return dev;
2516 dev = pci_upstream_bridge(dev);
e784930b 2517 }
6ae72bfa 2518
e784930b
JT		 2519 return NULL;
2520}
2521
39714fd7
EZ		 2522static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
2523{
2524 return dev->error_state == pci_channel_io_perm_failure;
2525}
2526
5d990b62 2527void pci_request_acs(void);
ad805758
AW		 2528bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2529bool pci_acs_path_enabled(struct pci_dev *start,
2530 struct pci_dev *end, u16 acs_flags);
430a2368 2531int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2532
7ad506fa 2533#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2534#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2535
2536/* Large Resource Data Type Tag Item Names */
2537#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2538#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2539#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2540
2541#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2542#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2543#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2544
4067a854 2545#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
16efafa3 2546#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
4067a854
MC		 2547#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2548#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2549#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2550
a2ce7662 2551/**
76f3c032
HK		 2552 * pci_vpd_alloc - Allocate buffer and read VPD into it
2553 * @dev: PCI device
2554 * @size: pointer to field where VPD length is returned
9eb45d5c 2555 *
76f3c032 2556 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
9eb45d5c 2557 */
76f3c032 2558void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
9eb45d5c 2559
e1d5bdab 2560/**
acfbb1b8
HK		 2561 * pci_vpd_find_id_string - Locate id string in VPD
2562 * @buf: Pointer to buffered VPD data
2563 * @len: The length of the buffer area in which to search
2564 * @size: Pointer to field where length of id string is returned
e1d5bdab 2565 *
acfbb1b8 2566 * Returns the index of the id string or -ENOENT if not found.
e1d5bdab 2567 */
acfbb1b8 2568int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
e1d5bdab 2569
b55ac1b2 2570/**
9e515c9f
HK		 2571 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2572 * @buf: Pointer to buffered VPD data
2573 * @len: The length of the buffer area in which to search
2574 * @kw: The keyword to search for
2575 * @size: Pointer to field where length of found keyword data is returned
b55ac1b2 2576 *
9e515c9f
HK		 2577 * Returns the index of the information field keyword data or -ENOENT if
2578 * not found.
b55ac1b2 2579 */
9e515c9f
HK		 2580int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2581 const char *kw, unsigned int *size);
b55ac1b2 2582
4067a854 2583/**
6107e5cb
HK		 2584 * pci_vpd_check_csum - Check VPD checksum
2585 * @buf: Pointer to buffered VPD data
2586 * @len: VPD size
4067a854 2587 *
6107e5cb 2588 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
4067a854 2589 */
6107e5cb 2590int pci_vpd_check_csum(const void *buf, unsigned int len);
4067a854 2591
98d9f30c
BH		 2592/* PCI <-> OF binding helpers */
2593#ifdef CONFIG_OF
2594struct device_node;
b165e2b6 2595struct irq_domain;
b165e2b6 2596struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
85aabbd7 2597bool pci_host_of_has_msi_map(struct device *dev);
98d9f30c
BH		 2598
2599/* Arch may override this (weak) */
723ec4d0 2600struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2601
0aa0f5d1 2602#else /* CONFIG_OF */
b165e2b6
MZ		 2603static inline struct irq_domain *
2604pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
85aabbd7 2605static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
98d9f30c
BH		 2606#endif /* CONFIG_OF */
2607
ad32eb2d
BM		 2608static inline struct device_node *
2609pci_device_to_OF_node(const struct pci_dev *pdev)
2610{
2611 return pdev ? pdev->dev.of_node : NULL;
2612}
2613
2614static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2615{
2616 return bus ? bus->dev.of_node : NULL;
2617}
2618
471036b2
SS		 2619#ifdef CONFIG_ACPI
2620struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2621
2622void
2623pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
52525b7a 2624bool pci_pr3_present(struct pci_dev *pdev);
471036b2
SS		 2625#else
2626static inline struct irq_domain *
2627pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
46b4bff6 2628static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
471036b2
SS		 2629#endif
2630
eb740b5f
GS		 2631#ifdef CONFIG_EEH
2632static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2633{
2634 return pdev->dev.archdata.edev;
2635}
2636#endif
2637
09298542 2638void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
338c3149 2639bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2640int pci_for_each_dma_alias(struct pci_dev *pdev,
2641 int (*fn)(struct pci_dev *pdev,
2642 u16 alias, void *data), void *data);
2643
0aa0f5d1 2644/* Helper functions for operation of device flag */
ce052984
EZ		 2645static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2646{
2647 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2648}
2649static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2650{
2651 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2652}
2653static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2654{
2655 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2656}
19bdb6e4
AW		 2657
2658/**
2659 * pci_ari_enabled - query ARI forwarding status
2660 * @bus: the PCI bus
2661 *
2662 * Returns true if ARI forwarding is enabled.
2663 */
2664static inline bool pci_ari_enabled(struct pci_bus *bus)
2665{
2666 return bus->self && bus->self->ari_enabled;
2667}
bc4b024a 2668
8531e283
LW		 2669/**
2670 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2671 * @pdev: PCI device to check
2672 *
2673 * Walk upwards from @pdev and check for each encountered bridge if it's part
2674 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2675 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2676 */
2677static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2678{
2679 struct pci_dev *parent = pdev;
2680
2681 if (pdev->is_thunderbolt)
2682 return true;
2683
2684 while ((parent = pci_upstream_bridge(parent)))
2685 if (parent->is_thunderbolt)
2686 return true;
2687
2688 return false;
2689}
2690
2e28bc84 2691#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2692void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2693#endif
856e1eb9 2694
79687789 2695#include <linux/dma-mapping.h>
bc4b024a 2696
7506dc79
FL		 2697#define pci_printk(level, pdev, fmt, arg...) \
2698 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2699
2700#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2701#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2702#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2703#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2704#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
27829479 2705#define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
7506dc79
FL		 2706#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2707#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2708#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2709
a88a7b3e
BH		 2710#define pci_notice_ratelimited(pdev, fmt, arg...) \
2711 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2712
7f1c62c4
KW		 2713#define pci_info_ratelimited(pdev, fmt, arg...) \
2714 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2715
12bcae44
BH		 2716#define pci_WARN(pdev, condition, fmt, arg...) \
2717 WARN(condition, "%s %s: " fmt, \
2718 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2719
2720#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2721 WARN_ONCE(condition, "%s %s: " fmt, \
2722 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2723
1da177e4 2724#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)