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PCI: Fix missing inline for pci_pr3_present()
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
7ce2e76a
KW		 9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
1da177e4
LT		 14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
7ce2e76a 20 * PCI Express Specification
1da177e4
LT		 21 * PCI System Design Guide
22 */
1da177e4
LT		 23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
1da177e4 26
778382e0
DW		 27#include <linux/mod_devicetable.h>
28
1da177e4 29#include <linux/types.h>
98db6f19 30#include <linux/init.h>
1da177e4
LT		 31#include <linux/ioport.h>
32#include <linux/list.h>
4a7fb636 33#include <linux/compiler.h>
1da177e4 34#include <linux/errno.h>
f46753c5 35#include <linux/kobject.h>
60063497 36#include <linux/atomic.h>
1da177e4 37#include <linux/device.h>
704e8953 38#include <linux/interrupt.h>
1388cc96 39#include <linux/io.h>
14d76b68 40#include <linux/resource_ext.h>
607ca46e 41#include <uapi/linux/pci.h>
1da177e4 42
7e7a43c3
AB		 43#include <linux/pci_ids.h>
44
85467136
SK		 45/*
46 * The PCI interface treats multi-function devices as independent
47 * devices. The slot/function address of each device is encoded
48 * in a single byte as follows:
49 *
50 * 7:3 = slot
51 * 2:0 = function
f7625980
BH		 52 *
53 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 54 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 55 * the following kernel-only defines are being added here.
85467136 56 */
0aa0f5d1 57#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 58/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
59#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
60
f46753c5
AC		 61/* pci_slot represents a physical slot */
62struct pci_slot {
0aa0f5d1
BH		 63 struct pci_bus *bus; /* Bus this slot is on */
64 struct list_head list; /* Node in list of slots */
65 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
66 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
67 struct kobject kobj;
f46753c5
AC		 68};
69
0ad772ec
AC		 70static inline const char *pci_slot_name(const struct pci_slot *slot)
71{
72 return kobject_name(&slot->kobj);
73}
74
1da177e4
LT		 75/* File state for mmap()s on /proc/bus/pci/X/Y */
76enum pci_mmap_state {
77 pci_mmap_io,
78 pci_mmap_mem
79};
80
0aa0f5d1 81/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 82enum {
83 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCES,
85 PCI_STD_RESOURCE_END = 5,
86
87 /* #6: expansion ROM resource */
88 PCI_ROM_RESOURCE,
89
0aa0f5d1 90 /* Device-specific resources */
d1b054da
YZ		 91#ifdef CONFIG_PCI_IOV
92 PCI_IOV_RESOURCES,
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94#endif
95
0aa0f5d1 96 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 97#define PCI_BRIDGE_RESOURCE_NUM 4
98
99 PCI_BRIDGE_RESOURCES,
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
102
0aa0f5d1 103 /* Total resources associated with a PCI device */
fde09c6d
YZ		 104 PCI_NUM_RESOURCES,
105
0aa0f5d1 106 /* Preserve this for compatibility */
cda57bf9 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 108};
1da177e4 109
b352baf1
PB		 110/**
111 * enum pci_interrupt_pin - PCI INTx interrupt values
112 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
113 * @PCI_INTERRUPT_INTA: PCI INTA pin
114 * @PCI_INTERRUPT_INTB: PCI INTB pin
115 * @PCI_INTERRUPT_INTC: PCI INTC pin
116 * @PCI_INTERRUPT_INTD: PCI INTD pin
117 *
118 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
119 * PCI_INTERRUPT_PIN register.
120 */
121enum pci_interrupt_pin {
122 PCI_INTERRUPT_UNKNOWN,
123 PCI_INTERRUPT_INTA,
124 PCI_INTERRUPT_INTB,
125 PCI_INTERRUPT_INTC,
126 PCI_INTERRUPT_INTD,
127};
128
129/* The number of legacy PCI INTx interrupts */
130#define PCI_NUM_INTX 4
131
224abb67
BH		 132/*
133 * pci_power_t values must match the bits in the Capabilities PME_Support
134 * and Control/Status PowerState fields in the Power Management capability.
135 */
1da177e4
LT		 136typedef int __bitwise pci_power_t;
137
4352dfd5
GKH		 138#define PCI_D0 ((pci_power_t __force) 0)
139#define PCI_D1 ((pci_power_t __force) 1)
140#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 141#define PCI_D3hot ((pci_power_t __force) 3)
142#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 143#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 144#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 145
00240c38
AS		 146/* Remember to update this when the list above changes! */
147extern const char *pci_power_names[];
148
149static inline const char *pci_power_name(pci_power_t state)
150{
9661e783 151 return pci_power_names[1 + (__force int) state];
00240c38
AS		 152}
153
0aa0f5d1 154/**
229b4e07
CD		 155 * typedef pci_channel_state_t
156 *
0aa0f5d1
BH		 157 * The pci_channel state describes connectivity between the CPU and
158 * the PCI device. If some PCI bus between here and the PCI device
159 * has crashed or locked up, this info is reflected here.
392a1ce7 160 */
161typedef unsigned int __bitwise pci_channel_state_t;
162
163enum pci_channel_state {
164 /* I/O channel is in normal state */
165 pci_channel_io_normal = (__force pci_channel_state_t) 1,
166
167 /* I/O to channel is blocked */
168 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
169
170 /* PCI card is dead */
171 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
172};
173
f7bdd12d
BK		 174typedef unsigned int __bitwise pcie_reset_state_t;
175
176enum pcie_reset_state {
177 /* Reset is NOT asserted (Use to deassert reset) */
178 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
179
f7625980 180 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 181 pcie_warm_reset = (__force pcie_reset_state_t) 2,
182
f7625980 183 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 184 pcie_hot_reset = (__force pcie_reset_state_t) 3
185};
186
ba698ad4
DM		 187typedef unsigned short __bitwise pci_dev_flags_t;
188enum pci_dev_flags {
0aa0f5d1 189 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 191 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 193 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 205 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 209 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 211};
212
e1d3a908
SA		 213enum pci_irq_reroute_variant {
214 INTEL_IRQ_REROUTE_VARIANT = 1,
215 MAX_IRQ_REROUTE_VARIANTS = 3
216};
217
6e325a62
MT		 218typedef unsigned short __bitwise pci_bus_flags_t;
219enum pci_bus_flags {
032c3d86
JD		 220 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
221 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 223 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 224};
225
0aa0f5d1 226/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 227enum pcie_link_width {
228 PCIE_LNK_WIDTH_RESRV = 0x00,
229 PCIE_LNK_X1 = 0x01,
230 PCIE_LNK_X2 = 0x02,
231 PCIE_LNK_X4 = 0x04,
232 PCIE_LNK_X8 = 0x08,
0aa0f5d1 233 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 234 PCIE_LNK_X16 = 0x10,
235 PCIE_LNK_X32 = 0x20,
0aa0f5d1 236 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 237};
238
536c8cb4
MW		 239/* Based on the PCI Hotplug Spec, but some values are made up by us */
240enum pci_bus_speed {
241 PCI_SPEED_33MHz = 0x00,
242 PCI_SPEED_66MHz = 0x01,
243 PCI_SPEED_66MHz_PCIX = 0x02,
244 PCI_SPEED_100MHz_PCIX = 0x03,
245 PCI_SPEED_133MHz_PCIX = 0x04,
246 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
247 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
248 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
249 PCI_SPEED_66MHz_PCIX_266 = 0x09,
250 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
251 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 252 AGP_UNKNOWN = 0x0c,
253 AGP_1X = 0x0d,
254 AGP_2X = 0x0e,
255 AGP_4X = 0x0f,
256 AGP_8X = 0x10,
536c8cb4
MW		 257 PCI_SPEED_66MHz_PCIX_533 = 0x11,
258 PCI_SPEED_100MHz_PCIX_533 = 0x12,
259 PCI_SPEED_133MHz_PCIX_533 = 0x13,
260 PCIE_SPEED_2_5GT = 0x14,
261 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 262 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 263 PCIE_SPEED_16_0GT = 0x17,
de76cda2 264 PCIE_SPEED_32_0GT = 0x18,
536c8cb4
MW		 265 PCI_SPEED_UNKNOWN = 0xff,
266};
267
576c7218
AD		 268enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
269enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
270
24a4742f 271struct pci_cap_saved_data {
0aa0f5d1
BH		 272 u16 cap_nr;
273 bool cap_extended;
274 unsigned int size;
275 u32 data[0];
41017f0c
SL		 276};
277
24a4742f 278struct pci_cap_saved_state {
0aa0f5d1
BH		 279 struct hlist_node next;
280 struct pci_cap_saved_data cap;
24a4742f
AW		 281};
282
402723ad 283struct irq_affinity;
7d715a6c 284struct pcie_link_state;
ee69439c 285struct pci_vpd;
d1b054da 286struct pci_sriov;
302b4215 287struct pci_ats;
52916982 288struct pci_p2pdma;
ee69439c 289
0aa0f5d1 290/* The pci_dev structure describes PCI devices */
1da177e4 291struct pci_dev {
0aa0f5d1
BH		 292 struct list_head bus_list; /* Node in per-bus list */
293 struct pci_bus *bus; /* Bus this device is on */
294 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 295
0aa0f5d1
BH		 296 void *sysdata; /* Hook for sys-specific extension */
297 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 298 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 299
0aa0f5d1 300 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 301 unsigned short vendor;
302 unsigned short device;
303 unsigned short subsystem_vendor;
304 unsigned short subsystem_device;
305 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 306 u8 revision; /* PCI revision, low byte of class word */
1da177e4 307 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 308#ifdef CONFIG_PCIEAER
309 u16 aer_cap; /* AER capability offset */
db89ccbe 310 struct aer_stats *aer_stats; /* AER stats for this device */
66b80809 311#endif
f7625980 312 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 313 u8 msi_cap; /* MSI capability offset */
314 u8 msix_cap; /* MSI-X capability offset */
f7625980 315 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 316 u8 rom_base_reg; /* Config register controlling ROM */
317 u8 pin; /* Interrupt pin this device uses */
318 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
319 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 320
0aa0f5d1 321 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 322 u64 dma_mask; /* Mask of the bits of bus address this
323 device implements. Normally this is
324 0xffffffff. You only need to change
325 this if your device has broken DMA
326 or supports 64-bit transfers. */
327
4d57cdfa
FT		 328 struct device_dma_parameters dma_parms;
329
0aa0f5d1
BH		 330 pci_power_t current_state; /* Current operating state. In ACPI,
331 this is D0-D3, D0 being fully
332 functional, and D3 being off. */
d6112f8d 333 unsigned int imm_ready:1; /* Supports Immediate Readiness */
703860ed 334 u8 pm_cap; /* PM capability offset */
337001b6
RW		 335 unsigned int pme_support:5; /* Bitmask of states from which PME#
336 can be generated */
379021d5 337 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 338 unsigned int d1_support:1; /* Low power state D1 is supported */
339 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 340 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
341 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 342 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 343 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 344 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
345 decoding during BAR sizing */
e80bb09d 346 unsigned int wakeup_prepared:1;
0aa0f5d1 347 unsigned int runtime_d3cold:1; /* Whether go through runtime
448bd857
HY		 348 D3cold, not set for devices
349 powered on/off by the
350 corresponding bridge */
d491f2b7 351 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 352 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 353 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
354 controlled exclusively by
355 user sysfs */
4ec73791
SM		 356 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
357 bit manually */
1ae861e6 358 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 359 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 360
7d715a6c 361#ifdef CONFIG_PCIEASPM
f7625980 362 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 363 unsigned int ltr_path:1; /* Latency Tolerance Reporting
364 supported from root to here */
7d715a6c 365#endif
7ce3f912 366 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 367
0aa0f5d1
BH		 368 pci_channel_state_t error_state; /* Current connectivity state */
369 struct device dev; /* Generic device interface */
1da177e4 370
0aa0f5d1 371 int cfg_size; /* Size of config space */
1da177e4
LT		 372
373 /*
374 * Instead of touching interrupt line and base address registers
375 * directly, use the values stored here. They might be different!
376 */
377 unsigned int irq;
378 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
379
0aa0f5d1
BH		 380 bool match_driver; /* Skip attaching driver */
381
382 unsigned int transparent:1; /* Subtractive decode bridge */
51c48b31
BH		 383 unsigned int io_window:1; /* Bridge has I/O window */
384 unsigned int pref_window:1; /* Bridge has pref mem window */
385 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
0aa0f5d1
BH		 386 unsigned int multifunction:1; /* Multi-function device */
387
0aa0f5d1
BH		 388 unsigned int is_busmaster:1; /* Is busmaster */
389 unsigned int no_msi:1; /* May not use MSI */
f6b6aefe 390 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
0aa0f5d1
BH		 391 unsigned int block_cfg_access:1; /* Config space access blocked */
392 unsigned int broken_parity_status:1; /* Generates false positive parity */
393 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 394 unsigned int msi_enabled:1;
99dc804d 395 unsigned int msix_enabled:1;
0aa0f5d1
BH		 396 unsigned int ari_enabled:1; /* ARI forwarding */
397 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 398 unsigned int pasid_enabled:1; /* Process Address Space ID */
399 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 400 unsigned int is_managed:1;
0aa0f5d1 401 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 402 unsigned int state_saved:1;
d1b054da 403 unsigned int is_physfn:1;
dd7cc44d 404 unsigned int is_virtfn:1;
711d5779 405 unsigned int reset_fn:1;
0aa0f5d1 406 unsigned int is_hotplug_bridge:1;
b03799b0 407 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
0aa0f5d1 408 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
617654aa
MW		 409 /*
410 * Devices marked being untrusted are the ones that can potentially
411 * execute DMA attacks and similar. They are typically connected
412 * through external ports such as Thunderbolt but not limited to
413 * that. When an IOMMU is enabled they should be getting full
414 * mappings to make sure they cannot access arbitrary memory.
415 */
416 unsigned int untrusted:1;
0aa0f5d1 417 unsigned int __aer_firmware_first_valid:1;
affb72c3 418 unsigned int __aer_firmware_first:1;
0aa0f5d1
BH		 419 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
420 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 421 unsigned int irq_managed:1;
0aa0f5d1
BH		 422 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
423 unsigned int is_probed:1; /* Device probing in progress */
f0157160 424 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
aff68a5a 425 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
ba698ad4 426 pci_dev_flags_t dev_flags;
bae94d02 427 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 428
0aa0f5d1 429 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 430 struct hlist_head saved_cap_space;
0aa0f5d1
BH		 431 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
432 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 433 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 434 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 435
d22b3621
BH		 436#ifdef CONFIG_HOTPLUG_PCI_PCIE
437 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
438#endif
9bb04a0c
JY		 439#ifdef CONFIG_PCIE_PTM
440 unsigned int ptm_root:1;
441 unsigned int ptm_enabled:1;
8b2ec318 442 u8 ptm_granularity;
9bb04a0c 443#endif
ded86d8d 444#ifdef CONFIG_PCI_MSI
1c51b50c 445 const struct attribute_group **msi_irq_groups;
ded86d8d 446#endif
94e61088 447 struct pci_vpd *vpd;
466b3ddf 448#ifdef CONFIG_PCI_ATS
dd7cc44d 449 union {
0aa0f5d1
BH		 450 struct pci_sriov *sriov; /* PF: SR-IOV info */
451 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 452 };
67930995
BH		 453 u16 ats_cap; /* ATS Capability offset */
454 u8 ats_stu; /* ATS Smallest Translation Unit */
0aa0f5d1 455 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
4ebeb1ec
CT		 456#endif
457#ifdef CONFIG_PCI_PRI
458 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
459#endif
460#ifdef CONFIG_PCI_PASID
461 u16 pasid_features;
52916982
LG		 462#endif
463#ifdef CONFIG_PCI_P2PDMA
464 struct pci_p2pdma *p2pdma;
d1b054da 465#endif
0aa0f5d1
BH		 466 phys_addr_t rom; /* Physical address if not from BAR */
467 size_t romlen; /* Length if not from BAR */
468 char *driver_override; /* Driver name to force a match */
89ee9f76 469
0aa0f5d1 470 unsigned long priv_flags; /* Private flags for the PCI driver */
1da177e4
LT		 471};
472
dda56549
Y		 473static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
474{
475#ifdef CONFIG_PCI_IOV
476 if (dev->is_virtfn)
477 dev = dev->physfn;
478#endif
dda56549
Y		 479 return dev;
480}
481
3c6e6ae7 482struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 483
1da177e4
LT		 484#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
485#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
486
a7369f1f
LV		 487static inline int pci_channel_offline(struct pci_dev *pdev)
488{
489 return (pdev->error_state != pci_channel_io_normal);
490}
491
5a21d70d 492struct pci_host_bridge {
0aa0f5d1
BH		 493 struct device dev;
494 struct pci_bus *bus; /* Root bus */
495 struct pci_ops *ops;
496 void *sysdata;
497 int busnr;
14d76b68 498 struct list_head windows; /* resource_entry */
e80a91ad 499 struct list_head dma_ranges; /* dma ranges resource list */
0aa0f5d1 500 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 501 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 502 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 503 void *release_data;
37d6a0a6 504 struct msi_controller *msi;
0aa0f5d1
BH		 505 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
506 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48 507 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 508 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 509 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 510 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 511 unsigned int native_ltr:1; /* OS may use PCIe LTR */
a78cf965
BH		 512 unsigned int preserve_config:1; /* Preserve FW resource setup */
513
7c7a0e94
GP		 514 /* Resource alignment requirements */
515 resource_size_t (*align_resource)(struct pci_dev *dev,
516 const struct resource *res,
517 resource_size_t start,
518 resource_size_t size,
519 resource_size_t align);
0aa0f5d1 520 unsigned long private[0] ____cacheline_aligned;
5a21d70d 521};
41017f0c 522
7b543663 523#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 524
59094065
TR		 525static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
526{
527 return (void *)bridge->private;
528}
529
530static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
531{
532 return container_of(priv, struct pci_host_bridge, private);
533}
534
a52d1443 535struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 536struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
537 size_t priv);
dff79b91 538void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 539struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
540
4fa2649a 541void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 542 void (*release_fn)(struct pci_host_bridge *),
543 void *release_data);
7b543663 544
6c0cc950
RW		 545int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
546
2fe2abf8
BH		 547/*
548 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
549 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
550 * buses below host bridges or subtractive decode bridges) go in the list.
551 * Use pci_bus_for_each_resource() to iterate through all the resources.
552 */
553
554/*
555 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
556 * and there's no way to program the bridge with the details of the window.
557 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
558 * decode bit set, because they are explicit and can be programmed with _SRS.
559 */
560#define PCI_SUBTRACTIVE_DECODE 0x1
561
562struct pci_bus_resource {
0aa0f5d1
BH		 563 struct list_head list;
564 struct resource *res;
565 unsigned int flags;
2fe2abf8 566};
4352dfd5
GKH		 567
568#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 569
570struct pci_bus {
0aa0f5d1
BH		 571 struct list_head node; /* Node in list of buses */
572 struct pci_bus *parent; /* Parent bus this bridge is on */
573 struct list_head children; /* List of child buses */
574 struct list_head devices; /* List of devices on this bus */
575 struct pci_dev *self; /* Bridge device as seen by parent */
576 struct list_head slots; /* List of slots on this bus;
67546762 577 protected by pci_slot_mutex */
2fe2abf8 578 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 579 struct list_head resources; /* Address space routed to this bus */
580 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 581
0aa0f5d1 582 struct pci_ops *ops; /* Configuration access functions */
c2791b80 583 struct msi_controller *msi; /* MSI controller */
0aa0f5d1
BH		 584 void *sysdata; /* Hook for sys-specific extension */
585 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 586
0aa0f5d1
BH		 587 unsigned char number; /* Bus number */
588 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 589 unsigned char max_bus_speed; /* enum pci_bus_speed */
590 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 591#ifdef CONFIG_PCI_DOMAINS_GENERIC
592 int domain_nr;
593#endif
1da177e4
LT		 594
595 char name[48];
596
0aa0f5d1
BH		 597 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
598 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 599 struct device *bridge;
fd7d1ced 600 struct device dev;
0aa0f5d1
BH		 601 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
602 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 603 unsigned int is_added:1;
1da177e4
LT		 604};
605
fd7d1ced 606#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 607
4e544bac
HK		 608static inline u16 pci_dev_id(struct pci_dev *dev)
609{
610 return PCI_DEVID(dev->bus->number, dev->devfn);
611}
612
79af72d7 613/*
f7625980 614 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 615 * false otherwise
77a0dfcd
BH		 616 *
617 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
618 * This is incorrect because "virtual" buses added for SR-IOV (via
619 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 620 */
621static inline bool pci_is_root_bus(struct pci_bus *pbus)
622{
623 return !(pbus->parent);
624}
625
1c86438c
YW		 626/**
627 * pci_is_bridge - check if the PCI device is a bridge
628 * @dev: PCI device
629 *
630 * Return true if the PCI device is bridge whether it has subordinate
631 * or not.
632 */
633static inline bool pci_is_bridge(struct pci_dev *dev)
634{
635 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
636 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
637}
638
24a0c654
AS		 639#define for_each_pci_bridge(dev, bus) \
640 list_for_each_entry(dev, &bus->devices, bus_list) \
641 if (!pci_is_bridge(dev)) {} else
642
c6bde215
BH		 643static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
644{
645 dev = pci_physfn(dev);
646 if (pci_is_root_bus(dev->bus))
647 return NULL;
648
649 return dev->bus->self;
650}
651
16cf0ebc
RW		 652#ifdef CONFIG_PCI_MSI
653static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
654{
655 return pci_dev->msi_enabled || pci_dev->msix_enabled;
656}
657#else
658static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
659#endif
660
0aa0f5d1 661/* Error values that may be returned by PCI functions */
1da177e4
LT		 662#define PCIBIOS_SUCCESSFUL 0x00
663#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
664#define PCIBIOS_BAD_VENDOR_ID 0x83
665#define PCIBIOS_DEVICE_NOT_FOUND 0x86
666#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
667#define PCIBIOS_SET_FAILED 0x88
668#define PCIBIOS_BUFFER_TOO_SMALL 0x89
669
0aa0f5d1 670/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 671static inline int pcibios_err_to_errno(int err)
672{
673 if (err <= PCIBIOS_SUCCESSFUL)
674 return err; /* Assume already errno */
675
676 switch (err) {
677 case PCIBIOS_FUNC_NOT_SUPPORTED:
678 return -ENOENT;
679 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 680 return -ENOTTY;
a6961651
AW		 681 case PCIBIOS_DEVICE_NOT_FOUND:
682 return -ENODEV;
683 case PCIBIOS_BAD_REGISTER_NUMBER:
684 return -EFAULT;
685 case PCIBIOS_SET_FAILED:
686 return -EIO;
687 case PCIBIOS_BUFFER_TOO_SMALL:
688 return -ENOSPC;
689 }
690
d97ffe23 691 return -ERANGE;
a6961651
AW		 692}
693
1da177e4
LT		 694/* Low-level architecture-dependent routines */
695
696struct pci_ops {
057bd2e0
TR		 697 int (*add_bus)(struct pci_bus *bus);
698 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 699 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 700 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
701 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
702};
703
b6ce068a
MW		 704/*
705 * ACPI needs to be able to access PCI config space before we've done a
706 * PCI bus scan and created pci_bus structures.
707 */
f39d5b72
BH		 708int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
709 int reg, int len, u32 *val);
710int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
711 int reg, int len, u32 val);
1da177e4 712
8e639079 713#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 714typedef u64 pci_bus_addr_t;
715#else
716typedef u32 pci_bus_addr_t;
717#endif
718
1da177e4 719struct pci_bus_region {
0aa0f5d1
BH		 720 pci_bus_addr_t start;
721 pci_bus_addr_t end;
1da177e4
LT		 722};
723
724struct pci_dynids {
0aa0f5d1
BH		 725 spinlock_t lock; /* Protects list, index */
726 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 727};
728
f7625980
BH		 729
730/*
731 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
732 * a set of callbacks in struct pci_error_handlers, that device driver
733 * will be notified of PCI bus errors, and will be driven to recovery
734 * when an error occurs.
392a1ce7 735 */
736
737typedef unsigned int __bitwise pci_ers_result_t;
738
739enum pci_ers_result {
0aa0f5d1 740 /* No result/none/not supported in device driver */
392a1ce7 741 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
742
743 /* Device driver can recover without slot reset */
744 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
745
0aa0f5d1 746 /* Device driver wants slot to be reset */
392a1ce7 747 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
748
749 /* Device has completely failed, is unrecoverable */
750 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
751
752 /* Device driver is fully recovered and operational */
753 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 754
755 /* No AER capabilities registered for the driver */
756 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 757};
758
759/* PCI bus error event callbacks */
05cca6e5 760struct pci_error_handlers {
392a1ce7 761 /* PCI bus error detected on this device */
762 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 763 enum pci_channel_state error);
392a1ce7 764
765 /* MMIO has been re-enabled, but not DMA */
766 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
767
392a1ce7 768 /* PCI slot has been reset */
769 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
770
3ebe7f9f 771 /* PCI function reset prepare or completed */
775755ed
CH		 772 void (*reset_prepare)(struct pci_dev *dev);
773 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 774
392a1ce7 775 /* Device driver may resume normal operations */
776 void (*resume)(struct pci_dev *dev);
777};
778
392a1ce7 779
1da177e4 780struct module;
229b4e07
CD		 781
782/**
783 * struct pci_driver - PCI driver structure
784 * @node: List of driver structures.
785 * @name: Driver name.
786 * @id_table: Pointer to table of device IDs the driver is
787 * interested in. Most drivers should export this
788 * table using MODULE_DEVICE_TABLE(pci,...).
789 * @probe: This probing function gets called (during execution
790 * of pci_register_driver() for already existing
791 * devices or later if a new device gets inserted) for
792 * all PCI devices which match the ID table and are not
793 * "owned" by the other drivers yet. This function gets
794 * passed a "struct pci_dev \*" for each device whose
795 * entry in the ID table matches the device. The probe
796 * function returns zero when the driver chooses to
797 * take "ownership" of the device or an error code
798 * (negative number) otherwise.
799 * The probe function always gets called from process
800 * context, so it can sleep.
801 * @remove: The remove() function gets called whenever a device
802 * being handled by this driver is removed (either during
803 * deregistration of the driver or when it's manually
804 * pulled out of a hot-pluggable slot).
805 * The remove function always gets called from process
806 * context, so it can sleep.
807 * @suspend: Put device into low power state.
808 * @suspend_late: Put device into low power state.
809 * @resume_early: Wake device from low power state.
810 * @resume: Wake device from low power state.
151f4e2b 811 * (Please see Documentation/power/pci.rst for descriptions
229b4e07
CD		 812 * of PCI Power Management and the related functions.)
813 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
814 * Intended to stop any idling DMA operations.
815 * Useful for enabling wake-on-lan (NIC) or changing
816 * the power state of a device before reboot.
817 * e.g. drivers/net/e100.c.
818 * @sriov_configure: Optional driver callback to allow configuration of
819 * number of VFs to enable via sysfs "sriov_numvfs" file.
820 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
821 * @groups: Sysfs attribute groups.
822 * @driver: Driver model structure.
823 * @dynids: List of dynamically added device IDs.
824 */
1da177e4 825struct pci_driver {
0aa0f5d1
BH		 826 struct list_head node;
827 const char *name;
828 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
829 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
830 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
831 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
832 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
833 int (*resume_early)(struct pci_dev *dev);
7cb30264
BY		 834 int (*resume)(struct pci_dev *dev); /* Device woken up */
835 void (*shutdown)(struct pci_dev *dev);
836 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
49453028 837 const struct pci_error_handlers *err_handler;
92d50fc1 838 const struct attribute_group **groups;
1da177e4 839 struct device_driver driver;
0aa0f5d1 840 struct pci_dynids dynids;
1da177e4
LT		 841};
842
05cca6e5 843#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 844
845/**
0aa0f5d1 846 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 847 * @vend: the 16 bit PCI Vendor ID
848 * @dev: the 16 bit PCI Device ID
849 *
850 * This macro is used to create a struct pci_device_id that matches a
851 * specific device. The subvendor and subdevice fields will be set to
852 * PCI_ANY_ID.
853 */
854#define PCI_DEVICE(vend,dev) \
855 .vendor = (vend), .device = (dev), \
856 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
857
3d567e0e 858/**
0aa0f5d1 859 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 860 * @vend: the 16 bit PCI Vendor ID
861 * @dev: the 16 bit PCI Device ID
862 * @subvend: the 16 bit PCI Subvendor ID
863 * @subdev: the 16 bit PCI Subdevice ID
864 *
865 * This macro is used to create a struct pci_device_id that matches a
866 * specific device with subsystem information.
867 */
868#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
869 .vendor = (vend), .device = (dev), \
870 .subvendor = (subvend), .subdevice = (subdev)
871
1da177e4 872/**
0aa0f5d1 873 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 874 * @dev_class: the class, subclass, prog-if triple for this device
875 * @dev_class_mask: the class mask for this device
876 *
877 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 878 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 879 * fields will be set to PCI_ANY_ID.
880 */
881#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
882 .class = (dev_class), .class_mask = (dev_class_mask), \
883 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
884 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
885
1597cacb 886/**
0aa0f5d1 887 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 888 * @vend: the vendor name
889 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 890 *
891 * This macro is used to create a struct pci_device_id that matches a
892 * specific PCI device. The subvendor, and subdevice fields will be set
893 * to PCI_ANY_ID. The macro allows the next field to follow as the device
894 * private data.
895 */
c1309040
MR		 896#define PCI_VDEVICE(vend, dev) \
897 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
898 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 899
b72ae8ca
AS		 900/**
901 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
902 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
903 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
904 * @data: the driver data to be filled
905 *
906 * This macro is used to create a struct pci_device_id that matches a
907 * specific PCI device. The subvendor, and subdevice fields will be set
908 * to PCI_ANY_ID.
909 */
910#define PCI_DEVICE_DATA(vend, dev, data) \
911 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
912 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
913 .driver_data = (kernel_ulong_t)(data)
914
5bbe029f 915enum {
0aa0f5d1
BH		 916 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
917 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
918 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
919 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
920 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 921 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 922 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 923};
924
0d8006dd
HX		 925#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
926#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
927#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
928#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
929
0aa0f5d1 930/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 931#ifdef CONFIG_PCI
932
5bbe029f
BH		 933extern unsigned int pci_flags;
934
935static inline void pci_set_flags(int flags) { pci_flags = flags; }
936static inline void pci_add_flags(int flags) { pci_flags |= flags; }
937static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
938static inline int pci_has_flag(int flag) { return pci_flags & flag; }
939
a58674ff 940void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 941
942enum pcie_bus_config_types {
0aa0f5d1
BH		 943 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
944 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
945 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
946 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
947 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 948};
949
950extern enum pcie_bus_config_types pcie_bus_config;
951
1da177e4
LT		 952extern struct bus_type pci_bus_type;
953
f7625980
BH		 954/* Do NOT directly access these two variables, unless you are arch-specific PCI
955 * code, or PCI core code. */
0aa0f5d1 956extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 957/* Some device drivers need know if PCI is initiated */
f39d5b72 958int no_pci_devices(void);
1da177e4 959
3c449ed0 960void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 961void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 962void pcibios_add_bus(struct pci_bus *bus);
963void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 964void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 965int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 966/* Architecture-specific versions may override this (weak) */
05cca6e5 967char *pcibios_setup(char *str);
1da177e4
LT		 968
969/* Used only when drivers/pci/setup.c is used */
3b7a17fc 970resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 971 resource_size_t,
e31dd6e4 972 resource_size_t);
1da177e4 973
d1bbf38a 974/* Weak but can be overridden by arch */
2d1c8618
BH		 975void pci_fixup_cardbus(struct pci_bus *);
976
1da177e4
LT		 977/* Generic PCI functions used internally */
978
fc279850 979void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 980 struct resource *res);
fc279850 981void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 982 struct pci_bus_region *region);
d1fd4fb6 983void pcibios_scan_specific_bus(int busn);
f39d5b72 984struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 985void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 986struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 987struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
988 struct pci_ops *ops, void *sysdata,
989 struct list_head *resources);
49b8e3f3 990int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 991int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
992int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
993void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 994struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 995 struct pci_ops *ops, void *sysdata,
996 struct list_head *resources);
1228c4b6 997int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 998struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
999 int busnr);
f46753c5 1000struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 1001 const char *name,
1002 struct hotplug_slot *hotplug);
f46753c5 1003void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 1004#ifdef CONFIG_SYSFS
1005void pci_dev_assign_slot(struct pci_dev *dev);
1006#else
1007static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1008#endif
1da177e4 1009int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 1010struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 1011void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 1012unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 1013void pci_bus_add_device(struct pci_dev *dev);
1da177e4 1014void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 1015struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1016 struct resource *res);
c56d4450 1017struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 1018u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 1019int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 1020u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 1021struct pci_dev *pci_dev_get(struct pci_dev *dev);
1022void pci_dev_put(struct pci_dev *dev);
1023void pci_remove_bus(struct pci_bus *b);
1024void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 1025void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 1026void pci_stop_root_bus(struct pci_bus *bus);
1027void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 1028void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 1029void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 1030void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 1031#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1032#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 1033
1034/* Generic PCI functions exported to card drivers */
1035
388c8c16
JB		 1036enum pci_lost_interrupt_reason {
1037 PCI_LOST_IRQ_NO_INFORMATION = 0,
1038 PCI_LOST_IRQ_DISABLE_MSI,
1039 PCI_LOST_IRQ_DISABLE_MSIX,
1040 PCI_LOST_IRQ_DISABLE_ACPI,
1041};
1042enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 1043int pci_find_capability(struct pci_dev *dev, int cap);
1044int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1045int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 1046int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 1047int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1048int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 1049struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 1050
d42552c3 1051struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 1052 struct pci_dev *from);
05cca6e5 1053struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 1054 unsigned int ss_vendor, unsigned int ss_device,
1055 struct pci_dev *from);
05cca6e5 1056struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 1057struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1058 unsigned int devfn);
05cca6e5 1059struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 1060int pci_dev_present(const struct pci_device_id *ids);
1061
05cca6e5
GKH		 1062int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1063 int where, u8 *val);
1064int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1065 int where, u16 *val);
1066int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1067 int where, u32 *val);
1068int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1069 int where, u8 val);
1070int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1071 int where, u16 val);
1072int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1073 int where, u32 val);
1f94a94f
RH		 1074
1075int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1076 int where, int size, u32 *val);
1077int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1078 int where, int size, u32 val);
1079int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1080 int where, int size, u32 *val);
1081int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1082 int where, int size, u32 val);
1083
a72b46c3 1084struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1085
d3881e50
KB		 1086int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1087int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1088int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1089int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1090int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1091int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 1092
8c0d3a02
JL		 1093int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1094int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1095int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1096int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1097int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1098 u16 clear, u16 set);
1099int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1100 u32 clear, u32 set);
1101
1102static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1103 u16 set)
1104{
1105 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1106}
1107
1108static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1109 u32 set)
1110{
1111 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1112}
1113
1114static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1115 u16 clear)
1116{
1117 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1118}
1119
1120static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1121 u32 clear)
1122{
1123 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1124}
1125
0aa0f5d1 1126/* User-space driven config access */
c63587d7
AW		 1127int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1128int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1129int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1130int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1131int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1132int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1133
4a7fb636 1134int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1135int __must_check pci_enable_device_io(struct pci_dev *dev);
1136int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1137int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1138int __must_check pcim_enable_device(struct pci_dev *pdev);
1139void pcim_pin_device(struct pci_dev *pdev);
1140
99b3c58f
PG		 1141static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1142{
1143 /*
1144 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1145 * writable and no quirk has marked the feature broken.
1146 */
1147 return !pdev->broken_intx_masking;
1148}
1149
296ccb08
YS		 1150static inline int pci_is_enabled(struct pci_dev *pdev)
1151{
1152 return (atomic_read(&pdev->enable_cnt) > 0);
1153}
1154
9ac7849e
TH		 1155static inline int pci_is_managed(struct pci_dev *pdev)
1156{
1157 return pdev->is_managed;
1158}
1159
1da177e4 1160void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1161
1162extern unsigned int pcibios_max_latency;
1da177e4 1163void pci_set_master(struct pci_dev *dev);
6a479079 1164void pci_clear_master(struct pci_dev *dev);
96c55900 1165
f7bdd12d 1166int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1167int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1168#define HAVE_PCI_SET_MWI
4a7fb636 1169int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1170int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1171int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1172void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1173void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1174bool pci_check_and_mask_intx(struct pci_dev *dev);
1175bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1176int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1177int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1178int pcix_get_max_mmrbc(struct pci_dev *dev);
1179int pcix_get_mmrbc(struct pci_dev *dev);
1180int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1181int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1182int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1183int pcie_get_mps(struct pci_dev *dev);
1184int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1185u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1186 enum pci_bus_speed *speed,
1187 enum pcie_link_width *width);
9e506a7b 1188void pcie_print_link_status(struct pci_dev *dev);
2d2917f7 1189bool pcie_has_flr(struct pci_dev *dev);
91295d79 1190int pcie_flr(struct pci_dev *dev);
a96d627a 1191int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1192int pci_reset_function(struct pci_dev *dev);
a477b9cd 1193int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1194int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1195int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1196int pci_probe_reset_bus(struct pci_bus *bus);
c6a44ba9 1197int pci_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1198void pci_reset_secondary_bus(struct pci_dev *dev);
1199void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1200void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1201int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1202int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1203void pci_release_resource(struct pci_dev *dev, int resno);
1204int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1205int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1206bool pci_device_is_present(struct pci_dev *pdev);
08249651 1207void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1208
704e8953
CH		 1209int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1210 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1211 const char *fmt, ...);
1212void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1213
1da177e4 1214/* ROM control related routines */
e416de5e
AC		 1215int pci_enable_rom(struct pci_dev *pdev);
1216void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1217void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1218void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
fffe01f7 1219void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1220
1221/* Power management related routines */
1222int pci_save_state(struct pci_dev *dev);
1d3c16a8 1223void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1224struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1225int pci_load_saved_state(struct pci_dev *dev,
1226 struct pci_saved_state *state);
ffbdd3f7
AW		 1227int pci_load_and_free_saved_state(struct pci_dev *dev,
1228 struct pci_saved_state **state);
fd0f7f73
AW		 1229struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1230struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1231 u16 cap);
1232int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1233int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1234 u16 cap, unsigned int size);
0e5dd46b 1235int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1236int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1237pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1238bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1239void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1240int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1241int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1242int pci_prepare_to_sleep(struct pci_dev *dev);
1243int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1244bool pci_dev_run_wake(struct pci_dev *dev);
9d26d3a8
MW		 1245void pci_d3cold_enable(struct pci_dev *dev);
1246void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1247bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
2a4d2c42
LW		 1248void pci_wakeup_bus(struct pci_bus *bus);
1249void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1250
bb209c82
BH		 1251/* For use by arch with custom probe code */
1252void set_pcie_port_type(struct pci_dev *pdev);
1253void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1254
ce5ccdef 1255/* Functions for PCI Hotplug drivers to use */
05cca6e5 1256int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1257unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1258unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1259void pci_lock_rescan_remove(void);
1260void pci_unlock_rescan_remove(void);
ce5ccdef 1261
0aa0f5d1 1262/* Vital Product Data routines */
287d19ce
SH		 1263ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1264ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1265int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1266
1da177e4 1267/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1268resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1269void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1270void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1271void pci_bus_size_bridges(struct pci_bus *bus);
1272int pci_claim_resource(struct pci_dev *, int);
8505e729 1273int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1274void pci_assign_unassigned_resources(void);
6841ec68 1275void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1276void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1277void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1278int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1279void pdev_enable_device(struct pci_dev *);
842de40d 1280int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1281void pci_assign_irq(struct pci_dev *dev);
afd29f90 1282struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1283#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1284int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1285int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1286void pci_release_regions(struct pci_dev *);
4a7fb636 1287int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 1288void pci_release_region(struct pci_dev *, int);
c87deff7 1289int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1290int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1291void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1292
1293/* drivers/pci/bus.c */
45ca9e97 1294void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1295void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1296 resource_size_t offset);
45ca9e97 1297void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1298void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1299 unsigned int flags);
2fe2abf8
BH		 1300struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1301void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1302int devm_request_pci_bus_resources(struct device *dev,
1303 struct list_head *resources);
2fe2abf8 1304
bfc45606
DD		 1305/* Temporary until new and working PCI SBR API in place */
1306int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1307
89a74ecc 1308#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1309 for (i = 0; \
1310 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1311 i++)
89a74ecc 1312
4a7fb636
AM		 1313int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1314 struct resource *res, resource_size_t size,
1315 resource_size_t align, resource_size_t min,
664c2848 1316 unsigned long type_mask,
3b7a17fc
DB		 1317 resource_size_t (*alignf)(void *,
1318 const struct resource *,
b26b2d49
DB		 1319 resource_size_t,
1320 resource_size_t),
4a7fb636 1321 void *alignf_data);
1da177e4 1322
8b921acf 1323
fcfaab30
GP		 1324int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1325 resource_size_t size);
c5076cfe
TN		 1326unsigned long pci_address_to_pio(phys_addr_t addr);
1327phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1328int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
a5fb9fb0
SS		 1329int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1330 phys_addr_t phys_addr);
4d3f1384 1331void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1332void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1333 resource_size_t offset,
1334 resource_size_t size);
1335void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1336 struct resource *res);
8b921acf 1337
3a9ad0b4 1338static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1339{
1340 struct pci_bus_region region;
1341
1342 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1343 return region.start;
1344}
1345
863b18f4 1346/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1347int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1348 const char *mod_name);
bba81165 1349
0aa0f5d1 1350/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1351#define pci_register_driver(driver) \
1352 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1353
05cca6e5 1354void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1355
1356/**
1357 * module_pci_driver() - Helper macro for registering a PCI driver
1358 * @__pci_driver: pci_driver struct
1359 *
1360 * Helper macro for PCI drivers which do not do anything special in module
1361 * init/exit. This eliminates a lot of boilerplate. Each module may only
1362 * use this macro once, and calling it replaces module_init() and module_exit()
1363 */
1364#define module_pci_driver(__pci_driver) \
0aa0f5d1 1365 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1366
b4eb6cdb
PG		 1367/**
1368 * builtin_pci_driver() - Helper macro for registering a PCI driver
1369 * @__pci_driver: pci_driver struct
1370 *
1371 * Helper macro for PCI drivers which do not do anything special in their
1372 * init code. This eliminates a lot of boilerplate. Each driver may only
1373 * use this macro once, and calling it replaces device_initcall(...)
1374 */
1375#define builtin_pci_driver(__pci_driver) \
1376 builtin_driver(__pci_driver, pci_register_driver)
1377
05cca6e5 1378struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1379int pci_add_dynid(struct pci_driver *drv,
1380 unsigned int vendor, unsigned int device,
1381 unsigned int subvendor, unsigned int subdevice,
1382 unsigned int class, unsigned int class_mask,
1383 unsigned long driver_data);
05cca6e5
GKH		 1384const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1385 struct pci_dev *dev);
1386int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1387 int pass);
1da177e4 1388
70298c6e 1389void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1390 void *userdata);
ac7dc65a 1391int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1392unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1393void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1394resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1395 unsigned long type);
cecf4864 1396
3448a19d
DA		 1397#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1398#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1399
deb2d2ec 1400int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1401 unsigned int command_bits, u32 flags);
fe537670 1402
d7cc609f
LG		 1403/*
1404 * Virtual interrupts allow for more interrupts to be allocated
1405 * than the device has interrupts for. These are not programmed
1406 * into the device's MSI-X table and must be handled by some
1407 * other driver means.
1408 */
1409#define PCI_IRQ_VIRTUAL (1 << 4)
1410
4fe0d154
CH		 1411#define PCI_IRQ_ALL_TYPES \
1412 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1413
1da177e4
LT		 1414/* kmem_cache style wrapper around pci_alloc_consistent() */
1415
1416#include <linux/dmapool.h>
1417
1418#define pci_pool dma_pool
1419#define pci_pool_create(name, pdev, size, align, allocation) \
1420 dma_pool_create(name, &pdev->dev, size, align, allocation)
1421#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1422#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1423#define pci_pool_zalloc(pool, flags, handle) \
1424 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1425#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1426
1da177e4 1427struct msix_entry {
0aa0f5d1
BH		 1428 u32 vector; /* Kernel uses to write allocated vector */
1429 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1430};
1431
4c859804
BH		 1432#ifdef CONFIG_PCI_MSI
1433int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1434void pci_disable_msi(struct pci_dev *dev);
4c859804 1435int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1436void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1437void pci_restore_msi_state(struct pci_dev *dev);
1438int pci_msi_enabled(void);
4fe03955 1439int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1440int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1441 int minvec, int maxvec);
f7fc32cb
AG		 1442static inline int pci_enable_msix_exact(struct pci_dev *dev,
1443 struct msix_entry *entries, int nvec)
1444{
1445 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1446 if (rc < 0)
1447 return rc;
1448 return 0;
1449}
402723ad
CH		 1450int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1451 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1452 struct irq_affinity *affd);
402723ad 1453
aff17164
CH		 1454void pci_free_irq_vectors(struct pci_dev *dev);
1455int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1456const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1457int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1458
4c859804 1459#else
2ee546c4 1460static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1461static inline void pci_disable_msi(struct pci_dev *dev) { }
1462static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1463static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1464static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1465static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1466static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1467{ return -ENOSYS; }
302a2523 1468static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1469 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1470{ return -ENOSYS; }
f7fc32cb 1471static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1472 struct msix_entry *entries, int nvec)
f7fc32cb 1473{ return -ENOSYS; }
402723ad
CH		 1474
1475static inline int
1476pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1477 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1478 struct irq_affinity *aff_desc)
aff17164 1479{
83b4605b
CH		 1480 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1481 return 1;
1482 return -ENOSPC;
aff17164 1483}
402723ad 1484
aff17164
CH		 1485static inline void pci_free_irq_vectors(struct pci_dev *dev)
1486{
1487}
1488
1489static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1490{
1491 if (WARN_ON_ONCE(nr > 0))
1492 return -EINVAL;
1493 return dev->irq;
1494}
ee8d41e5
TG		 1495static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1496 int vec)
1497{
1498 return cpu_possible_mask;
1499}
27ddb689
SL		 1500
1501static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1502{
1503 return first_online_node;
1504}
1da177e4
LT		 1505#endif
1506
0d58e6c1
PB		 1507/**
1508 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1509 * @d: the INTx IRQ domain
1510 * @node: the DT node for the device whose interrupt we're translating
1511 * @intspec: the interrupt specifier data from the DT
1512 * @intsize: the number of entries in @intspec
1513 * @out_hwirq: pointer at which to write the hwirq number
1514 * @out_type: pointer at which to write the interrupt type
1515 *
1516 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1517 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1518 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1519 * INTx value to obtain the hwirq number.
1520 *
1521 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1522 */
1523static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1524 struct device_node *node,
1525 const u32 *intspec,
1526 unsigned int intsize,
1527 unsigned long *out_hwirq,
1528 unsigned int *out_type)
1529{
1530 const u32 intx = intspec[0];
1531
1532 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1533 return -EINVAL;
1534
1535 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1536 return 0;
1537}
1538
ab0724ff 1539#ifdef CONFIG_PCIEPORTBUS
415e12b2 1540extern bool pcie_ports_disabled;
5352a44a 1541extern bool pcie_ports_native;
ab0724ff
MT		 1542#else
1543#define pcie_ports_disabled true
5352a44a 1544#define pcie_ports_native false
ab0724ff 1545#endif
415e12b2 1546
7ce2e76a
KW		 1547#define PCIE_LINK_STATE_L0S 1
1548#define PCIE_LINK_STATE_L1 2
1549#define PCIE_LINK_STATE_CLKPM 4
1550
4c859804 1551#ifdef CONFIG_PCIEASPM
7ce2e76a
KW		 1552int pci_disable_link_state(struct pci_dev *pdev, int state);
1553int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1554void pcie_no_aspm(void);
f39d5b72 1555bool pcie_aspm_support_enabled(void);
accd2dd7 1556bool pcie_aspm_enabled(struct pci_dev *pdev);
4c859804 1557#else
7ce2e76a
KW		 1558static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1559{ return 0; }
1560static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1561{ return 0; }
1562static inline void pcie_no_aspm(void) { }
4c859804 1563static inline bool pcie_aspm_support_enabled(void) { return false; }
accd2dd7 1564static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
3e1b1600
AP		 1565#endif
1566
415e12b2 1567#ifdef CONFIG_PCIEAER
415e12b2
RW		 1568bool pci_aer_available(void);
1569#else
415e12b2
RW		 1570static inline bool pci_aer_available(void) { return false; }
1571#endif
1572
cef74409
GK		 1573bool pci_ats_disabled(void);
1574
f39d5b72
BH		 1575void pci_cfg_access_lock(struct pci_dev *dev);
1576bool pci_cfg_access_trylock(struct pci_dev *dev);
1577void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1578
4352dfd5
GKH		 1579/*
1580 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1581 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1582 * configuration space.
1583 */
32a2eea7
JG		 1584#ifdef CONFIG_PCI_DOMAINS
1585extern int pci_domains_supported;
1586#else
1587enum { pci_domains_supported = 0 };
2ee546c4
BH		 1588static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1589static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1590#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1591
670ba0c8
CM		 1592/*
1593 * Generic implementation for PCI domain support. If your
1594 * architecture does not need custom management of PCI
1595 * domains then this implementation will be used
1596 */
1597#ifdef CONFIG_PCI_DOMAINS_GENERIC
1598static inline int pci_domain_nr(struct pci_bus *bus)
1599{
1600 return bus->domain_nr;
1601}
2ab51dde
TN		 1602#ifdef CONFIG_ACPI
1603int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1604#else
2ab51dde
TN		 1605static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1606{ return 0; }
1607#endif
9c7cb891 1608int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1609#endif
1610
0aa0f5d1 1611/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1612typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1613 unsigned int command_bits, u32 flags);
f39d5b72 1614void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1615
be9d2e89
JT		 1616static inline int
1617pci_request_io_regions(struct pci_dev *pdev, const char *name)
1618{
1619 return pci_request_selected_regions(pdev,
1620 pci_select_bars(pdev, IORESOURCE_IO), name);
1621}
1622
1623static inline void
1624pci_release_io_regions(struct pci_dev *pdev)
1625{
1626 return pci_release_selected_regions(pdev,
1627 pci_select_bars(pdev, IORESOURCE_IO));
1628}
1629
1630static inline int
1631pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1632{
1633 return pci_request_selected_regions(pdev,
1634 pci_select_bars(pdev, IORESOURCE_MEM), name);
1635}
1636
1637static inline void
1638pci_release_mem_regions(struct pci_dev *pdev)
1639{
1640 return pci_release_selected_regions(pdev,
1641 pci_select_bars(pdev, IORESOURCE_MEM));
1642}
1643
4352dfd5 1644#else /* CONFIG_PCI is not enabled */
1da177e4 1645
5bbe029f
BH		 1646static inline void pci_set_flags(int flags) { }
1647static inline void pci_add_flags(int flags) { }
1648static inline void pci_clear_flags(int flags) { }
1649static inline int pci_has_flag(int flag) { return 0; }
1650
1da177e4 1651/*
0aa0f5d1
BH		 1652 * If the system does not have PCI, clearly these return errors. Define
1653 * these as simple inline functions to avoid hair in drivers.
1da177e4 1654 */
05cca6e5
GKH		 1655#define _PCI_NOP(o, s, t) \
1656 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1657 int where, t val) \
1da177e4 1658 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1659
1660#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1661 _PCI_NOP(o, word, u16 x) \
1662 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1663_PCI_NOP_ALL(read, *)
1664_PCI_NOP_ALL(write,)
1665
d42552c3 1666static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1667 unsigned int device,
1668 struct pci_dev *from)
2ee546c4 1669{ return NULL; }
d42552c3 1670
05cca6e5
GKH		 1671static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1672 unsigned int device,
1673 unsigned int ss_vendor,
1674 unsigned int ss_device,
b08508c4 1675 struct pci_dev *from)
2ee546c4 1676{ return NULL; }
1da177e4 1677
05cca6e5
GKH		 1678static inline struct pci_dev *pci_get_class(unsigned int class,
1679 struct pci_dev *from)
2ee546c4 1680{ return NULL; }
1da177e4
LT		 1681
1682#define pci_dev_present(ids) (0)
ed4aaadb 1683#define no_pci_devices() (1)
1da177e4
LT		 1684#define pci_dev_put(dev) do { } while (0)
1685
2ee546c4
BH		 1686static inline void pci_set_master(struct pci_dev *dev) { }
1687static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1688static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1689static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1690{ return -EBUSY; }
05cca6e5
GKH		 1691static inline int __pci_register_driver(struct pci_driver *drv,
1692 struct module *owner)
2ee546c4 1693{ return 0; }
05cca6e5 1694static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1695{ return 0; }
1696static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1697static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1698{ return 0; }
05cca6e5
GKH		 1699static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1700 int cap)
2ee546c4 1701{ return 0; }
05cca6e5 1702static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1703{ return 0; }
05cca6e5 1704
1da177e4 1705/* Power management related routines */
2ee546c4
BH		 1706static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1707static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1708static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1709{ return 0; }
3449248c 1710static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1711{ return 0; }
05cca6e5
GKH		 1712static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1713 pm_message_t state)
2ee546c4 1714{ return PCI_D0; }
05cca6e5
GKH		 1715static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1716 int enable)
2ee546c4 1717{ return 0; }
48a92a81 1718
afd29f90
MW		 1719static inline struct resource *pci_find_resource(struct pci_dev *dev,
1720 struct resource *res)
1721{ return NULL; }
05cca6e5 1722static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1723{ return -EIO; }
1724static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1725
c5076cfe
TN		 1726static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1727
d80d0217
RD		 1728static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1729{ return NULL; }
d80d0217
RD		 1730static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1731 unsigned int devfn)
1732{ return NULL; }
7912af5c
RD		 1733static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1734 unsigned int bus, unsigned int devfn)
1735{ return NULL; }
d80d0217 1736
2ee546c4
BH		 1737static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1738static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 1739
fb8a0d9d
WM		 1740#define dev_is_pci(d) (false)
1741#define dev_is_pf(d) (false)
fe594932
GU		 1742static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1743{ return false; }
80db6f08
NC		 1744static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1745 struct device_node *node,
1746 const u32 *intspec,
1747 unsigned int intsize,
1748 unsigned long *out_hwirq,
1749 unsigned int *out_type)
1750{ return -EINVAL; }
9c212009
LR		 1751
1752static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1753 struct pci_dev *dev)
1754{ return NULL; }
b9ae16d8 1755static inline bool pci_ats_disabled(void) { return true; }
0d8006dd
HX		 1756
1757static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1758{
1759 return -EINVAL;
1760}
1761
1762static inline int
1763pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1764 unsigned int max_vecs, unsigned int flags,
1765 struct irq_affinity *aff_desc)
1766{
1767 return -ENOSPC;
1768}
4352dfd5 1769#endif /* CONFIG_PCI */
1da177e4 1770
0d8006dd
HX		 1771static inline int
1772pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1773 unsigned int max_vecs, unsigned int flags)
1774{
1775 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1776 NULL);
1777}
1778
6e1ffbb7
JPB		 1779#ifdef CONFIG_PCI_ATS
1780/* Address Translation Service */
6e1ffbb7
JPB		 1781int pci_enable_ats(struct pci_dev *dev, int ps);
1782void pci_disable_ats(struct pci_dev *dev);
1783int pci_ats_queue_depth(struct pci_dev *dev);
1784int pci_ats_page_aligned(struct pci_dev *dev);
1785#else
6e1ffbb7
JPB		 1786static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1787static inline void pci_disable_ats(struct pci_dev *d) { }
1788static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1789static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
1790#endif
1791
4352dfd5
GKH		 1792/* Include architecture-dependent settings and functions */
1793
1794#include <asm/pci.h>
1da177e4 1795
d1bbf38a 1796/* These two functions provide almost identical functionality. Depending
f7195824
DW		 1797 * on the architecture, one will be implemented as a wrapper around the
1798 * other (in drivers/pci/mmap.c).
1799 *
1800 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1801 * is expected to be an offset within that region.
1802 *
1803 * pci_mmap_page_range() is the legacy architecture-specific interface,
1804 * which accepts a "user visible" resource address converted by
1805 * pci_resource_to_user(), as used in the legacy mmap() interface in
1806 * /proc/bus/pci/.
1807 */
1808int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1809 struct vm_area_struct *vma,
1810 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1811int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1812 struct vm_area_struct *vma,
11df1954
DW		 1813 enum pci_mmap_state mmap_state, int write_combine);
1814
ae749c7a
DW		 1815#ifndef arch_can_pci_mmap_wc
1816#define arch_can_pci_mmap_wc() 0
1817#endif
2bea36fd 1818
e854d8b2
DW		 1819#ifndef arch_can_pci_mmap_io
1820#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1821#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1822#else
1823int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1824#endif
ae749c7a 1825
92016ba5
JO		 1826#ifndef pci_root_bus_fwnode
1827#define pci_root_bus_fwnode(bus) NULL
1828#endif
1829
0aa0f5d1
BH		 1830/*
1831 * These helpers provide future and backwards compatibility
1832 * for accessing popular PCI BAR info
1833 */
05cca6e5
GKH		 1834#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1835#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1836#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1837#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1838 ((pci_resource_start((dev), (bar)) == 0 && \
1839 pci_resource_end((dev), (bar)) == \
1840 pci_resource_start((dev), (bar))) ? 0 : \
1841 \
1842 (pci_resource_end((dev), (bar)) - \
1843 pci_resource_start((dev), (bar)) + 1))
1da177e4 1844
0aa0f5d1
BH		 1845/*
1846 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1847 * driver-specific data. They are really just a wrapper around
1848 * the generic device structure functions of these calls.
1849 */
05cca6e5 1850static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1851{
1852 return dev_get_drvdata(&pdev->dev);
1853}
1854
05cca6e5 1855static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1856{
1857 dev_set_drvdata(&pdev->dev, data);
1858}
1859
2fc90f61 1860static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1861{
c6c4f070 1862 return dev_name(&pdev->dev);
1da177e4
LT		 1863}
1864
8221a013
BH		 1865void pci_resource_to_user(const struct pci_dev *dev, int bar,
1866 const struct resource *rsrc,
1867 resource_size_t *start, resource_size_t *end);
2311b1f2 1868
1da177e4 1869/*
0aa0f5d1
BH		 1870 * The world is not perfect and supplies us with broken PCI devices.
1871 * For at least a part of these bugs we need a work-around, so both
1872 * generic (drivers/pci/quirks.c) and per-architecture code can define
1873 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1874 */
1875
1876struct pci_fixup {
0aa0f5d1
BH		 1877 u16 vendor; /* Or PCI_ANY_ID */
1878 u16 device; /* Or PCI_ANY_ID */
1879 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 1880 unsigned int class_shift; /* should be 0, 8, 16 */
c9d8b55f
AB		 1881#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1882 int hook_offset;
1883#else
1da177e4 1884 void (*hook)(struct pci_dev *dev);
c9d8b55f 1885#endif
1da177e4
LT		 1886};
1887
1888enum pci_fixup_pass {
1889 pci_fixup_early, /* Before probing BARs */
1890 pci_fixup_header, /* After reading configuration header */
1891 pci_fixup_final, /* Final phase of device fixups */
1892 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1893 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1894 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1895 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1896 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1897};
1898
c9d8b55f
AB		 1899#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1900#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1901 class_shift, hook) \
1902 __ADDRESSABLE(hook) \
1903 asm(".section " #sec ", \"a\" \n" \
1904 ".balign 16 \n" \
1905 ".short " #vendor ", " #device " \n" \
1906 ".long " #class ", " #class_shift " \n" \
1907 ".long " #hook " - . \n" \
1908 ".previous \n");
1909#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1910 class_shift, hook) \
1911 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1912 class_shift, hook)
1913#else
1da177e4 1914/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1915#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1916 class_shift, hook) \
ecf61c78 1917 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1918 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1919 = { vendor, device, class, class_shift, hook };
c9d8b55f 1920#endif
f4ca5c6a
YL		 1921
1922#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1923 class_shift, hook) \
1924 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1925 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1926#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1927 class_shift, hook) \
1928 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1929 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1930#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1931 class_shift, hook) \
1932 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1933 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1934#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1935 class_shift, hook) \
1936 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1937 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1938#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1939 class_shift, hook) \
1940 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1941 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1942#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1943 class_shift, hook) \
1944 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1945 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1946#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1947 class_shift, hook) \
1948 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1949 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 1950#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1951 class_shift, hook) \
1952 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1953 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 1954
1da177e4
LT		 1955#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1956 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1957 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1958#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1960 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1961#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1963 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1964#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1966 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1967#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1969 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1970#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1972 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1973#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1975 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1976#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1977 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1978 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 1979
93177a74 1980#ifdef CONFIG_PCI_QUIRKS
1da177e4 1981void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1982#else
1983static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1984 struct pci_dev *dev) { }
93177a74 1985#endif
1da177e4 1986
05cca6e5 1987void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1988void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1989void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1990int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1991int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1992 const char *name);
fb7ebfe4 1993void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1994
1da177e4 1995extern int pci_pci_problems;
236561e5 1996#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1997#define PCIPCI_TRITON 2
1998#define PCIPCI_NATOMA 4
1999#define PCIPCI_VIAETBF 8
2000#define PCIPCI_VSFX 16
236561e5
AC		 2001#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2002#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 2003
4516a618
AN		 2004extern unsigned long pci_cardbus_io_size;
2005extern unsigned long pci_cardbus_mem_size;
15856ad5 2006extern u8 pci_dfl_cache_line_size;
ac1aa47b 2007extern u8 pci_cache_line_size;
4516a618 2008
f7625980 2009/* Architecture-specific versions may override these (weak) */
19792a08 2010void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 2011void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 2012int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2013 enum pcie_reset_state state);
eca0d467 2014int pcibios_add_device(struct pci_dev *dev);
6ae32c53 2015void pcibios_release_device(struct pci_dev *dev);
5d32a665 2016#ifdef CONFIG_PCI
a43ae58c 2017void pcibios_penalize_isa_irq(int irq, int active);
5d32a665
SK		 2018#else
2019static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2020#endif
890e4847
JL		 2021int pcibios_alloc_irq(struct pci_dev *dev);
2022void pcibios_free_irq(struct pci_dev *dev);
619e6f34 2023resource_size_t pcibios_default_alignment(void);
575e3348 2024
699c1985
SO		 2025#ifdef CONFIG_HIBERNATE_CALLBACKS
2026extern struct dev_pm_ops pcibios_pm_ops;
2027#endif
2028
935c760e 2029#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 2030void __init pci_mmcfg_early_init(void);
2031void __init pci_mmcfg_late_init(void);
7752d5cf 2032#else
bb63b421 2033static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 2034static inline void pci_mmcfg_late_init(void) { }
2035#endif
2036
642c92da 2037int pci_ext_cfg_avail(void);
0ef5f8f6 2038
1684f5dd 2039void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 2040void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 2041
dd7cc44d 2042#ifdef CONFIG_PCI_IOV
b07579c0
WY		 2043int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2044int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2045
f39d5b72
BH		 2046int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2047void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 2048int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2049void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 2050int pci_num_vf(struct pci_dev *dev);
5a8eb242 2051int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 2052int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2053int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 2054int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 2055resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 2056void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 2057
2058/* Arch may override these (weak) */
2059int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2060int pcibios_sriov_disable(struct pci_dev *pdev);
2061resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 2062#else
b07579c0
WY		 2063static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2064{
2065 return -ENOSYS;
2066}
2067static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2068{
2069 return -ENOSYS;
2070}
dd7cc44d 2071static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2072{ return -ENODEV; }
753f6124 2073static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2074{
2075 return -ENOSYS;
2076}
2077static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2078 int id) { }
2ee546c4 2079static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2080static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2081static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2082{ return 0; }
bff73156 2083static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2084{ return 0; }
bff73156 2085static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2086{ return 0; }
8effc395 2087#define pci_sriov_configure_simple NULL
0e6c9122
WY		 2088static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2089{ return 0; }
608c0d88 2090static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 2091#endif
2092
c825bc94 2093#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2094void pci_hp_create_module_link(struct pci_slot *pci_slot);
2095void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2096#endif
2097
d7b7e605
KK		 2098/**
2099 * pci_pcie_cap - get the saved PCIe capability offset
2100 * @dev: PCI device
2101 *
2102 * PCIe capability offset is calculated at PCI device initialization
2103 * time and saved in the data structure. This function returns saved
2104 * PCIe capability offset. Using this instead of pci_find_capability()
2105 * reduces unnecessary search in the PCI configuration space. If you
2106 * need to calculate PCIe capability offset from raw device for some
2107 * reasons, please use pci_find_capability() instead.
2108 */
2109static inline int pci_pcie_cap(struct pci_dev *dev)
2110{
2111 return dev->pcie_cap;
2112}
2113
7eb776c4
KK		 2114/**
2115 * pci_is_pcie - check if the PCI device is PCI Express capable
2116 * @dev: PCI device
2117 *
a895c28a 2118 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2119 */
2120static inline bool pci_is_pcie(struct pci_dev *dev)
2121{
a895c28a 2122 return pci_pcie_cap(dev);
7eb776c4
KK		 2123}
2124
7c9c003c
MS		 2125/**
2126 * pcie_caps_reg - get the PCIe Capabilities Register
2127 * @dev: PCI device
2128 */
2129static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2130{
2131 return dev->pcie_flags_reg;
2132}
2133
786e2288
YW		 2134/**
2135 * pci_pcie_type - get the PCIe device/port type
2136 * @dev: PCI device
2137 */
2138static inline int pci_pcie_type(const struct pci_dev *dev)
2139{
1c531d82 2140 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2141}
2142
e784930b
JT		 2143static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2144{
2145 while (1) {
2146 if (!pci_is_pcie(dev))
2147 break;
2148 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2149 return dev;
2150 if (!dev->bus->self)
2151 break;
2152 dev = dev->bus->self;
2153 }
2154 return NULL;
2155}
2156
5d990b62 2157void pci_request_acs(void);
ad805758
AW		 2158bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2159bool pci_acs_path_enabled(struct pci_dev *start,
2160 struct pci_dev *end, u16 acs_flags);
430a2368 2161int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2162
7ad506fa 2163#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2164#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2165
2166/* Large Resource Data Type Tag Item Names */
2167#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2168#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2169#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2170
2171#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2172#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2173#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2174
2175/* Small Resource Data Type Tag Item Names */
9eb45d5c 2176#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2177
9eb45d5c 2178#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2179
2180#define PCI_VPD_SRDT_TIN_MASK 0x78
2181#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2182#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2183
2184#define PCI_VPD_LRDT_TAG_SIZE 3
2185#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2186
e1d5bdab
MC		 2187#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2188
4067a854
MC		 2189#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2190#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2191#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2192#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2193
a2ce7662
MC		 2194/**
2195 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2196 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2197 *
2198 * Returns the extracted Large Resource Data Type length.
2199 */
2200static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2201{
2202 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2203}
2204
9eb45d5c
HR		 2205/**
2206 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2207 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2208 *
2209 * Returns the extracted Large Resource Data Type Tag item.
2210 */
2211static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2212{
0aa0f5d1 2213 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
9eb45d5c
HR		 2214}
2215
7ad506fa
MC		 2216/**
2217 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2218 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2219 *
2220 * Returns the extracted Small Resource Data Type length.
2221 */
2222static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2223{
2224 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2225}
2226
9eb45d5c
HR		 2227/**
2228 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2229 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2230 *
2231 * Returns the extracted Small Resource Data Type Tag Item.
2232 */
2233static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2234{
2235 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2236}
2237
e1d5bdab
MC		 2238/**
2239 * pci_vpd_info_field_size - Extracts the information field length
229b4e07 2240 * @info_field: Pointer to the beginning of an information field header
e1d5bdab
MC		 2241 *
2242 * Returns the extracted information field length.
2243 */
2244static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2245{
2246 return info_field[2];
2247}
2248
b55ac1b2
MC		 2249/**
2250 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2251 * @buf: Pointer to buffered vpd data
2252 * @off: The offset into the buffer at which to begin the search
2253 * @len: The length of the vpd buffer
2254 * @rdt: The Resource Data Type to search for
2255 *
2256 * Returns the index where the Resource Data Type was found or
2257 * -ENOENT otherwise.
2258 */
2259int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2260
4067a854
MC		 2261/**
2262 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2263 * @buf: Pointer to buffered vpd data
2264 * @off: The offset into the buffer at which to begin the search
2265 * @len: The length of the buffer area, relative to off, in which to search
2266 * @kw: The keyword to search for
2267 *
2268 * Returns the index where the information field keyword was found or
2269 * -ENOENT otherwise.
2270 */
2271int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2272 unsigned int len, const char *kw);
2273
98d9f30c
BH		 2274/* PCI <-> OF binding helpers */
2275#ifdef CONFIG_OF
2276struct device_node;
b165e2b6 2277struct irq_domain;
b165e2b6 2278struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
3a8f77e4
CP		 2279int pci_parse_request_of_pci_ranges(struct device *dev,
2280 struct list_head *resources,
2281 struct resource **bus_range);
98d9f30c
BH		 2282
2283/* Arch may override this (weak) */
723ec4d0 2284struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2285
0aa0f5d1 2286#else /* CONFIG_OF */
b165e2b6
MZ		 2287static inline struct irq_domain *
2288pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
3a8f77e4
CP		 2289static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2290 struct list_head *resources,
2291 struct resource **bus_range)
2292{
2293 return -EINVAL;
2294}
98d9f30c
BH		 2295#endif /* CONFIG_OF */
2296
ad32eb2d
BM		 2297static inline struct device_node *
2298pci_device_to_OF_node(const struct pci_dev *pdev)
2299{
2300 return pdev ? pdev->dev.of_node : NULL;
2301}
2302
2303static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2304{
2305 return bus ? bus->dev.of_node : NULL;
2306}
2307
471036b2
SS		 2308#ifdef CONFIG_ACPI
2309struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2310
2311void
2312pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
52525b7a 2313bool pci_pr3_present(struct pci_dev *pdev);
471036b2
SS		 2314#else
2315static inline struct irq_domain *
2316pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
46b4bff6 2317static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
471036b2
SS		 2318#endif
2319
eb740b5f
GS		 2320#ifdef CONFIG_EEH
2321static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2322{
2323 return pdev->dev.archdata.edev;
2324}
2325#endif
2326
f0af9593 2327void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2328bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2329int pci_for_each_dma_alias(struct pci_dev *pdev,
2330 int (*fn)(struct pci_dev *pdev,
2331 u16 alias, void *data), void *data);
2332
0aa0f5d1 2333/* Helper functions for operation of device flag */
ce052984
EZ		 2334static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2335{
2336 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2337}
2338static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2339{
2340 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2341}
2342static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2343{
2344 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2345}
19bdb6e4
AW		 2346
2347/**
2348 * pci_ari_enabled - query ARI forwarding status
2349 * @bus: the PCI bus
2350 *
2351 * Returns true if ARI forwarding is enabled.
2352 */
2353static inline bool pci_ari_enabled(struct pci_bus *bus)
2354{
2355 return bus->self && bus->self->ari_enabled;
2356}
bc4b024a 2357
8531e283
LW		 2358/**
2359 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2360 * @pdev: PCI device to check
2361 *
2362 * Walk upwards from @pdev and check for each encountered bridge if it's part
2363 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2364 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2365 */
2366static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2367{
2368 struct pci_dev *parent = pdev;
2369
2370 if (pdev->is_thunderbolt)
2371 return true;
2372
2373 while ((parent = pci_upstream_bridge(parent)))
2374 if (parent->is_thunderbolt)
2375 return true;
2376
2377 return false;
2378}
2379
2e28bc84 2380#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2381void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2382#endif
856e1eb9 2383
0aa0f5d1 2384/* Provide the legacy pci_dma_* API */
bc4b024a
CH		 2385#include <linux/pci-dma-compat.h>
2386
7506dc79
FL		 2387#define pci_printk(level, pdev, fmt, arg...) \
2388 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2389
2390#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2391#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2392#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2393#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2394#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2395#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2396#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2397#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2398
a88a7b3e
BH		 2399#define pci_notice_ratelimited(pdev, fmt, arg...) \
2400 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2401
7f1c62c4
KW		 2402#define pci_info_ratelimited(pdev, fmt, arg...) \
2403 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2404
1da177e4 2405#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)