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PCI: Add resizable BAR infrastructure
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
1da177e4
LT		 16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
1da177e4 19
778382e0
DW		 20#include <linux/mod_devicetable.h>
21
1da177e4 22#include <linux/types.h>
98db6f19 23#include <linux/init.h>
1da177e4
LT		 24#include <linux/ioport.h>
25#include <linux/list.h>
4a7fb636 26#include <linux/compiler.h>
1da177e4 27#include <linux/errno.h>
f46753c5 28#include <linux/kobject.h>
60063497 29#include <linux/atomic.h>
1da177e4 30#include <linux/device.h>
704e8953 31#include <linux/interrupt.h>
1388cc96 32#include <linux/io.h>
14d76b68 33#include <linux/resource_ext.h>
607ca46e 34#include <uapi/linux/pci.h>
1da177e4 35
7e7a43c3
AB		 36#include <linux/pci_ids.h>
37
85467136
SK		 38/*
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
42 *
43 * 7:3 = slot
44 * 2:0 = function
f7625980
BH		 45 *
46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 47 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 48 * the following kernel-only defines are being added here.
85467136 49 */
63ddc0b8 50#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 51/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
52#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53
f46753c5
AC		 54/* pci_slot represents a physical slot */
55struct pci_slot {
56 struct pci_bus *bus; /* The bus this slot is on */
57 struct list_head list; /* node in list of slots on this bus */
58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
60 struct kobject kobj;
61};
62
0ad772ec
AC		 63static inline const char *pci_slot_name(const struct pci_slot *slot)
64{
65 return kobject_name(&slot->kobj);
66}
67
1da177e4
LT		 68/* File state for mmap()s on /proc/bus/pci/X/Y */
69enum pci_mmap_state {
70 pci_mmap_io,
71 pci_mmap_mem
72};
73
fde09c6d
YZ		 74/*
75 * For PCI devices, the region numbers are assigned this way:
76 */
77enum {
78 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCES,
80 PCI_STD_RESOURCE_END = 5,
81
82 /* #6: expansion ROM resource */
83 PCI_ROM_RESOURCE,
84
d1b054da
YZ		 85 /* device specific resources */
86#ifdef CONFIG_PCI_IOV
87 PCI_IOV_RESOURCES,
88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
89#endif
90
fde09c6d
YZ		 91 /* resources assigned to buses behind the bridge */
92#define PCI_BRIDGE_RESOURCE_NUM 4
93
94 PCI_BRIDGE_RESOURCES,
95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
96 PCI_BRIDGE_RESOURCE_NUM - 1,
97
98 /* total resources associated with a PCI device */
99 PCI_NUM_RESOURCES,
100
101 /* preserve this for compatibility */
cda57bf9 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 103};
1da177e4 104
b352baf1
PB		 105/**
106 * enum pci_interrupt_pin - PCI INTx interrupt values
107 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
108 * @PCI_INTERRUPT_INTA: PCI INTA pin
109 * @PCI_INTERRUPT_INTB: PCI INTB pin
110 * @PCI_INTERRUPT_INTC: PCI INTC pin
111 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 *
113 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
114 * PCI_INTERRUPT_PIN register.
115 */
116enum pci_interrupt_pin {
117 PCI_INTERRUPT_UNKNOWN,
118 PCI_INTERRUPT_INTA,
119 PCI_INTERRUPT_INTB,
120 PCI_INTERRUPT_INTC,
121 PCI_INTERRUPT_INTD,
122};
123
124/* The number of legacy PCI INTx interrupts */
125#define PCI_NUM_INTX 4
126
224abb67
BH		 127/*
128 * pci_power_t values must match the bits in the Capabilities PME_Support
129 * and Control/Status PowerState fields in the Power Management capability.
130 */
1da177e4
LT		 131typedef int __bitwise pci_power_t;
132
4352dfd5
GKH		 133#define PCI_D0 ((pci_power_t __force) 0)
134#define PCI_D1 ((pci_power_t __force) 1)
135#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 136#define PCI_D3hot ((pci_power_t __force) 3)
137#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 138#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 139#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 140
00240c38
AS		 141/* Remember to update this when the list above changes! */
142extern const char *pci_power_names[];
143
144static inline const char *pci_power_name(pci_power_t state)
145{
9661e783 146 return pci_power_names[1 + (__force int) state];
00240c38
AS		 147}
148
448bd857
HY		 149#define PCI_PM_D2_DELAY 200
150#define PCI_PM_D3_WAIT 10
151#define PCI_PM_D3COLD_WAIT 100
152#define PCI_PM_BUS_WAIT 50
aa8c6c93 153
392a1ce7 154/** The pci_channel state describes connectivity between the CPU and
155 * the pci device. If some PCI bus between here and the pci device
156 * has crashed or locked up, this info is reflected here.
157 */
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
f7bdd12d
BK		 171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
f7625980 177 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
f7625980 180 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
ba698ad4
DM		 184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI
187 * generation too.
188 */
6b121592 189 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 190 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 191 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 192 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 193 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 194 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 195 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 196 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
197 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 198 /* Do not use bus resets for device */
199 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 200 /* Do not use PM reset even if device advertises NoSoftRst- */
201 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 202 /* Get VPD from function 0 VPD */
203 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
ffff8858
J		 204 /* a non-root bridge where translation occurs, stop alias search here */
205 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 206 /* Do not use FLR even if device advertises PCI_AF_CAP */
207 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
4d071c32
ID		 208 /*
209 * Resume before calling the driver's system suspend hooks, disabling
210 * the direct_complete optimization.
211 */
212 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
a99b646a 213 /* Don't use Relaxed Ordering for TLPs directed at this device */
214 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
ba698ad4
DM		 215};
216
e1d3a908
SA		 217enum pci_irq_reroute_variant {
218 INTEL_IRQ_REROUTE_VARIANT = 1,
219 MAX_IRQ_REROUTE_VARIANTS = 3
220};
221
6e325a62
MT		 222typedef unsigned short __bitwise pci_bus_flags_t;
223enum pci_bus_flags {
032c3d86
JD		 224 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
225 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
226 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
6e325a62
MT		 227};
228
59da381e
JK		 229/* These values come from the PCI Express Spec */
230enum pcie_link_width {
231 PCIE_LNK_WIDTH_RESRV = 0x00,
232 PCIE_LNK_X1 = 0x01,
233 PCIE_LNK_X2 = 0x02,
234 PCIE_LNK_X4 = 0x04,
235 PCIE_LNK_X8 = 0x08,
236 PCIE_LNK_X12 = 0x0C,
237 PCIE_LNK_X16 = 0x10,
238 PCIE_LNK_X32 = 0x20,
239 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
240};
241
536c8cb4
MW		 242/* Based on the PCI Hotplug Spec, but some values are made up by us */
243enum pci_bus_speed {
244 PCI_SPEED_33MHz = 0x00,
245 PCI_SPEED_66MHz = 0x01,
246 PCI_SPEED_66MHz_PCIX = 0x02,
247 PCI_SPEED_100MHz_PCIX = 0x03,
248 PCI_SPEED_133MHz_PCIX = 0x04,
249 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
250 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
251 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
252 PCI_SPEED_66MHz_PCIX_266 = 0x09,
253 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
254 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 255 AGP_UNKNOWN = 0x0c,
256 AGP_1X = 0x0d,
257 AGP_2X = 0x0e,
258 AGP_4X = 0x0f,
259 AGP_8X = 0x10,
536c8cb4
MW		 260 PCI_SPEED_66MHz_PCIX_533 = 0x11,
261 PCI_SPEED_100MHz_PCIX_533 = 0x12,
262 PCI_SPEED_133MHz_PCIX_533 = 0x13,
263 PCIE_SPEED_2_5GT = 0x14,
264 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 265 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 266 PCI_SPEED_UNKNOWN = 0xff,
267};
268
24a4742f 269struct pci_cap_saved_data {
fd0f7f73
AW		 270 u16 cap_nr;
271 bool cap_extended;
24a4742f 272 unsigned int size;
41017f0c
SL		 273 u32 data[0];
274};
275
24a4742f
AW		 276struct pci_cap_saved_state {
277 struct hlist_node next;
278 struct pci_cap_saved_data cap;
279};
280
402723ad 281struct irq_affinity;
7d715a6c 282struct pcie_link_state;
ee69439c 283struct pci_vpd;
d1b054da 284struct pci_sriov;
302b4215 285struct pci_ats;
ee69439c 286
1da177e4
LT		 287/*
288 * The pci_dev structure is used to describe PCI devices.
289 */
290struct pci_dev {
1da177e4
LT		 291 struct list_head bus_list; /* node in per-bus list */
292 struct pci_bus *bus; /* bus this device is on */
293 struct pci_bus *subordinate; /* bus this device bridges to */
294
295 void *sysdata; /* hook for sys-specific extension */
296 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 297 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 298
299 unsigned int devfn; /* encoded device & function index */
300 unsigned short vendor;
301 unsigned short device;
302 unsigned short subsystem_vendor;
303 unsigned short subsystem_device;
304 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 305 u8 revision; /* PCI revision, low byte of class word */
1da177e4 306 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 307#ifdef CONFIG_PCIEAER
308 u16 aer_cap; /* AER capability offset */
309#endif
f7625980 310 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 311 u8 msi_cap; /* MSI capability offset */
312 u8 msix_cap; /* MSI-X capability offset */
f7625980 313 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
1da177e4 314 u8 rom_base_reg; /* which config register controls the ROM */
f7625980
BH		 315 u8 pin; /* which interrupt pin this device uses */
316 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
338c3149 317 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
1da177e4
LT		 318
319 struct pci_driver *driver; /* which driver has allocated this device */
320 u64 dma_mask; /* Mask of the bits of bus address this
321 device implements. Normally this is
322 0xffffffff. You only need to change
323 this if your device has broken DMA
324 or supports 64-bit transfers. */
325
4d57cdfa
FT		 326 struct device_dma_parameters dma_parms;
327
1da177e4
LT		 328 pci_power_t current_state; /* Current operating state. In ACPI-speak,
329 this is D0-D3, D0 being fully functional,
330 and D3 being off. */
703860ed 331 u8 pm_cap; /* PM capability offset */
337001b6
RW		 332 unsigned int pme_support:5; /* Bitmask of states from which PME#
333 can be generated */
379021d5 334 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 335 unsigned int d1_support:1; /* Low power state D1 is supported */
336 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 337 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
338 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 339 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 340 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 341 unsigned int mmio_always_on:1; /* disallow turning off io/mem
342 decoding during bar sizing */
e80bb09d 343 unsigned int wakeup_prepared:1;
448bd857
HY		 344 unsigned int runtime_d3cold:1; /* whether go through runtime
345 D3cold, not set for devices
346 powered on/off by the
347 corresponding bridge */
b440bde7 348 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 349 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
350 controlled exclusively by
351 user sysfs */
1ae861e6 352 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 353 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 354
7d715a6c 355#ifdef CONFIG_PCIEASPM
f7625980 356 struct pcie_link_state *link_state; /* ASPM link state */
7d715a6c
SL		 357#endif
358
392a1ce7 359 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 360 struct device dev; /* Generic device interface */
361
1da177e4
LT		 362 int cfg_size; /* Size of configuration space */
363
364 /*
365 * Instead of touching interrupt line and base address registers
366 * directly, use the values stored here. They might be different!
367 */
368 unsigned int irq;
369 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
370
58d9a38f 371 bool match_driver; /* Skip attaching driver */
1da177e4 372 /* These fields are used by common fixups */
f7625980 373 unsigned int transparent:1; /* Subtractive decode PCI bridge */
1da177e4
LT		 374 unsigned int multifunction:1;/* Part of multi-function device */
375 /* keep track of device state */
8a1bc901 376 unsigned int is_added:1;
1da177e4 377 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 378 unsigned int no_msi:1; /* device may not use msi */
f144d149 379 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
fb51ccbf 380 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 381 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 382 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
f7625980 383 unsigned int msi_enabled:1;
99dc804d 384 unsigned int msix_enabled:1;
58c3a727 385 unsigned int ari_enabled:1; /* ARI forwarding */
d544d75a 386 unsigned int ats_enabled:1; /* Address Translation Service */
a4f4fa68
JPB		 387 unsigned int pasid_enabled:1; /* Process Address Space ID */
388 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 389 unsigned int is_managed:1;
260d703a 390 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 391 unsigned int state_saved:1;
d1b054da 392 unsigned int is_physfn:1;
dd7cc44d 393 unsigned int is_virtfn:1;
711d5779 394 unsigned int reset_fn:1;
28760489 395 unsigned int is_hotplug_bridge:1;
8531e283 396 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
affb72c3
HY		 397 unsigned int __aer_firmware_first_valid:1;
398 unsigned int __aer_firmware_first:1;
99b3c58f 399 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
2b28ae19 400 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
cffe0a2b 401 unsigned int irq_managed:1;
d0751b98 402 unsigned int has_secondary_link:1;
b84106b4 403 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
0b2c2a71 404 unsigned int is_probed:1; /* device probing in progress */
ba698ad4 405 pci_dev_flags_t dev_flags;
bae94d02 406 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 407
1da177e4 408 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 409 struct hlist_head saved_cap_space;
1da177e4
LT		 410 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
411 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
412 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 413 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c
JY		 414
415#ifdef CONFIG_PCIE_PTM
416 unsigned int ptm_root:1;
417 unsigned int ptm_enabled:1;
8b2ec318 418 u8 ptm_granularity;
9bb04a0c 419#endif
ded86d8d 420#ifdef CONFIG_PCI_MSI
1c51b50c 421 const struct attribute_group **msi_irq_groups;
ded86d8d 422#endif
94e61088 423 struct pci_vpd *vpd;
466b3ddf 424#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 425 union {
426 struct pci_sriov *sriov; /* SR-IOV capability related */
427 struct pci_dev *physfn; /* the PF this VF is associated with */
428 };
67930995
BH		 429 u16 ats_cap; /* ATS Capability offset */
430 u8 ats_stu; /* ATS Smallest Translation Unit */
d544d75a 431 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
4ebeb1ec
CT		 432#endif
433#ifdef CONFIG_PCI_PRI
434 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
435#endif
436#ifdef CONFIG_PCI_PASID
437 u16 pasid_features;
d1b054da 438#endif
dbd3fc33 439 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 440 size_t romlen; /* Length of ROM if it's not from the BAR */
782a985d 441 char *driver_override; /* Driver name to force a match */
89ee9f76
KB		 442
443 unsigned long priv_flags; /* Private flags for the pci driver */
1da177e4
LT		 444};
445
dda56549
Y		 446static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
447{
448#ifdef CONFIG_PCI_IOV
449 if (dev->is_virtfn)
450 dev = dev->physfn;
451#endif
dda56549
Y		 452 return dev;
453}
454
3c6e6ae7 455struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 456
1da177e4
LT		 457#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
458#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
459
a7369f1f
LV		 460static inline int pci_channel_offline(struct pci_dev *pdev)
461{
462 return (pdev->error_state != pci_channel_io_normal);
463}
464
5a21d70d 465struct pci_host_bridge {
7b543663 466 struct device dev;
5a21d70d 467 struct pci_bus *bus; /* root bus */
37d6a0a6
AB		 468 struct pci_ops *ops;
469 void *sysdata;
470 int busnr;
14d76b68 471 struct list_head windows; /* resource_entry */
3aa8a41e
MM		 472 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
473 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a
YL		 474 void (*release_fn)(struct pci_host_bridge *);
475 void *release_data;
37d6a0a6 476 struct msi_controller *msi;
e33caa82 477 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
62ce94a7 478 unsigned int no_ext_tags:1; /* no Extended Tags */
7c7a0e94
GP		 479 /* Resource alignment requirements */
480 resource_size_t (*align_resource)(struct pci_dev *dev,
481 const struct resource *res,
482 resource_size_t start,
483 resource_size_t size,
484 resource_size_t align);
59094065 485 unsigned long private[0] ____cacheline_aligned;
5a21d70d 486};
41017f0c 487
7b543663 488#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 489
59094065
TR		 490static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
491{
492 return (void *)bridge->private;
493}
494
495static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
496{
497 return container_of(priv, struct pci_host_bridge, private);
498}
499
a52d1443 500struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 501struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
502 size_t priv);
dff79b91 503void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 504struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
505
4fa2649a
YL		 506void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
507 void (*release_fn)(struct pci_host_bridge *),
508 void *release_data);
7b543663 509
6c0cc950
RW		 510int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
511
2fe2abf8
BH		 512/*
513 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
514 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
515 * buses below host bridges or subtractive decode bridges) go in the list.
516 * Use pci_bus_for_each_resource() to iterate through all the resources.
517 */
518
519/*
520 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
521 * and there's no way to program the bridge with the details of the window.
522 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
523 * decode bit set, because they are explicit and can be programmed with _SRS.
524 */
525#define PCI_SUBTRACTIVE_DECODE 0x1
526
527struct pci_bus_resource {
528 struct list_head list;
529 struct resource *res;
530 unsigned int flags;
531};
4352dfd5
GKH		 532
533#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 534
535struct pci_bus {
536 struct list_head node; /* node in list of buses */
537 struct pci_bus *parent; /* parent bus this bridge is on */
538 struct list_head children; /* list of child buses */
539 struct list_head devices; /* list of devices on this bus */
540 struct pci_dev *self; /* bridge device as seen by parent */
67546762
YW		 541 struct list_head slots; /* list of slots on this bus;
542 protected by pci_slot_mutex */
2fe2abf8
BH		 543 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
544 struct list_head resources; /* address space routed to this bus */
92f02430 545 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 546
547 struct pci_ops *ops; /* configuration access functions */
c2791b80 548 struct msi_controller *msi; /* MSI controller */
1da177e4
LT		 549 void *sysdata; /* hook for sys-specific extension */
550 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
551
552 unsigned char number; /* bus number */
553 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 554 unsigned char max_bus_speed; /* enum pci_bus_speed */
555 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 556#ifdef CONFIG_PCI_DOMAINS_GENERIC
557 int domain_nr;
558#endif
1da177e4
LT		 559
560 char name[48];
561
562 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
f7625980 563 pci_bus_flags_t bus_flags; /* inherited by child buses */
1da177e4 564 struct device *bridge;
fd7d1ced 565 struct device dev;
1da177e4
LT		 566 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
567 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 568 unsigned int is_added:1;
1da177e4
LT		 569};
570
fd7d1ced 571#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 572
79af72d7 573/*
f7625980 574 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 575 * false otherwise
77a0dfcd
BH		 576 *
577 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
578 * This is incorrect because "virtual" buses added for SR-IOV (via
579 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 580 */
581static inline bool pci_is_root_bus(struct pci_bus *pbus)
582{
583 return !(pbus->parent);
584}
585
1c86438c
YW		 586/**
587 * pci_is_bridge - check if the PCI device is a bridge
588 * @dev: PCI device
589 *
590 * Return true if the PCI device is bridge whether it has subordinate
591 * or not.
592 */
593static inline bool pci_is_bridge(struct pci_dev *dev)
594{
595 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
596 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
597}
598
c6bde215
BH		 599static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
600{
601 dev = pci_physfn(dev);
602 if (pci_is_root_bus(dev->bus))
603 return NULL;
604
605 return dev->bus->self;
606}
607
6675a601
MK		 608struct device *pci_get_host_bridge_device(struct pci_dev *dev);
609void pci_put_host_bridge_device(struct device *dev);
610
16cf0ebc
RW		 611#ifdef CONFIG_PCI_MSI
612static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
613{
614 return pci_dev->msi_enabled || pci_dev->msix_enabled;
615}
616#else
617static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
618#endif
619
1da177e4
LT		 620/*
621 * Error values that may be returned by PCI functions.
622 */
623#define PCIBIOS_SUCCESSFUL 0x00
624#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
625#define PCIBIOS_BAD_VENDOR_ID 0x83
626#define PCIBIOS_DEVICE_NOT_FOUND 0x86
627#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
628#define PCIBIOS_SET_FAILED 0x88
629#define PCIBIOS_BUFFER_TOO_SMALL 0x89
630
a6961651 631/*
f7625980 632 * Translate above to generic errno for passing back through non-PCI code.
a6961651
AW		 633 */
634static inline int pcibios_err_to_errno(int err)
635{
636 if (err <= PCIBIOS_SUCCESSFUL)
637 return err; /* Assume already errno */
638
639 switch (err) {
640 case PCIBIOS_FUNC_NOT_SUPPORTED:
641 return -ENOENT;
642 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 643 return -ENOTTY;
a6961651
AW		 644 case PCIBIOS_DEVICE_NOT_FOUND:
645 return -ENODEV;
646 case PCIBIOS_BAD_REGISTER_NUMBER:
647 return -EFAULT;
648 case PCIBIOS_SET_FAILED:
649 return -EIO;
650 case PCIBIOS_BUFFER_TOO_SMALL:
651 return -ENOSPC;
652 }
653
d97ffe23 654 return -ERANGE;
a6961651
AW		 655}
656
1da177e4
LT		 657/* Low-level architecture-dependent routines */
658
659struct pci_ops {
057bd2e0
TR		 660 int (*add_bus)(struct pci_bus *bus);
661 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 662 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 663 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
664 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
665};
666
b6ce068a
MW		 667/*
668 * ACPI needs to be able to access PCI config space before we've done a
669 * PCI bus scan and created pci_bus structures.
670 */
f39d5b72
BH		 671int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
672 int reg, int len, u32 *val);
673int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
674 int reg, int len, u32 val);
1da177e4 675
3a9ad0b4
YL		 676#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
677typedef u64 pci_bus_addr_t;
678#else
679typedef u32 pci_bus_addr_t;
680#endif
681
1da177e4 682struct pci_bus_region {
3a9ad0b4
YL		 683 pci_bus_addr_t start;
684 pci_bus_addr_t end;
1da177e4
LT		 685};
686
687struct pci_dynids {
688 spinlock_t lock; /* protects list, index */
689 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 690};
691
f7625980
BH		 692
693/*
694 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
695 * a set of callbacks in struct pci_error_handlers, that device driver
696 * will be notified of PCI bus errors, and will be driven to recovery
697 * when an error occurs.
392a1ce7 698 */
699
700typedef unsigned int __bitwise pci_ers_result_t;
701
702enum pci_ers_result {
703 /* no result/none/not supported in device driver */
704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
705
706 /* Device driver can recover without slot reset */
707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
708
709 /* Device driver wants slot to be reset. */
710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
711
712 /* Device has completely failed, is unrecoverable */
713 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
714
715 /* Device driver is fully recovered and operational */
716 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 717
718 /* No AER capabilities registered for the driver */
719 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 720};
721
722/* PCI bus error event callbacks */
05cca6e5 723struct pci_error_handlers {
392a1ce7 724 /* PCI bus error detected on this device */
725 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 726 enum pci_channel_state error);
392a1ce7 727
728 /* MMIO has been re-enabled, but not DMA */
729 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
730
392a1ce7 731 /* PCI slot has been reset */
732 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
733
3ebe7f9f 734 /* PCI function reset prepare or completed */
775755ed
CH		 735 void (*reset_prepare)(struct pci_dev *dev);
736 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 737
392a1ce7 738 /* Device driver may resume normal operations */
739 void (*resume)(struct pci_dev *dev);
740};
741
392a1ce7 742
1da177e4
LT		 743struct module;
744struct pci_driver {
745 struct list_head node;
42b21932 746 const char *name;
1da177e4
LT		 747 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
748 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
749 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
750 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 751 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
752 int (*resume_early) (struct pci_dev *dev);
1da177e4 753 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 754 void (*shutdown) (struct pci_dev *dev);
1789382a 755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 756 const struct pci_error_handlers *err_handler;
92d50fc1 757 const struct attribute_group **groups;
1da177e4
LT		 758 struct device_driver driver;
759 struct pci_dynids dynids;
760};
761
05cca6e5 762#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 763
764/**
765 * PCI_DEVICE - macro used to describe a specific pci device
766 * @vend: the 16 bit PCI Vendor ID
767 * @dev: the 16 bit PCI Device ID
768 *
769 * This macro is used to create a struct pci_device_id that matches a
770 * specific device. The subvendor and subdevice fields will be set to
771 * PCI_ANY_ID.
772 */
773#define PCI_DEVICE(vend,dev) \
774 .vendor = (vend), .device = (dev), \
775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
776
3d567e0e
NNS		 777/**
778 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
779 * @vend: the 16 bit PCI Vendor ID
780 * @dev: the 16 bit PCI Device ID
781 * @subvend: the 16 bit PCI Subvendor ID
782 * @subdev: the 16 bit PCI Subdevice ID
783 *
784 * This macro is used to create a struct pci_device_id that matches a
785 * specific device with subsystem information.
786 */
787#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
788 .vendor = (vend), .device = (dev), \
789 .subvendor = (subvend), .subdevice = (subdev)
790
1da177e4
LT		 791/**
792 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
793 * @dev_class: the class, subclass, prog-if triple for this device
794 * @dev_class_mask: the class mask for this device
795 *
796 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 797 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 798 * fields will be set to PCI_ANY_ID.
799 */
800#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
801 .class = (dev_class), .class_mask = (dev_class_mask), \
802 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
804
1597cacb
AC		 805/**
806 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c1309040
MR		 807 * @vend: the vendor name
808 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 809 *
810 * This macro is used to create a struct pci_device_id that matches a
811 * specific PCI device. The subvendor, and subdevice fields will be set
812 * to PCI_ANY_ID. The macro allows the next field to follow as the device
813 * private data.
814 */
815
c1309040
MR		 816#define PCI_VDEVICE(vend, dev) \
817 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
818 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 819
5bbe029f
BH		 820enum {
821 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
822 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
823 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
824 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
825 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
826 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
827 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
828};
829
1da177e4
LT		 830/* these external functions are only available when PCI support is enabled */
831#ifdef CONFIG_PCI
832
5bbe029f
BH		 833extern unsigned int pci_flags;
834
835static inline void pci_set_flags(int flags) { pci_flags = flags; }
836static inline void pci_add_flags(int flags) { pci_flags |= flags; }
837static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
838static inline int pci_has_flag(int flag) { return pci_flags & flag; }
839
a58674ff 840void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 841
842enum pcie_bus_config_types {
27d868b5
KB		 843 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
844 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
845 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
846 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
847 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
b03e7495
JM		 848};
849
850extern enum pcie_bus_config_types pcie_bus_config;
851
1da177e4
LT		 852extern struct bus_type pci_bus_type;
853
f7625980
BH		 854/* Do NOT directly access these two variables, unless you are arch-specific PCI
855 * code, or PCI core code. */
1da177e4 856extern struct list_head pci_root_buses; /* list of all known PCI buses */
f7625980 857/* Some device drivers need know if PCI is initiated */
f39d5b72 858int no_pci_devices(void);
1da177e4 859
3c449ed0 860void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 861void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 862void pcibios_add_bus(struct pci_bus *bus);
863void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 864void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 865int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 866/* Architecture-specific versions may override this (weak) */
05cca6e5 867char *pcibios_setup(char *str);
1da177e4
LT		 868
869/* Used only when drivers/pci/setup.c is used */
3b7a17fc 870resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 871 resource_size_t,
e31dd6e4 872 resource_size_t);
1da177e4 873
2d1c8618
BH		 874/* Weak but can be overriden by arch */
875void pci_fixup_cardbus(struct pci_bus *);
876
1da177e4
LT		 877/* Generic PCI functions used internally */
878
fc279850 879void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 880 struct resource *res);
fc279850 881void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 882 struct pci_bus_region *region);
d1fd4fb6 883void pcibios_scan_specific_bus(int busn);
f39d5b72 884struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 885void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 886struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 887struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
888 struct pci_ops *ops, void *sysdata,
889 struct list_head *resources);
98a35831
YL		 890int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
891int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
892void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 893struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 894 struct pci_ops *ops, void *sysdata,
895 struct list_head *resources);
1228c4b6 896int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 897struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
898 int busnr);
3749c51a 899void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 900struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 901 const char *name,
902 struct hotplug_slot *hotplug);
f46753c5 903void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 904#ifdef CONFIG_SYSFS
905void pci_dev_assign_slot(struct pci_dev *dev);
906#else
907static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
908#endif
1da177e4 909int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 910struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 911void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 912unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 913void pci_bus_add_device(struct pci_dev *dev);
1da177e4 914void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 915struct resource *pci_find_parent_resource(const struct pci_dev *dev,
916 struct resource *res);
c56d4450 917struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 918u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 919int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 920u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 921struct pci_dev *pci_dev_get(struct pci_dev *dev);
922void pci_dev_put(struct pci_dev *dev);
923void pci_remove_bus(struct pci_bus *b);
924void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 925void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 926void pci_stop_root_bus(struct pci_bus *bus);
927void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 928void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 929void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 930void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 931#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
932#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 933
934/* Generic PCI functions exported to card drivers */
935
388c8c16
JB		 936enum pci_lost_interrupt_reason {
937 PCI_LOST_IRQ_NO_INFORMATION = 0,
938 PCI_LOST_IRQ_DISABLE_MSI,
939 PCI_LOST_IRQ_DISABLE_MSIX,
940 PCI_LOST_IRQ_DISABLE_ACPI,
941};
942enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 943int pci_find_capability(struct pci_dev *dev, int cap);
944int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
945int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 946int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 947int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
948int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 949struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 950
d42552c3
AM		 951struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
952 struct pci_dev *from);
05cca6e5 953struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 954 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 955 struct pci_dev *from);
05cca6e5 956struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 957struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
958 unsigned int devfn);
959static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
960 unsigned int devfn)
961{
962 return pci_get_domain_bus_and_slot(0, bus, devfn);
963}
05cca6e5 964struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 965int pci_dev_present(const struct pci_device_id *ids);
966
05cca6e5
GKH		 967int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
968 int where, u8 *val);
969int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
970 int where, u16 *val);
971int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
972 int where, u32 *val);
973int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
974 int where, u8 val);
975int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
976 int where, u16 val);
977int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
978 int where, u32 val);
1f94a94f
RH		 979
980int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
981 int where, int size, u32 *val);
982int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
983 int where, int size, u32 val);
984int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
985 int where, int size, u32 *val);
986int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
987 int where, int size, u32 val);
988
a72b46c3 989struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 990
d3881e50
KB		 991int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
992int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
993int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
994int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
995int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
996int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 997
8c0d3a02
JL		 998int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
999int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1000int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1001int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1002int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1003 u16 clear, u16 set);
1004int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1005 u32 clear, u32 set);
1006
1007static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1008 u16 set)
1009{
1010 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1011}
1012
1013static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1014 u32 set)
1015{
1016 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1017}
1018
1019static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1020 u16 clear)
1021{
1022 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1023}
1024
1025static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1026 u32 clear)
1027{
1028 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1029}
1030
c63587d7
AW		 1031/* user-space driven config access */
1032int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1033int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1034int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1035int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1036int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1037int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1038
4a7fb636 1039int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1040int __must_check pci_enable_device_io(struct pci_dev *dev);
1041int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1042int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1043int __must_check pcim_enable_device(struct pci_dev *pdev);
1044void pcim_pin_device(struct pci_dev *pdev);
1045
99b3c58f
PG		 1046static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1047{
1048 /*
1049 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1050 * writable and no quirk has marked the feature broken.
1051 */
1052 return !pdev->broken_intx_masking;
1053}
1054
296ccb08
YS		 1055static inline int pci_is_enabled(struct pci_dev *pdev)
1056{
1057 return (atomic_read(&pdev->enable_cnt) > 0);
1058}
1059
9ac7849e
TH		 1060static inline int pci_is_managed(struct pci_dev *pdev)
1061{
1062 return pdev->is_managed;
1063}
1064
1da177e4 1065void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1066
1067extern unsigned int pcibios_max_latency;
1da177e4 1068void pci_set_master(struct pci_dev *dev);
6a479079 1069void pci_clear_master(struct pci_dev *dev);
96c55900 1070
f7bdd12d 1071int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1072int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1073#define HAVE_PCI_SET_MWI
4a7fb636 1074int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 1075int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1076void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1077void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1078bool pci_check_and_mask_intx(struct pci_dev *dev);
1079bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1080int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1081int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1082int pcix_get_max_mmrbc(struct pci_dev *dev);
1083int pcix_get_mmrbc(struct pci_dev *dev);
1084int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1085int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1086int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1087int pcie_get_mps(struct pci_dev *dev);
1088int pcie_set_mps(struct pci_dev *dev, int mps);
81377c8d
JK		 1089int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1090 enum pcie_link_width *width);
a60a2b73 1091void pcie_flr(struct pci_dev *dev);
8c1c699f 1092int __pci_reset_function(struct pci_dev *dev);
a96d627a 1093int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1094int pci_reset_function(struct pci_dev *dev);
a477b9cd 1095int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1096int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1097int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1098int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1099int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1100int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1101int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1102int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1103void pci_reset_secondary_bus(struct pci_dev *dev);
1104void pcibios_reset_secondary_bus(struct pci_dev *dev);
64e8674f 1105void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1106void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1107int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1108int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 1109int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1110bool pci_device_is_present(struct pci_dev *pdev);
08249651 1111void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1112
704e8953
CH		 1113int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1114 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1115 const char *fmt, ...);
1116void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1117
1da177e4 1118/* ROM control related routines */
e416de5e
AC		 1119int pci_enable_rom(struct pci_dev *pdev);
1120void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1121void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1122void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1123size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1124void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1125
1126/* Power management related routines */
1127int pci_save_state(struct pci_dev *dev);
1d3c16a8 1128void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1129struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1130int pci_load_saved_state(struct pci_dev *dev,
1131 struct pci_saved_state *state);
ffbdd3f7
AW		 1132int pci_load_and_free_saved_state(struct pci_dev *dev,
1133 struct pci_saved_state **state);
fd0f7f73
AW		 1134struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1135struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1136 u16 cap);
1137int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1138int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1139 u16 cap, unsigned int size);
0e5dd46b 1140int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1141int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1142pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1143bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1144void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1145int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1146int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1147int pci_prepare_to_sleep(struct pci_dev *dev);
1148int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1149bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1150bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1151void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1152void pci_d3cold_enable(struct pci_dev *dev);
1153void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1154bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1da177e4 1155
425c1b22
AW		 1156/* PCI Virtual Channel */
1157int pci_save_vc_state(struct pci_dev *dev);
1158void pci_restore_vc_state(struct pci_dev *dev);
1159void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1160
bb209c82
BH		 1161/* For use by arch with custom probe code */
1162void set_pcie_port_type(struct pci_dev *pdev);
1163void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1164
ce5ccdef 1165/* Functions for PCI Hotplug drivers to use */
05cca6e5 1166int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1167unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1168unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1169void pci_lock_rescan_remove(void);
1170void pci_unlock_rescan_remove(void);
ce5ccdef 1171
287d19ce
SH		 1172/* Vital product data routines */
1173ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1174ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1175int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1176
1da177e4 1177/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1178resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1179void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1180void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1181void pci_bus_size_bridges(struct pci_bus *bus);
1182int pci_claim_resource(struct pci_dev *, int);
8505e729 1183int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1184void pci_assign_unassigned_resources(void);
6841ec68 1185void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1186void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1187void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1da177e4 1188void pdev_enable_device(struct pci_dev *);
842de40d 1189int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1190void pci_assign_irq(struct pci_dev *dev);
afd29f90 1191struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1192#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1193int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1194int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1195void pci_release_regions(struct pci_dev *);
4a7fb636 1196int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1197int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1198void pci_release_region(struct pci_dev *, int);
c87deff7 1199int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1200int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1201void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1202
1203/* drivers/pci/bus.c */
fe830ef6
JL		 1204struct pci_bus *pci_bus_get(struct pci_bus *bus);
1205void pci_bus_put(struct pci_bus *bus);
45ca9e97 1206void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1207void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1208 resource_size_t offset);
45ca9e97 1209void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1210void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1211 unsigned int flags);
2fe2abf8
BH		 1212struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1213void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1214int devm_request_pci_bus_resources(struct device *dev,
1215 struct list_head *resources);
2fe2abf8 1216
89a74ecc 1217#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1218 for (i = 0; \
1219 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1220 i++)
89a74ecc 1221
4a7fb636
AM		 1222int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1223 struct resource *res, resource_size_t size,
1224 resource_size_t align, resource_size_t min,
664c2848 1225 unsigned long type_mask,
3b7a17fc
DB		 1226 resource_size_t (*alignf)(void *,
1227 const struct resource *,
b26b2d49
DB		 1228 resource_size_t,
1229 resource_size_t),
4a7fb636 1230 void *alignf_data);
1da177e4 1231
8b921acf 1232
c5076cfe
TN		 1233int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1234unsigned long pci_address_to_pio(phys_addr_t addr);
1235phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1236int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
4d3f1384 1237void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1238void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1239 resource_size_t offset,
1240 resource_size_t size);
1241void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1242 struct resource *res);
8b921acf 1243
3a9ad0b4 1244static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1245{
1246 struct pci_bus_region region;
1247
1248 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1249 return region.start;
1250}
1251
863b18f4 1252/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1253int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1254 const char *mod_name);
bba81165
AM		 1255
1256/*
1257 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1258 */
1259#define pci_register_driver(driver) \
1260 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1261
05cca6e5 1262void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1263
1264/**
1265 * module_pci_driver() - Helper macro for registering a PCI driver
1266 * @__pci_driver: pci_driver struct
1267 *
1268 * Helper macro for PCI drivers which do not do anything special in module
1269 * init/exit. This eliminates a lot of boilerplate. Each module may only
1270 * use this macro once, and calling it replaces module_init() and module_exit()
1271 */
1272#define module_pci_driver(__pci_driver) \
1273 module_driver(__pci_driver, pci_register_driver, \
1274 pci_unregister_driver)
1275
b4eb6cdb
PG		 1276/**
1277 * builtin_pci_driver() - Helper macro for registering a PCI driver
1278 * @__pci_driver: pci_driver struct
1279 *
1280 * Helper macro for PCI drivers which do not do anything special in their
1281 * init code. This eliminates a lot of boilerplate. Each driver may only
1282 * use this macro once, and calling it replaces device_initcall(...)
1283 */
1284#define builtin_pci_driver(__pci_driver) \
1285 builtin_driver(__pci_driver, pci_register_driver)
1286
05cca6e5 1287struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1288int pci_add_dynid(struct pci_driver *drv,
1289 unsigned int vendor, unsigned int device,
1290 unsigned int subvendor, unsigned int subdevice,
1291 unsigned int class, unsigned int class_mask,
1292 unsigned long driver_data);
05cca6e5
GKH		 1293const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1294 struct pci_dev *dev);
1295int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1296 int pass);
1da177e4 1297
70298c6e 1298void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1299 void *userdata);
ac7dc65a 1300int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1301unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1302void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1303resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1304 unsigned long type);
978d2d68 1305resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
cecf4864 1306
3448a19d
DA		 1307#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1308#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1309
deb2d2ec 1310int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1311 unsigned int command_bits, u32 flags);
fe537670 1312
4fe0d154
CH		 1313#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1314#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1315#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1316#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1317#define PCI_IRQ_ALL_TYPES \
1318 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1319
1da177e4
LT		 1320/* kmem_cache style wrapper around pci_alloc_consistent() */
1321
f41b1771 1322#include <linux/pci-dma.h>
1da177e4
LT		 1323#include <linux/dmapool.h>
1324
1325#define pci_pool dma_pool
1326#define pci_pool_create(name, pdev, size, align, allocation) \
1327 dma_pool_create(name, &pdev->dev, size, align, allocation)
1328#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1329#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1330#define pci_pool_zalloc(pool, flags, handle) \
1331 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1332#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1333
1da177e4 1334struct msix_entry {
16dbef4a 1335 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1336 u16 entry; /* driver uses to specify entry, OS writes */
1337};
1338
4c859804
BH		 1339#ifdef CONFIG_PCI_MSI
1340int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1341void pci_disable_msi(struct pci_dev *dev);
4c859804 1342int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1343void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1344void pci_restore_msi_state(struct pci_dev *dev);
1345int pci_msi_enabled(void);
4fe03955 1346int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1347int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1348 int minvec, int maxvec);
f7fc32cb
AG		 1349static inline int pci_enable_msix_exact(struct pci_dev *dev,
1350 struct msix_entry *entries, int nvec)
1351{
1352 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1353 if (rc < 0)
1354 return rc;
1355 return 0;
1356}
402723ad
CH		 1357int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1358 unsigned int max_vecs, unsigned int flags,
1359 const struct irq_affinity *affd);
1360
aff17164
CH		 1361void pci_free_irq_vectors(struct pci_dev *dev);
1362int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1363const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1364int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1365
4c859804 1366#else
2ee546c4 1367static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1368static inline void pci_disable_msi(struct pci_dev *dev) { }
1369static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1370static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1371static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1372static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1373static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1374{ return -ENOSYS; }
302a2523
AG		 1375static inline int pci_enable_msix_range(struct pci_dev *dev,
1376 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1377{ return -ENOSYS; }
f7fc32cb
AG		 1378static inline int pci_enable_msix_exact(struct pci_dev *dev,
1379 struct msix_entry *entries, int nvec)
1380{ return -ENOSYS; }
402723ad
CH		 1381
1382static inline int
1383pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1384 unsigned int max_vecs, unsigned int flags,
1385 const struct irq_affinity *aff_desc)
aff17164 1386{
83b4605b
CH		 1387 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1388 return 1;
1389 return -ENOSPC;
aff17164 1390}
402723ad 1391
aff17164
CH		 1392static inline void pci_free_irq_vectors(struct pci_dev *dev)
1393{
1394}
1395
1396static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1397{
1398 if (WARN_ON_ONCE(nr > 0))
1399 return -EINVAL;
1400 return dev->irq;
1401}
ee8d41e5
TG		 1402static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1403 int vec)
1404{
1405 return cpu_possible_mask;
1406}
27ddb689
SL		 1407
1408static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1409{
1410 return first_online_node;
1411}
1da177e4
LT		 1412#endif
1413
402723ad
CH		 1414static inline int
1415pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1416 unsigned int max_vecs, unsigned int flags)
1417{
1418 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1419 NULL);
1420}
1421
0d58e6c1
PB		 1422/**
1423 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1424 * @d: the INTx IRQ domain
1425 * @node: the DT node for the device whose interrupt we're translating
1426 * @intspec: the interrupt specifier data from the DT
1427 * @intsize: the number of entries in @intspec
1428 * @out_hwirq: pointer at which to write the hwirq number
1429 * @out_type: pointer at which to write the interrupt type
1430 *
1431 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1432 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1433 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1434 * INTx value to obtain the hwirq number.
1435 *
1436 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1437 */
1438static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1439 struct device_node *node,
1440 const u32 *intspec,
1441 unsigned int intsize,
1442 unsigned long *out_hwirq,
1443 unsigned int *out_type)
1444{
1445 const u32 intx = intspec[0];
1446
1447 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1448 return -EINVAL;
1449
1450 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1451 return 0;
1452}
1453
ab0724ff 1454#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1455extern bool pcie_ports_disabled;
1456extern bool pcie_ports_auto;
ab0724ff
MT		 1457#else
1458#define pcie_ports_disabled true
1459#define pcie_ports_auto false
1460#endif
415e12b2 1461
4c859804 1462#ifdef CONFIG_PCIEASPM
f39d5b72 1463bool pcie_aspm_support_enabled(void);
4c859804
BH		 1464#else
1465static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1466#endif
1467
415e12b2
RW		 1468#ifdef CONFIG_PCIEAER
1469void pci_no_aer(void);
1470bool pci_aer_available(void);
66b80809 1471int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1472#else
1473static inline void pci_no_aer(void) { }
1474static inline bool pci_aer_available(void) { return false; }
66b80809 1475static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1476#endif
1477
4c859804 1478#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1479void pcie_set_ecrc_checking(struct pci_dev *dev);
1480void pcie_ecrc_get_policy(char *str);
4c859804 1481#else
2ee546c4
BH		 1482static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1483static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1484#endif
1485
8b955b0d 1486#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1487/* The functions a driver should call */
1488int ht_create_irq(struct pci_dev *dev, int idx);
1489void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1490#endif /* CONFIG_HT_IRQ */
1491
edc90fee
BH		 1492#ifdef CONFIG_PCI_ATS
1493/* Address Translation Service */
1494void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1495int pci_enable_ats(struct pci_dev *dev, int ps);
1496void pci_disable_ats(struct pci_dev *dev);
1497int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1498#else
ff9bee89
BH		 1499static inline void pci_ats_init(struct pci_dev *d) { }
1500static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1501static inline void pci_disable_ats(struct pci_dev *d) { }
1502static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1503#endif
1504
eec097d4
BH		 1505#ifdef CONFIG_PCIE_PTM
1506int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1507#else
1508static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1509{ return -EINVAL; }
1510#endif
1511
f39d5b72
BH		 1512void pci_cfg_access_lock(struct pci_dev *dev);
1513bool pci_cfg_access_trylock(struct pci_dev *dev);
1514void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1515
4352dfd5
GKH		 1516/*
1517 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1518 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1519 * configuration space.
1520 */
32a2eea7
JG		 1521#ifdef CONFIG_PCI_DOMAINS
1522extern int pci_domains_supported;
41e5c0f8 1523int pci_get_new_domain_nr(void);
32a2eea7
JG		 1524#else
1525enum { pci_domains_supported = 0 };
2ee546c4
BH		 1526static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1527static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
41e5c0f8 1528static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
32a2eea7 1529#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1530
670ba0c8
CM		 1531/*
1532 * Generic implementation for PCI domain support. If your
1533 * architecture does not need custom management of PCI
1534 * domains then this implementation will be used
1535 */
1536#ifdef CONFIG_PCI_DOMAINS_GENERIC
1537static inline int pci_domain_nr(struct pci_bus *bus)
1538{
1539 return bus->domain_nr;
1540}
2ab51dde
TN		 1541#ifdef CONFIG_ACPI
1542int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1543#else
2ab51dde
TN		 1544static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1545{ return 0; }
1546#endif
9c7cb891 1547int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1548#endif
1549
95a8b6ef
MT		 1550/* some architectures require additional setup to direct VGA traffic */
1551typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1552 unsigned int command_bits, u32 flags);
f39d5b72 1553void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1554
be9d2e89
JT		 1555static inline int
1556pci_request_io_regions(struct pci_dev *pdev, const char *name)
1557{
1558 return pci_request_selected_regions(pdev,
1559 pci_select_bars(pdev, IORESOURCE_IO), name);
1560}
1561
1562static inline void
1563pci_release_io_regions(struct pci_dev *pdev)
1564{
1565 return pci_release_selected_regions(pdev,
1566 pci_select_bars(pdev, IORESOURCE_IO));
1567}
1568
1569static inline int
1570pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1571{
1572 return pci_request_selected_regions(pdev,
1573 pci_select_bars(pdev, IORESOURCE_MEM), name);
1574}
1575
1576static inline void
1577pci_release_mem_regions(struct pci_dev *pdev)
1578{
1579 return pci_release_selected_regions(pdev,
1580 pci_select_bars(pdev, IORESOURCE_MEM));
1581}
1582
4352dfd5 1583#else /* CONFIG_PCI is not enabled */
1da177e4 1584
5bbe029f
BH		 1585static inline void pci_set_flags(int flags) { }
1586static inline void pci_add_flags(int flags) { }
1587static inline void pci_clear_flags(int flags) { }
1588static inline int pci_has_flag(int flag) { return 0; }
1589
1da177e4
LT		 1590/*
1591 * If the system does not have PCI, clearly these return errors. Define
1592 * these as simple inline functions to avoid hair in drivers.
1593 */
1594
05cca6e5
GKH		 1595#define _PCI_NOP(o, s, t) \
1596 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1597 int where, t val) \
1da177e4 1598 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1599
1600#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1601 _PCI_NOP(o, word, u16 x) \
1602 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1603_PCI_NOP_ALL(read, *)
1604_PCI_NOP_ALL(write,)
1605
d42552c3 1606static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1607 unsigned int device,
1608 struct pci_dev *from)
2ee546c4 1609{ return NULL; }
d42552c3 1610
05cca6e5
GKH		 1611static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1612 unsigned int device,
1613 unsigned int ss_vendor,
1614 unsigned int ss_device,
b08508c4 1615 struct pci_dev *from)
2ee546c4 1616{ return NULL; }
1da177e4 1617
05cca6e5
GKH		 1618static inline struct pci_dev *pci_get_class(unsigned int class,
1619 struct pci_dev *from)
2ee546c4 1620{ return NULL; }
1da177e4
LT		 1621
1622#define pci_dev_present(ids) (0)
ed4aaadb 1623#define no_pci_devices() (1)
1da177e4
LT		 1624#define pci_dev_put(dev) do { } while (0)
1625
2ee546c4
BH		 1626static inline void pci_set_master(struct pci_dev *dev) { }
1627static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1628static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1629static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1630{ return -EBUSY; }
05cca6e5
GKH		 1631static inline int __pci_register_driver(struct pci_driver *drv,
1632 struct module *owner)
2ee546c4 1633{ return 0; }
05cca6e5 1634static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1635{ return 0; }
1636static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1637static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1638{ return 0; }
05cca6e5
GKH		 1639static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1640 int cap)
2ee546c4 1641{ return 0; }
05cca6e5 1642static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1643{ return 0; }
05cca6e5 1644
1da177e4 1645/* Power management related routines */
2ee546c4
BH		 1646static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1647static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1648static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1649{ return 0; }
3449248c 1650static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1651{ return 0; }
05cca6e5
GKH		 1652static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1653 pm_message_t state)
2ee546c4 1654{ return PCI_D0; }
05cca6e5
GKH		 1655static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1656 int enable)
2ee546c4 1657{ return 0; }
48a92a81 1658
afd29f90
MW		 1659static inline struct resource *pci_find_resource(struct pci_dev *dev,
1660 struct resource *res)
1661{ return NULL; }
05cca6e5 1662static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1663{ return -EIO; }
1664static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1665
c5076cfe
TN		 1666static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1667
2ee546c4 1668static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1669static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1670{ return 0; }
2ee546c4 1671static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1672
d80d0217
RD		 1673static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1674{ return NULL; }
d80d0217
RD		 1675static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1676 unsigned int devfn)
1677{ return NULL; }
d80d0217
RD		 1678static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1679 unsigned int devfn)
1680{ return NULL; }
1681
2ee546c4
BH		 1682static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1683static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
41e5c0f8 1684static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
12ea6cad 1685
fb8a0d9d
WM		 1686#define dev_is_pci(d) (false)
1687#define dev_is_pf(d) (false)
fe594932
GU		 1688static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1689{ return false; }
4352dfd5 1690#endif /* CONFIG_PCI */
1da177e4 1691
4352dfd5
GKH		 1692/* Include architecture-dependent settings and functions */
1693
1694#include <asm/pci.h>
1da177e4 1695
f7195824
DW		 1696/* These two functions provide almost identical functionality. Depennding
1697 * on the architecture, one will be implemented as a wrapper around the
1698 * other (in drivers/pci/mmap.c).
1699 *
1700 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1701 * is expected to be an offset within that region.
1702 *
1703 * pci_mmap_page_range() is the legacy architecture-specific interface,
1704 * which accepts a "user visible" resource address converted by
1705 * pci_resource_to_user(), as used in the legacy mmap() interface in
1706 * /proc/bus/pci/.
1707 */
1708int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1709 struct vm_area_struct *vma,
1710 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1711int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1712 struct vm_area_struct *vma,
11df1954
DW		 1713 enum pci_mmap_state mmap_state, int write_combine);
1714
ae749c7a
DW		 1715#ifndef arch_can_pci_mmap_wc
1716#define arch_can_pci_mmap_wc() 0
1717#endif
2bea36fd 1718
e854d8b2
DW		 1719#ifndef arch_can_pci_mmap_io
1720#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1721#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1722#else
1723int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1724#endif
ae749c7a 1725
92016ba5
JO		 1726#ifndef pci_root_bus_fwnode
1727#define pci_root_bus_fwnode(bus) NULL
1728#endif
1729
1da177e4
LT		 1730/* these helpers provide future and backwards compatibility
1731 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1732#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1733#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1734#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1735#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1736 ((pci_resource_start((dev), (bar)) == 0 && \
1737 pci_resource_end((dev), (bar)) == \
1738 pci_resource_start((dev), (bar))) ? 0 : \
1739 \
1740 (pci_resource_end((dev), (bar)) - \
1741 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1742
1743/* Similar to the helpers above, these manipulate per-pci_dev
1744 * driver-specific data. They are really just a wrapper around
1745 * the generic device structure functions of these calls.
1746 */
05cca6e5 1747static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1748{
1749 return dev_get_drvdata(&pdev->dev);
1750}
1751
05cca6e5 1752static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1753{
1754 dev_set_drvdata(&pdev->dev, data);
1755}
1756
1757/* If you want to know what to call your pci_dev, ask this function.
1758 * Again, it's a wrapper around the generic device.
1759 */
2fc90f61 1760static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1761{
c6c4f070 1762 return dev_name(&pdev->dev);
1da177e4
LT		 1763}
1764
2311b1f2
ME		 1765
1766/* Some archs don't want to expose struct resource to userland as-is
1767 * in sysfs and /proc
1768 */
8221a013
BH		 1769#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1770void pci_resource_to_user(const struct pci_dev *dev, int bar,
1771 const struct resource *rsrc,
1772 resource_size_t *start, resource_size_t *end);
1773#else
2311b1f2 1774static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1775 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1776 resource_size_t *end)
2311b1f2
ME		 1777{
1778 *start = rsrc->start;
1779 *end = rsrc->end;
1780}
1781#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1782
1783
1da177e4
LT		 1784/*
1785 * The world is not perfect and supplies us with broken PCI devices.
1786 * For at least a part of these bugs we need a work-around, so both
1787 * generic (drivers/pci/quirks.c) and per-architecture code can define
1788 * fixup hooks to be called for particular buggy devices.
1789 */
1790
1791struct pci_fixup {
f4ca5c6a
YL		 1792 u16 vendor; /* You can use PCI_ANY_ID here of course */
1793 u16 device; /* You can use PCI_ANY_ID here of course */
1794 u32 class; /* You can use PCI_ANY_ID here too */
1795 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1796 void (*hook)(struct pci_dev *dev);
1797};
1798
1799enum pci_fixup_pass {
1800 pci_fixup_early, /* Before probing BARs */
1801 pci_fixup_header, /* After reading configuration header */
1802 pci_fixup_final, /* Final phase of device fixups */
1803 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1804 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1805 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1806 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1807 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1808};
1809
1810/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1811#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1812 class_shift, hook) \
ecf61c78 1813 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1814 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1815 = { vendor, device, class, class_shift, hook };
1816
1817#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1818 class_shift, hook) \
1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1820 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1821#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1822 class_shift, hook) \
1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1824 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1825#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1826 class_shift, hook) \
1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1828 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1829#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1830 class_shift, hook) \
1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1832 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1833#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1834 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1836 resume##hook, vendor, device, class, \
f4ca5c6a
YL		 1837 class_shift, hook)
1838#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1839 class_shift, hook) \
1840 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1841 resume_early##hook, vendor, device, \
f4ca5c6a
YL		 1842 class, class_shift, hook)
1843#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1844 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1846 suspend##hook, vendor, device, class, \
f4ca5c6a 1847 class_shift, hook)
7d2a01b8
AN		 1848#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1849 class_shift, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1851 suspend_late##hook, vendor, device, \
1852 class, class_shift, hook)
f4ca5c6a 1853
1da177e4
LT		 1854#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1856 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1857#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1859 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1860#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1861 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1862 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1863#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1864 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1865 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1866#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1868 resume##hook, vendor, device, \
f4ca5c6a 1869 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1870#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1872 resume_early##hook, vendor, device, \
f4ca5c6a 1873 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1874#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1876 suspend##hook, vendor, device, \
f4ca5c6a 1877 PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1878#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1880 suspend_late##hook, vendor, device, \
1881 PCI_ANY_ID, 0, hook)
1da177e4 1882
93177a74 1883#ifdef CONFIG_PCI_QUIRKS
1da177e4 1884void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1885int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1886int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1887#else
1888static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1889 struct pci_dev *dev) { }
ad805758
AW		 1890static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1891 u16 acs_flags)
1892{
1893 return -ENOTTY;
1894}
c1d61c9b
AW		 1895static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1896{
1897 return -ENOTTY;
1898}
93177a74 1899#endif
1da177e4 1900
05cca6e5 1901void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1902void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1903void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1904int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1905int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1906 const char *name);
fb7ebfe4 1907void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1908
1da177e4 1909extern int pci_pci_problems;
236561e5 1910#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1911#define PCIPCI_TRITON 2
1912#define PCIPCI_NATOMA 4
1913#define PCIPCI_VIAETBF 8
1914#define PCIPCI_VSFX 16
236561e5
AC		 1915#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1916#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1917
4516a618
AN		 1918extern unsigned long pci_cardbus_io_size;
1919extern unsigned long pci_cardbus_mem_size;
15856ad5 1920extern u8 pci_dfl_cache_line_size;
ac1aa47b 1921extern u8 pci_cache_line_size;
4516a618 1922
28760489
EB		 1923extern unsigned long pci_hotplug_io_size;
1924extern unsigned long pci_hotplug_mem_size;
e16b4660 1925extern unsigned long pci_hotplug_bus_size;
28760489 1926
f7625980 1927/* Architecture-specific versions may override these (weak) */
19792a08 1928void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1929void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1930int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1931 enum pcie_reset_state state);
eca0d467 1932int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1933void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1934void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1935int pcibios_alloc_irq(struct pci_dev *dev);
1936void pcibios_free_irq(struct pci_dev *dev);
575e3348 1937
699c1985
SO		 1938#ifdef CONFIG_HIBERNATE_CALLBACKS
1939extern struct dev_pm_ops pcibios_pm_ops;
1940#endif
1941
935c760e 1942#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1943void __init pci_mmcfg_early_init(void);
1944void __init pci_mmcfg_late_init(void);
7752d5cf 1945#else
bb63b421 1946static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1947static inline void pci_mmcfg_late_init(void) { }
1948#endif
1949
642c92da 1950int pci_ext_cfg_avail(void);
0ef5f8f6 1951
1684f5dd 1952void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1953void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1954
dd7cc44d 1955#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1956int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1957int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1958
f39d5b72
BH		 1959int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1960void pci_disable_sriov(struct pci_dev *dev);
c194f7ea
WY		 1961int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1962void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
f39d5b72 1963int pci_num_vf(struct pci_dev *dev);
5a8eb242 1964int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1965int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1966int pci_sriov_get_totalvfs(struct pci_dev *dev);
0e6c9122 1967resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
dd7cc44d 1968#else
b07579c0
WY		 1969static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1970{
1971 return -ENOSYS;
1972}
1973static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1974{
1975 return -ENOSYS;
1976}
dd7cc44d 1977static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1978{ return -ENODEV; }
c194f7ea
WY		 1979static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1980{
1981 return -ENOSYS;
1982}
1983static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1984 int id, int reset) { }
2ee546c4 1985static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1986static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1987static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1988{ return 0; }
bff73156 1989static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1990{ return 0; }
bff73156 1991static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1992{ return 0; }
0e6c9122
WY		 1993static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1994{ return 0; }
dd7cc44d
YZ		 1995#endif
1996
c825bc94 1997#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1998void pci_hp_create_module_link(struct pci_slot *pci_slot);
1999void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2000#endif
2001
d7b7e605
KK		 2002/**
2003 * pci_pcie_cap - get the saved PCIe capability offset
2004 * @dev: PCI device
2005 *
2006 * PCIe capability offset is calculated at PCI device initialization
2007 * time and saved in the data structure. This function returns saved
2008 * PCIe capability offset. Using this instead of pci_find_capability()
2009 * reduces unnecessary search in the PCI configuration space. If you
2010 * need to calculate PCIe capability offset from raw device for some
2011 * reasons, please use pci_find_capability() instead.
2012 */
2013static inline int pci_pcie_cap(struct pci_dev *dev)
2014{
2015 return dev->pcie_cap;
2016}
2017
7eb776c4
KK		 2018/**
2019 * pci_is_pcie - check if the PCI device is PCI Express capable
2020 * @dev: PCI device
2021 *
a895c28a 2022 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2023 */
2024static inline bool pci_is_pcie(struct pci_dev *dev)
2025{
a895c28a 2026 return pci_pcie_cap(dev);
7eb776c4
KK		 2027}
2028
7c9c003c
MS		 2029/**
2030 * pcie_caps_reg - get the PCIe Capabilities Register
2031 * @dev: PCI device
2032 */
2033static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2034{
2035 return dev->pcie_flags_reg;
2036}
2037
786e2288
YW		 2038/**
2039 * pci_pcie_type - get the PCIe device/port type
2040 * @dev: PCI device
2041 */
2042static inline int pci_pcie_type(const struct pci_dev *dev)
2043{
1c531d82 2044 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2045}
2046
e784930b
JT		 2047static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2048{
2049 while (1) {
2050 if (!pci_is_pcie(dev))
2051 break;
2052 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2053 return dev;
2054 if (!dev->bus->self)
2055 break;
2056 dev = dev->bus->self;
2057 }
2058 return NULL;
2059}
2060
5d990b62 2061void pci_request_acs(void);
ad805758
AW		 2062bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2063bool pci_acs_path_enabled(struct pci_dev *start,
2064 struct pci_dev *end, u16 acs_flags);
a2ce7662 2065
7ad506fa 2066#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2067#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2068
2069/* Large Resource Data Type Tag Item Names */
2070#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2071#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2072#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2073
2074#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2075#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2076#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2077
2078/* Small Resource Data Type Tag Item Names */
9eb45d5c 2079#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2080
9eb45d5c 2081#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2082
2083#define PCI_VPD_SRDT_TIN_MASK 0x78
2084#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2085#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2086
2087#define PCI_VPD_LRDT_TAG_SIZE 3
2088#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2089
e1d5bdab
MC		 2090#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2091
4067a854
MC		 2092#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2093#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2094#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2095#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2096
a2ce7662
MC		 2097/**
2098 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2099 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2100 *
2101 * Returns the extracted Large Resource Data Type length.
2102 */
2103static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2104{
2105 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2106}
2107
9eb45d5c
HR		 2108/**
2109 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2110 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2111 *
2112 * Returns the extracted Large Resource Data Type Tag item.
2113 */
2114static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2115{
2116 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2117}
2118
7ad506fa
MC		 2119/**
2120 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2121 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2122 *
2123 * Returns the extracted Small Resource Data Type length.
2124 */
2125static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2126{
2127 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2128}
2129
9eb45d5c
HR		 2130/**
2131 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2132 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2133 *
2134 * Returns the extracted Small Resource Data Type Tag Item.
2135 */
2136static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2137{
2138 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2139}
2140
e1d5bdab
MC		 2141/**
2142 * pci_vpd_info_field_size - Extracts the information field length
2143 * @lrdt: Pointer to the beginning of an information field header
2144 *
2145 * Returns the extracted information field length.
2146 */
2147static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2148{
2149 return info_field[2];
2150}
2151
b55ac1b2
MC		 2152/**
2153 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2154 * @buf: Pointer to buffered vpd data
2155 * @off: The offset into the buffer at which to begin the search
2156 * @len: The length of the vpd buffer
2157 * @rdt: The Resource Data Type to search for
2158 *
2159 * Returns the index where the Resource Data Type was found or
2160 * -ENOENT otherwise.
2161 */
2162int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2163
4067a854
MC		 2164/**
2165 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2166 * @buf: Pointer to buffered vpd data
2167 * @off: The offset into the buffer at which to begin the search
2168 * @len: The length of the buffer area, relative to off, in which to search
2169 * @kw: The keyword to search for
2170 *
2171 * Returns the index where the information field keyword was found or
2172 * -ENOENT otherwise.
2173 */
2174int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2175 unsigned int len, const char *kw);
2176
98d9f30c
BH		 2177/* PCI <-> OF binding helpers */
2178#ifdef CONFIG_OF
2179struct device_node;
b165e2b6 2180struct irq_domain;
f39d5b72
BH		 2181void pci_set_of_node(struct pci_dev *dev);
2182void pci_release_of_node(struct pci_dev *dev);
2183void pci_set_bus_of_node(struct pci_bus *bus);
2184void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2185struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
98d9f30c
BH		 2186
2187/* Arch may override this (weak) */
723ec4d0 2188struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2189
3df425f3
JC		 2190static inline struct device_node *
2191pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 2192{
2193 return pdev ? pdev->dev.of_node : NULL;
2194}
2195
ef3b4f8c
BH		 2196static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2197{
2198 return bus ? bus->dev.of_node : NULL;
2199}
2200
98d9f30c
BH		 2201#else /* CONFIG_OF */
2202static inline void pci_set_of_node(struct pci_dev *dev) { }
2203static inline void pci_release_of_node(struct pci_dev *dev) { }
2204static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2205static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
f0b66a2c
KH		 2206static inline struct device_node *
2207pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
b165e2b6
MZ		 2208static inline struct irq_domain *
2209pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
98d9f30c
BH		 2210#endif /* CONFIG_OF */
2211
471036b2
SS		 2212#ifdef CONFIG_ACPI
2213struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2214
2215void
2216pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2217#else
2218static inline struct irq_domain *
2219pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2220#endif
2221
eb740b5f
GS		 2222#ifdef CONFIG_EEH
2223static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2224{
2225 return pdev->dev.archdata.edev;
2226}
2227#endif
2228
f0af9593 2229void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2230bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2231int pci_for_each_dma_alias(struct pci_dev *pdev,
2232 int (*fn)(struct pci_dev *pdev,
2233 u16 alias, void *data), void *data);
2234
ce052984
EZ		 2235/* helper functions for operation of device flag */
2236static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2237{
2238 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2239}
2240static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2241{
2242 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2243}
2244static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2245{
2246 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2247}
19bdb6e4
AW		 2248
2249/**
2250 * pci_ari_enabled - query ARI forwarding status
2251 * @bus: the PCI bus
2252 *
2253 * Returns true if ARI forwarding is enabled.
2254 */
2255static inline bool pci_ari_enabled(struct pci_bus *bus)
2256{
2257 return bus->self && bus->self->ari_enabled;
2258}
bc4b024a 2259
8531e283
LW		 2260/**
2261 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2262 * @pdev: PCI device to check
2263 *
2264 * Walk upwards from @pdev and check for each encountered bridge if it's part
2265 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2266 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2267 */
2268static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2269{
2270 struct pci_dev *parent = pdev;
2271
2272 if (pdev->is_thunderbolt)
2273 return true;
2274
2275 while ((parent = pci_upstream_bridge(parent)))
2276 if (parent->is_thunderbolt)
2277 return true;
2278
2279 return false;
2280}
2281
bc4b024a
CH		 2282/* provide the legacy pci_dma_* API */
2283#include <linux/pci-dma-compat.h>
2284
1da177e4 2285#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)