Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 | 53 | #include <linux/device.h> |
1388cc96 | 54 | #include <linux/io.h> |
74bb1bcc | 55 | #include <linux/irqreturn.h> |
1da177e4 | 56 | |
7e7a43c3 AB |
57 | /* Include the ID list */ |
58 | #include <linux/pci_ids.h> | |
59 | ||
f46753c5 AC |
60 | /* pci_slot represents a physical slot */ |
61 | struct pci_slot { | |
62 | struct pci_bus *bus; /* The bus this slot is on */ | |
63 | struct list_head list; /* node in list of slots on this bus */ | |
64 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
65 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
66 | struct kobject kobj; | |
67 | }; | |
68 | ||
0ad772ec AC |
69 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
70 | { | |
71 | return kobject_name(&slot->kobj); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
75 | enum pci_mmap_state { | |
76 | pci_mmap_io, | |
77 | pci_mmap_mem | |
78 | }; | |
79 | ||
80 | /* This defines the direction arg to the DMA mapping routines. */ | |
81 | #define PCI_DMA_BIDIRECTIONAL 0 | |
82 | #define PCI_DMA_TODEVICE 1 | |
83 | #define PCI_DMA_FROMDEVICE 2 | |
84 | #define PCI_DMA_NONE 3 | |
85 | ||
fde09c6d YZ |
86 | /* |
87 | * For PCI devices, the region numbers are assigned this way: | |
88 | */ | |
89 | enum { | |
90 | /* #0-5: standard PCI resources */ | |
91 | PCI_STD_RESOURCES, | |
92 | PCI_STD_RESOURCE_END = 5, | |
93 | ||
94 | /* #6: expansion ROM resource */ | |
95 | PCI_ROM_RESOURCE, | |
96 | ||
d1b054da YZ |
97 | /* device specific resources */ |
98 | #ifdef CONFIG_PCI_IOV | |
99 | PCI_IOV_RESOURCES, | |
100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
101 | #endif | |
102 | ||
fde09c6d YZ |
103 | /* resources assigned to buses behind the bridge */ |
104 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
105 | ||
106 | PCI_BRIDGE_RESOURCES, | |
107 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
108 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
109 | ||
110 | /* total resources associated with a PCI device */ | |
111 | PCI_NUM_RESOURCES, | |
112 | ||
113 | /* preserve this for compatibility */ | |
114 | DEVICE_COUNT_RESOURCE | |
115 | }; | |
1da177e4 LT |
116 | |
117 | typedef int __bitwise pci_power_t; | |
118 | ||
4352dfd5 GKH |
119 | #define PCI_D0 ((pci_power_t __force) 0) |
120 | #define PCI_D1 ((pci_power_t __force) 1) | |
121 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
122 | #define PCI_D3hot ((pci_power_t __force) 3) |
123 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 124 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 125 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 126 | |
00240c38 AS |
127 | /* Remember to update this when the list above changes! */ |
128 | extern const char *pci_power_names[]; | |
129 | ||
130 | static inline const char *pci_power_name(pci_power_t state) | |
131 | { | |
132 | return pci_power_names[1 + (int) state]; | |
133 | } | |
134 | ||
aa8c6c93 RW |
135 | #define PCI_PM_D2_DELAY 200 |
136 | #define PCI_PM_D3_WAIT 10 | |
137 | #define PCI_PM_BUS_WAIT 50 | |
138 | ||
392a1ce7 | 139 | /** The pci_channel state describes connectivity between the CPU and |
140 | * the pci device. If some PCI bus between here and the pci device | |
141 | * has crashed or locked up, this info is reflected here. | |
142 | */ | |
143 | typedef unsigned int __bitwise pci_channel_state_t; | |
144 | ||
145 | enum pci_channel_state { | |
146 | /* I/O channel is in normal state */ | |
147 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
148 | ||
149 | /* I/O to channel is blocked */ | |
150 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
151 | ||
152 | /* PCI card is dead */ | |
153 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
154 | }; | |
155 | ||
f7bdd12d BK |
156 | typedef unsigned int __bitwise pcie_reset_state_t; |
157 | ||
158 | enum pcie_reset_state { | |
159 | /* Reset is NOT asserted (Use to deassert reset) */ | |
160 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
161 | ||
162 | /* Use #PERST to reset PCI-E device */ | |
163 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
164 | ||
165 | /* Use PCI-E Hot Reset to reset device */ | |
166 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
167 | }; | |
168 | ||
ba698ad4 DM |
169 | typedef unsigned short __bitwise pci_dev_flags_t; |
170 | enum pci_dev_flags { | |
171 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
172 | * generation too. | |
173 | */ | |
174 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
175 | /* Device configuration is irrevocably lost if disabled into D3 */ |
176 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
ba698ad4 DM |
177 | }; |
178 | ||
e1d3a908 SA |
179 | enum pci_irq_reroute_variant { |
180 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
181 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
182 | }; | |
183 | ||
6e325a62 MT |
184 | typedef unsigned short __bitwise pci_bus_flags_t; |
185 | enum pci_bus_flags { | |
d556ad4b PO |
186 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
187 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
188 | }; |
189 | ||
536c8cb4 MW |
190 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
191 | enum pci_bus_speed { | |
192 | PCI_SPEED_33MHz = 0x00, | |
193 | PCI_SPEED_66MHz = 0x01, | |
194 | PCI_SPEED_66MHz_PCIX = 0x02, | |
195 | PCI_SPEED_100MHz_PCIX = 0x03, | |
196 | PCI_SPEED_133MHz_PCIX = 0x04, | |
197 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
198 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
199 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
200 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
201 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
202 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
203 | AGP_UNKNOWN = 0x0c, |
204 | AGP_1X = 0x0d, | |
205 | AGP_2X = 0x0e, | |
206 | AGP_4X = 0x0f, | |
207 | AGP_8X = 0x10, | |
536c8cb4 MW |
208 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
209 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
210 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
211 | PCIE_SPEED_2_5GT = 0x14, | |
212 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 213 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
214 | PCI_SPEED_UNKNOWN = 0xff, |
215 | }; | |
216 | ||
24a4742f | 217 | struct pci_cap_saved_data { |
41017f0c | 218 | char cap_nr; |
24a4742f | 219 | unsigned int size; |
41017f0c SL |
220 | u32 data[0]; |
221 | }; | |
222 | ||
24a4742f AW |
223 | struct pci_cap_saved_state { |
224 | struct hlist_node next; | |
225 | struct pci_cap_saved_data cap; | |
226 | }; | |
227 | ||
7d715a6c | 228 | struct pcie_link_state; |
ee69439c | 229 | struct pci_vpd; |
d1b054da | 230 | struct pci_sriov; |
302b4215 | 231 | struct pci_ats; |
ee69439c | 232 | |
1da177e4 LT |
233 | /* |
234 | * The pci_dev structure is used to describe PCI devices. | |
235 | */ | |
236 | struct pci_dev { | |
1da177e4 LT |
237 | struct list_head bus_list; /* node in per-bus list */ |
238 | struct pci_bus *bus; /* bus this device is on */ | |
239 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
240 | ||
241 | void *sysdata; /* hook for sys-specific extension */ | |
242 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 243 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
244 | |
245 | unsigned int devfn; /* encoded device & function index */ | |
246 | unsigned short vendor; | |
247 | unsigned short device; | |
248 | unsigned short subsystem_vendor; | |
249 | unsigned short subsystem_device; | |
250 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 251 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 252 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
0efea000 | 253 | u8 pcie_cap; /* PCI-E capability offset */ |
994a65e2 | 254 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 255 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 256 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
257 | |
258 | struct pci_driver *driver; /* which driver has allocated this device */ | |
259 | u64 dma_mask; /* Mask of the bits of bus address this | |
260 | device implements. Normally this is | |
261 | 0xffffffff. You only need to change | |
262 | this if your device has broken DMA | |
263 | or supports 64-bit transfers. */ | |
264 | ||
4d57cdfa FT |
265 | struct device_dma_parameters dma_parms; |
266 | ||
1da177e4 LT |
267 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
268 | this is D0-D3, D0 being fully functional, | |
269 | and D3 being off. */ | |
337001b6 RW |
270 | int pm_cap; /* PM capability offset in the |
271 | configuration space */ | |
272 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
273 | can be generated */ | |
c7f48656 | 274 | unsigned int pme_interrupt:1; |
337001b6 RW |
275 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
276 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
277 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
253d2e54 JP |
278 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
279 | decoding during bar sizing */ | |
e80bb09d | 280 | unsigned int wakeup_prepared:1; |
1ae861e6 | 281 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
1da177e4 | 282 | |
7d715a6c SL |
283 | #ifdef CONFIG_PCIEASPM |
284 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
285 | #endif | |
286 | ||
392a1ce7 | 287 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
288 | struct device dev; /* Generic device interface */ |
289 | ||
1da177e4 LT |
290 | int cfg_size; /* Size of configuration space */ |
291 | ||
292 | /* | |
293 | * Instead of touching interrupt line and base address registers | |
294 | * directly, use the values stored here. They might be different! | |
295 | */ | |
296 | unsigned int irq; | |
297 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
58c84eda | 298 | resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
1da177e4 LT |
299 | |
300 | /* These fields are used by common fixups */ | |
301 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
302 | unsigned int multifunction:1;/* Part of multi-function device */ | |
303 | /* keep track of device state */ | |
8a1bc901 | 304 | unsigned int is_added:1; |
1da177e4 | 305 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 306 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 307 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 308 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 309 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
310 | unsigned int msi_enabled:1; |
311 | unsigned int msix_enabled:1; | |
58c3a727 | 312 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 313 | unsigned int is_managed:1; |
6d3be84a KK |
314 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
315 | Use pci_is_pcie() instead */ | |
260d703a | 316 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 317 | unsigned int state_saved:1; |
d1b054da | 318 | unsigned int is_physfn:1; |
dd7cc44d | 319 | unsigned int is_virtfn:1; |
711d5779 | 320 | unsigned int reset_fn:1; |
28760489 | 321 | unsigned int is_hotplug_bridge:1; |
affb72c3 HY |
322 | unsigned int __aer_firmware_first_valid:1; |
323 | unsigned int __aer_firmware_first:1; | |
ba698ad4 | 324 | pci_dev_flags_t dev_flags; |
bae94d02 | 325 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 326 | |
1da177e4 | 327 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 328 | struct hlist_head saved_cap_space; |
1da177e4 LT |
329 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
330 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
331 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 332 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 333 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 334 | struct list_head msi_list; |
ded86d8d | 335 | #endif |
94e61088 | 336 | struct pci_vpd *vpd; |
d1b054da | 337 | #ifdef CONFIG_PCI_IOV |
dd7cc44d YZ |
338 | union { |
339 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
340 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
341 | }; | |
302b4215 | 342 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 343 | #endif |
1da177e4 LT |
344 | }; |
345 | ||
dda56549 Y |
346 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
347 | { | |
348 | #ifdef CONFIG_PCI_IOV | |
349 | if (dev->is_virtfn) | |
350 | dev = dev->physfn; | |
351 | #endif | |
352 | ||
353 | return dev; | |
354 | } | |
355 | ||
65891215 ME |
356 | extern struct pci_dev *alloc_pci_dev(void); |
357 | ||
1da177e4 LT |
358 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
359 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
360 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
361 | ||
a7369f1f LV |
362 | static inline int pci_channel_offline(struct pci_dev *pdev) |
363 | { | |
364 | return (pdev->error_state != pci_channel_io_normal); | |
365 | } | |
366 | ||
41017f0c | 367 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 368 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
369 | { |
370 | struct pci_cap_saved_state *tmp; | |
371 | struct hlist_node *pos; | |
372 | ||
373 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
24a4742f | 374 | if (tmp->cap.cap_nr == cap) |
41017f0c SL |
375 | return tmp; |
376 | } | |
377 | return NULL; | |
378 | } | |
379 | ||
380 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
381 | struct pci_cap_saved_state *new_cap) | |
382 | { | |
383 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
384 | } | |
385 | ||
2fe2abf8 BH |
386 | /* |
387 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
388 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
389 | * buses below host bridges or subtractive decode bridges) go in the list. | |
390 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
391 | */ | |
392 | ||
393 | /* | |
394 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
395 | * and there's no way to program the bridge with the details of the window. | |
396 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
397 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
398 | */ | |
399 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
400 | ||
401 | struct pci_bus_resource { | |
402 | struct list_head list; | |
403 | struct resource *res; | |
404 | unsigned int flags; | |
405 | }; | |
4352dfd5 GKH |
406 | |
407 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
408 | |
409 | struct pci_bus { | |
410 | struct list_head node; /* node in list of buses */ | |
411 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
412 | struct list_head children; /* list of child buses */ | |
413 | struct list_head devices; /* list of devices on this bus */ | |
414 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 415 | struct list_head slots; /* list of slots on this bus */ |
2fe2abf8 BH |
416 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
417 | struct list_head resources; /* address space routed to this bus */ | |
1da177e4 LT |
418 | |
419 | struct pci_ops *ops; /* configuration access functions */ | |
420 | void *sysdata; /* hook for sys-specific extension */ | |
421 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
422 | ||
423 | unsigned char number; /* bus number */ | |
424 | unsigned char primary; /* number of primary bridge */ | |
425 | unsigned char secondary; /* number of secondary bridge */ | |
426 | unsigned char subordinate; /* max number of subordinate buses */ | |
3749c51a MW |
427 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
428 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
1da177e4 LT |
429 | |
430 | char name[48]; | |
431 | ||
432 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 433 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 434 | struct device *bridge; |
fd7d1ced | 435 | struct device dev; |
1da177e4 LT |
436 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
437 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 438 | unsigned int is_added:1; |
1da177e4 LT |
439 | }; |
440 | ||
441 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 442 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 443 | |
79af72d7 KK |
444 | /* |
445 | * Returns true if the pci bus is root (behind host-pci bridge), | |
446 | * false otherwise | |
447 | */ | |
448 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
449 | { | |
450 | return !(pbus->parent); | |
451 | } | |
452 | ||
16cf0ebc RW |
453 | #ifdef CONFIG_PCI_MSI |
454 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
455 | { | |
456 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
457 | } | |
458 | #else | |
459 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
460 | #endif | |
461 | ||
1da177e4 LT |
462 | /* |
463 | * Error values that may be returned by PCI functions. | |
464 | */ | |
465 | #define PCIBIOS_SUCCESSFUL 0x00 | |
466 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
467 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
468 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
469 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
470 | #define PCIBIOS_SET_FAILED 0x88 | |
471 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
472 | ||
473 | /* Low-level architecture-dependent routines */ | |
474 | ||
475 | struct pci_ops { | |
476 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
477 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
478 | }; | |
479 | ||
b6ce068a MW |
480 | /* |
481 | * ACPI needs to be able to access PCI config space before we've done a | |
482 | * PCI bus scan and created pci_bus structures. | |
483 | */ | |
484 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
485 | unsigned int devfn, int reg, int len, u32 *val); | |
486 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
487 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
488 | |
489 | struct pci_bus_region { | |
c40a22e0 BH |
490 | resource_size_t start; |
491 | resource_size_t end; | |
1da177e4 LT |
492 | }; |
493 | ||
494 | struct pci_dynids { | |
495 | spinlock_t lock; /* protects list, index */ | |
496 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
497 | }; |
498 | ||
392a1ce7 | 499 | /* ---------------------------------------------------------------- */ |
500 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 501 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 502 | * will be notified of PCI bus errors, and will be driven to recovery |
503 | * when an error occurs. | |
504 | */ | |
505 | ||
506 | typedef unsigned int __bitwise pci_ers_result_t; | |
507 | ||
508 | enum pci_ers_result { | |
509 | /* no result/none/not supported in device driver */ | |
510 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
511 | ||
512 | /* Device driver can recover without slot reset */ | |
513 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
514 | ||
515 | /* Device driver wants slot to be reset. */ | |
516 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
517 | ||
518 | /* Device has completely failed, is unrecoverable */ | |
519 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
520 | ||
521 | /* Device driver is fully recovered and operational */ | |
522 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
523 | }; | |
524 | ||
525 | /* PCI bus error event callbacks */ | |
05cca6e5 | 526 | struct pci_error_handlers { |
392a1ce7 | 527 | /* PCI bus error detected on this device */ |
528 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 529 | enum pci_channel_state error); |
392a1ce7 | 530 | |
531 | /* MMIO has been re-enabled, but not DMA */ | |
532 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
533 | ||
534 | /* PCI Express link has been reset */ | |
535 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
536 | ||
537 | /* PCI slot has been reset */ | |
538 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
539 | ||
540 | /* Device driver may resume normal operations */ | |
541 | void (*resume)(struct pci_dev *dev); | |
542 | }; | |
543 | ||
544 | /* ---------------------------------------------------------------- */ | |
545 | ||
1da177e4 LT |
546 | struct module; |
547 | struct pci_driver { | |
548 | struct list_head node; | |
42b21932 | 549 | const char *name; |
1da177e4 LT |
550 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
551 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
552 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
553 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
554 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
555 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 556 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 557 | void (*shutdown) (struct pci_dev *dev); |
392a1ce7 | 558 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
559 | struct device_driver driver; |
560 | struct pci_dynids dynids; | |
561 | }; | |
562 | ||
05cca6e5 | 563 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 564 | |
90a1ba0c | 565 | /** |
9f9351bb | 566 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
567 | * @_table: device table name |
568 | * | |
569 | * This macro is used to create a struct pci_device_id array (a device table) | |
570 | * in a generic manner. | |
571 | */ | |
9f9351bb | 572 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
573 | const struct pci_device_id _table[] __devinitconst |
574 | ||
1da177e4 LT |
575 | /** |
576 | * PCI_DEVICE - macro used to describe a specific pci device | |
577 | * @vend: the 16 bit PCI Vendor ID | |
578 | * @dev: the 16 bit PCI Device ID | |
579 | * | |
580 | * This macro is used to create a struct pci_device_id that matches a | |
581 | * specific device. The subvendor and subdevice fields will be set to | |
582 | * PCI_ANY_ID. | |
583 | */ | |
584 | #define PCI_DEVICE(vend,dev) \ | |
585 | .vendor = (vend), .device = (dev), \ | |
586 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
587 | ||
588 | /** | |
589 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
590 | * @dev_class: the class, subclass, prog-if triple for this device | |
591 | * @dev_class_mask: the class mask for this device | |
592 | * | |
593 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 594 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
595 | * fields will be set to PCI_ANY_ID. |
596 | */ | |
597 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
598 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
599 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
600 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
601 | ||
1597cacb AC |
602 | /** |
603 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
604 | * @vendor: the vendor name |
605 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
606 | * |
607 | * This macro is used to create a struct pci_device_id that matches a | |
608 | * specific PCI device. The subvendor, and subdevice fields will be set | |
609 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
610 | * private data. | |
611 | */ | |
612 | ||
613 | #define PCI_VDEVICE(vendor, device) \ | |
614 | PCI_VENDOR_ID_##vendor, (device), \ | |
615 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
616 | ||
1da177e4 LT |
617 | /* these external functions are only available when PCI support is enabled */ |
618 | #ifdef CONFIG_PCI | |
619 | ||
620 | extern struct bus_type pci_bus_type; | |
621 | ||
622 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
623 | * code, or pci core code. */ | |
624 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
625 | /* Some device drivers need know if pci is initiated */ |
626 | extern int no_pci_devices(void); | |
1da177e4 LT |
627 | |
628 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 629 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 630 | char *pcibios_setup(char *str); |
1da177e4 LT |
631 | |
632 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 633 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 634 | resource_size_t, |
e31dd6e4 | 635 | resource_size_t); |
1da177e4 LT |
636 | void pcibios_update_irq(struct pci_dev *, int irq); |
637 | ||
2d1c8618 BH |
638 | /* Weak but can be overriden by arch */ |
639 | void pci_fixup_cardbus(struct pci_bus *); | |
640 | ||
1da177e4 LT |
641 | /* Generic PCI functions used internally */ |
642 | ||
d1fd4fb6 | 643 | void pcibios_scan_specific_bus(int busn); |
1da177e4 | 644 | extern struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 645 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
646 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
647 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 648 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 649 | void *sysdata) |
1da177e4 | 650 | { |
c431ada4 RS |
651 | struct pci_bus *root_bus; |
652 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
653 | if (root_bus) | |
654 | pci_bus_add_devices(root_bus); | |
655 | return root_bus; | |
1da177e4 | 656 | } |
05cca6e5 GKH |
657 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
658 | struct pci_ops *ops, void *sysdata); | |
659 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
660 | int busnr); | |
3749c51a | 661 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 662 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
663 | const char *name, |
664 | struct hotplug_slot *hotplug); | |
f46753c5 | 665 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 666 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 667 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 668 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 669 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 670 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 671 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 672 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
673 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
674 | struct resource *res); | |
57c2cf71 | 675 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
1da177e4 | 676 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 677 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
1da177e4 LT |
678 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
679 | extern void pci_dev_put(struct pci_dev *dev); | |
680 | extern void pci_remove_bus(struct pci_bus *b); | |
681 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 682 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 683 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 684 | extern void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
685 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
686 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
687 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) | |
1da177e4 LT |
688 | |
689 | /* Generic PCI functions exported to card drivers */ | |
690 | ||
388c8c16 JB |
691 | enum pci_lost_interrupt_reason { |
692 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
693 | PCI_LOST_IRQ_DISABLE_MSI, | |
694 | PCI_LOST_IRQ_DISABLE_MSIX, | |
695 | PCI_LOST_IRQ_DISABLE_ACPI, | |
696 | }; | |
697 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
698 | int pci_find_capability(struct pci_dev *dev, int cap); |
699 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
700 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
cf4c43dd JB |
701 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
702 | int cap); | |
05cca6e5 GKH |
703 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
704 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 705 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 706 | |
d42552c3 AM |
707 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
708 | struct pci_dev *from); | |
05cca6e5 | 709 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 710 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 711 | struct pci_dev *from); |
05cca6e5 | 712 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
713 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
714 | unsigned int devfn); | |
715 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
716 | unsigned int devfn) | |
717 | { | |
718 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
719 | } | |
05cca6e5 | 720 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
721 | int pci_dev_present(const struct pci_device_id *ids); |
722 | ||
05cca6e5 GKH |
723 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
724 | int where, u8 *val); | |
725 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
726 | int where, u16 *val); | |
727 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
728 | int where, u32 *val); | |
729 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
730 | int where, u8 val); | |
731 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
732 | int where, u16 val); | |
733 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
734 | int where, u32 val); | |
a72b46c3 | 735 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 LT |
736 | |
737 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
738 | { | |
05cca6e5 | 739 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
740 | } |
741 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
742 | { | |
05cca6e5 | 743 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 744 | } |
05cca6e5 GKH |
745 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
746 | u32 *val) | |
1da177e4 | 747 | { |
05cca6e5 | 748 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
749 | } |
750 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
751 | { | |
05cca6e5 | 752 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
753 | } |
754 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
755 | { | |
05cca6e5 | 756 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 757 | } |
05cca6e5 GKH |
758 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
759 | u32 val) | |
1da177e4 | 760 | { |
05cca6e5 | 761 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
762 | } |
763 | ||
4a7fb636 | 764 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
765 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
766 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 767 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
768 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
769 | void pcim_pin_device(struct pci_dev *pdev); | |
770 | ||
296ccb08 YS |
771 | static inline int pci_is_enabled(struct pci_dev *pdev) |
772 | { | |
773 | return (atomic_read(&pdev->enable_cnt) > 0); | |
774 | } | |
775 | ||
9ac7849e TH |
776 | static inline int pci_is_managed(struct pci_dev *pdev) |
777 | { | |
778 | return pdev->is_managed; | |
779 | } | |
780 | ||
1da177e4 LT |
781 | void pci_disable_device(struct pci_dev *dev); |
782 | void pci_set_master(struct pci_dev *dev); | |
6a479079 | 783 | void pci_clear_master(struct pci_dev *dev); |
f7bdd12d | 784 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 785 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 786 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 787 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 788 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 789 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 790 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 791 | void pci_msi_off(struct pci_dev *dev); |
4d57cdfa | 792 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 793 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
794 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
795 | int pcix_get_mmrbc(struct pci_dev *dev); | |
796 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 797 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 798 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
8c1c699f | 799 | int __pci_reset_function(struct pci_dev *dev); |
8dd7f803 | 800 | int pci_reset_function(struct pci_dev *dev); |
14add80b | 801 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 802 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 803 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
804 | |
805 | /* ROM control related routines */ | |
e416de5e AC |
806 | int pci_enable_rom(struct pci_dev *pdev); |
807 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 808 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 809 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 810 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
1da177e4 LT |
811 | |
812 | /* Power management related routines */ | |
813 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 814 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 AW |
815 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
816 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); | |
817 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
818 | struct pci_saved_state **state); | |
0e5dd46b | 819 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
820 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
821 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 822 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 823 | void pci_pme_active(struct pci_dev *dev, bool enable); |
6cbf8214 RW |
824 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
825 | bool runtime, bool enable); | |
0235c4fc | 826 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 827 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
828 | int pci_prepare_to_sleep(struct pci_dev *dev); |
829 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 830 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 831 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 832 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
1da177e4 | 833 | |
6cbf8214 RW |
834 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
835 | bool enable) | |
836 | { | |
837 | return __pci_enable_wake(dev, state, false, enable); | |
838 | } | |
1da177e4 | 839 | |
b48d4425 JB |
840 | #define PCI_EXP_IDO_REQUEST (1<<0) |
841 | #define PCI_EXP_IDO_COMPLETION (1<<1) | |
842 | void pci_enable_ido(struct pci_dev *dev, unsigned long type); | |
843 | void pci_disable_ido(struct pci_dev *dev, unsigned long type); | |
844 | ||
48a92a81 JB |
845 | enum pci_obff_signal_type { |
846 | PCI_EXP_OBFF_SIGNAL_L0, | |
847 | PCI_EXP_OBFF_SIGNAL_ALWAYS, | |
848 | }; | |
849 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); | |
850 | void pci_disable_obff(struct pci_dev *dev); | |
851 | ||
51c2e0a7 JB |
852 | bool pci_ltr_supported(struct pci_dev *dev); |
853 | int pci_enable_ltr(struct pci_dev *dev); | |
854 | void pci_disable_ltr(struct pci_dev *dev); | |
855 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); | |
856 | ||
bb209c82 BH |
857 | /* For use by arch with custom probe code */ |
858 | void set_pcie_port_type(struct pci_dev *pdev); | |
859 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
860 | ||
ce5ccdef | 861 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 862 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
3ed4fd96 AC |
863 | #ifdef CONFIG_HOTPLUG |
864 | unsigned int pci_rescan_bus(struct pci_bus *bus); | |
865 | #endif | |
ce5ccdef | 866 | |
287d19ce SH |
867 | /* Vital product data routines */ |
868 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
869 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 870 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 871 | |
1da177e4 | 872 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
ea741551 | 873 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
874 | void pci_bus_size_bridges(struct pci_bus *bus); |
875 | int pci_claim_resource(struct pci_dev *, int); | |
876 | void pci_assign_unassigned_resources(void); | |
6841ec68 | 877 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
1da177e4 LT |
878 | void pdev_enable_device(struct pci_dev *); |
879 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 880 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
881 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
882 | int (*)(struct pci_dev *, u8, u8)); | |
883 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 884 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 885 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 886 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 887 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 888 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 889 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 890 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 891 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 892 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
893 | |
894 | /* drivers/pci/bus.c */ | |
2fe2abf8 BH |
895 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
896 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); | |
897 | void pci_bus_remove_resources(struct pci_bus *bus); | |
898 | ||
89a74ecc | 899 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
900 | for (i = 0; \ |
901 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
902 | i++) | |
89a74ecc | 903 | |
4a7fb636 AM |
904 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
905 | struct resource *res, resource_size_t size, | |
906 | resource_size_t align, resource_size_t min, | |
907 | unsigned int type_mask, | |
3b7a17fc DB |
908 | resource_size_t (*alignf)(void *, |
909 | const struct resource *, | |
b26b2d49 DB |
910 | resource_size_t, |
911 | resource_size_t), | |
4a7fb636 | 912 | void *alignf_data); |
1da177e4 LT |
913 | void pci_enable_bridges(struct pci_bus *bus); |
914 | ||
863b18f4 | 915 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
916 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
917 | const char *mod_name); | |
bba81165 AM |
918 | |
919 | /* | |
920 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
921 | */ | |
922 | #define pci_register_driver(driver) \ | |
923 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 924 | |
05cca6e5 GKH |
925 | void pci_unregister_driver(struct pci_driver *dev); |
926 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
927 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
9dba910e TH |
928 | int pci_add_dynid(struct pci_driver *drv, |
929 | unsigned int vendor, unsigned int device, | |
930 | unsigned int subvendor, unsigned int subdevice, | |
931 | unsigned int class, unsigned int class_mask, | |
932 | unsigned long driver_data); | |
05cca6e5 GKH |
933 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
934 | struct pci_dev *dev); | |
935 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
936 | int pass); | |
1da177e4 | 937 | |
70298c6e | 938 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 939 | void *userdata); |
70b9f7dc | 940 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 941 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 942 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 943 | |
3448a19d DA |
944 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
945 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
946 | ||
deb2d2ec | 947 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 948 | unsigned int command_bits, u32 flags); |
1da177e4 LT |
949 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
950 | ||
f41b1771 | 951 | #include <linux/pci-dma.h> |
1da177e4 LT |
952 | #include <linux/dmapool.h> |
953 | ||
954 | #define pci_pool dma_pool | |
955 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
956 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
957 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
958 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
959 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
960 | ||
e24c2d96 DM |
961 | enum pci_dma_burst_strategy { |
962 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
963 | strategy_parameter is N/A */ | |
964 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
965 | byte boundaries */ | |
966 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
967 | strategy_parameter byte boundaries */ | |
968 | }; | |
969 | ||
1da177e4 | 970 | struct msix_entry { |
16dbef4a | 971 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
972 | u16 entry; /* driver uses to specify entry, OS writes */ |
973 | }; | |
974 | ||
0366f8f7 | 975 | |
1da177e4 | 976 | #ifndef CONFIG_PCI_MSI |
1c8d7b0a | 977 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
05cca6e5 GKH |
978 | { |
979 | return -1; | |
980 | } | |
981 | ||
d52877c7 YL |
982 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
983 | { } | |
05cca6e5 GKH |
984 | static inline void pci_disable_msi(struct pci_dev *dev) |
985 | { } | |
986 | ||
a52e2e35 RW |
987 | static inline int pci_msix_table_size(struct pci_dev *dev) |
988 | { | |
989 | return 0; | |
990 | } | |
05cca6e5 GKH |
991 | static inline int pci_enable_msix(struct pci_dev *dev, |
992 | struct msix_entry *entries, int nvec) | |
993 | { | |
994 | return -1; | |
995 | } | |
996 | ||
d52877c7 YL |
997 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
998 | { } | |
05cca6e5 GKH |
999 | static inline void pci_disable_msix(struct pci_dev *dev) |
1000 | { } | |
1001 | ||
1002 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
1003 | { } | |
1004 | ||
1005 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
1006 | { } | |
07ae95f9 AP |
1007 | static inline int pci_msi_enabled(void) |
1008 | { | |
1009 | return 0; | |
1010 | } | |
1da177e4 | 1011 | #else |
1c8d7b0a | 1012 | extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
d52877c7 | 1013 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 1014 | extern void pci_disable_msi(struct pci_dev *dev); |
a52e2e35 | 1015 | extern int pci_msix_table_size(struct pci_dev *dev); |
05cca6e5 | 1016 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 1017 | struct msix_entry *entries, int nvec); |
d52877c7 | 1018 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
1019 | extern void pci_disable_msix(struct pci_dev *dev); |
1020 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 1021 | extern void pci_restore_msi_state(struct pci_dev *dev); |
07ae95f9 | 1022 | extern int pci_msi_enabled(void); |
1da177e4 LT |
1023 | #endif |
1024 | ||
ab0724ff | 1025 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 RW |
1026 | extern bool pcie_ports_disabled; |
1027 | extern bool pcie_ports_auto; | |
ab0724ff MT |
1028 | #else |
1029 | #define pcie_ports_disabled true | |
1030 | #define pcie_ports_auto false | |
1031 | #endif | |
415e12b2 | 1032 | |
3e1b1600 | 1033 | #ifndef CONFIG_PCIEASPM |
8b8bae90 RW |
1034 | static inline int pcie_aspm_enabled(void) { return 0; } |
1035 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 AP |
1036 | #else |
1037 | extern int pcie_aspm_enabled(void); | |
8b8bae90 | 1038 | extern bool pcie_aspm_support_enabled(void); |
3e1b1600 AP |
1039 | #endif |
1040 | ||
415e12b2 RW |
1041 | #ifdef CONFIG_PCIEAER |
1042 | void pci_no_aer(void); | |
1043 | bool pci_aer_available(void); | |
1044 | #else | |
1045 | static inline void pci_no_aer(void) { } | |
1046 | static inline bool pci_aer_available(void) { return false; } | |
1047 | #endif | |
1048 | ||
43c16408 AP |
1049 | #ifndef CONFIG_PCIE_ECRC |
1050 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) | |
1051 | { | |
1052 | return; | |
1053 | } | |
1054 | static inline void pcie_ecrc_get_policy(char *str) {}; | |
1055 | #else | |
1056 | extern void pcie_set_ecrc_checking(struct pci_dev *dev); | |
1057 | extern void pcie_ecrc_get_policy(char *str); | |
1058 | #endif | |
1059 | ||
1c8d7b0a MW |
1060 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
1061 | ||
8b955b0d | 1062 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
1063 | /* The functions a driver should call */ |
1064 | int ht_create_irq(struct pci_dev *dev, int idx); | |
1065 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
1066 | #endif /* CONFIG_HT_IRQ */ |
1067 | ||
e04b0ea2 BK |
1068 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
1069 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
1070 | ||
4352dfd5 GKH |
1071 | /* |
1072 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
1073 | * a PCI domain is defined to be a set of PCI busses which share | |
1074 | * configuration space. | |
1075 | */ | |
32a2eea7 JG |
1076 | #ifdef CONFIG_PCI_DOMAINS |
1077 | extern int pci_domains_supported; | |
1078 | #else | |
1079 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
1080 | static inline int pci_domain_nr(struct pci_bus *bus) |
1081 | { | |
1082 | return 0; | |
1083 | } | |
1084 | ||
4352dfd5 GKH |
1085 | static inline int pci_proc_domain(struct pci_bus *bus) |
1086 | { | |
1087 | return 0; | |
1088 | } | |
32a2eea7 | 1089 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1090 | |
95a8b6ef MT |
1091 | /* some architectures require additional setup to direct VGA traffic */ |
1092 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, | |
3448a19d | 1093 | unsigned int command_bits, u32 flags); |
95a8b6ef MT |
1094 | extern void pci_register_set_vga_state(arch_set_vga_state_t func); |
1095 | ||
4352dfd5 | 1096 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
1097 | |
1098 | /* | |
1099 | * If the system does not have PCI, clearly these return errors. Define | |
1100 | * these as simple inline functions to avoid hair in drivers. | |
1101 | */ | |
1102 | ||
05cca6e5 GKH |
1103 | #define _PCI_NOP(o, s, t) \ |
1104 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1105 | int where, t val) \ | |
1da177e4 | 1106 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1107 | |
1108 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1109 | _PCI_NOP(o, word, u16 x) \ | |
1110 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1111 | _PCI_NOP_ALL(read, *) |
1112 | _PCI_NOP_ALL(write,) | |
1113 | ||
d42552c3 | 1114 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1115 | unsigned int device, |
1116 | struct pci_dev *from) | |
1117 | { | |
1118 | return NULL; | |
1119 | } | |
d42552c3 | 1120 | |
05cca6e5 GKH |
1121 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1122 | unsigned int device, | |
1123 | unsigned int ss_vendor, | |
1124 | unsigned int ss_device, | |
b08508c4 | 1125 | struct pci_dev *from) |
05cca6e5 GKH |
1126 | { |
1127 | return NULL; | |
1128 | } | |
1da177e4 | 1129 | |
05cca6e5 GKH |
1130 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1131 | struct pci_dev *from) | |
1132 | { | |
1133 | return NULL; | |
1134 | } | |
1da177e4 LT |
1135 | |
1136 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1137 | #define no_pci_devices() (1) |
1da177e4 LT |
1138 | #define pci_dev_put(dev) do { } while (0) |
1139 | ||
05cca6e5 GKH |
1140 | static inline void pci_set_master(struct pci_dev *dev) |
1141 | { } | |
1142 | ||
1143 | static inline int pci_enable_device(struct pci_dev *dev) | |
1144 | { | |
1145 | return -EIO; | |
1146 | } | |
1147 | ||
1148 | static inline void pci_disable_device(struct pci_dev *dev) | |
1149 | { } | |
1150 | ||
1151 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1152 | { | |
1153 | return -EIO; | |
1154 | } | |
1155 | ||
80be0385 RD |
1156 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1157 | { | |
1158 | return -EIO; | |
1159 | } | |
1160 | ||
4d57cdfa FT |
1161 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1162 | unsigned int size) | |
1163 | { | |
1164 | return -EIO; | |
1165 | } | |
1166 | ||
59fc67de FT |
1167 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1168 | unsigned long mask) | |
1169 | { | |
1170 | return -EIO; | |
1171 | } | |
1172 | ||
05cca6e5 GKH |
1173 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1174 | { | |
1175 | return -EBUSY; | |
1176 | } | |
1177 | ||
1178 | static inline int __pci_register_driver(struct pci_driver *drv, | |
1179 | struct module *owner) | |
1180 | { | |
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static inline int pci_register_driver(struct pci_driver *drv) | |
1185 | { | |
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
1190 | { } | |
1191 | ||
1192 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
1193 | { | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
1198 | int cap) | |
1199 | { | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
1204 | { | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1da177e4 | 1208 | /* Power management related routines */ |
05cca6e5 GKH |
1209 | static inline int pci_save_state(struct pci_dev *dev) |
1210 | { | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1d3c16a8 JM |
1214 | static inline void pci_restore_state(struct pci_dev *dev) |
1215 | { } | |
1da177e4 | 1216 | |
05cca6e5 GKH |
1217 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1218 | { | |
1219 | return 0; | |
1220 | } | |
1221 | ||
3449248c RD |
1222 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
1223 | { | |
1224 | return 0; | |
1225 | } | |
1226 | ||
05cca6e5 GKH |
1227 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1228 | pm_message_t state) | |
1229 | { | |
1230 | return PCI_D0; | |
1231 | } | |
1232 | ||
1233 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1234 | int enable) | |
1235 | { | |
1236 | return 0; | |
1237 | } | |
1238 | ||
b48d4425 JB |
1239 | static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
1240 | { | |
1241 | } | |
1242 | ||
1243 | static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |
1244 | { | |
1245 | } | |
1246 | ||
48a92a81 JB |
1247 | static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) |
1248 | { | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static inline void pci_disable_obff(struct pci_dev *dev) | |
1253 | { | |
1254 | } | |
1255 | ||
05cca6e5 GKH |
1256 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
1257 | { | |
1258 | return -EIO; | |
1259 | } | |
1260 | ||
1261 | static inline void pci_release_regions(struct pci_dev *dev) | |
1262 | { } | |
0da0ead9 | 1263 | |
a46e8126 KG |
1264 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1265 | ||
05cca6e5 GKH |
1266 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
1267 | { } | |
1268 | ||
1269 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
1270 | { } | |
e04b0ea2 | 1271 | |
d80d0217 RD |
1272 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1273 | { return NULL; } | |
1274 | ||
1275 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1276 | unsigned int devfn) | |
1277 | { return NULL; } | |
1278 | ||
1279 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1280 | unsigned int devfn) | |
1281 | { return NULL; } | |
1282 | ||
92298e66 DA |
1283 | static inline int pci_domain_nr(struct pci_bus *bus) |
1284 | { return 0; } | |
1285 | ||
fb8a0d9d WM |
1286 | #define dev_is_pci(d) (false) |
1287 | #define dev_is_pf(d) (false) | |
1288 | #define dev_num_vf(d) (0) | |
4352dfd5 | 1289 | #endif /* CONFIG_PCI */ |
1da177e4 | 1290 | |
4352dfd5 GKH |
1291 | /* Include architecture-dependent settings and functions */ |
1292 | ||
1293 | #include <asm/pci.h> | |
1da177e4 | 1294 | |
1f82de10 YL |
1295 | #ifndef PCIBIOS_MAX_MEM_32 |
1296 | #define PCIBIOS_MAX_MEM_32 (-1) | |
1297 | #endif | |
1298 | ||
1da177e4 LT |
1299 | /* these helpers provide future and backwards compatibility |
1300 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1301 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1302 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1303 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1304 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1305 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1306 | pci_resource_end((dev), (bar)) == \ | |
1307 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1308 | \ | |
1309 | (pci_resource_end((dev), (bar)) - \ | |
1310 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1311 | |
1312 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1313 | * driver-specific data. They are really just a wrapper around | |
1314 | * the generic device structure functions of these calls. | |
1315 | */ | |
05cca6e5 | 1316 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1317 | { |
1318 | return dev_get_drvdata(&pdev->dev); | |
1319 | } | |
1320 | ||
05cca6e5 | 1321 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1322 | { |
1323 | dev_set_drvdata(&pdev->dev, data); | |
1324 | } | |
1325 | ||
1326 | /* If you want to know what to call your pci_dev, ask this function. | |
1327 | * Again, it's a wrapper around the generic device. | |
1328 | */ | |
2fc90f61 | 1329 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1330 | { |
c6c4f070 | 1331 | return dev_name(&pdev->dev); |
1da177e4 LT |
1332 | } |
1333 | ||
2311b1f2 ME |
1334 | |
1335 | /* Some archs don't want to expose struct resource to userland as-is | |
1336 | * in sysfs and /proc | |
1337 | */ | |
1338 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1339 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1340 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1341 | resource_size_t *end) |
2311b1f2 ME |
1342 | { |
1343 | *start = rsrc->start; | |
1344 | *end = rsrc->end; | |
1345 | } | |
1346 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1347 | ||
1348 | ||
1da177e4 LT |
1349 | /* |
1350 | * The world is not perfect and supplies us with broken PCI devices. | |
1351 | * For at least a part of these bugs we need a work-around, so both | |
1352 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1353 | * fixup hooks to be called for particular buggy devices. | |
1354 | */ | |
1355 | ||
1356 | struct pci_fixup { | |
1357 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1358 | void (*hook)(struct pci_dev *dev); | |
1359 | }; | |
1360 | ||
1361 | enum pci_fixup_pass { | |
1362 | pci_fixup_early, /* Before probing BARs */ | |
1363 | pci_fixup_header, /* After reading configuration header */ | |
1364 | pci_fixup_final, /* Final phase of device fixups */ | |
1365 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1366 | pci_fixup_resume, /* pci_device_resume() */ |
1367 | pci_fixup_suspend, /* pci_device_suspend */ | |
1368 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1369 | }; |
1370 | ||
1371 | /* Anonymous variables would be nice... */ | |
1372 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1373 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1374 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1375 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1376 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1377 | vendor##device##hook, vendor, device, hook) | |
1378 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1379 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1380 | vendor##device##hook, vendor, device, hook) | |
1381 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1382 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1383 | vendor##device##hook, vendor, device, hook) | |
1384 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1385 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1386 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1387 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1388 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1389 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1390 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1391 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1392 | resume_early##vendor##device##hook, vendor, device, hook) | |
1393 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1394 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1395 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 | 1396 | |
93177a74 | 1397 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1398 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
1399 | #else |
1400 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
1401 | struct pci_dev *dev) {} | |
1402 | #endif | |
1da177e4 | 1403 | |
05cca6e5 | 1404 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1405 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1406 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1407 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1408 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1409 | const char *name); | |
ec04b075 | 1410 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1411 | |
1da177e4 | 1412 | extern int pci_pci_problems; |
236561e5 | 1413 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1414 | #define PCIPCI_TRITON 2 |
1415 | #define PCIPCI_NATOMA 4 | |
1416 | #define PCIPCI_VIAETBF 8 | |
1417 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1418 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1419 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1420 | |
4516a618 AN |
1421 | extern unsigned long pci_cardbus_io_size; |
1422 | extern unsigned long pci_cardbus_mem_size; | |
491424c0 | 1423 | extern u8 __devinitdata pci_dfl_cache_line_size; |
ac1aa47b | 1424 | extern u8 pci_cache_line_size; |
4516a618 | 1425 | |
28760489 EB |
1426 | extern unsigned long pci_hotplug_io_size; |
1427 | extern unsigned long pci_hotplug_mem_size; | |
1428 | ||
19792a08 AB |
1429 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1430 | void pcibios_disable_device(struct pci_dev *dev); | |
1431 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1432 | enum pcie_reset_state state); | |
575e3348 | 1433 | |
7752d5cf | 1434 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1435 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1436 | extern void __init pci_mmcfg_late_init(void); |
1437 | #else | |
bb63b421 | 1438 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1439 | static inline void pci_mmcfg_late_init(void) { } |
1440 | #endif | |
1441 | ||
0ef5f8f6 AP |
1442 | int pci_ext_cfg_avail(struct pci_dev *dev); |
1443 | ||
1684f5dd | 1444 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1445 | |
dd7cc44d YZ |
1446 | #ifdef CONFIG_PCI_IOV |
1447 | extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); | |
1448 | extern void pci_disable_sriov(struct pci_dev *dev); | |
74bb1bcc | 1449 | extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
fb8a0d9d | 1450 | extern int pci_num_vf(struct pci_dev *dev); |
dd7cc44d YZ |
1451 | #else |
1452 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
1453 | { | |
1454 | return -ENODEV; | |
1455 | } | |
1456 | static inline void pci_disable_sriov(struct pci_dev *dev) | |
1457 | { | |
1458 | } | |
74bb1bcc YZ |
1459 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1460 | { | |
1461 | return IRQ_NONE; | |
1462 | } | |
fb8a0d9d WM |
1463 | static inline int pci_num_vf(struct pci_dev *dev) |
1464 | { | |
1465 | return 0; | |
1466 | } | |
dd7cc44d YZ |
1467 | #endif |
1468 | ||
c825bc94 KK |
1469 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
1470 | extern void pci_hp_create_module_link(struct pci_slot *pci_slot); | |
1471 | extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
1472 | #endif | |
1473 | ||
d7b7e605 KK |
1474 | /** |
1475 | * pci_pcie_cap - get the saved PCIe capability offset | |
1476 | * @dev: PCI device | |
1477 | * | |
1478 | * PCIe capability offset is calculated at PCI device initialization | |
1479 | * time and saved in the data structure. This function returns saved | |
1480 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1481 | * reduces unnecessary search in the PCI configuration space. If you | |
1482 | * need to calculate PCIe capability offset from raw device for some | |
1483 | * reasons, please use pci_find_capability() instead. | |
1484 | */ | |
1485 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1486 | { | |
1487 | return dev->pcie_cap; | |
1488 | } | |
1489 | ||
7eb776c4 KK |
1490 | /** |
1491 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1492 | * @dev: PCI device | |
1493 | * | |
1494 | * Retrun true if the PCI device is PCI Express capable, false otherwise. | |
1495 | */ | |
1496 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1497 | { | |
1498 | return !!pci_pcie_cap(dev); | |
1499 | } | |
1500 | ||
5d990b62 CW |
1501 | void pci_request_acs(void); |
1502 | ||
a2ce7662 | 1503 | |
7ad506fa MC |
1504 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
1505 | #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) | |
1506 | ||
1507 | /* Large Resource Data Type Tag Item Names */ | |
1508 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
1509 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
1510 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
1511 | ||
1512 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
1513 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
1514 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
1515 | ||
1516 | /* Small Resource Data Type Tag Item Names */ | |
1517 | #define PCI_VPD_STIN_END 0x78 /* End */ | |
1518 | ||
1519 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END | |
1520 | ||
1521 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
1522 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
1523 | ||
1524 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
1525 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 1526 | |
e1d5bdab MC |
1527 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1528 | ||
4067a854 MC |
1529 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1530 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
1531 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 1532 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 1533 | |
a2ce7662 MC |
1534 | /** |
1535 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
1536 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1537 | * | |
1538 | * Returns the extracted Large Resource Data Type length. | |
1539 | */ | |
1540 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
1541 | { | |
1542 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
1543 | } | |
1544 | ||
7ad506fa MC |
1545 | /** |
1546 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
1547 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
1548 | * | |
1549 | * Returns the extracted Small Resource Data Type length. | |
1550 | */ | |
1551 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
1552 | { | |
1553 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
1554 | } | |
1555 | ||
e1d5bdab MC |
1556 | /** |
1557 | * pci_vpd_info_field_size - Extracts the information field length | |
1558 | * @lrdt: Pointer to the beginning of an information field header | |
1559 | * | |
1560 | * Returns the extracted information field length. | |
1561 | */ | |
1562 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
1563 | { | |
1564 | return info_field[2]; | |
1565 | } | |
1566 | ||
b55ac1b2 MC |
1567 | /** |
1568 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
1569 | * @buf: Pointer to buffered vpd data | |
1570 | * @off: The offset into the buffer at which to begin the search | |
1571 | * @len: The length of the vpd buffer | |
1572 | * @rdt: The Resource Data Type to search for | |
1573 | * | |
1574 | * Returns the index where the Resource Data Type was found or | |
1575 | * -ENOENT otherwise. | |
1576 | */ | |
1577 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
1578 | ||
4067a854 MC |
1579 | /** |
1580 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
1581 | * @buf: Pointer to buffered vpd data | |
1582 | * @off: The offset into the buffer at which to begin the search | |
1583 | * @len: The length of the buffer area, relative to off, in which to search | |
1584 | * @kw: The keyword to search for | |
1585 | * | |
1586 | * Returns the index where the information field keyword was found or | |
1587 | * -ENOENT otherwise. | |
1588 | */ | |
1589 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
1590 | unsigned int len, const char *kw); | |
1591 | ||
1da177e4 LT |
1592 | #endif /* __KERNEL__ */ |
1593 | #endif /* LINUX_PCI_H */ |