Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * pci.h | |
4 | * | |
5 | * PCI defines and function prototypes | |
6 | * Copyright 1994, Drew Eckhardt | |
7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
8 | * | |
7ce2e76a KW |
9 | * PCI Express ASPM defines and function prototypes |
10 | * Copyright (c) 2007 Intel Corp. | |
11 | * Zhang Yanmin (yanmin.zhang@intel.com) | |
12 | * Shaohua Li (shaohua.li@intel.com) | |
13 | * | |
1da177e4 LT |
14 | * For more information, please consult the following manuals (look at |
15 | * http://www.pcisig.com/ for how to get them): | |
16 | * | |
17 | * PCI BIOS Specification | |
18 | * PCI Local Bus Specification | |
19 | * PCI to PCI Bridge Specification | |
7ce2e76a | 20 | * PCI Express Specification |
1da177e4 LT |
21 | * PCI System Design Guide |
22 | */ | |
1da177e4 LT |
23 | #ifndef LINUX_PCI_H |
24 | #define LINUX_PCI_H | |
25 | ||
1da177e4 | 26 | |
778382e0 DW |
27 | #include <linux/mod_devicetable.h> |
28 | ||
1da177e4 | 29 | #include <linux/types.h> |
98db6f19 | 30 | #include <linux/init.h> |
1da177e4 LT |
31 | #include <linux/ioport.h> |
32 | #include <linux/list.h> | |
4a7fb636 | 33 | #include <linux/compiler.h> |
1da177e4 | 34 | #include <linux/errno.h> |
f46753c5 | 35 | #include <linux/kobject.h> |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <linux/device.h> |
704e8953 | 38 | #include <linux/interrupt.h> |
1388cc96 | 39 | #include <linux/io.h> |
14d76b68 | 40 | #include <linux/resource_ext.h> |
607ca46e | 41 | #include <uapi/linux/pci.h> |
1da177e4 | 42 | |
7e7a43c3 AB |
43 | #include <linux/pci_ids.h> |
44 | ||
d6e055e8 HK |
45 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
46 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | |
47 | PCI_STATUS_REC_MASTER_ABORT | \ | |
48 | PCI_STATUS_REC_TARGET_ABORT | \ | |
49 | PCI_STATUS_SIG_TARGET_ABORT | \ | |
50 | PCI_STATUS_PARITY) | |
51 | ||
85467136 SK |
52 | /* |
53 | * The PCI interface treats multi-function devices as independent | |
54 | * devices. The slot/function address of each device is encoded | |
55 | * in a single byte as follows: | |
56 | * | |
57 | * 7:3 = slot | |
58 | * 2:0 = function | |
f7625980 BH |
59 | * |
60 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 61 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 62 | * the following kernel-only defines are being added here. |
85467136 | 63 | */ |
0aa0f5d1 | 64 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
65 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
66 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
67 | ||
f46753c5 AC |
68 | /* pci_slot represents a physical slot */ |
69 | struct pci_slot { | |
0aa0f5d1 BH |
70 | struct pci_bus *bus; /* Bus this slot is on */ |
71 | struct list_head list; /* Node in list of slots */ | |
72 | struct hotplug_slot *hotplug; /* Hotplug info (move here) */ | |
73 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
74 | struct kobject kobj; | |
f46753c5 AC |
75 | }; |
76 | ||
0ad772ec AC |
77 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
78 | { | |
79 | return kobject_name(&slot->kobj); | |
80 | } | |
81 | ||
1da177e4 LT |
82 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
83 | enum pci_mmap_state { | |
84 | pci_mmap_io, | |
85 | pci_mmap_mem | |
86 | }; | |
87 | ||
0aa0f5d1 | 88 | /* For PCI devices, the region numbers are assigned this way: */ |
fde09c6d YZ |
89 | enum { |
90 | /* #0-5: standard PCI resources */ | |
91 | PCI_STD_RESOURCES, | |
c9c13ba4 | 92 | PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, |
fde09c6d YZ |
93 | |
94 | /* #6: expansion ROM resource */ | |
95 | PCI_ROM_RESOURCE, | |
96 | ||
0aa0f5d1 | 97 | /* Device-specific resources */ |
d1b054da YZ |
98 | #ifdef CONFIG_PCI_IOV |
99 | PCI_IOV_RESOURCES, | |
100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
101 | #endif | |
102 | ||
6e0688db KW |
103 | /* PCI-to-PCI (P2P) bridge windows */ |
104 | #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
105 | #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
106 | #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
107 | ||
108 | /* CardBus bridge windows */ | |
109 | #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
110 | #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
111 | #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
112 | #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) | |
113 | ||
114 | /* Total number of bridge resources for P2P and CardBus */ | |
fde09c6d YZ |
115 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
116 | ||
6e0688db | 117 | /* Resources assigned to buses behind the bridge */ |
fde09c6d YZ |
118 | PCI_BRIDGE_RESOURCES, |
119 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
120 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
121 | ||
0aa0f5d1 | 122 | /* Total resources associated with a PCI device */ |
fde09c6d YZ |
123 | PCI_NUM_RESOURCES, |
124 | ||
0aa0f5d1 | 125 | /* Preserve this for compatibility */ |
cda57bf9 | 126 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 127 | }; |
1da177e4 | 128 | |
b352baf1 PB |
129 | /** |
130 | * enum pci_interrupt_pin - PCI INTx interrupt values | |
131 | * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt | |
132 | * @PCI_INTERRUPT_INTA: PCI INTA pin | |
133 | * @PCI_INTERRUPT_INTB: PCI INTB pin | |
134 | * @PCI_INTERRUPT_INTC: PCI INTC pin | |
135 | * @PCI_INTERRUPT_INTD: PCI INTD pin | |
136 | * | |
137 | * Corresponds to values for legacy PCI INTx interrupts, as can be found in the | |
138 | * PCI_INTERRUPT_PIN register. | |
139 | */ | |
140 | enum pci_interrupt_pin { | |
141 | PCI_INTERRUPT_UNKNOWN, | |
142 | PCI_INTERRUPT_INTA, | |
143 | PCI_INTERRUPT_INTB, | |
144 | PCI_INTERRUPT_INTC, | |
145 | PCI_INTERRUPT_INTD, | |
146 | }; | |
147 | ||
148 | /* The number of legacy PCI INTx interrupts */ | |
149 | #define PCI_NUM_INTX 4 | |
150 | ||
224abb67 BH |
151 | /* |
152 | * pci_power_t values must match the bits in the Capabilities PME_Support | |
153 | * and Control/Status PowerState fields in the Power Management capability. | |
154 | */ | |
1da177e4 LT |
155 | typedef int __bitwise pci_power_t; |
156 | ||
4352dfd5 GKH |
157 | #define PCI_D0 ((pci_power_t __force) 0) |
158 | #define PCI_D1 ((pci_power_t __force) 1) | |
159 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
160 | #define PCI_D3hot ((pci_power_t __force) 3) |
161 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 162 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 163 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 164 | |
00240c38 AS |
165 | /* Remember to update this when the list above changes! */ |
166 | extern const char *pci_power_names[]; | |
167 | ||
168 | static inline const char *pci_power_name(pci_power_t state) | |
169 | { | |
9661e783 | 170 | return pci_power_names[1 + (__force int) state]; |
00240c38 AS |
171 | } |
172 | ||
0aa0f5d1 | 173 | /** |
229b4e07 CD |
174 | * typedef pci_channel_state_t |
175 | * | |
0aa0f5d1 BH |
176 | * The pci_channel state describes connectivity between the CPU and |
177 | * the PCI device. If some PCI bus between here and the PCI device | |
178 | * has crashed or locked up, this info is reflected here. | |
392a1ce7 | 179 | */ |
180 | typedef unsigned int __bitwise pci_channel_state_t; | |
181 | ||
16d79cd4 | 182 | enum { |
392a1ce7 | 183 | /* I/O channel is in normal state */ |
184 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
185 | ||
186 | /* I/O to channel is blocked */ | |
187 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
188 | ||
189 | /* PCI card is dead */ | |
190 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
191 | }; | |
192 | ||
f7bdd12d BK |
193 | typedef unsigned int __bitwise pcie_reset_state_t; |
194 | ||
195 | enum pcie_reset_state { | |
196 | /* Reset is NOT asserted (Use to deassert reset) */ | |
197 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
198 | ||
f7625980 | 199 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
200 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
201 | ||
f7625980 | 202 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
203 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
204 | }; | |
205 | ||
ba698ad4 DM |
206 | typedef unsigned short __bitwise pci_dev_flags_t; |
207 | enum pci_dev_flags { | |
0aa0f5d1 | 208 | /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ |
6b121592 | 209 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 210 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 211 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 212 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 213 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 214 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 215 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
c8fe16e3 AW |
216 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
217 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
218 | /* Do not use bus resets for device */ |
219 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
220 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
221 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
932c435c MR |
222 | /* Get VPD from function 0 VPD */ |
223 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), | |
0aa0f5d1 | 224 | /* A non-root bridge where translation occurs, stop alias search here */ |
ffff8858 | 225 | PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), |
f65fd1aa SN |
226 | /* Do not use FLR even if device advertises PCI_AF_CAP */ |
227 | PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), | |
a99b646a | 228 | /* Don't use Relaxed Ordering for TLPs directed at this device */ |
c2eac4d3 | 229 | PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), |
ba698ad4 DM |
230 | }; |
231 | ||
e1d3a908 SA |
232 | enum pci_irq_reroute_variant { |
233 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
234 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
235 | }; | |
236 | ||
6e325a62 MT |
237 | typedef unsigned short __bitwise pci_bus_flags_t; |
238 | enum pci_bus_flags { | |
032c3d86 JD |
239 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
240 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
241 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, | |
17e8f0d4 | 242 | PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, |
6e325a62 MT |
243 | }; |
244 | ||
0aa0f5d1 | 245 | /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ |
59da381e JK |
246 | enum pcie_link_width { |
247 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
248 | PCIE_LNK_X1 = 0x01, | |
249 | PCIE_LNK_X2 = 0x02, | |
250 | PCIE_LNK_X4 = 0x04, | |
251 | PCIE_LNK_X8 = 0x08, | |
0aa0f5d1 | 252 | PCIE_LNK_X12 = 0x0c, |
59da381e JK |
253 | PCIE_LNK_X16 = 0x10, |
254 | PCIE_LNK_X32 = 0x20, | |
0aa0f5d1 | 255 | PCIE_LNK_WIDTH_UNKNOWN = 0xff, |
59da381e JK |
256 | }; |
257 | ||
e56faff5 | 258 | /* See matching string table in pci_speed_string() */ |
536c8cb4 MW |
259 | enum pci_bus_speed { |
260 | PCI_SPEED_33MHz = 0x00, | |
261 | PCI_SPEED_66MHz = 0x01, | |
262 | PCI_SPEED_66MHz_PCIX = 0x02, | |
263 | PCI_SPEED_100MHz_PCIX = 0x03, | |
264 | PCI_SPEED_133MHz_PCIX = 0x04, | |
265 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
266 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
267 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
268 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
269 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
270 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
271 | AGP_UNKNOWN = 0x0c, |
272 | AGP_1X = 0x0d, | |
273 | AGP_2X = 0x0e, | |
274 | AGP_4X = 0x0f, | |
275 | AGP_8X = 0x10, | |
536c8cb4 MW |
276 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
277 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
278 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
279 | PCIE_SPEED_2_5GT = 0x14, | |
280 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 281 | PCIE_SPEED_8_0GT = 0x16, |
1acfb9b7 | 282 | PCIE_SPEED_16_0GT = 0x17, |
de76cda2 | 283 | PCIE_SPEED_32_0GT = 0x18, |
536c8cb4 MW |
284 | PCI_SPEED_UNKNOWN = 0xff, |
285 | }; | |
286 | ||
576c7218 AD |
287 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
288 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); | |
289 | ||
24a4742f | 290 | struct pci_cap_saved_data { |
0aa0f5d1 BH |
291 | u16 cap_nr; |
292 | bool cap_extended; | |
293 | unsigned int size; | |
914a1951 | 294 | u32 data[]; |
41017f0c SL |
295 | }; |
296 | ||
24a4742f | 297 | struct pci_cap_saved_state { |
0aa0f5d1 BH |
298 | struct hlist_node next; |
299 | struct pci_cap_saved_data cap; | |
24a4742f AW |
300 | }; |
301 | ||
402723ad | 302 | struct irq_affinity; |
7d715a6c | 303 | struct pcie_link_state; |
ee69439c | 304 | struct pci_vpd; |
d1b054da | 305 | struct pci_sriov; |
52916982 | 306 | struct pci_p2pdma; |
ee69439c | 307 | |
0aa0f5d1 | 308 | /* The pci_dev structure describes PCI devices */ |
1da177e4 | 309 | struct pci_dev { |
0aa0f5d1 BH |
310 | struct list_head bus_list; /* Node in per-bus list */ |
311 | struct pci_bus *bus; /* Bus this device is on */ | |
312 | struct pci_bus *subordinate; /* Bus this device bridges to */ | |
1da177e4 | 313 | |
0aa0f5d1 BH |
314 | void *sysdata; /* Hook for sys-specific extension */ |
315 | struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ | |
f46753c5 | 316 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 | 317 | |
0aa0f5d1 | 318 | unsigned int devfn; /* Encoded device & function index */ |
1da177e4 LT |
319 | unsigned short vendor; |
320 | unsigned short device; | |
321 | unsigned short subsystem_vendor; | |
322 | unsigned short subsystem_device; | |
323 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 324 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 325 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
66b80809 KB |
326 | #ifdef CONFIG_PCIEAER |
327 | u16 aer_cap; /* AER capability offset */ | |
db89ccbe | 328 | struct aer_stats *aer_stats; /* AER stats for this device */ |
66b80809 | 329 | #endif |
f7625980 | 330 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
331 | u8 msi_cap; /* MSI capability offset */ |
332 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 333 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
0aa0f5d1 BH |
334 | u8 rom_base_reg; /* Config register controlling ROM */ |
335 | u8 pin; /* Interrupt pin this device uses */ | |
336 | u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ | |
337 | unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ | |
1da177e4 | 338 | |
0aa0f5d1 | 339 | struct pci_driver *driver; /* Driver bound to this device */ |
1da177e4 LT |
340 | u64 dma_mask; /* Mask of the bits of bus address this |
341 | device implements. Normally this is | |
342 | 0xffffffff. You only need to change | |
343 | this if your device has broken DMA | |
344 | or supports 64-bit transfers. */ | |
345 | ||
4d57cdfa FT |
346 | struct device_dma_parameters dma_parms; |
347 | ||
0aa0f5d1 BH |
348 | pci_power_t current_state; /* Current operating state. In ACPI, |
349 | this is D0-D3, D0 being fully | |
350 | functional, and D3 being off. */ | |
d6112f8d | 351 | unsigned int imm_ready:1; /* Supports Immediate Readiness */ |
703860ed | 352 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
353 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
354 | can be generated */ | |
379021d5 | 355 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
356 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
357 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
358 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
359 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
9d26d3a8 | 360 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
448bd857 | 361 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
0aa0f5d1 BH |
362 | unsigned int mmio_always_on:1; /* Disallow turning off io/mem |
363 | decoding during BAR sizing */ | |
e80bb09d | 364 | unsigned int wakeup_prepared:1; |
0aa0f5d1 | 365 | unsigned int runtime_d3cold:1; /* Whether go through runtime |
448bd857 HY |
366 | D3cold, not set for devices |
367 | powered on/off by the | |
368 | corresponding bridge */ | |
d491f2b7 | 369 | unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ |
b440bde7 | 370 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
576243b3 KB |
371 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
372 | controlled exclusively by | |
373 | user sysfs */ | |
4ec73791 SM |
374 | unsigned int clear_retrain_link:1; /* Need to clear Retrain Link |
375 | bit manually */ | |
1ae861e6 | 376 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
448bd857 | 377 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 378 | |
7d715a6c | 379 | #ifdef CONFIG_PCIEASPM |
f7625980 | 380 | struct pcie_link_state *link_state; /* ASPM link state */ |
c46fd358 BH |
381 | unsigned int ltr_path:1; /* Latency Tolerance Reporting |
382 | supported from root to here */ | |
7d715a6c | 383 | #endif |
7ce3f912 | 384 | unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ |
7d715a6c | 385 | |
0aa0f5d1 BH |
386 | pci_channel_state_t error_state; /* Current connectivity state */ |
387 | struct device dev; /* Generic device interface */ | |
1da177e4 | 388 | |
0aa0f5d1 | 389 | int cfg_size; /* Size of config space */ |
1da177e4 LT |
390 | |
391 | /* | |
392 | * Instead of touching interrupt line and base address registers | |
393 | * directly, use the values stored here. They might be different! | |
394 | */ | |
395 | unsigned int irq; | |
396 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
397 | ||
0aa0f5d1 BH |
398 | bool match_driver; /* Skip attaching driver */ |
399 | ||
400 | unsigned int transparent:1; /* Subtractive decode bridge */ | |
51c48b31 BH |
401 | unsigned int io_window:1; /* Bridge has I/O window */ |
402 | unsigned int pref_window:1; /* Bridge has pref mem window */ | |
403 | unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ | |
0aa0f5d1 BH |
404 | unsigned int multifunction:1; /* Multi-function device */ |
405 | ||
0aa0f5d1 BH |
406 | unsigned int is_busmaster:1; /* Is busmaster */ |
407 | unsigned int no_msi:1; /* May not use MSI */ | |
f6b6aefe | 408 | unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ |
0aa0f5d1 BH |
409 | unsigned int block_cfg_access:1; /* Config space access blocked */ |
410 | unsigned int broken_parity_status:1; /* Generates false positive parity */ | |
411 | unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ | |
f7625980 | 412 | unsigned int msi_enabled:1; |
99dc804d | 413 | unsigned int msix_enabled:1; |
0aa0f5d1 BH |
414 | unsigned int ari_enabled:1; /* ARI forwarding */ |
415 | unsigned int ats_enabled:1; /* Address Translation Svc */ | |
a4f4fa68 JPB |
416 | unsigned int pasid_enabled:1; /* Process Address Space ID */ |
417 | unsigned int pri_enabled:1; /* Page Request Interface */ | |
9ac7849e | 418 | unsigned int is_managed:1; |
0aa0f5d1 | 419 | unsigned int needs_freset:1; /* Requires fundamental reset */ |
aa8c6c93 | 420 | unsigned int state_saved:1; |
d1b054da | 421 | unsigned int is_physfn:1; |
dd7cc44d | 422 | unsigned int is_virtfn:1; |
711d5779 | 423 | unsigned int reset_fn:1; |
0aa0f5d1 | 424 | unsigned int is_hotplug_bridge:1; |
b03799b0 | 425 | unsigned int shpc_managed:1; /* SHPC owned by shpchp */ |
0aa0f5d1 | 426 | unsigned int is_thunderbolt:1; /* Thunderbolt controller */ |
617654aa MW |
427 | /* |
428 | * Devices marked being untrusted are the ones that can potentially | |
429 | * execute DMA attacks and similar. They are typically connected | |
430 | * through external ports such as Thunderbolt but not limited to | |
431 | * that. When an IOMMU is enabled they should be getting full | |
432 | * mappings to make sure they cannot access arbitrary memory. | |
433 | */ | |
434 | unsigned int untrusted:1; | |
99b50be9 RJ |
435 | /* |
436 | * Info from the platform, e.g., ACPI or device tree, may mark a | |
437 | * device as "external-facing". An external-facing device is | |
438 | * itself internal but devices downstream from it are external. | |
439 | */ | |
440 | unsigned int external_facing:1; | |
0aa0f5d1 BH |
441 | unsigned int broken_intx_masking:1; /* INTx masking can't be used */ |
442 | unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ | |
cffe0a2b | 443 | unsigned int irq_managed:1; |
0aa0f5d1 BH |
444 | unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ |
445 | unsigned int is_probed:1; /* Device probing in progress */ | |
f0157160 | 446 | unsigned int link_active_reporting:1;/* Device capable of reporting link active */ |
aff68a5a | 447 | unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ |
ba698ad4 | 448 | pci_dev_flags_t dev_flags; |
bae94d02 | 449 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 450 | |
0aa0f5d1 | 451 | u32 saved_config_space[16]; /* Config space saved at suspend time */ |
41017f0c | 452 | struct hlist_head saved_cap_space; |
0aa0f5d1 BH |
453 | struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ |
454 | int rom_attr_enabled; /* Display of ROM attribute enabled? */ | |
1da177e4 | 455 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
45aec1ae | 456 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
9bb04a0c | 457 | |
d22b3621 BH |
458 | #ifdef CONFIG_HOTPLUG_PCI_PCIE |
459 | unsigned int broken_cmd_compl:1; /* No compl for some cmds */ | |
460 | #endif | |
9bb04a0c JY |
461 | #ifdef CONFIG_PCIE_PTM |
462 | unsigned int ptm_root:1; | |
463 | unsigned int ptm_enabled:1; | |
8b2ec318 | 464 | u8 ptm_granularity; |
9bb04a0c | 465 | #endif |
ded86d8d | 466 | #ifdef CONFIG_PCI_MSI |
1c51b50c | 467 | const struct attribute_group **msi_irq_groups; |
ded86d8d | 468 | #endif |
94e61088 | 469 | struct pci_vpd *vpd; |
be06c1b4 BH |
470 | #ifdef CONFIG_PCIE_DPC |
471 | u16 dpc_cap; | |
472 | unsigned int dpc_rp_extensions:1; | |
473 | u8 dpc_rp_log_size; | |
474 | #endif | |
466b3ddf | 475 | #ifdef CONFIG_PCI_ATS |
dd7cc44d | 476 | union { |
0aa0f5d1 BH |
477 | struct pci_sriov *sriov; /* PF: SR-IOV info */ |
478 | struct pci_dev *physfn; /* VF: related PF */ | |
dd7cc44d | 479 | }; |
67930995 BH |
480 | u16 ats_cap; /* ATS Capability offset */ |
481 | u8 ats_stu; /* ATS Smallest Translation Unit */ | |
4ebeb1ec CT |
482 | #endif |
483 | #ifdef CONFIG_PCI_PRI | |
c065190b | 484 | u16 pri_cap; /* PRI Capability offset */ |
4ebeb1ec | 485 | u32 pri_reqs_alloc; /* Number of PRI requests allocated */ |
e5adf79a | 486 | unsigned int pasid_required:1; /* PRG Response PASID Required */ |
4ebeb1ec CT |
487 | #endif |
488 | #ifdef CONFIG_PCI_PASID | |
751035b8 | 489 | u16 pasid_cap; /* PASID Capability offset */ |
4ebeb1ec | 490 | u16 pasid_features; |
52916982 LG |
491 | #endif |
492 | #ifdef CONFIG_PCI_P2PDMA | |
493 | struct pci_p2pdma *p2pdma; | |
d1b054da | 494 | #endif |
52fbf5bd | 495 | u16 acs_cap; /* ACS Capability offset */ |
0aa0f5d1 BH |
496 | phys_addr_t rom; /* Physical address if not from BAR */ |
497 | size_t romlen; /* Length if not from BAR */ | |
498 | char *driver_override; /* Driver name to force a match */ | |
89ee9f76 | 499 | |
0aa0f5d1 | 500 | unsigned long priv_flags; /* Private flags for the PCI driver */ |
1da177e4 LT |
501 | }; |
502 | ||
dda56549 Y |
503 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
504 | { | |
505 | #ifdef CONFIG_PCI_IOV | |
506 | if (dev->is_virtfn) | |
507 | dev = dev->physfn; | |
508 | #endif | |
dda56549 Y |
509 | return dev; |
510 | } | |
511 | ||
3c6e6ae7 | 512 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 513 | |
1da177e4 LT |
514 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
515 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
516 | ||
a7369f1f LV |
517 | static inline int pci_channel_offline(struct pci_dev *pdev) |
518 | { | |
519 | return (pdev->error_state != pci_channel_io_normal); | |
520 | } | |
521 | ||
5a21d70d | 522 | struct pci_host_bridge { |
0aa0f5d1 BH |
523 | struct device dev; |
524 | struct pci_bus *bus; /* Root bus */ | |
525 | struct pci_ops *ops; | |
526 | void *sysdata; | |
527 | int busnr; | |
14d76b68 | 528 | struct list_head windows; /* resource_entry */ |
e80a91ad | 529 | struct list_head dma_ranges; /* dma ranges resource list */ |
0aa0f5d1 | 530 | u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ |
3aa8a41e | 531 | int (*map_irq)(const struct pci_dev *, u8, u8); |
4fa2649a | 532 | void (*release_fn)(struct pci_host_bridge *); |
0aa0f5d1 | 533 | void *release_data; |
37d6a0a6 | 534 | struct msi_controller *msi; |
0aa0f5d1 BH |
535 | unsigned int ignore_reset_delay:1; /* For entire hierarchy */ |
536 | unsigned int no_ext_tags:1; /* No Extended Tags */ | |
02bfeb48 | 537 | unsigned int native_aer:1; /* OS may use PCIe AER */ |
9310f0dc | 538 | unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ |
1df81a6d | 539 | unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ |
02bfeb48 | 540 | unsigned int native_pme:1; /* OS may use PCIe PME */ |
af8bb9f8 | 541 | unsigned int native_ltr:1; /* OS may use PCIe LTR */ |
ac1c8e35 | 542 | unsigned int native_dpc:1; /* OS may use PCIe DPC */ |
a78cf965 | 543 | unsigned int preserve_config:1; /* Preserve FW resource setup */ |
2c8d5a2d | 544 | unsigned int size_windows:1; /* Enable root bus sizing */ |
a78cf965 | 545 | |
7c7a0e94 GP |
546 | /* Resource alignment requirements */ |
547 | resource_size_t (*align_resource)(struct pci_dev *dev, | |
548 | const struct resource *res, | |
549 | resource_size_t start, | |
550 | resource_size_t size, | |
551 | resource_size_t align); | |
914a1951 | 552 | unsigned long private[] ____cacheline_aligned; |
5a21d70d | 553 | }; |
41017f0c | 554 | |
7b543663 | 555 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
7c7a0e94 | 556 | |
59094065 TR |
557 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
558 | { | |
559 | return (void *)bridge->private; | |
560 | } | |
561 | ||
562 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) | |
563 | { | |
564 | return container_of(priv, struct pci_host_bridge, private); | |
565 | } | |
566 | ||
a52d1443 | 567 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); |
5c3f18cc LP |
568 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
569 | size_t priv); | |
dff79b91 | 570 | void pci_free_host_bridge(struct pci_host_bridge *bridge); |
7c7a0e94 GP |
571 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
572 | ||
4fa2649a | 573 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
0aa0f5d1 BH |
574 | void (*release_fn)(struct pci_host_bridge *), |
575 | void *release_data); | |
7b543663 | 576 | |
6c0cc950 RW |
577 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
578 | ||
2fe2abf8 BH |
579 | /* |
580 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
581 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
582 | * buses below host bridges or subtractive decode bridges) go in the list. | |
583 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
584 | */ | |
585 | ||
586 | /* | |
587 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
588 | * and there's no way to program the bridge with the details of the window. | |
589 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
590 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
591 | */ | |
592 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
593 | ||
594 | struct pci_bus_resource { | |
0aa0f5d1 BH |
595 | struct list_head list; |
596 | struct resource *res; | |
597 | unsigned int flags; | |
2fe2abf8 | 598 | }; |
4352dfd5 GKH |
599 | |
600 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
601 | |
602 | struct pci_bus { | |
0aa0f5d1 BH |
603 | struct list_head node; /* Node in list of buses */ |
604 | struct pci_bus *parent; /* Parent bus this bridge is on */ | |
605 | struct list_head children; /* List of child buses */ | |
606 | struct list_head devices; /* List of devices on this bus */ | |
607 | struct pci_dev *self; /* Bridge device as seen by parent */ | |
608 | struct list_head slots; /* List of slots on this bus; | |
67546762 | 609 | protected by pci_slot_mutex */ |
2fe2abf8 | 610 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
0aa0f5d1 BH |
611 | struct list_head resources; /* Address space routed to this bus */ |
612 | struct resource busn_res; /* Bus numbers routed to this bus */ | |
1da177e4 | 613 | |
0aa0f5d1 | 614 | struct pci_ops *ops; /* Configuration access functions */ |
c2791b80 | 615 | struct msi_controller *msi; /* MSI controller */ |
0aa0f5d1 BH |
616 | void *sysdata; /* Hook for sys-specific extension */ |
617 | struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ | |
1da177e4 | 618 | |
0aa0f5d1 BH |
619 | unsigned char number; /* Bus number */ |
620 | unsigned char primary; /* Number of primary bridge */ | |
3749c51a MW |
621 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
622 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
623 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
624 | int domain_nr; | |
625 | #endif | |
1da177e4 LT |
626 | |
627 | char name[48]; | |
628 | ||
0aa0f5d1 BH |
629 | unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ |
630 | pci_bus_flags_t bus_flags; /* Inherited by child buses */ | |
1da177e4 | 631 | struct device *bridge; |
fd7d1ced | 632 | struct device dev; |
0aa0f5d1 BH |
633 | struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ |
634 | struct bin_attribute *legacy_mem; /* Legacy mem */ | |
cc74d96f | 635 | unsigned int is_added:1; |
1da177e4 LT |
636 | }; |
637 | ||
fd7d1ced | 638 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 639 | |
4e544bac HK |
640 | static inline u16 pci_dev_id(struct pci_dev *dev) |
641 | { | |
642 | return PCI_DEVID(dev->bus->number, dev->devfn); | |
643 | } | |
644 | ||
79af72d7 | 645 | /* |
f7625980 | 646 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 647 | * false otherwise |
77a0dfcd BH |
648 | * |
649 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
650 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
651 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
652 | */ |
653 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
654 | { | |
655 | return !(pbus->parent); | |
656 | } | |
657 | ||
1c86438c YW |
658 | /** |
659 | * pci_is_bridge - check if the PCI device is a bridge | |
660 | * @dev: PCI device | |
661 | * | |
662 | * Return true if the PCI device is bridge whether it has subordinate | |
663 | * or not. | |
664 | */ | |
665 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
666 | { | |
667 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
668 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
669 | } | |
670 | ||
24a0c654 AS |
671 | #define for_each_pci_bridge(dev, bus) \ |
672 | list_for_each_entry(dev, &bus->devices, bus_list) \ | |
673 | if (!pci_is_bridge(dev)) {} else | |
674 | ||
c6bde215 BH |
675 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
676 | { | |
677 | dev = pci_physfn(dev); | |
678 | if (pci_is_root_bus(dev->bus)) | |
679 | return NULL; | |
680 | ||
681 | return dev->bus->self; | |
682 | } | |
683 | ||
16cf0ebc RW |
684 | #ifdef CONFIG_PCI_MSI |
685 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
686 | { | |
687 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
688 | } | |
689 | #else | |
690 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
691 | #endif | |
692 | ||
0aa0f5d1 | 693 | /* Error values that may be returned by PCI functions */ |
1da177e4 LT |
694 | #define PCIBIOS_SUCCESSFUL 0x00 |
695 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
696 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
697 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
698 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
699 | #define PCIBIOS_SET_FAILED 0x88 | |
700 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
701 | ||
0aa0f5d1 | 702 | /* Translate above to generic errno for passing back through non-PCI code */ |
a6961651 AW |
703 | static inline int pcibios_err_to_errno(int err) |
704 | { | |
705 | if (err <= PCIBIOS_SUCCESSFUL) | |
706 | return err; /* Assume already errno */ | |
707 | ||
708 | switch (err) { | |
709 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
710 | return -ENOENT; | |
711 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 712 | return -ENOTTY; |
a6961651 AW |
713 | case PCIBIOS_DEVICE_NOT_FOUND: |
714 | return -ENODEV; | |
715 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
716 | return -EFAULT; | |
717 | case PCIBIOS_SET_FAILED: | |
718 | return -EIO; | |
719 | case PCIBIOS_BUFFER_TOO_SMALL: | |
720 | return -ENOSPC; | |
721 | } | |
722 | ||
d97ffe23 | 723 | return -ERANGE; |
a6961651 AW |
724 | } |
725 | ||
1da177e4 LT |
726 | /* Low-level architecture-dependent routines */ |
727 | ||
728 | struct pci_ops { | |
057bd2e0 TR |
729 | int (*add_bus)(struct pci_bus *bus); |
730 | void (*remove_bus)(struct pci_bus *bus); | |
1f94a94f | 731 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
732 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
733 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
734 | }; | |
735 | ||
b6ce068a MW |
736 | /* |
737 | * ACPI needs to be able to access PCI config space before we've done a | |
738 | * PCI bus scan and created pci_bus structures. | |
739 | */ | |
f39d5b72 BH |
740 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
741 | int reg, int len, u32 *val); | |
742 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
743 | int reg, int len, u32 val); | |
1da177e4 | 744 | |
8e639079 | 745 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
3a9ad0b4 YL |
746 | typedef u64 pci_bus_addr_t; |
747 | #else | |
748 | typedef u32 pci_bus_addr_t; | |
749 | #endif | |
750 | ||
1da177e4 | 751 | struct pci_bus_region { |
0aa0f5d1 BH |
752 | pci_bus_addr_t start; |
753 | pci_bus_addr_t end; | |
1da177e4 LT |
754 | }; |
755 | ||
756 | struct pci_dynids { | |
0aa0f5d1 BH |
757 | spinlock_t lock; /* Protects list, index */ |
758 | struct list_head list; /* For IDs added at runtime */ | |
1da177e4 LT |
759 | }; |
760 | ||
f7625980 BH |
761 | |
762 | /* | |
763 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
764 | * a set of callbacks in struct pci_error_handlers, that device driver | |
765 | * will be notified of PCI bus errors, and will be driven to recovery | |
766 | * when an error occurs. | |
392a1ce7 | 767 | */ |
768 | ||
769 | typedef unsigned int __bitwise pci_ers_result_t; | |
770 | ||
771 | enum pci_ers_result { | |
0aa0f5d1 | 772 | /* No result/none/not supported in device driver */ |
392a1ce7 | 773 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
774 | ||
775 | /* Device driver can recover without slot reset */ | |
776 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
777 | ||
0aa0f5d1 | 778 | /* Device driver wants slot to be reset */ |
392a1ce7 | 779 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
780 | ||
781 | /* Device has completely failed, is unrecoverable */ | |
782 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
783 | ||
784 | /* Device driver is fully recovered and operational */ | |
785 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
786 | |
787 | /* No AER capabilities registered for the driver */ | |
788 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 | 789 | }; |
790 | ||
791 | /* PCI bus error event callbacks */ | |
05cca6e5 | 792 | struct pci_error_handlers { |
392a1ce7 | 793 | /* PCI bus error detected on this device */ |
794 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
16d79cd4 | 795 | pci_channel_state_t error); |
392a1ce7 | 796 | |
797 | /* MMIO has been re-enabled, but not DMA */ | |
798 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
799 | ||
392a1ce7 | 800 | /* PCI slot has been reset */ |
801 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
802 | ||
3ebe7f9f | 803 | /* PCI function reset prepare or completed */ |
775755ed CH |
804 | void (*reset_prepare)(struct pci_dev *dev); |
805 | void (*reset_done)(struct pci_dev *dev); | |
3ebe7f9f | 806 | |
392a1ce7 | 807 | /* Device driver may resume normal operations */ |
808 | void (*resume)(struct pci_dev *dev); | |
809 | }; | |
810 | ||
392a1ce7 | 811 | |
1da177e4 | 812 | struct module; |
229b4e07 CD |
813 | |
814 | /** | |
815 | * struct pci_driver - PCI driver structure | |
816 | * @node: List of driver structures. | |
817 | * @name: Driver name. | |
818 | * @id_table: Pointer to table of device IDs the driver is | |
819 | * interested in. Most drivers should export this | |
820 | * table using MODULE_DEVICE_TABLE(pci,...). | |
821 | * @probe: This probing function gets called (during execution | |
822 | * of pci_register_driver() for already existing | |
823 | * devices or later if a new device gets inserted) for | |
824 | * all PCI devices which match the ID table and are not | |
825 | * "owned" by the other drivers yet. This function gets | |
826 | * passed a "struct pci_dev \*" for each device whose | |
827 | * entry in the ID table matches the device. The probe | |
828 | * function returns zero when the driver chooses to | |
829 | * take "ownership" of the device or an error code | |
830 | * (negative number) otherwise. | |
831 | * The probe function always gets called from process | |
832 | * context, so it can sleep. | |
833 | * @remove: The remove() function gets called whenever a device | |
834 | * being handled by this driver is removed (either during | |
835 | * deregistration of the driver or when it's manually | |
836 | * pulled out of a hot-pluggable slot). | |
837 | * The remove function always gets called from process | |
838 | * context, so it can sleep. | |
839 | * @suspend: Put device into low power state. | |
229b4e07 | 840 | * @resume: Wake device from low power state. |
151f4e2b | 841 | * (Please see Documentation/power/pci.rst for descriptions |
229b4e07 CD |
842 | * of PCI Power Management and the related functions.) |
843 | * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). | |
844 | * Intended to stop any idling DMA operations. | |
845 | * Useful for enabling wake-on-lan (NIC) or changing | |
846 | * the power state of a device before reboot. | |
847 | * e.g. drivers/net/e100.c. | |
848 | * @sriov_configure: Optional driver callback to allow configuration of | |
849 | * number of VFs to enable via sysfs "sriov_numvfs" file. | |
850 | * @err_handler: See Documentation/PCI/pci-error-recovery.rst | |
851 | * @groups: Sysfs attribute groups. | |
852 | * @driver: Driver model structure. | |
853 | * @dynids: List of dynamically added device IDs. | |
854 | */ | |
1da177e4 | 855 | struct pci_driver { |
0aa0f5d1 BH |
856 | struct list_head node; |
857 | const char *name; | |
858 | const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ | |
859 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
860 | void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
861 | int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
7cb30264 BY |
862 | int (*resume)(struct pci_dev *dev); /* Device woken up */ |
863 | void (*shutdown)(struct pci_dev *dev); | |
864 | int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ | |
49453028 | 865 | const struct pci_error_handlers *err_handler; |
92d50fc1 | 866 | const struct attribute_group **groups; |
1da177e4 | 867 | struct device_driver driver; |
0aa0f5d1 | 868 | struct pci_dynids dynids; |
1da177e4 LT |
869 | }; |
870 | ||
05cca6e5 | 871 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 LT |
872 | |
873 | /** | |
0aa0f5d1 | 874 | * PCI_DEVICE - macro used to describe a specific PCI device |
1da177e4 LT |
875 | * @vend: the 16 bit PCI Vendor ID |
876 | * @dev: the 16 bit PCI Device ID | |
877 | * | |
878 | * This macro is used to create a struct pci_device_id that matches a | |
879 | * specific device. The subvendor and subdevice fields will be set to | |
880 | * PCI_ANY_ID. | |
881 | */ | |
882 | #define PCI_DEVICE(vend,dev) \ | |
883 | .vendor = (vend), .device = (dev), \ | |
884 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
885 | ||
3d567e0e | 886 | /** |
0aa0f5d1 | 887 | * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem |
3d567e0e NNS |
888 | * @vend: the 16 bit PCI Vendor ID |
889 | * @dev: the 16 bit PCI Device ID | |
890 | * @subvend: the 16 bit PCI Subvendor ID | |
891 | * @subdev: the 16 bit PCI Subdevice ID | |
892 | * | |
893 | * This macro is used to create a struct pci_device_id that matches a | |
894 | * specific device with subsystem information. | |
895 | */ | |
896 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
897 | .vendor = (vend), .device = (dev), \ | |
898 | .subvendor = (subvend), .subdevice = (subdev) | |
899 | ||
1da177e4 | 900 | /** |
0aa0f5d1 | 901 | * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class |
1da177e4 LT |
902 | * @dev_class: the class, subclass, prog-if triple for this device |
903 | * @dev_class_mask: the class mask for this device | |
904 | * | |
905 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 906 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
907 | * fields will be set to PCI_ANY_ID. |
908 | */ | |
909 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
910 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
911 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
912 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
913 | ||
1597cacb | 914 | /** |
0aa0f5d1 | 915 | * PCI_VDEVICE - macro used to describe a specific PCI device in short form |
c1309040 MR |
916 | * @vend: the vendor name |
917 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
918 | * |
919 | * This macro is used to create a struct pci_device_id that matches a | |
920 | * specific PCI device. The subvendor, and subdevice fields will be set | |
921 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
922 | * private data. | |
923 | */ | |
c1309040 MR |
924 | #define PCI_VDEVICE(vend, dev) \ |
925 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
926 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 927 | |
b72ae8ca AS |
928 | /** |
929 | * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form | |
930 | * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) | |
931 | * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) | |
932 | * @data: the driver data to be filled | |
933 | * | |
934 | * This macro is used to create a struct pci_device_id that matches a | |
935 | * specific PCI device. The subvendor, and subdevice fields will be set | |
936 | * to PCI_ANY_ID. | |
937 | */ | |
938 | #define PCI_DEVICE_DATA(vend, dev, data) \ | |
939 | .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ | |
940 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ | |
941 | .driver_data = (kernel_ulong_t)(data) | |
942 | ||
5bbe029f | 943 | enum { |
0aa0f5d1 BH |
944 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ |
945 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ | |
946 | PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ | |
947 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ | |
948 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ | |
5bbe029f | 949 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
0aa0f5d1 | 950 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ |
5bbe029f BH |
951 | }; |
952 | ||
0d8006dd HX |
953 | #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ |
954 | #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ | |
955 | #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ | |
956 | #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ | |
957 | ||
0aa0f5d1 | 958 | /* These external functions are only available when PCI support is enabled */ |
1da177e4 LT |
959 | #ifdef CONFIG_PCI |
960 | ||
5bbe029f BH |
961 | extern unsigned int pci_flags; |
962 | ||
963 | static inline void pci_set_flags(int flags) { pci_flags = flags; } | |
964 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } | |
965 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } | |
966 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } | |
967 | ||
a58674ff | 968 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
969 | |
970 | enum pcie_bus_config_types { | |
0aa0f5d1 BH |
971 | PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ |
972 | PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ | |
973 | PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ | |
974 | PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ | |
975 | PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ | |
b03e7495 JM |
976 | }; |
977 | ||
978 | extern enum pcie_bus_config_types pcie_bus_config; | |
979 | ||
1da177e4 LT |
980 | extern struct bus_type pci_bus_type; |
981 | ||
f7625980 BH |
982 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
983 | * code, or PCI core code. */ | |
0aa0f5d1 | 984 | extern struct list_head pci_root_buses; /* List of all known PCI buses */ |
f7625980 | 985 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 986 | int no_pci_devices(void); |
1da177e4 | 987 | |
3c449ed0 | 988 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
7b77061f | 989 | void pcibios_bus_add_device(struct pci_dev *pdev); |
10a95747 JL |
990 | void pcibios_add_bus(struct pci_bus *bus); |
991 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 992 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 993 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 994 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 995 | char *pcibios_setup(char *str); |
1da177e4 LT |
996 | |
997 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 998 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 999 | resource_size_t, |
e31dd6e4 | 1000 | resource_size_t); |
1da177e4 | 1001 | |
d1bbf38a | 1002 | /* Weak but can be overridden by arch */ |
2d1c8618 BH |
1003 | void pci_fixup_cardbus(struct pci_bus *); |
1004 | ||
1da177e4 LT |
1005 | /* Generic PCI functions used internally */ |
1006 | ||
fc279850 | 1007 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 1008 | struct resource *res); |
fc279850 | 1009 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 1010 | struct pci_bus_region *region); |
d1fd4fb6 | 1011 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 1012 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 1013 | void pci_bus_add_devices(const struct pci_bus *bus); |
de4b2f76 | 1014 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
1015 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1016 | struct pci_ops *ops, void *sysdata, | |
1017 | struct list_head *resources); | |
49b8e3f3 | 1018 | int pci_host_probe(struct pci_host_bridge *bridge); |
98a35831 YL |
1019 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
1020 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
1021 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 1022 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
0aa0f5d1 BH |
1023 | struct pci_ops *ops, void *sysdata, |
1024 | struct list_head *resources); | |
1228c4b6 | 1025 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); |
05cca6e5 GKH |
1026 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
1027 | int busnr); | |
f46753c5 | 1028 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
1029 | const char *name, |
1030 | struct hotplug_slot *hotplug); | |
f46753c5 | 1031 | void pci_destroy_slot(struct pci_slot *slot); |
017ffe64 YW |
1032 | #ifdef CONFIG_SYSFS |
1033 | void pci_dev_assign_slot(struct pci_dev *dev); | |
1034 | #else | |
1035 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } | |
1036 | #endif | |
1da177e4 | 1037 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 1038 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 1039 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 1040 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 1041 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 1042 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
1043 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
1044 | struct resource *res); | |
3df425f3 | 1045 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 1046 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 1047 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
1048 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
1049 | void pci_dev_put(struct pci_dev *dev); | |
1050 | void pci_remove_bus(struct pci_bus *b); | |
1051 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 1052 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
1053 | void pci_stop_root_bus(struct pci_bus *bus); |
1054 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 1055 | void pci_setup_cardbus(struct pci_bus *bus); |
d366d28c | 1056 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
f39d5b72 | 1057 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
1058 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
1059 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
1da177e4 LT |
1060 | |
1061 | /* Generic PCI functions exported to card drivers */ | |
1062 | ||
05cca6e5 GKH |
1063 | int pci_find_capability(struct pci_dev *dev, int cap); |
1064 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
1065 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
44a9a36f | 1066 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
05cca6e5 GKH |
1067 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
1068 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 1069 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 1070 | |
70c0923b JK |
1071 | u64 pci_get_dsn(struct pci_dev *dev); |
1072 | ||
d42552c3 | 1073 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
0aa0f5d1 | 1074 | struct pci_dev *from); |
05cca6e5 | 1075 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
0aa0f5d1 BH |
1076 | unsigned int ss_vendor, unsigned int ss_device, |
1077 | struct pci_dev *from); | |
05cca6e5 | 1078 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
1079 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
1080 | unsigned int devfn); | |
05cca6e5 | 1081 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
1082 | int pci_dev_present(const struct pci_device_id *ids); |
1083 | ||
05cca6e5 GKH |
1084 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
1085 | int where, u8 *val); | |
1086 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
1087 | int where, u16 *val); | |
1088 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1089 | int where, u32 *val); | |
1090 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
1091 | int where, u8 val); | |
1092 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
1093 | int where, u16 val); | |
1094 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1095 | int where, u32 val); | |
1f94a94f RH |
1096 | |
1097 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
1098 | int where, int size, u32 *val); | |
1099 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
1100 | int where, int size, u32 val); | |
1101 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
1102 | int where, int size, u32 *val); | |
1103 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
1104 | int where, int size, u32 val); | |
1105 | ||
a72b46c3 | 1106 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 1107 | |
d3881e50 KB |
1108 | int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); |
1109 | int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); | |
1110 | int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); | |
1111 | int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); | |
1112 | int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); | |
1113 | int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); | |
1da177e4 | 1114 | |
8c0d3a02 JL |
1115 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
1116 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
1117 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
1118 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
1119 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
1120 | u16 clear, u16 set); | |
1121 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
1122 | u32 clear, u32 set); | |
1123 | ||
1124 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
1125 | u16 set) | |
1126 | { | |
1127 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
1128 | } | |
1129 | ||
1130 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
1131 | u32 set) | |
1132 | { | |
1133 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
1134 | } | |
1135 | ||
1136 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
1137 | u16 clear) | |
1138 | { | |
1139 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
1140 | } | |
1141 | ||
1142 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
1143 | u32 clear) | |
1144 | { | |
1145 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
1146 | } | |
1147 | ||
0aa0f5d1 | 1148 | /* User-space driven config access */ |
c63587d7 AW |
1149 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
1150 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
1151 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
1152 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
1153 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
1154 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
1155 | ||
4a7fb636 | 1156 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
1157 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
1158 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 1159 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
1160 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
1161 | void pcim_pin_device(struct pci_dev *pdev); | |
1162 | ||
99b3c58f PG |
1163 | static inline bool pci_intx_mask_supported(struct pci_dev *pdev) |
1164 | { | |
1165 | /* | |
1166 | * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is | |
1167 | * writable and no quirk has marked the feature broken. | |
1168 | */ | |
1169 | return !pdev->broken_intx_masking; | |
1170 | } | |
1171 | ||
296ccb08 YS |
1172 | static inline int pci_is_enabled(struct pci_dev *pdev) |
1173 | { | |
1174 | return (atomic_read(&pdev->enable_cnt) > 0); | |
1175 | } | |
1176 | ||
9ac7849e TH |
1177 | static inline int pci_is_managed(struct pci_dev *pdev) |
1178 | { | |
1179 | return pdev->is_managed; | |
1180 | } | |
1181 | ||
1da177e4 | 1182 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
1183 | |
1184 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 1185 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 1186 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 1187 | |
f7bdd12d | 1188 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 1189 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 1190 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 1191 | int __must_check pci_set_mwi(struct pci_dev *dev); |
fc0f9f4d | 1192 | int __must_check pcim_set_mwi(struct pci_dev *dev); |
694625c0 | 1193 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 1194 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 1195 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
1196 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
1197 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
157e876f | 1198 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 1199 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
1200 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
1201 | int pcix_get_mmrbc(struct pci_dev *dev); | |
1202 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 1203 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 1204 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
1205 | int pcie_get_mps(struct pci_dev *dev); |
1206 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
6db79a88 TG |
1207 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, |
1208 | enum pci_bus_speed *speed, | |
1209 | enum pcie_link_width *width); | |
9e506a7b | 1210 | void pcie_print_link_status(struct pci_dev *dev); |
2d2917f7 | 1211 | bool pcie_has_flr(struct pci_dev *dev); |
91295d79 | 1212 | int pcie_flr(struct pci_dev *dev); |
a96d627a | 1213 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 1214 | int pci_reset_function(struct pci_dev *dev); |
a477b9cd | 1215 | int pci_reset_function_locked(struct pci_dev *dev); |
61cf16d8 | 1216 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 1217 | int pci_probe_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 1218 | int pci_probe_reset_bus(struct pci_bus *bus); |
c6a44ba9 | 1219 | int pci_reset_bus(struct pci_dev *dev); |
9e33002f GS |
1220 | void pci_reset_secondary_bus(struct pci_dev *dev); |
1221 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
14add80b | 1222 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1223 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1224 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
8bb705e3 CK |
1225 | void pci_release_resource(struct pci_dev *dev, int resno); |
1226 | int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); | |
c87deff7 | 1227 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1228 | bool pci_device_is_present(struct pci_dev *pdev); |
08249651 | 1229 | void pci_ignore_hotplug(struct pci_dev *dev); |
2856ba60 | 1230 | struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); |
ec5d9e87 | 1231 | int pci_status_get_and_clear_errors(struct pci_dev *pdev); |
1da177e4 | 1232 | |
704e8953 CH |
1233 | int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, |
1234 | irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, | |
1235 | const char *fmt, ...); | |
1236 | void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); | |
1237 | ||
1da177e4 | 1238 | /* ROM control related routines */ |
e416de5e AC |
1239 | int pci_enable_rom(struct pci_dev *pdev); |
1240 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1241 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1242 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
1da177e4 LT |
1243 | |
1244 | /* Power management related routines */ | |
1245 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1246 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1247 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1248 | int pci_load_saved_state(struct pci_dev *dev, |
1249 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1250 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1251 | struct pci_saved_state **state); | |
fd0f7f73 AW |
1252 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
1253 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, | |
1254 | u16 cap); | |
1255 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); | |
1256 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, | |
1257 | u16 cap, unsigned int size); | |
d6aa37cd | 1258 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1259 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1260 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1261 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1262 | void pci_pme_active(struct pci_dev *dev, bool enable); |
0847684c | 1263 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 1264 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1265 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1266 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1267 | bool pci_dev_run_wake(struct pci_dev *dev); |
9d26d3a8 MW |
1268 | void pci_d3cold_enable(struct pci_dev *dev); |
1269 | void pci_d3cold_disable(struct pci_dev *dev); | |
a99b646a | 1270 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); |
2a4d2c42 LW |
1271 | void pci_wakeup_bus(struct pci_bus *bus); |
1272 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); | |
1da177e4 | 1273 | |
bb209c82 BH |
1274 | /* For use by arch with custom probe code */ |
1275 | void set_pcie_port_type(struct pci_dev *pdev); | |
1276 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1277 | ||
ce5ccdef | 1278 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 1279 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
2f320521 | 1280 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1281 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1282 | void pci_lock_rescan_remove(void); |
1283 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1284 | |
0aa0f5d1 | 1285 | /* Vital Product Data routines */ |
287d19ce SH |
1286 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1287 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
cb92148b | 1288 | int pci_set_vpd_size(struct pci_dev *dev, size_t len); |
287d19ce | 1289 | |
1da177e4 | 1290 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1291 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1292 | void pci_bus_assign_resources(const struct pci_bus *bus); |
765bf9b7 | 1293 | void pci_bus_claim_resources(struct pci_bus *bus); |
1da177e4 LT |
1294 | void pci_bus_size_bridges(struct pci_bus *bus); |
1295 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1296 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1297 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1298 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1299 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1300 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
8bb705e3 | 1301 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); |
1da177e4 | 1302 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1303 | int pci_enable_resources(struct pci_dev *, int mask); |
47a650f2 | 1304 | void pci_assign_irq(struct pci_dev *dev); |
afd29f90 | 1305 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
1da177e4 | 1306 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1307 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1308 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1309 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1310 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 1311 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1312 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1313 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1314 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1315 | |
1316 | /* drivers/pci/bus.c */ | |
45ca9e97 | 1317 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1318 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1319 | resource_size_t offset); | |
45ca9e97 | 1320 | void pci_free_resource_list(struct list_head *resources); |
950334bc BH |
1321 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
1322 | unsigned int flags); | |
2fe2abf8 BH |
1323 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1324 | void pci_bus_remove_resources(struct pci_bus *bus); | |
950334bc BH |
1325 | int devm_request_pci_bus_resources(struct device *dev, |
1326 | struct list_head *resources); | |
2fe2abf8 | 1327 | |
bfc45606 DD |
1328 | /* Temporary until new and working PCI SBR API in place */ |
1329 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); | |
1330 | ||
89a74ecc | 1331 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1332 | for (i = 0; \ |
1333 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1334 | i++) | |
89a74ecc | 1335 | |
4a7fb636 AM |
1336 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1337 | struct resource *res, resource_size_t size, | |
1338 | resource_size_t align, resource_size_t min, | |
664c2848 | 1339 | unsigned long type_mask, |
3b7a17fc DB |
1340 | resource_size_t (*alignf)(void *, |
1341 | const struct resource *, | |
b26b2d49 DB |
1342 | resource_size_t, |
1343 | resource_size_t), | |
4a7fb636 | 1344 | void *alignf_data); |
1da177e4 | 1345 | |
8b921acf | 1346 | |
fcfaab30 GP |
1347 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
1348 | resource_size_t size); | |
c5076cfe TN |
1349 | unsigned long pci_address_to_pio(phys_addr_t addr); |
1350 | phys_addr_t pci_pio_to_address(unsigned long pio); | |
8b921acf | 1351 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
a5fb9fb0 SS |
1352 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, |
1353 | phys_addr_t phys_addr); | |
4d3f1384 | 1354 | void pci_unmap_iospace(struct resource *res); |
490cb6dd LP |
1355 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, |
1356 | resource_size_t offset, | |
1357 | resource_size_t size); | |
1358 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
1359 | struct resource *res); | |
8b921acf | 1360 | |
3a9ad0b4 | 1361 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
06cf56e4 BH |
1362 | { |
1363 | struct pci_bus_region region; | |
1364 | ||
1365 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1366 | return region.start; | |
1367 | } | |
1368 | ||
863b18f4 | 1369 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1370 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1371 | const char *mod_name); | |
bba81165 | 1372 | |
0aa0f5d1 | 1373 | /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ |
bba81165 AM |
1374 | #define pci_register_driver(driver) \ |
1375 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1376 | |
05cca6e5 | 1377 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1378 | |
1379 | /** | |
1380 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1381 | * @__pci_driver: pci_driver struct | |
1382 | * | |
1383 | * Helper macro for PCI drivers which do not do anything special in module | |
1384 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1385 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1386 | */ | |
1387 | #define module_pci_driver(__pci_driver) \ | |
0aa0f5d1 | 1388 | module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) |
aad4f400 | 1389 | |
b4eb6cdb PG |
1390 | /** |
1391 | * builtin_pci_driver() - Helper macro for registering a PCI driver | |
1392 | * @__pci_driver: pci_driver struct | |
1393 | * | |
1394 | * Helper macro for PCI drivers which do not do anything special in their | |
1395 | * init code. This eliminates a lot of boilerplate. Each driver may only | |
1396 | * use this macro once, and calling it replaces device_initcall(...) | |
1397 | */ | |
1398 | #define builtin_pci_driver(__pci_driver) \ | |
1399 | builtin_driver(__pci_driver, pci_register_driver) | |
1400 | ||
05cca6e5 | 1401 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1402 | int pci_add_dynid(struct pci_driver *drv, |
1403 | unsigned int vendor, unsigned int device, | |
1404 | unsigned int subvendor, unsigned int subdevice, | |
1405 | unsigned int class, unsigned int class_mask, | |
1406 | unsigned long driver_data); | |
05cca6e5 GKH |
1407 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1408 | struct pci_dev *dev); | |
1409 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1410 | int pass); | |
1da177e4 | 1411 | |
70298c6e | 1412 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1413 | void *userdata); |
ac7dc65a | 1414 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1415 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1416 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1417 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1418 | unsigned long type); | |
cecf4864 | 1419 | |
3448a19d DA |
1420 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1421 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1422 | ||
deb2d2ec | 1423 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1424 | unsigned int command_bits, u32 flags); |
fe537670 | 1425 | |
d7cc609f LG |
1426 | /* |
1427 | * Virtual interrupts allow for more interrupts to be allocated | |
1428 | * than the device has interrupts for. These are not programmed | |
1429 | * into the device's MSI-X table and must be handled by some | |
1430 | * other driver means. | |
1431 | */ | |
1432 | #define PCI_IRQ_VIRTUAL (1 << 4) | |
1433 | ||
4fe0d154 CH |
1434 | #define PCI_IRQ_ALL_TYPES \ |
1435 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) | |
aff17164 | 1436 | |
1da177e4 LT |
1437 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1438 | ||
1439 | #include <linux/dmapool.h> | |
1440 | ||
1441 | #define pci_pool dma_pool | |
1442 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
1443 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
1444 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
1445 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
01a7fd33 SS |
1446 | #define pci_pool_zalloc(pool, flags, handle) \ |
1447 | dma_pool_zalloc(pool, flags, handle) | |
1da177e4 LT |
1448 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
1449 | ||
1da177e4 | 1450 | struct msix_entry { |
0aa0f5d1 BH |
1451 | u32 vector; /* Kernel uses to write allocated vector */ |
1452 | u16 entry; /* Driver uses to specify entry, OS writes */ | |
1da177e4 LT |
1453 | }; |
1454 | ||
4c859804 BH |
1455 | #ifdef CONFIG_PCI_MSI |
1456 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 | 1457 | void pci_disable_msi(struct pci_dev *dev); |
4c859804 | 1458 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 | 1459 | void pci_disable_msix(struct pci_dev *dev); |
f39d5b72 BH |
1460 | void pci_restore_msi_state(struct pci_dev *dev); |
1461 | int pci_msi_enabled(void); | |
4fe03955 | 1462 | int pci_enable_msi(struct pci_dev *dev); |
4c859804 BH |
1463 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1464 | int minvec, int maxvec); | |
f7fc32cb AG |
1465 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1466 | struct msix_entry *entries, int nvec) | |
1467 | { | |
1468 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1469 | if (rc < 0) | |
1470 | return rc; | |
1471 | return 0; | |
1472 | } | |
402723ad CH |
1473 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1474 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1475 | struct irq_affinity *affd); |
402723ad | 1476 | |
aff17164 CH |
1477 | void pci_free_irq_vectors(struct pci_dev *dev); |
1478 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); | |
ee8d41e5 | 1479 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
aff17164 | 1480 | |
4c859804 | 1481 | #else |
2ee546c4 | 1482 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1483 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
1484 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
2ee546c4 | 1485 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
2ee546c4 BH |
1486 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1487 | static inline int pci_msi_enabled(void) { return 0; } | |
4fe03955 | 1488 | static inline int pci_enable_msi(struct pci_dev *dev) |
f7fc32cb | 1489 | { return -ENOSYS; } |
302a2523 | 1490 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
0aa0f5d1 | 1491 | struct msix_entry *entries, int minvec, int maxvec) |
2ee546c4 | 1492 | { return -ENOSYS; } |
f7fc32cb | 1493 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
0aa0f5d1 | 1494 | struct msix_entry *entries, int nvec) |
f7fc32cb | 1495 | { return -ENOSYS; } |
402723ad CH |
1496 | |
1497 | static inline int | |
1498 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1499 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1500 | struct irq_affinity *aff_desc) |
aff17164 | 1501 | { |
83b4605b CH |
1502 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) |
1503 | return 1; | |
1504 | return -ENOSPC; | |
aff17164 | 1505 | } |
402723ad | 1506 | |
aff17164 CH |
1507 | static inline void pci_free_irq_vectors(struct pci_dev *dev) |
1508 | { | |
1509 | } | |
1510 | ||
1511 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1512 | { | |
1513 | if (WARN_ON_ONCE(nr > 0)) | |
1514 | return -EINVAL; | |
1515 | return dev->irq; | |
1516 | } | |
ee8d41e5 TG |
1517 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
1518 | int vec) | |
1519 | { | |
1520 | return cpu_possible_mask; | |
1521 | } | |
1da177e4 LT |
1522 | #endif |
1523 | ||
0d58e6c1 PB |
1524 | /** |
1525 | * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq | |
1526 | * @d: the INTx IRQ domain | |
1527 | * @node: the DT node for the device whose interrupt we're translating | |
1528 | * @intspec: the interrupt specifier data from the DT | |
1529 | * @intsize: the number of entries in @intspec | |
1530 | * @out_hwirq: pointer at which to write the hwirq number | |
1531 | * @out_type: pointer at which to write the interrupt type | |
1532 | * | |
1533 | * Translate a PCI INTx interrupt number from device tree in the range 1-4, as | |
1534 | * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range | |
1535 | * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the | |
1536 | * INTx value to obtain the hwirq number. | |
1537 | * | |
1538 | * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. | |
1539 | */ | |
1540 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, | |
1541 | struct device_node *node, | |
1542 | const u32 *intspec, | |
1543 | unsigned int intsize, | |
1544 | unsigned long *out_hwirq, | |
1545 | unsigned int *out_type) | |
1546 | { | |
1547 | const u32 intx = intspec[0]; | |
1548 | ||
1549 | if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) | |
1550 | return -EINVAL; | |
1551 | ||
1552 | *out_hwirq = intx - PCI_INTERRUPT_INTA; | |
1553 | return 0; | |
1554 | } | |
1555 | ||
ab0724ff | 1556 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 | 1557 | extern bool pcie_ports_disabled; |
5352a44a | 1558 | extern bool pcie_ports_native; |
ab0724ff MT |
1559 | #else |
1560 | #define pcie_ports_disabled true | |
5352a44a | 1561 | #define pcie_ports_native false |
ab0724ff | 1562 | #endif |
415e12b2 | 1563 | |
aff5d055 HK |
1564 | #define PCIE_LINK_STATE_L0S BIT(0) |
1565 | #define PCIE_LINK_STATE_L1 BIT(1) | |
1566 | #define PCIE_LINK_STATE_CLKPM BIT(2) | |
1567 | #define PCIE_LINK_STATE_L1_1 BIT(3) | |
1568 | #define PCIE_LINK_STATE_L1_2 BIT(4) | |
1569 | #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) | |
1570 | #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) | |
7ce2e76a | 1571 | |
4c859804 | 1572 | #ifdef CONFIG_PCIEASPM |
7ce2e76a KW |
1573 | int pci_disable_link_state(struct pci_dev *pdev, int state); |
1574 | int pci_disable_link_state_locked(struct pci_dev *pdev, int state); | |
1575 | void pcie_no_aspm(void); | |
f39d5b72 | 1576 | bool pcie_aspm_support_enabled(void); |
accd2dd7 | 1577 | bool pcie_aspm_enabled(struct pci_dev *pdev); |
4c859804 | 1578 | #else |
7ce2e76a KW |
1579 | static inline int pci_disable_link_state(struct pci_dev *pdev, int state) |
1580 | { return 0; } | |
1581 | static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
1582 | { return 0; } | |
1583 | static inline void pcie_no_aspm(void) { } | |
4c859804 | 1584 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
accd2dd7 | 1585 | static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } |
3e1b1600 AP |
1586 | #endif |
1587 | ||
415e12b2 | 1588 | #ifdef CONFIG_PCIEAER |
415e12b2 RW |
1589 | bool pci_aer_available(void); |
1590 | #else | |
415e12b2 RW |
1591 | static inline bool pci_aer_available(void) { return false; } |
1592 | #endif | |
1593 | ||
cef74409 GK |
1594 | bool pci_ats_disabled(void); |
1595 | ||
f39d5b72 BH |
1596 | void pci_cfg_access_lock(struct pci_dev *dev); |
1597 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1598 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1599 | |
4352dfd5 GKH |
1600 | /* |
1601 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1602 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1603 | * configuration space. |
1604 | */ | |
32a2eea7 JG |
1605 | #ifdef CONFIG_PCI_DOMAINS |
1606 | extern int pci_domains_supported; | |
1607 | #else | |
1608 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1609 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1610 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
32a2eea7 | 1611 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1612 | |
670ba0c8 CM |
1613 | /* |
1614 | * Generic implementation for PCI domain support. If your | |
1615 | * architecture does not need custom management of PCI | |
1616 | * domains then this implementation will be used | |
1617 | */ | |
1618 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1619 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1620 | { | |
1621 | return bus->domain_nr; | |
1622 | } | |
2ab51dde TN |
1623 | #ifdef CONFIG_ACPI |
1624 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); | |
670ba0c8 | 1625 | #else |
2ab51dde TN |
1626 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
1627 | { return 0; } | |
1628 | #endif | |
9c7cb891 | 1629 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
670ba0c8 CM |
1630 | #endif |
1631 | ||
0aa0f5d1 | 1632 | /* Some architectures require additional setup to direct VGA traffic */ |
95a8b6ef | 1633 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
0aa0f5d1 | 1634 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1635 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1636 | |
be9d2e89 JT |
1637 | static inline int |
1638 | pci_request_io_regions(struct pci_dev *pdev, const char *name) | |
1639 | { | |
1640 | return pci_request_selected_regions(pdev, | |
1641 | pci_select_bars(pdev, IORESOURCE_IO), name); | |
1642 | } | |
1643 | ||
1644 | static inline void | |
1645 | pci_release_io_regions(struct pci_dev *pdev) | |
1646 | { | |
1647 | return pci_release_selected_regions(pdev, | |
1648 | pci_select_bars(pdev, IORESOURCE_IO)); | |
1649 | } | |
1650 | ||
1651 | static inline int | |
1652 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) | |
1653 | { | |
1654 | return pci_request_selected_regions(pdev, | |
1655 | pci_select_bars(pdev, IORESOURCE_MEM), name); | |
1656 | } | |
1657 | ||
1658 | static inline void | |
1659 | pci_release_mem_regions(struct pci_dev *pdev) | |
1660 | { | |
1661 | return pci_release_selected_regions(pdev, | |
1662 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1663 | } | |
1664 | ||
4352dfd5 | 1665 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 | 1666 | |
5bbe029f BH |
1667 | static inline void pci_set_flags(int flags) { } |
1668 | static inline void pci_add_flags(int flags) { } | |
1669 | static inline void pci_clear_flags(int flags) { } | |
1670 | static inline int pci_has_flag(int flag) { return 0; } | |
1671 | ||
1da177e4 | 1672 | /* |
0aa0f5d1 BH |
1673 | * If the system does not have PCI, clearly these return errors. Define |
1674 | * these as simple inline functions to avoid hair in drivers. | |
1da177e4 | 1675 | */ |
05cca6e5 GKH |
1676 | #define _PCI_NOP(o, s, t) \ |
1677 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1678 | int where, t val) \ | |
1da177e4 | 1679 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1680 | |
1681 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1682 | _PCI_NOP(o, word, u16 x) \ | |
1683 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1684 | _PCI_NOP_ALL(read, *) |
1685 | _PCI_NOP_ALL(write,) | |
1686 | ||
d42552c3 | 1687 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1688 | unsigned int device, |
1689 | struct pci_dev *from) | |
2ee546c4 | 1690 | { return NULL; } |
d42552c3 | 1691 | |
05cca6e5 GKH |
1692 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1693 | unsigned int device, | |
1694 | unsigned int ss_vendor, | |
1695 | unsigned int ss_device, | |
b08508c4 | 1696 | struct pci_dev *from) |
2ee546c4 | 1697 | { return NULL; } |
1da177e4 | 1698 | |
05cca6e5 GKH |
1699 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1700 | struct pci_dev *from) | |
2ee546c4 | 1701 | { return NULL; } |
1da177e4 LT |
1702 | |
1703 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1704 | #define no_pci_devices() (1) |
1da177e4 LT |
1705 | #define pci_dev_put(dev) do { } while (0) |
1706 | ||
2ee546c4 BH |
1707 | static inline void pci_set_master(struct pci_dev *dev) { } |
1708 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
1709 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
977da073 | 1710 | static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } |
05cca6e5 | 1711 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1712 | { return -EBUSY; } |
05cca6e5 GKH |
1713 | static inline int __pci_register_driver(struct pci_driver *drv, |
1714 | struct module *owner) | |
2ee546c4 | 1715 | { return 0; } |
05cca6e5 | 1716 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
1717 | { return 0; } |
1718 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
05cca6e5 | 1719 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1720 | { return 0; } |
05cca6e5 GKH |
1721 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1722 | int cap) | |
2ee546c4 | 1723 | { return 0; } |
05cca6e5 | 1724 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1725 | { return 0; } |
05cca6e5 | 1726 | |
70c0923b JK |
1727 | static inline u64 pci_get_dsn(struct pci_dev *dev) |
1728 | { return 0; } | |
1729 | ||
1da177e4 | 1730 | /* Power management related routines */ |
2ee546c4 BH |
1731 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
1732 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 1733 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 1734 | { return 0; } |
3449248c | 1735 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 1736 | { return 0; } |
05cca6e5 GKH |
1737 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1738 | pm_message_t state) | |
2ee546c4 | 1739 | { return PCI_D0; } |
05cca6e5 GKH |
1740 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1741 | int enable) | |
2ee546c4 | 1742 | { return 0; } |
48a92a81 | 1743 | |
afd29f90 MW |
1744 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
1745 | struct resource *res) | |
1746 | { return NULL; } | |
05cca6e5 | 1747 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
1748 | { return -EIO; } |
1749 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 1750 | |
c5076cfe TN |
1751 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
1752 | ||
d80d0217 RD |
1753 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1754 | { return NULL; } | |
d80d0217 RD |
1755 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1756 | unsigned int devfn) | |
1757 | { return NULL; } | |
7912af5c RD |
1758 | static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, |
1759 | unsigned int bus, unsigned int devfn) | |
1760 | { return NULL; } | |
d80d0217 | 1761 | |
2ee546c4 BH |
1762 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1763 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
12ea6cad | 1764 | |
fb8a0d9d WM |
1765 | #define dev_is_pci(d) (false) |
1766 | #define dev_is_pf(d) (false) | |
fe594932 GU |
1767 | static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) |
1768 | { return false; } | |
80db6f08 NC |
1769 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
1770 | struct device_node *node, | |
1771 | const u32 *intspec, | |
1772 | unsigned int intsize, | |
1773 | unsigned long *out_hwirq, | |
1774 | unsigned int *out_type) | |
1775 | { return -EINVAL; } | |
9c212009 LR |
1776 | |
1777 | static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
1778 | struct pci_dev *dev) | |
1779 | { return NULL; } | |
b9ae16d8 | 1780 | static inline bool pci_ats_disabled(void) { return true; } |
0d8006dd HX |
1781 | |
1782 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1783 | { | |
1784 | return -EINVAL; | |
1785 | } | |
1786 | ||
1787 | static inline int | |
1788 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1789 | unsigned int max_vecs, unsigned int flags, | |
1790 | struct irq_affinity *aff_desc) | |
1791 | { | |
1792 | return -ENOSPC; | |
1793 | } | |
4352dfd5 | 1794 | #endif /* CONFIG_PCI */ |
1da177e4 | 1795 | |
0d8006dd HX |
1796 | static inline int |
1797 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1798 | unsigned int max_vecs, unsigned int flags) | |
1799 | { | |
1800 | return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, | |
1801 | NULL); | |
1802 | } | |
1803 | ||
4352dfd5 GKH |
1804 | /* Include architecture-dependent settings and functions */ |
1805 | ||
1806 | #include <asm/pci.h> | |
1da177e4 | 1807 | |
d1bbf38a | 1808 | /* These two functions provide almost identical functionality. Depending |
f7195824 DW |
1809 | * on the architecture, one will be implemented as a wrapper around the |
1810 | * other (in drivers/pci/mmap.c). | |
1811 | * | |
1812 | * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff | |
1813 | * is expected to be an offset within that region. | |
1814 | * | |
1815 | * pci_mmap_page_range() is the legacy architecture-specific interface, | |
1816 | * which accepts a "user visible" resource address converted by | |
1817 | * pci_resource_to_user(), as used in the legacy mmap() interface in | |
1818 | * /proc/bus/pci/. | |
1819 | */ | |
1820 | int pci_mmap_resource_range(struct pci_dev *dev, int bar, | |
1821 | struct vm_area_struct *vma, | |
1822 | enum pci_mmap_state mmap_state, int write_combine); | |
f66e2258 DW |
1823 | int pci_mmap_page_range(struct pci_dev *pdev, int bar, |
1824 | struct vm_area_struct *vma, | |
11df1954 DW |
1825 | enum pci_mmap_state mmap_state, int write_combine); |
1826 | ||
ae749c7a DW |
1827 | #ifndef arch_can_pci_mmap_wc |
1828 | #define arch_can_pci_mmap_wc() 0 | |
1829 | #endif | |
2bea36fd | 1830 | |
e854d8b2 DW |
1831 | #ifndef arch_can_pci_mmap_io |
1832 | #define arch_can_pci_mmap_io() 0 | |
2bea36fd DW |
1833 | #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) |
1834 | #else | |
1835 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); | |
e854d8b2 | 1836 | #endif |
ae749c7a | 1837 | |
92016ba5 JO |
1838 | #ifndef pci_root_bus_fwnode |
1839 | #define pci_root_bus_fwnode(bus) NULL | |
1840 | #endif | |
1841 | ||
0aa0f5d1 BH |
1842 | /* |
1843 | * These helpers provide future and backwards compatibility | |
1844 | * for accessing popular PCI BAR info | |
1845 | */ | |
05cca6e5 GKH |
1846 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1847 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1848 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1849 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1850 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1851 | pci_resource_end((dev), (bar)) == \ | |
1852 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1853 | \ | |
1854 | (pci_resource_end((dev), (bar)) - \ | |
1855 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 | 1856 | |
0aa0f5d1 BH |
1857 | /* |
1858 | * Similar to the helpers above, these manipulate per-pci_dev | |
1da177e4 LT |
1859 | * driver-specific data. They are really just a wrapper around |
1860 | * the generic device structure functions of these calls. | |
1861 | */ | |
05cca6e5 | 1862 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1863 | { |
1864 | return dev_get_drvdata(&pdev->dev); | |
1865 | } | |
1866 | ||
05cca6e5 | 1867 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1868 | { |
1869 | dev_set_drvdata(&pdev->dev, data); | |
1870 | } | |
1871 | ||
2fc90f61 | 1872 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1873 | { |
c6c4f070 | 1874 | return dev_name(&pdev->dev); |
1da177e4 LT |
1875 | } |
1876 | ||
8221a013 BH |
1877 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1878 | const struct resource *rsrc, | |
1879 | resource_size_t *start, resource_size_t *end); | |
2311b1f2 | 1880 | |
1da177e4 | 1881 | /* |
0aa0f5d1 BH |
1882 | * The world is not perfect and supplies us with broken PCI devices. |
1883 | * For at least a part of these bugs we need a work-around, so both | |
1884 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1885 | * fixup hooks to be called for particular buggy devices. | |
1da177e4 LT |
1886 | */ |
1887 | ||
1888 | struct pci_fixup { | |
0aa0f5d1 BH |
1889 | u16 vendor; /* Or PCI_ANY_ID */ |
1890 | u16 device; /* Or PCI_ANY_ID */ | |
1891 | u32 class; /* Or PCI_ANY_ID */ | |
f4ca5c6a | 1892 | unsigned int class_shift; /* should be 0, 8, 16 */ |
c9d8b55f AB |
1893 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
1894 | int hook_offset; | |
1895 | #else | |
1da177e4 | 1896 | void (*hook)(struct pci_dev *dev); |
c9d8b55f | 1897 | #endif |
1da177e4 LT |
1898 | }; |
1899 | ||
1900 | enum pci_fixup_pass { | |
1901 | pci_fixup_early, /* Before probing BARs */ | |
1902 | pci_fixup_header, /* After reading configuration header */ | |
1903 | pci_fixup_final, /* Final phase of device fixups */ | |
1904 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 1905 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 1906 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 1907 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 1908 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
1909 | }; |
1910 | ||
c9d8b55f AB |
1911 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
1912 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1913 | class_shift, hook) \ | |
1914 | __ADDRESSABLE(hook) \ | |
1915 | asm(".section " #sec ", \"a\" \n" \ | |
1916 | ".balign 16 \n" \ | |
1917 | ".short " #vendor ", " #device " \n" \ | |
1918 | ".long " #class ", " #class_shift " \n" \ | |
1919 | ".long " #hook " - . \n" \ | |
1920 | ".previous \n"); | |
1921 | #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1922 | class_shift, hook) \ | |
1923 | __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1924 | class_shift, hook) | |
1925 | #else | |
1da177e4 | 1926 | /* Anonymous variables would be nice... */ |
f4ca5c6a YL |
1927 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1928 | class_shift, hook) \ | |
ecf61c78 | 1929 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
1930 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1931 | = { vendor, device, class, class_shift, hook }; | |
c9d8b55f | 1932 | #endif |
f4ca5c6a YL |
1933 | |
1934 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
1935 | class_shift, hook) \ | |
1936 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1937 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1938 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
1939 | class_shift, hook) \ | |
1940 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1941 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1942 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
1943 | class_shift, hook) \ | |
1944 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1945 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1946 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
1947 | class_shift, hook) \ | |
1948 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1949 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1950 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
1951 | class_shift, hook) \ | |
1952 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 1953 | resume##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1954 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
1955 | class_shift, hook) \ | |
1956 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 1957 | resume_early##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1958 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
1959 | class_shift, hook) \ | |
1960 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 1961 | suspend##hook, vendor, device, class, class_shift, hook) |
7d2a01b8 AN |
1962 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
1963 | class_shift, hook) \ | |
1964 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 1965 | suspend_late##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a | 1966 | |
1da177e4 LT |
1967 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1968 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1969 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1970 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1971 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1972 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1973 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1974 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1975 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1976 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1977 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1978 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
1979 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1980 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 1981 | resume##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1982 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1983 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 1984 | resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1985 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1986 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 1987 | suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
1988 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
1989 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 1990 | suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 | 1991 | |
93177a74 | 1992 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1993 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
1994 | #else |
1995 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 1996 | struct pci_dev *dev) { } |
93177a74 | 1997 | #endif |
1da177e4 | 1998 | |
05cca6e5 | 1999 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 2000 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 2001 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
2002 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
2003 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 2004 | const char *name); |
fb7ebfe4 | 2005 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 2006 | |
1da177e4 | 2007 | extern int pci_pci_problems; |
236561e5 | 2008 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
2009 | #define PCIPCI_TRITON 2 |
2010 | #define PCIPCI_NATOMA 4 | |
2011 | #define PCIPCI_VIAETBF 8 | |
2012 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
2013 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
2014 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 2015 | |
4516a618 AN |
2016 | extern unsigned long pci_cardbus_io_size; |
2017 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 2018 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 2019 | extern u8 pci_cache_line_size; |
4516a618 | 2020 | |
f7625980 | 2021 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 2022 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 2023 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
2024 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2025 | enum pcie_reset_state state); | |
eca0d467 | 2026 | int pcibios_add_device(struct pci_dev *dev); |
6ae32c53 | 2027 | void pcibios_release_device(struct pci_dev *dev); |
5d32a665 | 2028 | #ifdef CONFIG_PCI |
a43ae58c | 2029 | void pcibios_penalize_isa_irq(int irq, int active); |
5d32a665 SK |
2030 | #else |
2031 | static inline void pcibios_penalize_isa_irq(int irq, int active) {} | |
2032 | #endif | |
890e4847 JL |
2033 | int pcibios_alloc_irq(struct pci_dev *dev); |
2034 | void pcibios_free_irq(struct pci_dev *dev); | |
619e6f34 | 2035 | resource_size_t pcibios_default_alignment(void); |
575e3348 | 2036 | |
699c1985 SO |
2037 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
2038 | extern struct dev_pm_ops pcibios_pm_ops; | |
2039 | #endif | |
2040 | ||
935c760e | 2041 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
f39d5b72 BH |
2042 | void __init pci_mmcfg_early_init(void); |
2043 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 2044 | #else |
bb63b421 | 2045 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
2046 | static inline void pci_mmcfg_late_init(void) { } |
2047 | #endif | |
2048 | ||
642c92da | 2049 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 2050 | |
1684f5dd | 2051 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
c43996f4 | 2052 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 2053 | |
dd7cc44d | 2054 | #ifdef CONFIG_PCI_IOV |
b07579c0 WY |
2055 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
2056 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); | |
2057 | ||
f39d5b72 BH |
2058 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
2059 | void pci_disable_sriov(struct pci_dev *dev); | |
a1ceea67 NS |
2060 | |
2061 | int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); | |
753f6124 JS |
2062 | int pci_iov_add_virtfn(struct pci_dev *dev, int id); |
2063 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id); | |
f39d5b72 | 2064 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 2065 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
2066 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
2067 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
8effc395 | 2068 | int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); |
0e6c9122 | 2069 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
608c0d88 | 2070 | void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); |
619e6f34 MM |
2071 | |
2072 | /* Arch may override these (weak) */ | |
2073 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); | |
2074 | int pcibios_sriov_disable(struct pci_dev *pdev); | |
2075 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); | |
dd7cc44d | 2076 | #else |
b07579c0 WY |
2077 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
2078 | { | |
2079 | return -ENOSYS; | |
2080 | } | |
2081 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) | |
2082 | { | |
2083 | return -ENOSYS; | |
2084 | } | |
dd7cc44d | 2085 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
2ee546c4 | 2086 | { return -ENODEV; } |
a1ceea67 NS |
2087 | |
2088 | static inline int pci_iov_sysfs_link(struct pci_dev *dev, | |
2089 | struct pci_dev *virtfn, int id) | |
2090 | { | |
2091 | return -ENODEV; | |
2092 | } | |
753f6124 | 2093 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) |
c194f7ea WY |
2094 | { |
2095 | return -ENOSYS; | |
2096 | } | |
2097 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, | |
753f6124 | 2098 | int id) { } |
2ee546c4 | 2099 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
2ee546c4 | 2100 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 2101 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 2102 | { return 0; } |
bff73156 | 2103 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 2104 | { return 0; } |
bff73156 | 2105 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 2106 | { return 0; } |
8effc395 | 2107 | #define pci_sriov_configure_simple NULL |
0e6c9122 WY |
2108 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
2109 | { return 0; } | |
608c0d88 | 2110 | static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } |
dd7cc44d YZ |
2111 | #endif |
2112 | ||
c825bc94 | 2113 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
2114 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
2115 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
2116 | #endif |
2117 | ||
d7b7e605 KK |
2118 | /** |
2119 | * pci_pcie_cap - get the saved PCIe capability offset | |
2120 | * @dev: PCI device | |
2121 | * | |
2122 | * PCIe capability offset is calculated at PCI device initialization | |
2123 | * time and saved in the data structure. This function returns saved | |
2124 | * PCIe capability offset. Using this instead of pci_find_capability() | |
2125 | * reduces unnecessary search in the PCI configuration space. If you | |
2126 | * need to calculate PCIe capability offset from raw device for some | |
2127 | * reasons, please use pci_find_capability() instead. | |
2128 | */ | |
2129 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
2130 | { | |
2131 | return dev->pcie_cap; | |
2132 | } | |
2133 | ||
7eb776c4 KK |
2134 | /** |
2135 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
2136 | * @dev: PCI device | |
2137 | * | |
a895c28a | 2138 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
2139 | */ |
2140 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
2141 | { | |
a895c28a | 2142 | return pci_pcie_cap(dev); |
7eb776c4 KK |
2143 | } |
2144 | ||
7c9c003c MS |
2145 | /** |
2146 | * pcie_caps_reg - get the PCIe Capabilities Register | |
2147 | * @dev: PCI device | |
2148 | */ | |
2149 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
2150 | { | |
2151 | return dev->pcie_flags_reg; | |
2152 | } | |
2153 | ||
786e2288 YW |
2154 | /** |
2155 | * pci_pcie_type - get the PCIe device/port type | |
2156 | * @dev: PCI device | |
2157 | */ | |
2158 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
2159 | { | |
1c531d82 | 2160 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
2161 | } |
2162 | ||
6ae72bfa YY |
2163 | /** |
2164 | * pcie_find_root_port - Get the PCIe root port device | |
2165 | * @dev: PCI device | |
2166 | * | |
2167 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
2168 | * for a given PCI/PCIe Device. | |
2169 | */ | |
e784930b JT |
2170 | static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) |
2171 | { | |
5396956c MW |
2172 | while (dev) { |
2173 | if (pci_is_pcie(dev) && | |
2174 | pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2175 | return dev; | |
2176 | dev = pci_upstream_bridge(dev); | |
e784930b | 2177 | } |
6ae72bfa | 2178 | |
e784930b JT |
2179 | return NULL; |
2180 | } | |
2181 | ||
5d990b62 | 2182 | void pci_request_acs(void); |
ad805758 AW |
2183 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
2184 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2185 | struct pci_dev *end, u16 acs_flags); | |
430a2368 | 2186 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); |
a2ce7662 | 2187 | |
7ad506fa | 2188 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 2189 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
2190 | |
2191 | /* Large Resource Data Type Tag Item Names */ | |
2192 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
2193 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
2194 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
2195 | ||
2196 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
2197 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
2198 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
2199 | ||
2200 | /* Small Resource Data Type Tag Item Names */ | |
9eb45d5c | 2201 | #define PCI_VPD_STIN_END 0x0f /* End */ |
7ad506fa | 2202 | |
9eb45d5c | 2203 | #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) |
7ad506fa MC |
2204 | |
2205 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
2206 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
9eb45d5c | 2207 | #define PCI_VPD_LRDT_TIN_MASK 0x7f |
7ad506fa MC |
2208 | |
2209 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
2210 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 2211 | |
e1d5bdab MC |
2212 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
2213 | ||
4067a854 | 2214 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
16efafa3 | 2215 | #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" |
4067a854 MC |
2216 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
2217 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 2218 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 2219 | |
a2ce7662 MC |
2220 | /** |
2221 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
2222 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
2223 | * | |
2224 | * Returns the extracted Large Resource Data Type length. | |
2225 | */ | |
2226 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
2227 | { | |
2228 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
2229 | } | |
2230 | ||
9eb45d5c HR |
2231 | /** |
2232 | * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item | |
2233 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
2234 | * | |
2235 | * Returns the extracted Large Resource Data Type Tag item. | |
2236 | */ | |
2237 | static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) | |
2238 | { | |
0aa0f5d1 | 2239 | return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); |
9eb45d5c HR |
2240 | } |
2241 | ||
7ad506fa MC |
2242 | /** |
2243 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
0142626d | 2244 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
7ad506fa MC |
2245 | * |
2246 | * Returns the extracted Small Resource Data Type length. | |
2247 | */ | |
2248 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
2249 | { | |
2250 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
2251 | } | |
2252 | ||
9eb45d5c HR |
2253 | /** |
2254 | * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item | |
0142626d | 2255 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
9eb45d5c HR |
2256 | * |
2257 | * Returns the extracted Small Resource Data Type Tag Item. | |
2258 | */ | |
2259 | static inline u8 pci_vpd_srdt_tag(const u8 *srdt) | |
2260 | { | |
2261 | return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; | |
2262 | } | |
2263 | ||
e1d5bdab MC |
2264 | /** |
2265 | * pci_vpd_info_field_size - Extracts the information field length | |
229b4e07 | 2266 | * @info_field: Pointer to the beginning of an information field header |
e1d5bdab MC |
2267 | * |
2268 | * Returns the extracted information field length. | |
2269 | */ | |
2270 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
2271 | { | |
2272 | return info_field[2]; | |
2273 | } | |
2274 | ||
b55ac1b2 MC |
2275 | /** |
2276 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
2277 | * @buf: Pointer to buffered vpd data | |
2278 | * @off: The offset into the buffer at which to begin the search | |
2279 | * @len: The length of the vpd buffer | |
2280 | * @rdt: The Resource Data Type to search for | |
2281 | * | |
2282 | * Returns the index where the Resource Data Type was found or | |
2283 | * -ENOENT otherwise. | |
2284 | */ | |
2285 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
2286 | ||
4067a854 MC |
2287 | /** |
2288 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
2289 | * @buf: Pointer to buffered vpd data | |
2290 | * @off: The offset into the buffer at which to begin the search | |
2291 | * @len: The length of the buffer area, relative to off, in which to search | |
2292 | * @kw: The keyword to search for | |
2293 | * | |
2294 | * Returns the index where the information field keyword was found or | |
2295 | * -ENOENT otherwise. | |
2296 | */ | |
2297 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
2298 | unsigned int len, const char *kw); | |
2299 | ||
98d9f30c BH |
2300 | /* PCI <-> OF binding helpers */ |
2301 | #ifdef CONFIG_OF | |
2302 | struct device_node; | |
b165e2b6 | 2303 | struct irq_domain; |
b165e2b6 | 2304 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
98d9f30c BH |
2305 | |
2306 | /* Arch may override this (weak) */ | |
723ec4d0 | 2307 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 2308 | |
0aa0f5d1 | 2309 | #else /* CONFIG_OF */ |
b165e2b6 MZ |
2310 | static inline struct irq_domain * |
2311 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } | |
98d9f30c BH |
2312 | #endif /* CONFIG_OF */ |
2313 | ||
ad32eb2d BM |
2314 | static inline struct device_node * |
2315 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
2316 | { | |
2317 | return pdev ? pdev->dev.of_node : NULL; | |
2318 | } | |
2319 | ||
2320 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) | |
2321 | { | |
2322 | return bus ? bus->dev.of_node : NULL; | |
2323 | } | |
2324 | ||
471036b2 SS |
2325 | #ifdef CONFIG_ACPI |
2326 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); | |
2327 | ||
2328 | void | |
2329 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); | |
52525b7a | 2330 | bool pci_pr3_present(struct pci_dev *pdev); |
471036b2 SS |
2331 | #else |
2332 | static inline struct irq_domain * | |
2333 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } | |
46b4bff6 | 2334 | static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } |
471036b2 SS |
2335 | #endif |
2336 | ||
eb740b5f GS |
2337 | #ifdef CONFIG_EEH |
2338 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
2339 | { | |
2340 | return pdev->dev.archdata.edev; | |
2341 | } | |
2342 | #endif | |
2343 | ||
09298542 | 2344 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); |
338c3149 | 2345 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
c25dc828 AW |
2346 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
2347 | int (*fn)(struct pci_dev *pdev, | |
2348 | u16 alias, void *data), void *data); | |
2349 | ||
0aa0f5d1 | 2350 | /* Helper functions for operation of device flag */ |
ce052984 EZ |
2351 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
2352 | { | |
2353 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
2354 | } | |
2355 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
2356 | { | |
2357 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
2358 | } | |
2359 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
2360 | { | |
2361 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
2362 | } | |
19bdb6e4 AW |
2363 | |
2364 | /** | |
2365 | * pci_ari_enabled - query ARI forwarding status | |
2366 | * @bus: the PCI bus | |
2367 | * | |
2368 | * Returns true if ARI forwarding is enabled. | |
2369 | */ | |
2370 | static inline bool pci_ari_enabled(struct pci_bus *bus) | |
2371 | { | |
2372 | return bus->self && bus->self->ari_enabled; | |
2373 | } | |
bc4b024a | 2374 | |
8531e283 LW |
2375 | /** |
2376 | * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain | |
2377 | * @pdev: PCI device to check | |
2378 | * | |
2379 | * Walk upwards from @pdev and check for each encountered bridge if it's part | |
2380 | * of a Thunderbolt controller. Reaching the host bridge means @pdev is not | |
2381 | * Thunderbolt-attached. (But rather soldered to the mainboard usually.) | |
2382 | */ | |
2383 | static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) | |
2384 | { | |
2385 | struct pci_dev *parent = pdev; | |
2386 | ||
2387 | if (pdev->is_thunderbolt) | |
2388 | return true; | |
2389 | ||
2390 | while ((parent = pci_upstream_bridge(parent))) | |
2391 | if (parent->is_thunderbolt) | |
2392 | return true; | |
2393 | ||
2394 | return false; | |
2395 | } | |
2396 | ||
2e28bc84 | 2397 | #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) |
3ecac020 ME |
2398 | void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); |
2399 | #endif | |
856e1eb9 | 2400 | |
0aa0f5d1 | 2401 | /* Provide the legacy pci_dma_* API */ |
bc4b024a CH |
2402 | #include <linux/pci-dma-compat.h> |
2403 | ||
7506dc79 FL |
2404 | #define pci_printk(level, pdev, fmt, arg...) \ |
2405 | dev_printk(level, &(pdev)->dev, fmt, ##arg) | |
2406 | ||
2407 | #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) | |
2408 | #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) | |
2409 | #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) | |
2410 | #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) | |
2411 | #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) | |
2412 | #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) | |
2413 | #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) | |
2414 | #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) | |
2415 | ||
a88a7b3e BH |
2416 | #define pci_notice_ratelimited(pdev, fmt, arg...) \ |
2417 | dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2418 | ||
7f1c62c4 KW |
2419 | #define pci_info_ratelimited(pdev, fmt, arg...) \ |
2420 | dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2421 | ||
12bcae44 BH |
2422 | #define pci_WARN(pdev, condition, fmt, arg...) \ |
2423 | WARN(condition, "%s %s: " fmt, \ | |
2424 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2425 | ||
2426 | #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ | |
2427 | WARN_ONCE(condition, "%s %s: " fmt, \ | |
2428 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2429 | ||
1da177e4 | 2430 | #endif /* LINUX_PCI_H */ |