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PCI/MSI: Provide IMS (Interrupt Message Store) support
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
7ce2e76a
KW		 9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
1da177e4
LT		 14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
7ce2e76a 20 * PCI Express Specification
1da177e4
LT		 21 * PCI System Design Guide
22 */
1da177e4
LT		 23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
1da177e4 26
778382e0
DW		 27#include <linux/mod_devicetable.h>
28
1da177e4 29#include <linux/types.h>
98db6f19 30#include <linux/init.h>
1da177e4
LT		 31#include <linux/ioport.h>
32#include <linux/list.h>
4a7fb636 33#include <linux/compiler.h>
1da177e4 34#include <linux/errno.h>
f46753c5 35#include <linux/kobject.h>
60063497 36#include <linux/atomic.h>
1da177e4 37#include <linux/device.h>
704e8953 38#include <linux/interrupt.h>
1388cc96 39#include <linux/io.h>
14d76b68 40#include <linux/resource_ext.h>
34026364 41#include <linux/msi_api.h>
607ca46e 42#include <uapi/linux/pci.h>
1da177e4 43
7e7a43c3
AB		 44#include <linux/pci_ids.h>
45
d6e055e8
HK		 46#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
e20afa06 53/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
6937b7dd 54#define PCI_NUM_RESET_METHODS 7
e20afa06 55
9bdc81ce
AN		 56#define PCI_RESET_PROBE true
57#define PCI_RESET_DO_RESET false
58
85467136
SK		 59/*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
f7625980
BH		 66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 68 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 69 * the following kernel-only defines are being added here.
85467136 70 */
0aa0f5d1 71#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 72/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
f46753c5
AC		 75/* pci_slot represents a physical slot */
76struct pci_slot {
0aa0f5d1
BH		 77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
f46753c5
AC		 82};
83
0ad772ec
AC		 84static inline const char *pci_slot_name(const struct pci_slot *slot)
85{
86 return kobject_name(&slot->kobj);
87}
88
1da177e4
LT		 89/* File state for mmap()s on /proc/bus/pci/X/Y */
90enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93};
94
0aa0f5d1 95/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 96enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
c9c13ba4 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
fde09c6d
YZ		 100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
0aa0f5d1 104 /* Device-specific resources */
d1b054da
YZ		 105#ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108#endif
109
6e0688db
KW		 110/* PCI-to-PCI (P2P) bridge windows */
111#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115/* CardBus bridge windows */
116#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121/* Total number of bridge resources for P2P and CardBus */
fde09c6d
YZ		 122#define PCI_BRIDGE_RESOURCE_NUM 4
123
6e0688db 124 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
0aa0f5d1 129 /* Total resources associated with a PCI device */
fde09c6d
YZ		 130 PCI_NUM_RESOURCES,
131
0aa0f5d1 132 /* Preserve this for compatibility */
cda57bf9 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 134};
1da177e4 135
b352baf1
PB		 136/**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153};
154
155/* The number of legacy PCI INTx interrupts */
156#define PCI_NUM_INTX 4
157
57bdeef4
NN		 158/*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163#define PCI_ERROR_RESPONSE (~0ULL)
164#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
224abb67
BH		 167/*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
1da177e4
LT		 171typedef int __bitwise pci_power_t;
172
4352dfd5
GKH		 173#define PCI_D0 ((pci_power_t __force) 0)
174#define PCI_D1 ((pci_power_t __force) 1)
175#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 176#define PCI_D3hot ((pci_power_t __force) 3)
177#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 178#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 179#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 180
00240c38
AS		 181/* Remember to update this when the list above changes! */
182extern const char *pci_power_names[];
183
184static inline const char *pci_power_name(pci_power_t state)
185{
9661e783 186 return pci_power_names[1 + (__force int) state];
00240c38
AS		 187}
188
0aa0f5d1 189/**
229b4e07
CD		 190 * typedef pci_channel_state_t
191 *
0aa0f5d1
BH		 192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
392a1ce7 195 */
196typedef unsigned int __bitwise pci_channel_state_t;
197
16d79cd4 198enum {
392a1ce7 199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207};
208
f7bdd12d
BK		 209typedef unsigned int __bitwise pcie_reset_state_t;
210
211enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
f7625980 215 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
f7625980 218 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220};
221
ba698ad4
DM		 222typedef unsigned short __bitwise pci_dev_flags_t;
223enum pci_dev_flags {
0aa0f5d1 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 226 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 228 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 240 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 244 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
2226667a
MZ		 246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
ba698ad4
DM		 248};
249
e1d3a908
SA		 250enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253};
254
6e325a62
MT		 255typedef unsigned short __bitwise pci_bus_flags_t;
256enum pci_bus_flags {
032c3d86
JD		 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
17e8f0d4 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
6e325a62
MT		 261};
262
0aa0f5d1 263/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 264enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
0aa0f5d1 270 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
0aa0f5d1 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 274};
275
e56faff5 276/* See matching string table in pci_speed_string() */
536c8cb4
MW		 277enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
536c8cb4
MW		 294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 299 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 300 PCIE_SPEED_16_0GT = 0x17,
de76cda2 301 PCIE_SPEED_32_0GT = 0x18,
34191749 302 PCIE_SPEED_64_0GT = 0x19,
536c8cb4
MW		 303 PCI_SPEED_UNKNOWN = 0xff,
304};
305
576c7218
AD		 306enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
fd00faa3
HK		 309struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
24a4742f
AW		 313};
314
402723ad 315struct irq_affinity;
7d715a6c 316struct pcie_link_state;
d1b054da 317struct pci_sriov;
52916982 318struct pci_p2pdma;
90655631 319struct rcec_ea;
ee69439c 320
0aa0f5d1 321/* The pci_dev structure describes PCI devices */
1da177e4 322struct pci_dev {
0aa0f5d1
BH		 323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 326
0aa0f5d1
BH		 327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 329 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 330
0aa0f5d1 331 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 337 u8 revision; /* PCI revision, low byte of class word */
1da177e4 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 339#ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
db89ccbe 341 struct aer_stats *aer_stats; /* AER stats for this device */
90655631
SK		 342#endif
343#ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
507b460f 345 struct pci_dev *rcec; /* Associated RCEC device */
66b80809 346#endif
69139244 347 u32 devcap; /* PCIe Device Capabilities */
f7625980 348 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
f7625980 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 356
68da4e0e 357 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
4d57cdfa
FT		 364 struct device_dma_parameters dma_parms;
365
0aa0f5d1
BH		 366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
d6112f8d 369 unsigned int imm_ready:1; /* Supports Immediate Readiness */
703860ed 370 u8 pm_cap; /* PM capability offset */
337001b6
RW		 371 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 can be generated */
379021d5 373 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
e80bb09d 382 unsigned int wakeup_prepared:1;
d491f2b7 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
387 user sysfs */
4ec73791
SM		 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 bit manually */
3789af9a 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
448bd857 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 392
7d715a6c 393#ifdef CONFIG_PCIEASPM
f7625980 394 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 395 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 supported from root to here */
ee8b1c47 397 u16 l1ss; /* L1SS Capability pointer */
7d715a6c 398#endif
8c09e896 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
7ce3f912 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
7d715a6c 401
0aa0f5d1
BH		 402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
1da177e4 404
0aa0f5d1 405 int cfg_size; /* Size of config space */
1da177e4
LT		 406
407 /*
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
410 */
411 unsigned int irq;
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413
0aa0f5d1
BH		 414 bool match_driver; /* Skip attaching driver */
415
416 unsigned int transparent:1; /* Subtractive decode bridge */
51c48b31
BH		 417 unsigned int io_window:1; /* Bridge has I/O window */
418 unsigned int pref_window:1; /* Bridge has pref mem window */
419 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
0aa0f5d1
BH		 420 unsigned int multifunction:1; /* Multi-function device */
421
0aa0f5d1
BH		 422 unsigned int is_busmaster:1; /* Is busmaster */
423 unsigned int no_msi:1; /* May not use MSI */
f6b6aefe 424 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
0aa0f5d1
BH		 425 unsigned int block_cfg_access:1; /* Config space access blocked */
426 unsigned int broken_parity_status:1; /* Generates false positive parity */
427 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 428 unsigned int msi_enabled:1;
99dc804d 429 unsigned int msix_enabled:1;
0aa0f5d1
BH		 430 unsigned int ari_enabled:1; /* ARI forwarding */
431 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 432 unsigned int pasid_enabled:1; /* Process Address Space ID */
433 unsigned int pri_enabled:1; /* Page Request Interface */
3f35d2cf
TG		 434 unsigned int is_managed:1; /* Managed via devres */
435 unsigned int is_msi_managed:1; /* MSI release via devres installed */
0aa0f5d1 436 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 437 unsigned int state_saved:1;
d1b054da 438 unsigned int is_physfn:1;
dd7cc44d 439 unsigned int is_virtfn:1;
0aa0f5d1 440 unsigned int is_hotplug_bridge:1;
b03799b0 441 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
0aa0f5d1 442 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
617654aa
MW		 443 /*
444 * Devices marked being untrusted are the ones that can potentially
445 * execute DMA attacks and similar. They are typically connected
446 * through external ports such as Thunderbolt but not limited to
447 * that. When an IOMMU is enabled they should be getting full
448 * mappings to make sure they cannot access arbitrary memory.
449 */
450 unsigned int untrusted:1;
99b50be9
RJ		 451 /*
452 * Info from the platform, e.g., ACPI or device tree, may mark a
453 * device as "external-facing". An external-facing device is
454 * itself internal but devices downstream from it are external.
455 */
456 unsigned int external_facing:1;
0aa0f5d1
BH		 457 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
458 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 459 unsigned int irq_managed:1;
0aa0f5d1
BH		 460 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
461 unsigned int is_probed:1; /* Device probing in progress */
f0157160 462 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
aff68a5a 463 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
12856e7a 464 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
500b55b0 465 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
ba698ad4 466 pci_dev_flags_t dev_flags;
bae94d02 467 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 468
0aa0f5d1 469 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 470 struct hlist_head saved_cap_space;
0aa0f5d1 471 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 472 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 473 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 474
d22b3621
BH		 475#ifdef CONFIG_HOTPLUG_PCI_PCIE
476 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
477#endif
9bb04a0c 478#ifdef CONFIG_PCIE_PTM
a47126ec 479 u16 ptm_cap; /* PTM Capability */
9bb04a0c
JY		 480 unsigned int ptm_root:1;
481 unsigned int ptm_enabled:1;
8b2ec318 482 u8 ptm_granularity;
9bb04a0c 483#endif
ded86d8d 484#ifdef CONFIG_PCI_MSI
85aa607e 485 void __iomem *msix_base;
cd119b09 486 raw_spinlock_t msi_lock;
ded86d8d 487#endif
fd00faa3 488 struct pci_vpd vpd;
be06c1b4
BH		 489#ifdef CONFIG_PCIE_DPC
490 u16 dpc_cap;
491 unsigned int dpc_rp_extensions:1;
492 u8 dpc_rp_log_size;
493#endif
466b3ddf 494#ifdef CONFIG_PCI_ATS
dd7cc44d 495 union {
0aa0f5d1
BH		 496 struct pci_sriov *sriov; /* PF: SR-IOV info */
497 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 498 };
67930995
BH		 499 u16 ats_cap; /* ATS Capability offset */
500 u8 ats_stu; /* ATS Smallest Translation Unit */
4ebeb1ec
CT		 501#endif
502#ifdef CONFIG_PCI_PRI
c065190b 503 u16 pri_cap; /* PRI Capability offset */
4ebeb1ec 504 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
e5adf79a 505 unsigned int pasid_required:1; /* PRG Response PASID Required */
4ebeb1ec
CT		 506#endif
507#ifdef CONFIG_PCI_PASID
751035b8 508 u16 pasid_cap; /* PASID Capability offset */
4ebeb1ec 509 u16 pasid_features;
52916982
LG		 510#endif
511#ifdef CONFIG_PCI_P2PDMA
ae21f835 512 struct pci_p2pdma __rcu *p2pdma;
d1b054da 513#endif
52fbf5bd 514 u16 acs_cap; /* ACS Capability offset */
0aa0f5d1
BH		 515 phys_addr_t rom; /* Physical address if not from BAR */
516 size_t romlen; /* Length if not from BAR */
23d99baf
KK		 517 /*
518 * Driver name to force a match. Do not set directly, because core
519 * frees it. Use driver_set_override() to set or clear it.
520 */
521 const char *driver_override;
89ee9f76 522
0aa0f5d1 523 unsigned long priv_flags; /* Private flags for the PCI driver */
e20afa06
AN		 524
525 /* These methods index pci_reset_fn_methods[] */
526 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
1da177e4
LT		 527};
528
dda56549
Y		 529static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
530{
531#ifdef CONFIG_PCI_IOV
532 if (dev->is_virtfn)
533 dev = dev->physfn;
534#endif
dda56549
Y		 535 return dev;
536}
537
3c6e6ae7 538struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 539
1da177e4
LT		 540#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
541#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
542
a7369f1f
LV		 543static inline int pci_channel_offline(struct pci_dev *pdev)
544{
545 return (pdev->error_state != pci_channel_io_normal);
546}
547
15d82ca2
BF		 548/*
549 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
550 * Group number is limited to a 16-bit value, therefore (int)-1 is
551 * not a valid PCI domain number, and can be used as a sentinel
552 * value indicating ->domain_nr is not set by the driver (and
553 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
554 * pci_bus_find_domain_nr()).
555 */
556#define PCI_DOMAIN_NR_NOT_SET (-1)
557
5a21d70d 558struct pci_host_bridge {
0aa0f5d1
BH		 559 struct device dev;
560 struct pci_bus *bus; /* Root bus */
561 struct pci_ops *ops;
07e29295 562 struct pci_ops *child_ops;
0aa0f5d1
BH		 563 void *sysdata;
564 int busnr;
15d82ca2 565 int domain_nr;
14d76b68 566 struct list_head windows; /* resource_entry */
e80a91ad 567 struct list_head dma_ranges; /* dma ranges resource list */
0aa0f5d1 568 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 569 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 570 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 571 void *release_data;
0aa0f5d1
BH		 572 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
573 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48 574 unsigned int native_aer:1; /* OS may use PCIe AER */
9310f0dc 575 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
1df81a6d 576 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
02bfeb48 577 unsigned int native_pme:1; /* OS may use PCIe PME */
af8bb9f8 578 unsigned int native_ltr:1; /* OS may use PCIe LTR */
ac1c8e35 579 unsigned int native_dpc:1; /* OS may use PCIe DPC */
a78cf965 580 unsigned int preserve_config:1; /* Preserve FW resource setup */
2c8d5a2d 581 unsigned int size_windows:1; /* Enable root bus sizing */
94e89b14 582 unsigned int msi_domain:1; /* Bridge wants MSI domain */
a78cf965 583
7c7a0e94
GP		 584 /* Resource alignment requirements */
585 resource_size_t (*align_resource)(struct pci_dev *dev,
586 const struct resource *res,
587 resource_size_t start,
588 resource_size_t size,
589 resource_size_t align);
914a1951 590 unsigned long private[] ____cacheline_aligned;
5a21d70d 591};
41017f0c 592
7b543663 593#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 594
59094065
TR		 595static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
596{
597 return (void *)bridge->private;
598}
599
600static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
601{
602 return container_of(priv, struct pci_host_bridge, private);
603}
604
a52d1443 605struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 606struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
607 size_t priv);
dff79b91 608void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 609struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
610
4fa2649a 611void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 612 void (*release_fn)(struct pci_host_bridge *),
613 void *release_data);
7b543663 614
6c0cc950
RW		 615int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
616
2fe2abf8
BH		 617/*
618 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
619 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
620 * buses below host bridges or subtractive decode bridges) go in the list.
621 * Use pci_bus_for_each_resource() to iterate through all the resources.
622 */
623
624/*
625 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
626 * and there's no way to program the bridge with the details of the window.
627 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
628 * decode bit set, because they are explicit and can be programmed with _SRS.
629 */
630#define PCI_SUBTRACTIVE_DECODE 0x1
631
632struct pci_bus_resource {
0aa0f5d1
BH		 633 struct list_head list;
634 struct resource *res;
635 unsigned int flags;
2fe2abf8 636};
4352dfd5
GKH		 637
638#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 639
640struct pci_bus {
0aa0f5d1
BH		 641 struct list_head node; /* Node in list of buses */
642 struct pci_bus *parent; /* Parent bus this bridge is on */
643 struct list_head children; /* List of child buses */
644 struct list_head devices; /* List of devices on this bus */
645 struct pci_dev *self; /* Bridge device as seen by parent */
646 struct list_head slots; /* List of slots on this bus;
67546762 647 protected by pci_slot_mutex */
2fe2abf8 648 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 649 struct list_head resources; /* Address space routed to this bus */
650 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 651
0aa0f5d1 652 struct pci_ops *ops; /* Configuration access functions */
0aa0f5d1
BH		 653 void *sysdata; /* Hook for sys-specific extension */
654 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 655
0aa0f5d1
BH		 656 unsigned char number; /* Bus number */
657 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 658 unsigned char max_bus_speed; /* enum pci_bus_speed */
659 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 660#ifdef CONFIG_PCI_DOMAINS_GENERIC
661 int domain_nr;
662#endif
1da177e4
LT		 663
664 char name[48];
665
0aa0f5d1
BH		 666 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
667 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 668 struct device *bridge;
fd7d1ced 669 struct device dev;
0aa0f5d1
BH		 670 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
671 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 672 unsigned int is_added:1;
92c45b63 673 unsigned int unsafe_warn:1; /* warned about RW1C config write */
1da177e4
LT		 674};
675
fd7d1ced 676#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 677
4e544bac
HK		 678static inline u16 pci_dev_id(struct pci_dev *dev)
679{
680 return PCI_DEVID(dev->bus->number, dev->devfn);
681}
682
79af72d7 683/*
f7625980 684 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 685 * false otherwise
77a0dfcd
BH		 686 *
687 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
688 * This is incorrect because "virtual" buses added for SR-IOV (via
689 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 690 */
691static inline bool pci_is_root_bus(struct pci_bus *pbus)
692{
693 return !(pbus->parent);
694}
695
1c86438c
YW		 696/**
697 * pci_is_bridge - check if the PCI device is a bridge
698 * @dev: PCI device
699 *
700 * Return true if the PCI device is bridge whether it has subordinate
701 * or not.
702 */
703static inline bool pci_is_bridge(struct pci_dev *dev)
704{
705 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
706 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
707}
708
24a0c654
AS		 709#define for_each_pci_bridge(dev, bus) \
710 list_for_each_entry(dev, &bus->devices, bus_list) \
711 if (!pci_is_bridge(dev)) {} else
712
c6bde215
BH		 713static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
714{
715 dev = pci_physfn(dev);
716 if (pci_is_root_bus(dev->bus))
717 return NULL;
718
719 return dev->bus->self;
720}
721
16cf0ebc
RW		 722#ifdef CONFIG_PCI_MSI
723static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
724{
725 return pci_dev->msi_enabled || pci_dev->msix_enabled;
726}
727#else
728static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
729#endif
730
0aa0f5d1 731/* Error values that may be returned by PCI functions */
1da177e4
LT		 732#define PCIBIOS_SUCCESSFUL 0x00
733#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
734#define PCIBIOS_BAD_VENDOR_ID 0x83
735#define PCIBIOS_DEVICE_NOT_FOUND 0x86
736#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
737#define PCIBIOS_SET_FAILED 0x88
738#define PCIBIOS_BUFFER_TOO_SMALL 0x89
739
0aa0f5d1 740/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 741static inline int pcibios_err_to_errno(int err)
742{
743 if (err <= PCIBIOS_SUCCESSFUL)
744 return err; /* Assume already errno */
745
746 switch (err) {
747 case PCIBIOS_FUNC_NOT_SUPPORTED:
748 return -ENOENT;
749 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 750 return -ENOTTY;
a6961651
AW		 751 case PCIBIOS_DEVICE_NOT_FOUND:
752 return -ENODEV;
753 case PCIBIOS_BAD_REGISTER_NUMBER:
754 return -EFAULT;
755 case PCIBIOS_SET_FAILED:
756 return -EIO;
757 case PCIBIOS_BUFFER_TOO_SMALL:
758 return -ENOSPC;
759 }
760
d97ffe23 761 return -ERANGE;
a6961651
AW		 762}
763
1da177e4
LT		 764/* Low-level architecture-dependent routines */
765
766struct pci_ops {
057bd2e0
TR		 767 int (*add_bus)(struct pci_bus *bus);
768 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 769 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 770 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
771 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
772};
773
b6ce068a
MW		 774/*
775 * ACPI needs to be able to access PCI config space before we've done a
776 * PCI bus scan and created pci_bus structures.
777 */
f39d5b72
BH		 778int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
779 int reg, int len, u32 *val);
780int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
781 int reg, int len, u32 val);
1da177e4 782
8e639079 783#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3a9ad0b4
YL		 784typedef u64 pci_bus_addr_t;
785#else
786typedef u32 pci_bus_addr_t;
787#endif
788
1da177e4 789struct pci_bus_region {
0aa0f5d1
BH		 790 pci_bus_addr_t start;
791 pci_bus_addr_t end;
1da177e4
LT		 792};
793
794struct pci_dynids {
0aa0f5d1
BH		 795 spinlock_t lock; /* Protects list, index */
796 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 797};
798
f7625980
BH		 799
800/*
801 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
802 * a set of callbacks in struct pci_error_handlers, that device driver
803 * will be notified of PCI bus errors, and will be driven to recovery
804 * when an error occurs.
392a1ce7 805 */
806
807typedef unsigned int __bitwise pci_ers_result_t;
808
809enum pci_ers_result {
0aa0f5d1 810 /* No result/none/not supported in device driver */
392a1ce7 811 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
812
813 /* Device driver can recover without slot reset */
814 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
815
0aa0f5d1 816 /* Device driver wants slot to be reset */
392a1ce7 817 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
818
819 /* Device has completely failed, is unrecoverable */
820 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
821
822 /* Device driver is fully recovered and operational */
823 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 824
825 /* No AER capabilities registered for the driver */
826 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 827};
828
829/* PCI bus error event callbacks */
05cca6e5 830struct pci_error_handlers {
392a1ce7 831 /* PCI bus error detected on this device */
832 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
16d79cd4 833 pci_channel_state_t error);
392a1ce7 834
835 /* MMIO has been re-enabled, but not DMA */
836 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
837
392a1ce7 838 /* PCI slot has been reset */
839 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
840
3ebe7f9f 841 /* PCI function reset prepare or completed */
775755ed
CH		 842 void (*reset_prepare)(struct pci_dev *dev);
843 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 844
392a1ce7 845 /* Device driver may resume normal operations */
846 void (*resume)(struct pci_dev *dev);
847};
848
392a1ce7 849
1da177e4 850struct module;
229b4e07
CD		 851
852/**
853 * struct pci_driver - PCI driver structure
854 * @node: List of driver structures.
855 * @name: Driver name.
856 * @id_table: Pointer to table of device IDs the driver is
857 * interested in. Most drivers should export this
858 * table using MODULE_DEVICE_TABLE(pci,...).
859 * @probe: This probing function gets called (during execution
860 * of pci_register_driver() for already existing
861 * devices or later if a new device gets inserted) for
862 * all PCI devices which match the ID table and are not
863 * "owned" by the other drivers yet. This function gets
864 * passed a "struct pci_dev \*" for each device whose
865 * entry in the ID table matches the device. The probe
866 * function returns zero when the driver chooses to
867 * take "ownership" of the device or an error code
868 * (negative number) otherwise.
869 * The probe function always gets called from process
870 * context, so it can sleep.
871 * @remove: The remove() function gets called whenever a device
872 * being handled by this driver is removed (either during
873 * deregistration of the driver or when it's manually
874 * pulled out of a hot-pluggable slot).
875 * The remove function always gets called from process
876 * context, so it can sleep.
877 * @suspend: Put device into low power state.
229b4e07 878 * @resume: Wake device from low power state.
151f4e2b 879 * (Please see Documentation/power/pci.rst for descriptions
229b4e07
CD		 880 * of PCI Power Management and the related functions.)
881 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
882 * Intended to stop any idling DMA operations.
883 * Useful for enabling wake-on-lan (NIC) or changing
884 * the power state of a device before reboot.
885 * e.g. drivers/net/e100.c.
886 * @sriov_configure: Optional driver callback to allow configuration of
887 * number of VFs to enable via sysfs "sriov_numvfs" file.
c3d5c2d9
LR		 888 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
889 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
890 * This will change MSI-X Table Size in the VF Message Control
891 * registers.
892 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
893 * MSI-X vectors available for distribution to the VFs.
229b4e07
CD		 894 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
895 * @groups: Sysfs attribute groups.
ded13b9c
AG		 896 * @dev_groups: Attributes attached to the device that will be
897 * created once it is bound to the driver.
229b4e07
CD		 898 * @driver: Driver model structure.
899 * @dynids: List of dynamically added device IDs.
512881ea
LB		 900 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
901 * For most device drivers, no need to care about this flag
902 * as long as all DMAs are handled through the kernel DMA API.
903 * For some special ones, for example VFIO drivers, they know
904 * how to manage the DMA themselves and set this flag so that
905 * the IOMMU layer will allow them to setup and manage their
906 * own I/O address space.
229b4e07 907 */
1da177e4 908struct pci_driver {
0aa0f5d1
BH		 909 struct list_head node;
910 const char *name;
911 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
912 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
913 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
914 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
7cb30264
BY		 915 int (*resume)(struct pci_dev *dev); /* Device woken up */
916 void (*shutdown)(struct pci_dev *dev);
917 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
c3d5c2d9
LR		 918 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
919 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
49453028 920 const struct pci_error_handlers *err_handler;
92d50fc1 921 const struct attribute_group **groups;
ded13b9c 922 const struct attribute_group **dev_groups;
1da177e4 923 struct device_driver driver;
0aa0f5d1 924 struct pci_dynids dynids;
512881ea 925 bool driver_managed_dma;
1da177e4
LT		 926};
927
8e9028b3
BH		 928static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
929{
930 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
931}
1da177e4
LT		 932
933/**
0aa0f5d1 934 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 935 * @vend: the 16 bit PCI Vendor ID
936 * @dev: the 16 bit PCI Device ID
937 *
938 * This macro is used to create a struct pci_device_id that matches a
939 * specific device. The subvendor and subdevice fields will be set to
940 * PCI_ANY_ID.
941 */
942#define PCI_DEVICE(vend,dev) \
943 .vendor = (vend), .device = (dev), \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
945
343b7258
MG		 946/**
947 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
948 * override_only flags.
949 * @vend: the 16 bit PCI Vendor ID
950 * @dev: the 16 bit PCI Device ID
951 * @driver_override: the 32 bit PCI Device override_only
952 *
953 * This macro is used to create a struct pci_device_id that matches only a
954 * driver_override device. The subvendor and subdevice fields will be set to
955 * PCI_ANY_ID.
956 */
957#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
958 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
959 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
960
cc6711b0
MG		 961/**
962 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
963 * "driver_override" PCI device.
964 * @vend: the 16 bit PCI Vendor ID
965 * @dev: the 16 bit PCI Device ID
966 *
967 * This macro is used to create a struct pci_device_id that matches a
968 * specific device. The subvendor and subdevice fields will be set to
969 * PCI_ANY_ID and the driver_override will be set to
970 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
971 */
972#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
973 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
974
3d567e0e 975/**
0aa0f5d1 976 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 977 * @vend: the 16 bit PCI Vendor ID
978 * @dev: the 16 bit PCI Device ID
979 * @subvend: the 16 bit PCI Subvendor ID
980 * @subdev: the 16 bit PCI Subdevice ID
981 *
982 * This macro is used to create a struct pci_device_id that matches a
983 * specific device with subsystem information.
984 */
985#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
986 .vendor = (vend), .device = (dev), \
987 .subvendor = (subvend), .subdevice = (subdev)
988
1da177e4 989/**
0aa0f5d1 990 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 991 * @dev_class: the class, subclass, prog-if triple for this device
992 * @dev_class_mask: the class mask for this device
993 *
994 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 995 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 996 * fields will be set to PCI_ANY_ID.
997 */
998#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
999 .class = (dev_class), .class_mask = (dev_class_mask), \
1000 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1002
1597cacb 1003/**
0aa0f5d1 1004 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 1005 * @vend: the vendor name
1006 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 1007 *
1008 * This macro is used to create a struct pci_device_id that matches a
1009 * specific PCI device. The subvendor, and subdevice fields will be set
1010 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1011 * private data.
1012 */
c1309040
MR		 1013#define PCI_VDEVICE(vend, dev) \
1014 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1015 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 1016
b72ae8ca
AS		 1017/**
1018 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1019 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1020 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1021 * @data: the driver data to be filled
1022 *
1023 * This macro is used to create a struct pci_device_id that matches a
1024 * specific PCI device. The subvendor, and subdevice fields will be set
1025 * to PCI_ANY_ID.
1026 */
1027#define PCI_DEVICE_DATA(vend, dev, data) \
1028 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1029 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1030 .driver_data = (kernel_ulong_t)(data)
1031
5bbe029f 1032enum {
0aa0f5d1
BH		 1033 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1034 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1035 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1036 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1037 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 1038 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 1039 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 1040};
1041
0d8006dd
HX		 1042#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1043#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1044#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1045#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1046
0aa0f5d1 1047/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 1048#ifdef CONFIG_PCI
1049
5bbe029f
BH		 1050extern unsigned int pci_flags;
1051
1052static inline void pci_set_flags(int flags) { pci_flags = flags; }
1053static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1054static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1055static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1056
a58674ff 1057void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 1058
1059enum pcie_bus_config_types {
0aa0f5d1
BH		 1060 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1061 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1062 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1063 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1064 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 1065};
1066
1067extern enum pcie_bus_config_types pcie_bus_config;
1068
1da177e4
LT		 1069extern struct bus_type pci_bus_type;
1070
f7625980
BH		 1071/* Do NOT directly access these two variables, unless you are arch-specific PCI
1072 * code, or PCI core code. */
0aa0f5d1 1073extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 1074/* Some device drivers need know if PCI is initiated */
f39d5b72 1075int no_pci_devices(void);
1da177e4 1076
3c449ed0 1077void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 1078void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 1079void pcibios_add_bus(struct pci_bus *bus);
1080void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 1081void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 1082int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 1083/* Architecture-specific versions may override this (weak) */
05cca6e5 1084char *pcibios_setup(char *str);
1da177e4
LT		 1085
1086/* Used only when drivers/pci/setup.c is used */
3b7a17fc 1087resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 1088 resource_size_t,
e31dd6e4 1089 resource_size_t);
1da177e4 1090
d1bbf38a 1091/* Weak but can be overridden by arch */
2d1c8618
BH		 1092void pci_fixup_cardbus(struct pci_bus *);
1093
1da177e4
LT		 1094/* Generic PCI functions used internally */
1095
fc279850 1096void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 1097 struct resource *res);
fc279850 1098void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 1099 struct pci_bus_region *region);
d1fd4fb6 1100void pcibios_scan_specific_bus(int busn);
f39d5b72 1101struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 1102void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 1103struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 1104struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1105 struct pci_ops *ops, void *sysdata,
1106 struct list_head *resources);
49b8e3f3 1107int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 1108int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1109int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1110void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 1111struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 1112 struct pci_ops *ops, void *sysdata,
1113 struct list_head *resources);
1228c4b6 1114int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 1115struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1116 int busnr);
f46753c5 1117struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 1118 const char *name,
1119 struct hotplug_slot *hotplug);
f46753c5 1120void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 1121#ifdef CONFIG_SYSFS
1122void pci_dev_assign_slot(struct pci_dev *dev);
1123#else
1124static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1125#endif
1da177e4 1126int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 1127struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 1128void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 1129unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 1130void pci_bus_add_device(struct pci_dev *dev);
1da177e4 1131void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 1132struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1133 struct resource *res);
3df425f3 1134u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 1135int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 1136u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 1137struct pci_dev *pci_dev_get(struct pci_dev *dev);
1138void pci_dev_put(struct pci_dev *dev);
1139void pci_remove_bus(struct pci_bus *b);
1140void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 1141void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 1142void pci_stop_root_bus(struct pci_bus *bus);
1143void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 1144void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 1145void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 1146void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 1147#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1148#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 1149
1150/* Generic PCI functions exported to card drivers */
1151
f646c2a0
PM		 1152u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1153u8 pci_find_capability(struct pci_dev *dev, int cap);
1154u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1155u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1156u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
ee8b1c47
BH		 1157u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1158u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
29f3eb64 1159struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
c124fd9a 1160u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
ee122037 1161u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1da177e4 1162
70c0923b
JK		 1163u64 pci_get_dsn(struct pci_dev *dev);
1164
d42552c3 1165struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 1166 struct pci_dev *from);
05cca6e5 1167struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 1168 unsigned int ss_vendor, unsigned int ss_device,
1169 struct pci_dev *from);
05cca6e5 1170struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 1171struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1172 unsigned int devfn);
05cca6e5 1173struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 1174int pci_dev_present(const struct pci_device_id *ids);
1175
05cca6e5
GKH		 1176int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1177 int where, u8 *val);
1178int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1179 int where, u16 *val);
1180int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1181 int where, u32 *val);
1182int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1183 int where, u8 val);
1184int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1185 int where, u16 val);
1186int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1187 int where, u32 val);
1f94a94f
RH		 1188
1189int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1190 int where, int size, u32 *val);
1191int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1192 int where, int size, u32 val);
1193int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1194 int where, int size, u32 *val);
1195int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1196 int where, int size, u32 val);
1197
a72b46c3 1198struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1199
d3881e50
KB		 1200int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1201int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1202int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1203int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1204int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1205int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 1206
8c0d3a02
JL		 1207int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1208int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1209int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1210int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1211int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1212 u16 clear, u16 set);
1213int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1214 u32 clear, u32 set);
1215
1216static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1217 u16 set)
1218{
1219 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1220}
1221
1222static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1223 u32 set)
1224{
1225 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1226}
1227
1228static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1229 u16 clear)
1230{
1231 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1232}
1233
1234static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1235 u32 clear)
1236{
1237 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1238}
1239
0aa0f5d1 1240/* User-space driven config access */
c63587d7
AW		 1241int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1242int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1243int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1244int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1245int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1246int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1247
4a7fb636 1248int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1249int __must_check pci_enable_device_io(struct pci_dev *dev);
1250int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1251int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1252int __must_check pcim_enable_device(struct pci_dev *pdev);
1253void pcim_pin_device(struct pci_dev *pdev);
1254
99b3c58f
PG		 1255static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1256{
1257 /*
1258 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1259 * writable and no quirk has marked the feature broken.
1260 */
1261 return !pdev->broken_intx_masking;
1262}
1263
296ccb08
YS		 1264static inline int pci_is_enabled(struct pci_dev *pdev)
1265{
1266 return (atomic_read(&pdev->enable_cnt) > 0);
1267}
1268
9ac7849e
TH		 1269static inline int pci_is_managed(struct pci_dev *pdev)
1270{
1271 return pdev->is_managed;
1272}
1273
1da177e4 1274void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1275
1276extern unsigned int pcibios_max_latency;
1da177e4 1277void pci_set_master(struct pci_dev *dev);
6a479079 1278void pci_clear_master(struct pci_dev *dev);
96c55900 1279
f7bdd12d 1280int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1281int pci_set_cacheline_size(struct pci_dev *dev);
4a7fb636 1282int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1283int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1284int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1285void pci_clear_mwi(struct pci_dev *dev);
1fd3dde5 1286void pci_disable_parity(struct pci_dev *dev);
a04ce0ff 1287void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1288bool pci_check_and_mask_intx(struct pci_dev *dev);
1289bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1290int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1291int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1292int pcix_get_max_mmrbc(struct pci_dev *dev);
1293int pcix_get_mmrbc(struct pci_dev *dev);
1294int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1295int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1296int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1297int pcie_get_mps(struct pci_dev *dev);
1298int pcie_set_mps(struct pci_dev *dev, int mps);
6db79a88
TG		 1299u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1300 enum pci_bus_speed *speed,
1301 enum pcie_link_width *width);
9e506a7b 1302void pcie_print_link_status(struct pci_dev *dev);
9bdc81ce 1303int pcie_reset_flr(struct pci_dev *dev, bool probe);
91295d79 1304int pcie_flr(struct pci_dev *dev);
a96d627a 1305int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1306int pci_reset_function(struct pci_dev *dev);
a477b9cd 1307int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1308int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1309int pci_probe_reset_slot(struct pci_slot *slot);
9a3d2b9b 1310int pci_probe_reset_bus(struct pci_bus *bus);
c6a44ba9 1311int pci_reset_bus(struct pci_dev *dev);
9e33002f
GS		 1312void pci_reset_secondary_bus(struct pci_dev *dev);
1313void pcibios_reset_secondary_bus(struct pci_dev *dev);
14add80b 1314void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1315int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1316int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3 1317void pci_release_resource(struct pci_dev *dev, int resno);
192f1bf7
ND		 1318static inline int pci_rebar_bytes_to_size(u64 bytes)
1319{
1320 bytes = roundup_pow_of_two(bytes);
1321
1322 /* Return BAR size as defined in the resizable BAR specification */
1323 return max(ilog2(bytes), 20) - 20;
1324}
1325
8fbdbb66 1326u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
8bb705e3 1327int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1328int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1329bool pci_device_is_present(struct pci_dev *pdev);
08249651 1330void pci_ignore_hotplug(struct pci_dev *dev);
2856ba60 1331struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
ec5d9e87 1332int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1da177e4 1333
704e8953
CH		 1334int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1335 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1336 const char *fmt, ...);
1337void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1338
1da177e4 1339/* ROM control related routines */
e416de5e
AC		 1340int pci_enable_rom(struct pci_dev *pdev);
1341void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1342void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1343void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1da177e4
LT		 1344
1345/* Power management related routines */
1346int pci_save_state(struct pci_dev *dev);
1d3c16a8 1347void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1348struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1349int pci_load_saved_state(struct pci_dev *dev,
1350 struct pci_saved_state *state);
ffbdd3f7
AW		 1351int pci_load_and_free_saved_state(struct pci_dev *dev,
1352 struct pci_saved_state **state);
d6aa37cd 1353int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1354int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1355pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1356bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1357void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1358int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1359int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1360int pci_prepare_to_sleep(struct pci_dev *dev);
1361int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1362bool pci_dev_run_wake(struct pci_dev *dev);
9d26d3a8
MW		 1363void pci_d3cold_enable(struct pci_dev *dev);
1364void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1365bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
99efde6c 1366void pci_resume_bus(struct pci_bus *bus);
2a4d2c42 1367void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1368
bb209c82
BH		 1369/* For use by arch with custom probe code */
1370void set_pcie_port_type(struct pci_dev *pdev);
1371void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1372
ce5ccdef 1373/* Functions for PCI Hotplug drivers to use */
2f320521 1374unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1375unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1376void pci_lock_rescan_remove(void);
1377void pci_unlock_rescan_remove(void);
ce5ccdef 1378
0aa0f5d1 1379/* Vital Product Data routines */
287d19ce
SH		 1380ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1381ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
bf2928c7
HK		 1382ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1383ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
287d19ce 1384
1da177e4 1385/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1386resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1387void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1388void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1389void pci_bus_size_bridges(struct pci_bus *bus);
1390int pci_claim_resource(struct pci_dev *, int);
8505e729 1391int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1392void pci_assign_unassigned_resources(void);
6841ec68 1393void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1394void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1395void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1396int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1397void pdev_enable_device(struct pci_dev *);
842de40d 1398int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1399void pci_assign_irq(struct pci_dev *dev);
afd29f90 1400struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1401#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1402int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1403int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1404void pci_release_regions(struct pci_dev *);
4a7fb636 1405int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 1406void pci_release_region(struct pci_dev *, int);
c87deff7 1407int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1408int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1409void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1410
1411/* drivers/pci/bus.c */
45ca9e97 1412void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1413void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1414 resource_size_t offset);
45ca9e97 1415void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1416void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1417 unsigned int flags);
2fe2abf8
BH		 1418struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1419void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1420int devm_request_pci_bus_resources(struct device *dev,
1421 struct list_head *resources);
2fe2abf8 1422
bfc45606
DD		 1423/* Temporary until new and working PCI SBR API in place */
1424int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1425
89a74ecc 1426#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1427 for (i = 0; \
1428 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1429 i++)
89a74ecc 1430
4a7fb636
AM		 1431int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1432 struct resource *res, resource_size_t size,
1433 resource_size_t align, resource_size_t min,
664c2848 1434 unsigned long type_mask,
3b7a17fc
DB		 1435 resource_size_t (*alignf)(void *,
1436 const struct resource *,
b26b2d49
DB		 1437 resource_size_t,
1438 resource_size_t),
4a7fb636 1439 void *alignf_data);
1da177e4 1440
8b921acf 1441
fcfaab30
GP		 1442int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1443 resource_size_t size);
c5076cfe
TN		 1444unsigned long pci_address_to_pio(phys_addr_t addr);
1445phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1446int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
a5fb9fb0
SS		 1447int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1448 phys_addr_t phys_addr);
4d3f1384 1449void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1450void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1451 resource_size_t offset,
1452 resource_size_t size);
1453void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1454 struct resource *res);
8b921acf 1455
3a9ad0b4 1456static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1457{
1458 struct pci_bus_region region;
1459
1460 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1461 return region.start;
1462}
1463
863b18f4 1464/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1465int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1466 const char *mod_name);
bba81165 1467
0aa0f5d1 1468/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1469#define pci_register_driver(driver) \
1470 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1471
05cca6e5 1472void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1473
1474/**
1475 * module_pci_driver() - Helper macro for registering a PCI driver
1476 * @__pci_driver: pci_driver struct
1477 *
1478 * Helper macro for PCI drivers which do not do anything special in module
1479 * init/exit. This eliminates a lot of boilerplate. Each module may only
1480 * use this macro once, and calling it replaces module_init() and module_exit()
1481 */
1482#define module_pci_driver(__pci_driver) \
0aa0f5d1 1483 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1484
b4eb6cdb
PG		 1485/**
1486 * builtin_pci_driver() - Helper macro for registering a PCI driver
1487 * @__pci_driver: pci_driver struct
1488 *
1489 * Helper macro for PCI drivers which do not do anything special in their
1490 * init code. This eliminates a lot of boilerplate. Each driver may only
1491 * use this macro once, and calling it replaces device_initcall(...)
1492 */
1493#define builtin_pci_driver(__pci_driver) \
1494 builtin_driver(__pci_driver, pci_register_driver)
1495
05cca6e5 1496struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1497int pci_add_dynid(struct pci_driver *drv,
1498 unsigned int vendor, unsigned int device,
1499 unsigned int subvendor, unsigned int subdevice,
1500 unsigned int class, unsigned int class_mask,
1501 unsigned long driver_data);
05cca6e5
GKH		 1502const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1503 struct pci_dev *dev);
1504int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1505 int pass);
1da177e4 1506
70298c6e 1507void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1508 void *userdata);
ac7dc65a 1509int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1510unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1511void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1512resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1513 unsigned long type);
cecf4864 1514
3448a19d
DA		 1515#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1516#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1517
deb2d2ec 1518int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1519 unsigned int command_bits, u32 flags);
fe537670 1520
d7cc609f
LG		 1521/*
1522 * Virtual interrupts allow for more interrupts to be allocated
1523 * than the device has interrupts for. These are not programmed
1524 * into the device's MSI-X table and must be handled by some
1525 * other driver means.
1526 */
1527#define PCI_IRQ_VIRTUAL (1 << 4)
1528
4fe0d154
CH		 1529#define PCI_IRQ_ALL_TYPES \
1530 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1531
1da177e4
LT		 1532#include <linux/dmapool.h>
1533
1da177e4 1534struct msix_entry {
0aa0f5d1
BH		 1535 u32 vector; /* Kernel uses to write allocated vector */
1536 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1537};
1538
4c859804
BH		 1539#ifdef CONFIG_PCI_MSI
1540int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1541void pci_disable_msi(struct pci_dev *dev);
4c859804 1542int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1543void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1544void pci_restore_msi_state(struct pci_dev *dev);
1545int pci_msi_enabled(void);
4fe03955 1546int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1547int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1548 int minvec, int maxvec);
f7fc32cb
AG		 1549static inline int pci_enable_msix_exact(struct pci_dev *dev,
1550 struct msix_entry *entries, int nvec)
1551{
1552 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1553 if (rc < 0)
1554 return rc;
1555 return 0;
1556}
5c0997dc
AD		 1557int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1558 unsigned int max_vecs, unsigned int flags);
402723ad
CH		 1559int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1560 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1561 struct irq_affinity *affd);
402723ad 1562
34026364
TG		 1563bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1564struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1565 const struct irq_affinity_desc *affdesc);
1566void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1567
aff17164
CH		 1568void pci_free_irq_vectors(struct pci_dev *dev);
1569int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1570const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
aff17164 1571
4c859804 1572#else
2ee546c4 1573static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1574static inline void pci_disable_msi(struct pci_dev *dev) { }
1575static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1576static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1577static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1578static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1579static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1580{ return -ENOSYS; }
302a2523 1581static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1582 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1583{ return -ENOSYS; }
f7fc32cb 1584static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1585 struct msix_entry *entries, int nvec)
f7fc32cb 1586{ return -ENOSYS; }
402723ad
CH		 1587
1588static inline int
1589pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1590 unsigned int max_vecs, unsigned int flags,
c66d4bd1 1591 struct irq_affinity *aff_desc)
aff17164 1592{
83b4605b
CH		 1593 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1594 return 1;
1595 return -ENOSPC;
aff17164 1596}
5c0997dc
AD		 1597static inline int
1598pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1599 unsigned int max_vecs, unsigned int flags)
1600{
1601 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1602 flags, NULL);
1603}
402723ad 1604
aff17164
CH		 1605static inline void pci_free_irq_vectors(struct pci_dev *dev)
1606{
1607}
1608
1609static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1610{
1611 if (WARN_ON_ONCE(nr > 0))
1612 return -EINVAL;
1613 return dev->irq;
1614}
ee8d41e5
TG		 1615static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1616 int vec)
1617{
1618 return cpu_possible_mask;
1619}
1da177e4
LT		 1620#endif
1621
0d58e6c1
PB		 1622/**
1623 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1624 * @d: the INTx IRQ domain
1625 * @node: the DT node for the device whose interrupt we're translating
1626 * @intspec: the interrupt specifier data from the DT
1627 * @intsize: the number of entries in @intspec
1628 * @out_hwirq: pointer at which to write the hwirq number
1629 * @out_type: pointer at which to write the interrupt type
1630 *
1631 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1632 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1633 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1634 * INTx value to obtain the hwirq number.
1635 *
1636 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1637 */
1638static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1639 struct device_node *node,
1640 const u32 *intspec,
1641 unsigned int intsize,
1642 unsigned long *out_hwirq,
1643 unsigned int *out_type)
1644{
1645 const u32 intx = intspec[0];
1646
1647 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1648 return -EINVAL;
1649
1650 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1651 return 0;
1652}
1653
ab0724ff 1654#ifdef CONFIG_PCIEPORTBUS
415e12b2 1655extern bool pcie_ports_disabled;
5352a44a 1656extern bool pcie_ports_native;
ab0724ff
MT		 1657#else
1658#define pcie_ports_disabled true
5352a44a 1659#define pcie_ports_native false
ab0724ff 1660#endif
415e12b2 1661
aff5d055
HK		 1662#define PCIE_LINK_STATE_L0S BIT(0)
1663#define PCIE_LINK_STATE_L1 BIT(1)
1664#define PCIE_LINK_STATE_CLKPM BIT(2)
1665#define PCIE_LINK_STATE_L1_1 BIT(3)
1666#define PCIE_LINK_STATE_L1_2 BIT(4)
1667#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1668#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
7ce2e76a 1669
4c859804 1670#ifdef CONFIG_PCIEASPM
7ce2e76a
KW		 1671int pci_disable_link_state(struct pci_dev *pdev, int state);
1672int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1673void pcie_no_aspm(void);
f39d5b72 1674bool pcie_aspm_support_enabled(void);
accd2dd7 1675bool pcie_aspm_enabled(struct pci_dev *pdev);
4c859804 1676#else
7ce2e76a
KW		 1677static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1678{ return 0; }
1679static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1680{ return 0; }
1681static inline void pcie_no_aspm(void) { }
4c859804 1682static inline bool pcie_aspm_support_enabled(void) { return false; }
accd2dd7 1683static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
3e1b1600
AP		 1684#endif
1685
415e12b2 1686#ifdef CONFIG_PCIEAER
415e12b2
RW		 1687bool pci_aer_available(void);
1688#else
415e12b2
RW		 1689static inline bool pci_aer_available(void) { return false; }
1690#endif
1691
cef74409
GK		 1692bool pci_ats_disabled(void);
1693
1d71eb53
VCG		 1694#ifdef CONFIG_PCIE_PTM
1695int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
e8bdc5ea 1696void pci_disable_ptm(struct pci_dev *dev);
014408cd 1697bool pcie_ptm_enabled(struct pci_dev *dev);
1d71eb53
VCG		 1698#else
1699static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1700{ return -EINVAL; }
e8bdc5ea 1701static inline void pci_disable_ptm(struct pci_dev *dev) { }
014408cd
VCG		 1702static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1703{ return false; }
1d71eb53
VCG		 1704#endif
1705
f39d5b72
BH		 1706void pci_cfg_access_lock(struct pci_dev *dev);
1707bool pci_cfg_access_trylock(struct pci_dev *dev);
1708void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1709
dfd5bb23 1710void pci_dev_lock(struct pci_dev *dev);
e3a9b121
LC		 1711int pci_dev_trylock(struct pci_dev *dev);
1712void pci_dev_unlock(struct pci_dev *dev);
1713
4352dfd5
GKH		 1714/*
1715 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1716 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1717 * configuration space.
1718 */
32a2eea7
JG		 1719#ifdef CONFIG_PCI_DOMAINS
1720extern int pci_domains_supported;
1721#else
1722enum { pci_domains_supported = 0 };
2ee546c4
BH		 1723static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1724static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
32a2eea7 1725#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1726
670ba0c8
CM		 1727/*
1728 * Generic implementation for PCI domain support. If your
1729 * architecture does not need custom management of PCI
1730 * domains then this implementation will be used
1731 */
1732#ifdef CONFIG_PCI_DOMAINS_GENERIC
1733static inline int pci_domain_nr(struct pci_bus *bus)
1734{
1735 return bus->domain_nr;
1736}
2ab51dde
TN		 1737#ifdef CONFIG_ACPI
1738int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1739#else
2ab51dde
TN		 1740static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1741{ return 0; }
1742#endif
9c7cb891 1743int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1744#endif
1745
0aa0f5d1 1746/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1747typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1748 unsigned int command_bits, u32 flags);
f39d5b72 1749void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1750
be9d2e89
JT		 1751static inline int
1752pci_request_io_regions(struct pci_dev *pdev, const char *name)
1753{
1754 return pci_request_selected_regions(pdev,
1755 pci_select_bars(pdev, IORESOURCE_IO), name);
1756}
1757
1758static inline void
1759pci_release_io_regions(struct pci_dev *pdev)
1760{
1761 return pci_release_selected_regions(pdev,
1762 pci_select_bars(pdev, IORESOURCE_IO));
1763}
1764
1765static inline int
1766pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1767{
1768 return pci_request_selected_regions(pdev,
1769 pci_select_bars(pdev, IORESOURCE_MEM), name);
1770}
1771
1772static inline void
1773pci_release_mem_regions(struct pci_dev *pdev)
1774{
1775 return pci_release_selected_regions(pdev,
1776 pci_select_bars(pdev, IORESOURCE_MEM));
1777}
1778
4352dfd5 1779#else /* CONFIG_PCI is not enabled */
1da177e4 1780
5bbe029f
BH		 1781static inline void pci_set_flags(int flags) { }
1782static inline void pci_add_flags(int flags) { }
1783static inline void pci_clear_flags(int flags) { }
1784static inline int pci_has_flag(int flag) { return 0; }
1785
1da177e4 1786/*
0aa0f5d1
BH		 1787 * If the system does not have PCI, clearly these return errors. Define
1788 * these as simple inline functions to avoid hair in drivers.
1da177e4 1789 */
05cca6e5
GKH		 1790#define _PCI_NOP(o, s, t) \
1791 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1792 int where, t val) \
1da177e4 1793 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1794
1795#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1796 _PCI_NOP(o, word, u16 x) \
1797 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1798_PCI_NOP_ALL(read, *)
1799_PCI_NOP_ALL(write,)
1800
d42552c3 1801static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1802 unsigned int device,
1803 struct pci_dev *from)
2ee546c4 1804{ return NULL; }
d42552c3 1805
05cca6e5
GKH		 1806static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1807 unsigned int device,
1808 unsigned int ss_vendor,
1809 unsigned int ss_device,
b08508c4 1810 struct pci_dev *from)
2ee546c4 1811{ return NULL; }
1da177e4 1812
05cca6e5
GKH		 1813static inline struct pci_dev *pci_get_class(unsigned int class,
1814 struct pci_dev *from)
2ee546c4 1815{ return NULL; }
1da177e4 1816
877fee2a
HG		 1817
1818static inline int pci_dev_present(const struct pci_device_id *ids)
1819{ return 0; }
1820
ed4aaadb 1821#define no_pci_devices() (1)
1da177e4
LT		 1822#define pci_dev_put(dev) do { } while (0)
1823
2ee546c4
BH		 1824static inline void pci_set_master(struct pci_dev *dev) { }
1825static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1826static inline void pci_disable_device(struct pci_dev *dev) { }
977da073 1827static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
05cca6e5 1828static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1829{ return -EBUSY; }
817f9916
AS		 1830static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1831 struct module *owner,
1832 const char *mod_name)
2ee546c4 1833{ return 0; }
05cca6e5 1834static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1835{ return 0; }
1836static inline void pci_unregister_driver(struct pci_driver *drv) { }
f646c2a0 1837static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1838{ return 0; }
05cca6e5
GKH		 1839static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1840 int cap)
2ee546c4 1841{ return 0; }
05cca6e5 1842static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1843{ return 0; }
05cca6e5 1844
70c0923b
JK		 1845static inline u64 pci_get_dsn(struct pci_dev *dev)
1846{ return 0; }
1847
1da177e4 1848/* Power management related routines */
2ee546c4
BH		 1849static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1850static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1851static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1852{ return 0; }
3449248c 1853static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1854{ return 0; }
05cca6e5
GKH		 1855static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1856 pm_message_t state)
2ee546c4 1857{ return PCI_D0; }
05cca6e5
GKH		 1858static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1859 int enable)
2ee546c4 1860{ return 0; }
48a92a81 1861
afd29f90
MW		 1862static inline struct resource *pci_find_resource(struct pci_dev *dev,
1863 struct resource *res)
1864{ return NULL; }
05cca6e5 1865static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1866{ return -EIO; }
1867static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1868
00dcc7cf
RH		 1869static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1870 phys_addr_t addr, resource_size_t size)
1871{ return -EINVAL; }
1872
c5076cfe
TN		 1873static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1874
d80d0217
RD		 1875static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1876{ return NULL; }
d80d0217
RD		 1877static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1878 unsigned int devfn)
1879{ return NULL; }
7912af5c
RD		 1880static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1881 unsigned int bus, unsigned int devfn)
1882{ return NULL; }
d80d0217 1883
2ee546c4
BH		 1884static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1885static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
12ea6cad 1886
fb8a0d9d
WM		 1887#define dev_is_pci(d) (false)
1888#define dev_is_pf(d) (false)
fe594932
GU		 1889static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1890{ return false; }
80db6f08
NC		 1891static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1892 struct device_node *node,
1893 const u32 *intspec,
1894 unsigned int intsize,
1895 unsigned long *out_hwirq,
1896 unsigned int *out_type)
1897{ return -EINVAL; }
9c212009
LR		 1898
1899static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1900 struct pci_dev *dev)
1901{ return NULL; }
b9ae16d8 1902static inline bool pci_ats_disabled(void) { return true; }
0d8006dd
HX		 1903
1904static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1905{
1906 return -EINVAL;
1907}
1908
1909static inline int
1910pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1911 unsigned int max_vecs, unsigned int flags,
1912 struct irq_affinity *aff_desc)
1913{
1914 return -ENOSPC;
1915}
0d8006dd
HX		 1916static inline int
1917pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1918 unsigned int max_vecs, unsigned int flags)
1919{
5c0997dc 1920 return -ENOSPC;
0d8006dd 1921}
5c0997dc 1922#endif /* CONFIG_PCI */
0d8006dd 1923
4352dfd5
GKH		 1924/* Include architecture-dependent settings and functions */
1925
1926#include <asm/pci.h>
1da177e4 1927
0ad722f1 1928/*
f7195824
DW		 1929 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1930 * is expected to be an offset within that region.
1931 *
f7195824
DW		 1932 */
1933int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1934 struct vm_area_struct *vma,
1935 enum pci_mmap_state mmap_state, int write_combine);
11df1954 1936
ae749c7a
DW		 1937#ifndef arch_can_pci_mmap_wc
1938#define arch_can_pci_mmap_wc() 0
1939#endif
2bea36fd 1940
e854d8b2
DW		 1941#ifndef arch_can_pci_mmap_io
1942#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1943#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1944#else
1945int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1946#endif
ae749c7a 1947
92016ba5
JO		 1948#ifndef pci_root_bus_fwnode
1949#define pci_root_bus_fwnode(bus) NULL
1950#endif
1951
0aa0f5d1
BH		 1952/*
1953 * These helpers provide future and backwards compatibility
1954 * for accessing popular PCI BAR info
1955 */
05cca6e5
GKH		 1956#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1957#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1958#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1959#define pci_resource_len(dev,bar) \
ca32b531 1960 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
05cca6e5
GKH		 1961 \
1962 (pci_resource_end((dev), (bar)) - \
1963 pci_resource_start((dev), (bar)) + 1))
1da177e4 1964
0aa0f5d1
BH		 1965/*
1966 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1967 * driver-specific data. They are really just a wrapper around
1968 * the generic device structure functions of these calls.
1969 */
05cca6e5 1970static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1971{
1972 return dev_get_drvdata(&pdev->dev);
1973}
1974
05cca6e5 1975static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1976{
1977 dev_set_drvdata(&pdev->dev, data);
1978}
1979
2fc90f61 1980static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1981{
c6c4f070 1982 return dev_name(&pdev->dev);
1da177e4
LT		 1983}
1984
8221a013
BH		 1985void pci_resource_to_user(const struct pci_dev *dev, int bar,
1986 const struct resource *rsrc,
1987 resource_size_t *start, resource_size_t *end);
2311b1f2 1988
1da177e4 1989/*
0aa0f5d1
BH		 1990 * The world is not perfect and supplies us with broken PCI devices.
1991 * For at least a part of these bugs we need a work-around, so both
1992 * generic (drivers/pci/quirks.c) and per-architecture code can define
1993 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1994 */
1995
1996struct pci_fixup {
0aa0f5d1
BH		 1997 u16 vendor; /* Or PCI_ANY_ID */
1998 u16 device; /* Or PCI_ANY_ID */
1999 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 2000 unsigned int class_shift; /* should be 0, 8, 16 */
c9d8b55f
AB		 2001#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2002 int hook_offset;
2003#else
1da177e4 2004 void (*hook)(struct pci_dev *dev);
c9d8b55f 2005#endif
1da177e4
LT		 2006};
2007
2008enum pci_fixup_pass {
2009 pci_fixup_early, /* Before probing BARs */
2010 pci_fixup_header, /* After reading configuration header */
2011 pci_fixup_final, /* Final phase of device fixups */
2012 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 2013 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 2014 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 2015 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 2016 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 2017};
2018
c9d8b55f 2019#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
09a4e4d9 2020#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
c9d8b55f
AB		 2021 class_shift, hook) \
2022 __ADDRESSABLE(hook) \
2023 asm(".section " #sec ", \"a\" \n" \
2024 ".balign 16 \n" \
2025 ".short " #vendor ", " #device " \n" \
2026 ".long " #class ", " #class_shift " \n" \
2027 ".long " #hook " - . \n" \
2028 ".previous \n");
09a4e4d9
ST		 2029
2030/*
2031 * Clang's LTO may rename static functions in C, but has no way to
2032 * handle such renamings when referenced from inline asm. To work
2033 * around this, create global C stubs for these cases.
2034 */
2035#ifdef CONFIG_LTO_CLANG
2036#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2037 class_shift, hook, stub) \
5659b598
ST		 2038 void stub(struct pci_dev *dev); \
2039 void stub(struct pci_dev *dev) \
09a4e4d9
ST		 2040 { \
2041 hook(dev); \
2042 } \
2043 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2044 class_shift, stub)
2045#else
2046#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2047 class_shift, hook, stub) \
2048 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2049 class_shift, hook)
2050#endif
2051
c9d8b55f
AB		 2052#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2053 class_shift, hook) \
2054 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
09a4e4d9 2055 class_shift, hook, __UNIQUE_ID(hook))
c9d8b55f 2056#else
1da177e4 2057/* Anonymous variables would be nice... */
f4ca5c6a
YL		 2058#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2059 class_shift, hook) \
ecf61c78 2060 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 2061 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2062 = { vendor, device, class, class_shift, hook };
c9d8b55f 2063#endif
f4ca5c6a
YL		 2064
2065#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2066 class_shift, hook) \
2067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2068 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2069#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2070 class_shift, hook) \
2071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2072 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2073#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2074 class_shift, hook) \
2075 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2076 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2077#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2078 class_shift, hook) \
2079 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2080 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2081#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2082 class_shift, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2084 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2085#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2086 class_shift, hook) \
2087 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2088 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 2089#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2090 class_shift, hook) \
2091 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2092 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 2093#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2094 class_shift, hook) \
2095 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2096 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 2097
1da177e4
LT		 2098#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2099 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 2100 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2101#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2102 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 2103 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2104#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2105 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 2106 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 2107#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2108 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 2109 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 2110#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2111 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 2112 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2113#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2114 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 2115 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 2116#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2117 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 2118 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 2119#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2120 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 2121 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 2122
93177a74 2123#ifdef CONFIG_PCI_QUIRKS
1da177e4 2124void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 2125#else
2126static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 2127 struct pci_dev *dev) { }
93177a74 2128#endif
1da177e4 2129
05cca6e5 2130void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 2131void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 2132void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 2133int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2134int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 2135 const char *name);
fb7ebfe4 2136void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 2137
1da177e4 2138extern int pci_pci_problems;
236561e5 2139#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 2140#define PCIPCI_TRITON 2
2141#define PCIPCI_NATOMA 4
2142#define PCIPCI_VIAETBF 8
2143#define PCIPCI_VSFX 16
236561e5
AC		 2144#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2145#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 2146
4516a618
AN		 2147extern unsigned long pci_cardbus_io_size;
2148extern unsigned long pci_cardbus_mem_size;
15856ad5 2149extern u8 pci_dfl_cache_line_size;
ac1aa47b 2150extern u8 pci_cache_line_size;
4516a618 2151
f7625980 2152/* Architecture-specific versions may override these (weak) */
19792a08 2153void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 2154void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 2155int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2156 enum pcie_reset_state state);
06dc660e 2157int pcibios_device_add(struct pci_dev *dev);
6ae32c53 2158void pcibios_release_device(struct pci_dev *dev);
5d32a665 2159#ifdef CONFIG_PCI
a43ae58c 2160void pcibios_penalize_isa_irq(int irq, int active);
5d32a665
SK		 2161#else
2162static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2163#endif
890e4847
JL		 2164int pcibios_alloc_irq(struct pci_dev *dev);
2165void pcibios_free_irq(struct pci_dev *dev);
619e6f34 2166resource_size_t pcibios_default_alignment(void);
575e3348 2167
935c760e 2168#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 2169void __init pci_mmcfg_early_init(void);
2170void __init pci_mmcfg_late_init(void);
7752d5cf 2171#else
bb63b421 2172static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 2173static inline void pci_mmcfg_late_init(void) { }
2174#endif
2175
642c92da 2176int pci_ext_cfg_avail(void);
0ef5f8f6 2177
1684f5dd 2178void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 2179void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 2180
dd7cc44d 2181#ifdef CONFIG_PCI_IOV
b07579c0
WY		 2182int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2183int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
21ca9fb6 2184int pci_iov_vf_id(struct pci_dev *dev);
a7e9f240 2185void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
f39d5b72
BH		 2186int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2187void pci_disable_sriov(struct pci_dev *dev);
a1ceea67
NS		 2188
2189int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
753f6124
JS		 2190int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2191void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 2192int pci_num_vf(struct pci_dev *dev);
5a8eb242 2193int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 2194int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2195int pci_sriov_get_totalvfs(struct pci_dev *dev);
8effc395 2196int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
0e6c9122 2197resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 2198void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 2199
2200/* Arch may override these (weak) */
2201int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2202int pcibios_sriov_disable(struct pci_dev *pdev);
2203resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 2204#else
b07579c0
WY		 2205static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2206{
2207 return -ENOSYS;
2208}
2209static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2210{
2211 return -ENOSYS;
2212}
21ca9fb6
JG		 2213
2214static inline int pci_iov_vf_id(struct pci_dev *dev)
2215{
2216 return -ENOSYS;
2217}
2218
a7e9f240
JG		 2219static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2220 struct pci_driver *pf_driver)
2221{
2222 return ERR_PTR(-EINVAL);
2223}
2224
dd7cc44d 2225static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2226{ return -ENODEV; }
a1ceea67
NS		 2227
2228static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2229 struct pci_dev *virtfn, int id)
2230{
2231 return -ENODEV;
2232}
753f6124 2233static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2234{
2235 return -ENOSYS;
2236}
2237static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2238 int id) { }
2ee546c4 2239static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2240static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2241static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2242{ return 0; }
bff73156 2243static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2244{ return 0; }
bff73156 2245static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2246{ return 0; }
8effc395 2247#define pci_sriov_configure_simple NULL
0e6c9122
WY		 2248static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2249{ return 0; }
608c0d88 2250static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 2251#endif
2252
c825bc94 2253#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2254void pci_hp_create_module_link(struct pci_slot *pci_slot);
2255void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2256#endif
2257
d7b7e605
KK		 2258/**
2259 * pci_pcie_cap - get the saved PCIe capability offset
2260 * @dev: PCI device
2261 *
2262 * PCIe capability offset is calculated at PCI device initialization
2263 * time and saved in the data structure. This function returns saved
2264 * PCIe capability offset. Using this instead of pci_find_capability()
2265 * reduces unnecessary search in the PCI configuration space. If you
2266 * need to calculate PCIe capability offset from raw device for some
2267 * reasons, please use pci_find_capability() instead.
2268 */
2269static inline int pci_pcie_cap(struct pci_dev *dev)
2270{
2271 return dev->pcie_cap;
2272}
2273
7eb776c4
KK		 2274/**
2275 * pci_is_pcie - check if the PCI device is PCI Express capable
2276 * @dev: PCI device
2277 *
a895c28a 2278 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2279 */
2280static inline bool pci_is_pcie(struct pci_dev *dev)
2281{
a895c28a 2282 return pci_pcie_cap(dev);
7eb776c4
KK		 2283}
2284
7c9c003c
MS		 2285/**
2286 * pcie_caps_reg - get the PCIe Capabilities Register
2287 * @dev: PCI device
2288 */
2289static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2290{
2291 return dev->pcie_flags_reg;
2292}
2293
786e2288
YW		 2294/**
2295 * pci_pcie_type - get the PCIe device/port type
2296 * @dev: PCI device
2297 */
2298static inline int pci_pcie_type(const struct pci_dev *dev)
2299{
1c531d82 2300 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2301}
2302
6ae72bfa
YY		 2303/**
2304 * pcie_find_root_port - Get the PCIe root port device
2305 * @dev: PCI device
2306 *
2307 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2308 * for a given PCI/PCIe Device.
2309 */
e784930b
JT		 2310static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2311{
5396956c
MW		 2312 while (dev) {
2313 if (pci_is_pcie(dev) &&
2314 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2315 return dev;
2316 dev = pci_upstream_bridge(dev);
e784930b 2317 }
6ae72bfa 2318
e784930b
JT		 2319 return NULL;
2320}
2321
5d990b62 2322void pci_request_acs(void);
ad805758
AW		 2323bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2324bool pci_acs_path_enabled(struct pci_dev *start,
2325 struct pci_dev *end, u16 acs_flags);
430a2368 2326int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2327
7ad506fa 2328#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2329#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2330
2331/* Large Resource Data Type Tag Item Names */
2332#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2333#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2334#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2335
2336#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2337#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2338#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2339
4067a854 2340#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
16efafa3 2341#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
4067a854
MC		 2342#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2343#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2344#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2345
a2ce7662 2346/**
76f3c032
HK		 2347 * pci_vpd_alloc - Allocate buffer and read VPD into it
2348 * @dev: PCI device
2349 * @size: pointer to field where VPD length is returned
9eb45d5c 2350 *
76f3c032 2351 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
9eb45d5c 2352 */
76f3c032 2353void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
9eb45d5c 2354
e1d5bdab 2355/**
acfbb1b8
HK		 2356 * pci_vpd_find_id_string - Locate id string in VPD
2357 * @buf: Pointer to buffered VPD data
2358 * @len: The length of the buffer area in which to search
2359 * @size: Pointer to field where length of id string is returned
e1d5bdab 2360 *
acfbb1b8 2361 * Returns the index of the id string or -ENOENT if not found.
e1d5bdab 2362 */
acfbb1b8 2363int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
e1d5bdab 2364
b55ac1b2 2365/**
9e515c9f
HK		 2366 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2367 * @buf: Pointer to buffered VPD data
2368 * @len: The length of the buffer area in which to search
2369 * @kw: The keyword to search for
2370 * @size: Pointer to field where length of found keyword data is returned
b55ac1b2 2371 *
9e515c9f
HK		 2372 * Returns the index of the information field keyword data or -ENOENT if
2373 * not found.
b55ac1b2 2374 */
9e515c9f
HK		 2375int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2376 const char *kw, unsigned int *size);
b55ac1b2 2377
4067a854 2378/**
6107e5cb
HK		 2379 * pci_vpd_check_csum - Check VPD checksum
2380 * @buf: Pointer to buffered VPD data
2381 * @len: VPD size
4067a854 2382 *
6107e5cb 2383 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
4067a854 2384 */
6107e5cb 2385int pci_vpd_check_csum(const void *buf, unsigned int len);
4067a854 2386
98d9f30c
BH		 2387/* PCI <-> OF binding helpers */
2388#ifdef CONFIG_OF
2389struct device_node;
b165e2b6 2390struct irq_domain;
b165e2b6 2391struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
85aabbd7 2392bool pci_host_of_has_msi_map(struct device *dev);
98d9f30c
BH		 2393
2394/* Arch may override this (weak) */
723ec4d0 2395struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2396
0aa0f5d1 2397#else /* CONFIG_OF */
b165e2b6
MZ		 2398static inline struct irq_domain *
2399pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
85aabbd7 2400static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
98d9f30c
BH		 2401#endif /* CONFIG_OF */
2402
ad32eb2d
BM		 2403static inline struct device_node *
2404pci_device_to_OF_node(const struct pci_dev *pdev)
2405{
2406 return pdev ? pdev->dev.of_node : NULL;
2407}
2408
2409static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2410{
2411 return bus ? bus->dev.of_node : NULL;
2412}
2413
471036b2
SS		 2414#ifdef CONFIG_ACPI
2415struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2416
2417void
2418pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
52525b7a 2419bool pci_pr3_present(struct pci_dev *pdev);
471036b2
SS		 2420#else
2421static inline struct irq_domain *
2422pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
46b4bff6 2423static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
471036b2
SS		 2424#endif
2425
eb740b5f
GS		 2426#ifdef CONFIG_EEH
2427static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2428{
2429 return pdev->dev.archdata.edev;
2430}
2431#endif
2432
09298542 2433void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
338c3149 2434bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2435int pci_for_each_dma_alias(struct pci_dev *pdev,
2436 int (*fn)(struct pci_dev *pdev,
2437 u16 alias, void *data), void *data);
2438
0aa0f5d1 2439/* Helper functions for operation of device flag */
ce052984
EZ		 2440static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2441{
2442 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2443}
2444static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2445{
2446 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2447}
2448static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2449{
2450 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2451}
19bdb6e4
AW		 2452
2453/**
2454 * pci_ari_enabled - query ARI forwarding status
2455 * @bus: the PCI bus
2456 *
2457 * Returns true if ARI forwarding is enabled.
2458 */
2459static inline bool pci_ari_enabled(struct pci_bus *bus)
2460{
2461 return bus->self && bus->self->ari_enabled;
2462}
bc4b024a 2463
8531e283
LW		 2464/**
2465 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2466 * @pdev: PCI device to check
2467 *
2468 * Walk upwards from @pdev and check for each encountered bridge if it's part
2469 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2470 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2471 */
2472static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2473{
2474 struct pci_dev *parent = pdev;
2475
2476 if (pdev->is_thunderbolt)
2477 return true;
2478
2479 while ((parent = pci_upstream_bridge(parent)))
2480 if (parent->is_thunderbolt)
2481 return true;
2482
2483 return false;
2484}
2485
2e28bc84 2486#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
3ecac020
ME		 2487void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2488#endif
856e1eb9 2489
0194425a
TG		 2490struct msi_domain_template;
2491
2492bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
2493 unsigned int hwsize, void *data);
2494
79687789 2495#include <linux/dma-mapping.h>
bc4b024a 2496
7506dc79
FL		 2497#define pci_printk(level, pdev, fmt, arg...) \
2498 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2499
2500#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2501#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2502#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2503#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2504#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2505#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2506#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2507#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2508
a88a7b3e
BH		 2509#define pci_notice_ratelimited(pdev, fmt, arg...) \
2510 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2511
7f1c62c4
KW		 2512#define pci_info_ratelimited(pdev, fmt, arg...) \
2513 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2514
12bcae44
BH		 2515#define pci_WARN(pdev, condition, fmt, arg...) \
2516 WARN(condition, "%s %s: " fmt, \
2517 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2518
2519#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2520 WARN_ONCE(condition, "%s %s: " fmt, \
2521 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2522
1da177e4 2523#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)