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blk-mq: really fix plug list flushing for nomerge queues
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
1da177e4
LT		 16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
1da177e4 19
778382e0
DW		 20#include <linux/mod_devicetable.h>
21
1da177e4 22#include <linux/types.h>
98db6f19 23#include <linux/init.h>
1da177e4
LT		 24#include <linux/ioport.h>
25#include <linux/list.h>
4a7fb636 26#include <linux/compiler.h>
1da177e4 27#include <linux/errno.h>
f46753c5 28#include <linux/kobject.h>
60063497 29#include <linux/atomic.h>
1da177e4 30#include <linux/device.h>
1388cc96 31#include <linux/io.h>
14d76b68 32#include <linux/resource_ext.h>
607ca46e 33#include <uapi/linux/pci.h>
1da177e4 34
7e7a43c3
AB		 35#include <linux/pci_ids.h>
36
85467136
SK		 37/*
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
41 *
42 * 7:3 = slot
43 * 2:0 = function
f7625980
BH		 44 *
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 46 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 47 * the following kernel-only defines are being added here.
85467136 48 */
63ddc0b8 49#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 50/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52
f46753c5
AC		 53/* pci_slot represents a physical slot */
54struct pci_slot {
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
59 struct kobject kobj;
60};
61
0ad772ec
AC		 62static inline const char *pci_slot_name(const struct pci_slot *slot)
63{
64 return kobject_name(&slot->kobj);
65}
66
1da177e4
LT		 67/* File state for mmap()s on /proc/bus/pci/X/Y */
68enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71};
72
fde09c6d
YZ		 73/*
74 * For PCI devices, the region numbers are assigned this way:
75 */
76enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
d1b054da
YZ		 84 /* device specific resources */
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
fde09c6d
YZ		 90 /* resources assigned to buses behind the bridge */
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97 /* total resources associated with a PCI device */
98 PCI_NUM_RESOURCES,
99
100 /* preserve this for compatibility */
cda57bf9 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 102};
1da177e4
LT		 103
104typedef int __bitwise pci_power_t;
105
4352dfd5
GKH		 106#define PCI_D0 ((pci_power_t __force) 0)
107#define PCI_D1 ((pci_power_t __force) 1)
108#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 109#define PCI_D3hot ((pci_power_t __force) 3)
110#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 111#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 112#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 113
00240c38
AS		 114/* Remember to update this when the list above changes! */
115extern const char *pci_power_names[];
116
117static inline const char *pci_power_name(pci_power_t state)
118{
119 return pci_power_names[1 + (int) state];
120}
121
448bd857
HY		 122#define PCI_PM_D2_DELAY 200
123#define PCI_PM_D3_WAIT 10
124#define PCI_PM_D3COLD_WAIT 100
125#define PCI_PM_BUS_WAIT 50
aa8c6c93 126
392a1ce7 127/** The pci_channel state describes connectivity between the CPU and
128 * the pci device. If some PCI bus between here and the pci device
129 * has crashed or locked up, this info is reflected here.
130 */
131typedef unsigned int __bitwise pci_channel_state_t;
132
133enum pci_channel_state {
134 /* I/O channel is in normal state */
135 pci_channel_io_normal = (__force pci_channel_state_t) 1,
136
137 /* I/O to channel is blocked */
138 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
139
140 /* PCI card is dead */
141 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
142};
143
f7bdd12d
BK		 144typedef unsigned int __bitwise pcie_reset_state_t;
145
146enum pcie_reset_state {
147 /* Reset is NOT asserted (Use to deassert reset) */
148 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
149
f7625980 150 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 151 pcie_warm_reset = (__force pcie_reset_state_t) 2,
152
f7625980 153 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 154 pcie_hot_reset = (__force pcie_reset_state_t) 3
155};
156
ba698ad4
DM		 157typedef unsigned short __bitwise pci_dev_flags_t;
158enum pci_dev_flags {
159 /* INTX_DISABLE in PCI_COMMAND register disables MSI
160 * generation too.
161 */
6b121592 162 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 163 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 164 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 165 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 166 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 167 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 168 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 169 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
170 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 171 /* Do not use bus resets for device */
172 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 173 /* Do not use PM reset even if device advertises NoSoftRst- */
174 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 175 /* Get VPD from function 0 VPD */
176 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
ba698ad4
DM		 177};
178
e1d3a908
SA		 179enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182};
183
6e325a62
MT		 184typedef unsigned short __bitwise pci_bus_flags_t;
185enum pci_bus_flags {
d556ad4b
PO		 186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 188};
189
59da381e
JK		 190/* These values come from the PCI Express Spec */
191enum pcie_link_width {
192 PCIE_LNK_WIDTH_RESRV = 0x00,
193 PCIE_LNK_X1 = 0x01,
194 PCIE_LNK_X2 = 0x02,
195 PCIE_LNK_X4 = 0x04,
196 PCIE_LNK_X8 = 0x08,
197 PCIE_LNK_X12 = 0x0C,
198 PCIE_LNK_X16 = 0x10,
199 PCIE_LNK_X32 = 0x20,
200 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
201};
202
536c8cb4
MW		 203/* Based on the PCI Hotplug Spec, but some values are made up by us */
204enum pci_bus_speed {
205 PCI_SPEED_33MHz = 0x00,
206 PCI_SPEED_66MHz = 0x01,
207 PCI_SPEED_66MHz_PCIX = 0x02,
208 PCI_SPEED_100MHz_PCIX = 0x03,
209 PCI_SPEED_133MHz_PCIX = 0x04,
210 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
211 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
212 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
213 PCI_SPEED_66MHz_PCIX_266 = 0x09,
214 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
215 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 216 AGP_UNKNOWN = 0x0c,
217 AGP_1X = 0x0d,
218 AGP_2X = 0x0e,
219 AGP_4X = 0x0f,
220 AGP_8X = 0x10,
536c8cb4
MW		 221 PCI_SPEED_66MHz_PCIX_533 = 0x11,
222 PCI_SPEED_100MHz_PCIX_533 = 0x12,
223 PCI_SPEED_133MHz_PCIX_533 = 0x13,
224 PCIE_SPEED_2_5GT = 0x14,
225 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 226 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 227 PCI_SPEED_UNKNOWN = 0xff,
228};
229
24a4742f 230struct pci_cap_saved_data {
fd0f7f73
AW		 231 u16 cap_nr;
232 bool cap_extended;
24a4742f 233 unsigned int size;
41017f0c
SL		 234 u32 data[0];
235};
236
24a4742f
AW		 237struct pci_cap_saved_state {
238 struct hlist_node next;
239 struct pci_cap_saved_data cap;
240};
241
7d715a6c 242struct pcie_link_state;
ee69439c 243struct pci_vpd;
d1b054da 244struct pci_sriov;
302b4215 245struct pci_ats;
ee69439c 246
1da177e4
LT		 247/*
248 * The pci_dev structure is used to describe PCI devices.
249 */
250struct pci_dev {
1da177e4
LT		 251 struct list_head bus_list; /* node in per-bus list */
252 struct pci_bus *bus; /* bus this device is on */
253 struct pci_bus *subordinate; /* bus this device bridges to */
254
255 void *sysdata; /* hook for sys-specific extension */
256 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 257 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 258
259 unsigned int devfn; /* encoded device & function index */
260 unsigned short vendor;
261 unsigned short device;
262 unsigned short subsystem_vendor;
263 unsigned short subsystem_device;
264 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 265 u8 revision; /* PCI revision, low byte of class word */
1da177e4 266 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
f7625980 267 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 268 u8 msi_cap; /* MSI capability offset */
269 u8 msix_cap; /* MSI-X capability offset */
f7625980 270 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
1da177e4 271 u8 rom_base_reg; /* which config register controls the ROM */
f7625980
BH		 272 u8 pin; /* which interrupt pin this device uses */
273 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
338c3149 274 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
1da177e4
LT		 275
276 struct pci_driver *driver; /* which driver has allocated this device */
277 u64 dma_mask; /* Mask of the bits of bus address this
278 device implements. Normally this is
279 0xffffffff. You only need to change
280 this if your device has broken DMA
281 or supports 64-bit transfers. */
282
4d57cdfa
FT		 283 struct device_dma_parameters dma_parms;
284
1da177e4
LT		 285 pci_power_t current_state; /* Current operating state. In ACPI-speak,
286 this is D0-D3, D0 being fully functional,
287 and D3 being off. */
703860ed 288 u8 pm_cap; /* PM capability offset */
337001b6
RW		 289 unsigned int pme_support:5; /* Bitmask of states from which PME#
290 can be generated */
c7f48656 291 unsigned int pme_interrupt:1;
379021d5 292 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 293 unsigned int d1_support:1; /* Low power state D1 is supported */
294 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 295 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
296 unsigned int no_d3cold:1; /* D3cold is forbidden */
297 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 298 unsigned int mmio_always_on:1; /* disallow turning off io/mem
299 decoding during bar sizing */
e80bb09d 300 unsigned int wakeup_prepared:1;
448bd857
HY		 301 unsigned int runtime_d3cold:1; /* whether go through runtime
302 D3cold, not set for devices
303 powered on/off by the
304 corresponding bridge */
b440bde7 305 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
1ae861e6 306 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 307 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 308
7d715a6c 309#ifdef CONFIG_PCIEASPM
f7625980 310 struct pcie_link_state *link_state; /* ASPM link state */
7d715a6c
SL		 311#endif
312
392a1ce7 313 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 314 struct device dev; /* Generic device interface */
315
1da177e4
LT		 316 int cfg_size; /* Size of configuration space */
317
318 /*
319 * Instead of touching interrupt line and base address registers
320 * directly, use the values stored here. They might be different!
321 */
322 unsigned int irq;
323 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
324
58d9a38f 325 bool match_driver; /* Skip attaching driver */
1da177e4 326 /* These fields are used by common fixups */
f7625980 327 unsigned int transparent:1; /* Subtractive decode PCI bridge */
1da177e4
LT		 328 unsigned int multifunction:1;/* Part of multi-function device */
329 /* keep track of device state */
8a1bc901 330 unsigned int is_added:1;
1da177e4 331 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 332 unsigned int no_msi:1; /* device may not use msi */
f144d149 333 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
fb51ccbf 334 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 335 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 336 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
f7625980 337 unsigned int msi_enabled:1;
99dc804d 338 unsigned int msix_enabled:1;
58c3a727 339 unsigned int ari_enabled:1; /* ARI forwarding */
d544d75a 340 unsigned int ats_enabled:1; /* Address Translation Service */
9ac7849e 341 unsigned int is_managed:1;
260d703a 342 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 343 unsigned int state_saved:1;
d1b054da 344 unsigned int is_physfn:1;
dd7cc44d 345 unsigned int is_virtfn:1;
711d5779 346 unsigned int reset_fn:1;
28760489 347 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 348 unsigned int __aer_firmware_first_valid:1;
349 unsigned int __aer_firmware_first:1;
fbebb9fd 350 unsigned int broken_intx_masking:1;
2b28ae19 351 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
cffe0a2b 352 unsigned int irq_managed:1;
d0751b98 353 unsigned int has_secondary_link:1;
b84106b4 354 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
ba698ad4 355 pci_dev_flags_t dev_flags;
bae94d02 356 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 357
1da177e4 358 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 359 struct hlist_head saved_cap_space;
1da177e4
LT		 360 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
361 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
362 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 363 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 364#ifdef CONFIG_PCI_MSI
1c51b50c 365 const struct attribute_group **msi_irq_groups;
ded86d8d 366#endif
94e61088 367 struct pci_vpd *vpd;
466b3ddf 368#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 369 union {
370 struct pci_sriov *sriov; /* SR-IOV capability related */
371 struct pci_dev *physfn; /* the PF this VF is associated with */
372 };
67930995
BH		 373 u16 ats_cap; /* ATS Capability offset */
374 u8 ats_stu; /* ATS Smallest Translation Unit */
d544d75a 375 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
d1b054da 376#endif
dbd3fc33 377 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 378 size_t romlen; /* Length of ROM if it's not from the BAR */
782a985d 379 char *driver_override; /* Driver name to force a match */
1da177e4
LT		 380};
381
dda56549
Y		 382static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
383{
384#ifdef CONFIG_PCI_IOV
385 if (dev->is_virtfn)
386 dev = dev->physfn;
387#endif
dda56549
Y		 388 return dev;
389}
390
3c6e6ae7 391struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 392
1da177e4
LT		 393#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
394#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
395
a7369f1f
LV		 396static inline int pci_channel_offline(struct pci_dev *pdev)
397{
398 return (pdev->error_state != pci_channel_io_normal);
399}
400
5a21d70d 401struct pci_host_bridge {
7b543663 402 struct device dev;
5a21d70d 403 struct pci_bus *bus; /* root bus */
14d76b68 404 struct list_head windows; /* resource_entry */
4fa2649a
YL		 405 void (*release_fn)(struct pci_host_bridge *);
406 void *release_data;
e33caa82 407 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
7c7a0e94
GP		 408 /* Resource alignment requirements */
409 resource_size_t (*align_resource)(struct pci_dev *dev,
410 const struct resource *res,
411 resource_size_t start,
412 resource_size_t size,
413 resource_size_t align);
5a21d70d 414};
41017f0c 415
7b543663 416#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94
GP		 417
418struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
419
4fa2649a
YL		 420void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
421 void (*release_fn)(struct pci_host_bridge *),
422 void *release_data);
7b543663 423
6c0cc950
RW		 424int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
425
2fe2abf8
BH		 426/*
427 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
428 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
429 * buses below host bridges or subtractive decode bridges) go in the list.
430 * Use pci_bus_for_each_resource() to iterate through all the resources.
431 */
432
433/*
434 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
435 * and there's no way to program the bridge with the details of the window.
436 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
437 * decode bit set, because they are explicit and can be programmed with _SRS.
438 */
439#define PCI_SUBTRACTIVE_DECODE 0x1
440
441struct pci_bus_resource {
442 struct list_head list;
443 struct resource *res;
444 unsigned int flags;
445};
4352dfd5
GKH		 446
447#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 448
449struct pci_bus {
450 struct list_head node; /* node in list of buses */
451 struct pci_bus *parent; /* parent bus this bridge is on */
452 struct list_head children; /* list of child buses */
453 struct list_head devices; /* list of devices on this bus */
454 struct pci_dev *self; /* bridge device as seen by parent */
67546762
YW		 455 struct list_head slots; /* list of slots on this bus;
456 protected by pci_slot_mutex */
2fe2abf8
BH		 457 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
458 struct list_head resources; /* address space routed to this bus */
92f02430 459 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 460
461 struct pci_ops *ops; /* configuration access functions */
c2791b80 462 struct msi_controller *msi; /* MSI controller */
1da177e4
LT		 463 void *sysdata; /* hook for sys-specific extension */
464 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
465
466 unsigned char number; /* bus number */
467 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 468 unsigned char max_bus_speed; /* enum pci_bus_speed */
469 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 470#ifdef CONFIG_PCI_DOMAINS_GENERIC
471 int domain_nr;
472#endif
1da177e4
LT		 473
474 char name[48];
475
476 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
f7625980 477 pci_bus_flags_t bus_flags; /* inherited by child buses */
1da177e4 478 struct device *bridge;
fd7d1ced 479 struct device dev;
1da177e4
LT		 480 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
481 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 482 unsigned int is_added:1;
1da177e4
LT		 483};
484
fd7d1ced 485#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 486
79af72d7 487/*
f7625980 488 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 489 * false otherwise
77a0dfcd
BH		 490 *
491 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
492 * This is incorrect because "virtual" buses added for SR-IOV (via
493 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 494 */
495static inline bool pci_is_root_bus(struct pci_bus *pbus)
496{
497 return !(pbus->parent);
498}
499
1c86438c
YW		 500/**
501 * pci_is_bridge - check if the PCI device is a bridge
502 * @dev: PCI device
503 *
504 * Return true if the PCI device is bridge whether it has subordinate
505 * or not.
506 */
507static inline bool pci_is_bridge(struct pci_dev *dev)
508{
509 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
510 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
511}
512
c6bde215
BH		 513static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
514{
515 dev = pci_physfn(dev);
516 if (pci_is_root_bus(dev->bus))
517 return NULL;
518
519 return dev->bus->self;
520}
521
6675a601
MK		 522struct device *pci_get_host_bridge_device(struct pci_dev *dev);
523void pci_put_host_bridge_device(struct device *dev);
524
16cf0ebc
RW		 525#ifdef CONFIG_PCI_MSI
526static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
527{
528 return pci_dev->msi_enabled || pci_dev->msix_enabled;
529}
530#else
531static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
532#endif
533
1da177e4
LT		 534/*
535 * Error values that may be returned by PCI functions.
536 */
537#define PCIBIOS_SUCCESSFUL 0x00
538#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
539#define PCIBIOS_BAD_VENDOR_ID 0x83
540#define PCIBIOS_DEVICE_NOT_FOUND 0x86
541#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
542#define PCIBIOS_SET_FAILED 0x88
543#define PCIBIOS_BUFFER_TOO_SMALL 0x89
544
a6961651 545/*
f7625980 546 * Translate above to generic errno for passing back through non-PCI code.
a6961651
AW		 547 */
548static inline int pcibios_err_to_errno(int err)
549{
550 if (err <= PCIBIOS_SUCCESSFUL)
551 return err; /* Assume already errno */
552
553 switch (err) {
554 case PCIBIOS_FUNC_NOT_SUPPORTED:
555 return -ENOENT;
556 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 557 return -ENOTTY;
a6961651
AW		 558 case PCIBIOS_DEVICE_NOT_FOUND:
559 return -ENODEV;
560 case PCIBIOS_BAD_REGISTER_NUMBER:
561 return -EFAULT;
562 case PCIBIOS_SET_FAILED:
563 return -EIO;
564 case PCIBIOS_BUFFER_TOO_SMALL:
565 return -ENOSPC;
566 }
567
d97ffe23 568 return -ERANGE;
a6961651
AW		 569}
570
1da177e4
LT		 571/* Low-level architecture-dependent routines */
572
573struct pci_ops {
057bd2e0
TR		 574 int (*add_bus)(struct pci_bus *bus);
575 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 576 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 577 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
578 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
579};
580
b6ce068a
MW		 581/*
582 * ACPI needs to be able to access PCI config space before we've done a
583 * PCI bus scan and created pci_bus structures.
584 */
f39d5b72
BH		 585int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
586 int reg, int len, u32 *val);
587int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
588 int reg, int len, u32 val);
1da177e4 589
3a9ad0b4
YL		 590#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
591typedef u64 pci_bus_addr_t;
592#else
593typedef u32 pci_bus_addr_t;
594#endif
595
1da177e4 596struct pci_bus_region {
3a9ad0b4
YL		 597 pci_bus_addr_t start;
598 pci_bus_addr_t end;
1da177e4
LT		 599};
600
601struct pci_dynids {
602 spinlock_t lock; /* protects list, index */
603 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 604};
605
f7625980
BH		 606
607/*
608 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
609 * a set of callbacks in struct pci_error_handlers, that device driver
610 * will be notified of PCI bus errors, and will be driven to recovery
611 * when an error occurs.
392a1ce7 612 */
613
614typedef unsigned int __bitwise pci_ers_result_t;
615
616enum pci_ers_result {
617 /* no result/none/not supported in device driver */
618 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
619
620 /* Device driver can recover without slot reset */
621 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
622
623 /* Device driver wants slot to be reset. */
624 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
625
626 /* Device has completely failed, is unrecoverable */
627 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
628
629 /* Device driver is fully recovered and operational */
630 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 631
632 /* No AER capabilities registered for the driver */
633 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 634};
635
636/* PCI bus error event callbacks */
05cca6e5 637struct pci_error_handlers {
392a1ce7 638 /* PCI bus error detected on this device */
639 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 640 enum pci_channel_state error);
392a1ce7 641
642 /* MMIO has been re-enabled, but not DMA */
643 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
644
645 /* PCI Express link has been reset */
646 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
647
648 /* PCI slot has been reset */
649 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
650
3ebe7f9f
KB		 651 /* PCI function reset prepare or completed */
652 void (*reset_notify)(struct pci_dev *dev, bool prepare);
653
392a1ce7 654 /* Device driver may resume normal operations */
655 void (*resume)(struct pci_dev *dev);
656};
657
392a1ce7 658
1da177e4
LT		 659struct module;
660struct pci_driver {
661 struct list_head node;
42b21932 662 const char *name;
1da177e4
LT		 663 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
664 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
665 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
666 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 667 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
668 int (*resume_early) (struct pci_dev *dev);
1da177e4 669 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 670 void (*shutdown) (struct pci_dev *dev);
1789382a 671 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 672 const struct pci_error_handlers *err_handler;
1da177e4
LT		 673 struct device_driver driver;
674 struct pci_dynids dynids;
675};
676
05cca6e5 677#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 678
90a1ba0c 679/**
9f9351bb 680 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 681 * @_table: device table name
682 *
92e112fd 683 * This macro is deprecated and should not be used in new code.
90a1ba0c 684 */
9f9351bb 685#define DEFINE_PCI_DEVICE_TABLE(_table) \
15856ad5 686 const struct pci_device_id _table[]
90a1ba0c 687
1da177e4
LT		 688/**
689 * PCI_DEVICE - macro used to describe a specific pci device
690 * @vend: the 16 bit PCI Vendor ID
691 * @dev: the 16 bit PCI Device ID
692 *
693 * This macro is used to create a struct pci_device_id that matches a
694 * specific device. The subvendor and subdevice fields will be set to
695 * PCI_ANY_ID.
696 */
697#define PCI_DEVICE(vend,dev) \
698 .vendor = (vend), .device = (dev), \
699 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
700
3d567e0e
NNS		 701/**
702 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
703 * @vend: the 16 bit PCI Vendor ID
704 * @dev: the 16 bit PCI Device ID
705 * @subvend: the 16 bit PCI Subvendor ID
706 * @subdev: the 16 bit PCI Subdevice ID
707 *
708 * This macro is used to create a struct pci_device_id that matches a
709 * specific device with subsystem information.
710 */
711#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
712 .vendor = (vend), .device = (dev), \
713 .subvendor = (subvend), .subdevice = (subdev)
714
1da177e4
LT		 715/**
716 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
717 * @dev_class: the class, subclass, prog-if triple for this device
718 * @dev_class_mask: the class mask for this device
719 *
720 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 721 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 722 * fields will be set to PCI_ANY_ID.
723 */
724#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
725 .class = (dev_class), .class_mask = (dev_class_mask), \
726 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
727 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
728
1597cacb
AC		 729/**
730 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c1309040
MR		 731 * @vend: the vendor name
732 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 733 *
734 * This macro is used to create a struct pci_device_id that matches a
735 * specific PCI device. The subvendor, and subdevice fields will be set
736 * to PCI_ANY_ID. The macro allows the next field to follow as the device
737 * private data.
738 */
739
c1309040
MR		 740#define PCI_VDEVICE(vend, dev) \
741 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
742 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 743
5bbe029f
BH		 744enum {
745 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
746 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
747 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
748 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
749 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
750 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
751 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
752};
753
1da177e4
LT		 754/* these external functions are only available when PCI support is enabled */
755#ifdef CONFIG_PCI
756
5bbe029f
BH		 757extern unsigned int pci_flags;
758
759static inline void pci_set_flags(int flags) { pci_flags = flags; }
760static inline void pci_add_flags(int flags) { pci_flags |= flags; }
761static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
762static inline int pci_has_flag(int flag) { return pci_flags & flag; }
763
a58674ff 764void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 765
766enum pcie_bus_config_types {
27d868b5
KB		 767 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
768 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
769 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
770 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
771 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
b03e7495
JM		 772};
773
774extern enum pcie_bus_config_types pcie_bus_config;
775
1da177e4
LT		 776extern struct bus_type pci_bus_type;
777
f7625980
BH		 778/* Do NOT directly access these two variables, unless you are arch-specific PCI
779 * code, or PCI core code. */
1da177e4 780extern struct list_head pci_root_buses; /* list of all known PCI buses */
f7625980 781/* Some device drivers need know if PCI is initiated */
f39d5b72 782int no_pci_devices(void);
1da177e4 783
3c449ed0 784void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 785void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 786void pcibios_add_bus(struct pci_bus *bus);
787void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 788void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 789int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 790/* Architecture-specific versions may override this (weak) */
05cca6e5 791char *pcibios_setup(char *str);
1da177e4
LT		 792
793/* Used only when drivers/pci/setup.c is used */
3b7a17fc 794resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 795 resource_size_t,
e31dd6e4 796 resource_size_t);
1da177e4
LT		 797void pcibios_update_irq(struct pci_dev *, int irq);
798
2d1c8618
BH		 799/* Weak but can be overriden by arch */
800void pci_fixup_cardbus(struct pci_bus *);
801
1da177e4
LT		 802/* Generic PCI functions used internally */
803
fc279850 804void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 805 struct resource *res);
fc279850 806void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 807 struct pci_bus_region *region);
d1fd4fb6 808void pcibios_scan_specific_bus(int busn);
f39d5b72 809struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 810void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 811struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 812struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
813 struct pci_ops *ops, void *sysdata,
814 struct list_head *resources);
98a35831
YL		 815int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
816int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
817void pci_bus_release_busn_res(struct pci_bus *b);
d2a7926d
LP		 818struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
819 struct pci_ops *ops, void *sysdata,
820 struct list_head *resources,
821 struct msi_controller *msi);
15856ad5 822struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 823 struct pci_ops *ops, void *sysdata,
824 struct list_head *resources);
05cca6e5
GKH		 825struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
826 int busnr);
3749c51a 827void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 828struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 829 const char *name,
830 struct hotplug_slot *hotplug);
f46753c5 831void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 832#ifdef CONFIG_SYSFS
833void pci_dev_assign_slot(struct pci_dev *dev);
834#else
835static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
836#endif
1da177e4 837int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 838struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 839void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 840unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 841void pci_bus_add_device(struct pci_dev *dev);
1da177e4 842void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 843struct resource *pci_find_parent_resource(const struct pci_dev *dev,
844 struct resource *res);
c56d4450 845struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 846u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 847int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 848u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 849struct pci_dev *pci_dev_get(struct pci_dev *dev);
850void pci_dev_put(struct pci_dev *dev);
851void pci_remove_bus(struct pci_bus *b);
852void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 853void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 854void pci_stop_root_bus(struct pci_bus *bus);
855void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 856void pci_setup_cardbus(struct pci_bus *bus);
f39d5b72 857void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 858#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
859#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
860#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 861
862/* Generic PCI functions exported to card drivers */
863
388c8c16
JB		 864enum pci_lost_interrupt_reason {
865 PCI_LOST_IRQ_NO_INFORMATION = 0,
866 PCI_LOST_IRQ_DISABLE_MSI,
867 PCI_LOST_IRQ_DISABLE_MSIX,
868 PCI_LOST_IRQ_DISABLE_ACPI,
869};
870enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 871int pci_find_capability(struct pci_dev *dev, int cap);
872int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
873int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 874int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 875int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
876int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 877struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 878
d42552c3
AM		 879struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
880 struct pci_dev *from);
05cca6e5 881struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 882 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 883 struct pci_dev *from);
05cca6e5 884struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 885struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
886 unsigned int devfn);
887static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
888 unsigned int devfn)
889{
890 return pci_get_domain_bus_and_slot(0, bus, devfn);
891}
05cca6e5 892struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 893int pci_dev_present(const struct pci_device_id *ids);
894
05cca6e5
GKH		 895int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
896 int where, u8 *val);
897int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
898 int where, u16 *val);
899int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
900 int where, u32 *val);
901int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
902 int where, u8 val);
903int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
904 int where, u16 val);
905int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
906 int where, u32 val);
1f94a94f
RH		 907
908int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
909 int where, int size, u32 *val);
910int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
911 int where, int size, u32 val);
912int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
913 int where, int size, u32 *val);
914int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
915 int where, int size, u32 val);
916
a72b46c3 917struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 918
bf362f75 919static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 920{
05cca6e5 921 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 922}
bf362f75 923static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 924{
05cca6e5 925 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 926}
bf362f75 927static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 928 u32 *val)
1da177e4 929{
05cca6e5 930 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 931}
bf362f75 932static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 933{
05cca6e5 934 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 935}
bf362f75 936static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 937{
05cca6e5 938 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 939}
bf362f75 940static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 941 u32 val)
1da177e4 942{
05cca6e5 943 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 944}
945
8c0d3a02
JL		 946int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
947int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
948int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
949int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
950int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
951 u16 clear, u16 set);
952int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
953 u32 clear, u32 set);
954
955static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
956 u16 set)
957{
958 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
959}
960
961static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
962 u32 set)
963{
964 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
965}
966
967static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
968 u16 clear)
969{
970 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
971}
972
973static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
974 u32 clear)
975{
976 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
977}
978
c63587d7
AW		 979/* user-space driven config access */
980int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
981int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
982int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
983int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
984int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
985int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
986
4a7fb636 987int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 988int __must_check pci_enable_device_io(struct pci_dev *dev);
989int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 990int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 991int __must_check pcim_enable_device(struct pci_dev *pdev);
992void pcim_pin_device(struct pci_dev *pdev);
993
296ccb08
YS		 994static inline int pci_is_enabled(struct pci_dev *pdev)
995{
996 return (atomic_read(&pdev->enable_cnt) > 0);
997}
998
9ac7849e
TH		 999static inline int pci_is_managed(struct pci_dev *pdev)
1000{
1001 return pdev->is_managed;
1002}
1003
1da177e4 1004void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1005
1006extern unsigned int pcibios_max_latency;
1da177e4 1007void pci_set_master(struct pci_dev *dev);
6a479079 1008void pci_clear_master(struct pci_dev *dev);
96c55900 1009
f7bdd12d 1010int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1011int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1012#define HAVE_PCI_SET_MWI
4a7fb636 1013int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 1014int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1015void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1016void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1017bool pci_intx_mask_supported(struct pci_dev *dev);
1018bool pci_check_and_mask_intx(struct pci_dev *dev);
1019bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1020int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1021int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1022int pcix_get_max_mmrbc(struct pci_dev *dev);
1023int pcix_get_mmrbc(struct pci_dev *dev);
1024int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1025int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1026int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1027int pcie_get_mps(struct pci_dev *dev);
1028int pcie_set_mps(struct pci_dev *dev, int mps);
81377c8d
JK		 1029int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1030 enum pcie_link_width *width);
8c1c699f 1031int __pci_reset_function(struct pci_dev *dev);
a96d627a 1032int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1033int pci_reset_function(struct pci_dev *dev);
61cf16d8 1034int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1035int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1036int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1037int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1038int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1039int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1040int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1041void pci_reset_secondary_bus(struct pci_dev *dev);
1042void pcibios_reset_secondary_bus(struct pci_dev *dev);
64e8674f 1043void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1044void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1045int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1046int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 1047int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1048bool pci_device_is_present(struct pci_dev *pdev);
08249651 1049void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4
LT		 1050
1051/* ROM control related routines */
e416de5e
AC		 1052int pci_enable_rom(struct pci_dev *pdev);
1053void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1054void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1055void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1056size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1057void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1058
1059/* Power management related routines */
1060int pci_save_state(struct pci_dev *dev);
1d3c16a8 1061void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1062struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1063int pci_load_saved_state(struct pci_dev *dev,
1064 struct pci_saved_state *state);
ffbdd3f7
AW		 1065int pci_load_and_free_saved_state(struct pci_dev *dev,
1066 struct pci_saved_state **state);
fd0f7f73
AW		 1067struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1068struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1069 u16 cap);
1070int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1071int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1072 u16 cap, unsigned int size);
0e5dd46b 1073int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1074int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1075pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1076bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1077void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 1078int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1079 bool runtime, bool enable);
0235c4fc 1080int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1081int pci_prepare_to_sleep(struct pci_dev *dev);
1082int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1083bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1084bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1085void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 1086
6cbf8214
RW		 1087static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1088 bool enable)
1089{
1090 return __pci_enable_wake(dev, state, false, enable);
1091}
1da177e4 1092
425c1b22
AW		 1093/* PCI Virtual Channel */
1094int pci_save_vc_state(struct pci_dev *dev);
1095void pci_restore_vc_state(struct pci_dev *dev);
1096void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1097
bb209c82
BH		 1098/* For use by arch with custom probe code */
1099void set_pcie_port_type(struct pci_dev *pdev);
1100void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1101
ce5ccdef 1102/* Functions for PCI Hotplug drivers to use */
05cca6e5 1103int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1104unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1105unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1106void pci_lock_rescan_remove(void);
1107void pci_unlock_rescan_remove(void);
ce5ccdef 1108
287d19ce
SH		 1109/* Vital product data routines */
1110ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1111ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1112int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1113
1da177e4 1114/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1115resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1116void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 1117void pci_bus_size_bridges(struct pci_bus *bus);
1118int pci_claim_resource(struct pci_dev *, int);
8505e729 1119int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1120void pci_assign_unassigned_resources(void);
6841ec68 1121void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1122void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1123void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1da177e4 1124void pdev_enable_device(struct pci_dev *);
842de40d 1125int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 1126void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 1127 int (*)(const struct pci_dev *, u8, u8));
1da177e4 1128#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1129int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1130int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1131void pci_release_regions(struct pci_dev *);
4a7fb636 1132int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1133int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1134void pci_release_region(struct pci_dev *, int);
c87deff7 1135int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1136int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1137void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1138
1139/* drivers/pci/bus.c */
fe830ef6
JL		 1140struct pci_bus *pci_bus_get(struct pci_bus *bus);
1141void pci_bus_put(struct pci_bus *bus);
45ca9e97 1142void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1143void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1144 resource_size_t offset);
45ca9e97 1145void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 1146void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1147struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1148void pci_bus_remove_resources(struct pci_bus *bus);
1149
89a74ecc 1150#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1151 for (i = 0; \
1152 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1153 i++)
89a74ecc 1154
4a7fb636
AM		 1155int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1156 struct resource *res, resource_size_t size,
1157 resource_size_t align, resource_size_t min,
664c2848 1158 unsigned long type_mask,
3b7a17fc
DB		 1159 resource_size_t (*alignf)(void *,
1160 const struct resource *,
b26b2d49
DB		 1161 resource_size_t,
1162 resource_size_t),
4a7fb636 1163 void *alignf_data);
1da177e4 1164
8b921acf 1165
c5076cfe
TN		 1166int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1167unsigned long pci_address_to_pio(phys_addr_t addr);
1168phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf
LD		 1169int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1170
3a9ad0b4 1171static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1172{
1173 struct pci_bus_region region;
1174
1175 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1176 return region.start;
1177}
1178
863b18f4 1179/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1180int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1181 const char *mod_name);
bba81165
AM		 1182
1183/*
1184 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1185 */
1186#define pci_register_driver(driver) \
1187 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1188
05cca6e5 1189void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1190
1191/**
1192 * module_pci_driver() - Helper macro for registering a PCI driver
1193 * @__pci_driver: pci_driver struct
1194 *
1195 * Helper macro for PCI drivers which do not do anything special in module
1196 * init/exit. This eliminates a lot of boilerplate. Each module may only
1197 * use this macro once, and calling it replaces module_init() and module_exit()
1198 */
1199#define module_pci_driver(__pci_driver) \
1200 module_driver(__pci_driver, pci_register_driver, \
1201 pci_unregister_driver)
1202
b4eb6cdb
PG		 1203/**
1204 * builtin_pci_driver() - Helper macro for registering a PCI driver
1205 * @__pci_driver: pci_driver struct
1206 *
1207 * Helper macro for PCI drivers which do not do anything special in their
1208 * init code. This eliminates a lot of boilerplate. Each driver may only
1209 * use this macro once, and calling it replaces device_initcall(...)
1210 */
1211#define builtin_pci_driver(__pci_driver) \
1212 builtin_driver(__pci_driver, pci_register_driver)
1213
05cca6e5 1214struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1215int pci_add_dynid(struct pci_driver *drv,
1216 unsigned int vendor, unsigned int device,
1217 unsigned int subvendor, unsigned int subdevice,
1218 unsigned int class, unsigned int class_mask,
1219 unsigned long driver_data);
05cca6e5
GKH		 1220const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1221 struct pci_dev *dev);
1222int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1223 int pass);
1da177e4 1224
70298c6e 1225void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1226 void *userdata);
ac7dc65a 1227int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1228unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1229void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1230resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1231 unsigned long type);
978d2d68 1232resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
cecf4864 1233
3448a19d
DA		 1234#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1235#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1236
deb2d2ec 1237int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1238 unsigned int command_bits, u32 flags);
fe537670 1239
1da177e4
LT		 1240/* kmem_cache style wrapper around pci_alloc_consistent() */
1241
f41b1771 1242#include <linux/pci-dma.h>
1da177e4
LT		 1243#include <linux/dmapool.h>
1244
1245#define pci_pool dma_pool
1246#define pci_pool_create(name, pdev, size, align, allocation) \
1247 dma_pool_create(name, &pdev->dev, size, align, allocation)
1248#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1249#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1250#define pci_pool_zalloc(pool, flags, handle) \
1251 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1252#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1253
1da177e4 1254struct msix_entry {
16dbef4a 1255 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1256 u16 entry; /* driver uses to specify entry, OS writes */
1257};
1258
4c859804
BH		 1259#ifdef CONFIG_PCI_MSI
1260int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72
BH		 1261void pci_msi_shutdown(struct pci_dev *dev);
1262void pci_disable_msi(struct pci_dev *dev);
4c859804 1263int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72
BH		 1264int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1265void pci_msix_shutdown(struct pci_dev *dev);
1266void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1267void pci_restore_msi_state(struct pci_dev *dev);
1268int pci_msi_enabled(void);
4c859804 1269int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
f7fc32cb
AG		 1270static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1271{
1272 int rc = pci_enable_msi_range(dev, nvec, nvec);
1273 if (rc < 0)
1274 return rc;
1275 return 0;
1276}
4c859804
BH		 1277int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1278 int minvec, int maxvec);
f7fc32cb
AG		 1279static inline int pci_enable_msix_exact(struct pci_dev *dev,
1280 struct msix_entry *entries, int nvec)
1281{
1282 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1283 if (rc < 0)
1284 return rc;
1285 return 0;
1286}
4c859804 1287#else
2ee546c4 1288static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1289static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1290static inline void pci_disable_msi(struct pci_dev *dev) { }
1291static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
05cca6e5
GKH		 1292static inline int pci_enable_msix(struct pci_dev *dev,
1293 struct msix_entry *entries, int nvec)
2ee546c4
BH		 1294{ return -ENOSYS; }
1295static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1296static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1297static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1298static inline int pci_msi_enabled(void) { return 0; }
302a2523
AG		 1299static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1300 int maxvec)
2ee546c4 1301{ return -ENOSYS; }
f7fc32cb
AG		 1302static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1303{ return -ENOSYS; }
302a2523
AG		 1304static inline int pci_enable_msix_range(struct pci_dev *dev,
1305 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1306{ return -ENOSYS; }
f7fc32cb
AG		 1307static inline int pci_enable_msix_exact(struct pci_dev *dev,
1308 struct msix_entry *entries, int nvec)
1309{ return -ENOSYS; }
1da177e4
LT		 1310#endif
1311
ab0724ff 1312#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1313extern bool pcie_ports_disabled;
1314extern bool pcie_ports_auto;
ab0724ff
MT		 1315#else
1316#define pcie_ports_disabled true
1317#define pcie_ports_auto false
1318#endif
415e12b2 1319
4c859804 1320#ifdef CONFIG_PCIEASPM
f39d5b72 1321bool pcie_aspm_support_enabled(void);
4c859804
BH		 1322#else
1323static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1324#endif
1325
415e12b2
RW		 1326#ifdef CONFIG_PCIEAER
1327void pci_no_aer(void);
1328bool pci_aer_available(void);
1329#else
1330static inline void pci_no_aer(void) { }
1331static inline bool pci_aer_available(void) { return false; }
1332#endif
1333
4c859804 1334#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1335void pcie_set_ecrc_checking(struct pci_dev *dev);
1336void pcie_ecrc_get_policy(char *str);
4c859804 1337#else
2ee546c4
BH		 1338static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1339static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1340#endif
1341
034cd97e 1342#define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1c8d7b0a 1343
8b955b0d 1344#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1345/* The functions a driver should call */
1346int ht_create_irq(struct pci_dev *dev, int idx);
1347void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1348#endif /* CONFIG_HT_IRQ */
1349
edc90fee
BH		 1350#ifdef CONFIG_PCI_ATS
1351/* Address Translation Service */
1352void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1353int pci_enable_ats(struct pci_dev *dev, int ps);
1354void pci_disable_ats(struct pci_dev *dev);
1355int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1356#else
ff9bee89
BH		 1357static inline void pci_ats_init(struct pci_dev *d) { }
1358static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1359static inline void pci_disable_ats(struct pci_dev *d) { }
1360static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1361#endif
1362
f39d5b72
BH		 1363void pci_cfg_access_lock(struct pci_dev *dev);
1364bool pci_cfg_access_trylock(struct pci_dev *dev);
1365void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1366
4352dfd5
GKH		 1367/*
1368 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1369 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1370 * configuration space.
1371 */
32a2eea7
JG		 1372#ifdef CONFIG_PCI_DOMAINS
1373extern int pci_domains_supported;
41e5c0f8 1374int pci_get_new_domain_nr(void);
32a2eea7
JG		 1375#else
1376enum { pci_domains_supported = 0 };
2ee546c4
BH		 1377static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1378static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
41e5c0f8 1379static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
32a2eea7 1380#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1381
670ba0c8
CM		 1382/*
1383 * Generic implementation for PCI domain support. If your
1384 * architecture does not need custom management of PCI
1385 * domains then this implementation will be used
1386 */
1387#ifdef CONFIG_PCI_DOMAINS_GENERIC
1388static inline int pci_domain_nr(struct pci_bus *bus)
1389{
1390 return bus->domain_nr;
1391}
1392void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1393#else
1394static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1395 struct device *parent)
1396{
1397}
1398#endif
1399
95a8b6ef
MT		 1400/* some architectures require additional setup to direct VGA traffic */
1401typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1402 unsigned int command_bits, u32 flags);
f39d5b72 1403void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1404
4352dfd5 1405#else /* CONFIG_PCI is not enabled */
1da177e4 1406
5bbe029f
BH		 1407static inline void pci_set_flags(int flags) { }
1408static inline void pci_add_flags(int flags) { }
1409static inline void pci_clear_flags(int flags) { }
1410static inline int pci_has_flag(int flag) { return 0; }
1411
1da177e4
LT		 1412/*
1413 * If the system does not have PCI, clearly these return errors. Define
1414 * these as simple inline functions to avoid hair in drivers.
1415 */
1416
05cca6e5
GKH		 1417#define _PCI_NOP(o, s, t) \
1418 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1419 int where, t val) \
1da177e4 1420 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1421
1422#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1423 _PCI_NOP(o, word, u16 x) \
1424 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1425_PCI_NOP_ALL(read, *)
1426_PCI_NOP_ALL(write,)
1427
d42552c3 1428static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1429 unsigned int device,
1430 struct pci_dev *from)
2ee546c4 1431{ return NULL; }
d42552c3 1432
05cca6e5
GKH		 1433static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1434 unsigned int device,
1435 unsigned int ss_vendor,
1436 unsigned int ss_device,
b08508c4 1437 struct pci_dev *from)
2ee546c4 1438{ return NULL; }
1da177e4 1439
05cca6e5
GKH		 1440static inline struct pci_dev *pci_get_class(unsigned int class,
1441 struct pci_dev *from)
2ee546c4 1442{ return NULL; }
1da177e4
LT		 1443
1444#define pci_dev_present(ids) (0)
ed4aaadb 1445#define no_pci_devices() (1)
1da177e4
LT		 1446#define pci_dev_put(dev) do { } while (0)
1447
2ee546c4
BH		 1448static inline void pci_set_master(struct pci_dev *dev) { }
1449static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1450static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1451static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1452{ return -EBUSY; }
05cca6e5
GKH		 1453static inline int __pci_register_driver(struct pci_driver *drv,
1454 struct module *owner)
2ee546c4 1455{ return 0; }
05cca6e5 1456static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1457{ return 0; }
1458static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1459static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1460{ return 0; }
05cca6e5
GKH		 1461static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1462 int cap)
2ee546c4 1463{ return 0; }
05cca6e5 1464static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1465{ return 0; }
05cca6e5 1466
1da177e4 1467/* Power management related routines */
2ee546c4
BH		 1468static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1469static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1470static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1471{ return 0; }
3449248c 1472static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1473{ return 0; }
05cca6e5
GKH		 1474static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1475 pm_message_t state)
2ee546c4 1476{ return PCI_D0; }
05cca6e5
GKH		 1477static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1478 int enable)
2ee546c4 1479{ return 0; }
48a92a81 1480
05cca6e5 1481static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1482{ return -EIO; }
1483static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1484
c5076cfe
TN		 1485static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1486
2ee546c4 1487static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1488static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1489{ return 0; }
2ee546c4 1490static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1491
d80d0217
RD		 1492static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1493{ return NULL; }
d80d0217
RD		 1494static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1495 unsigned int devfn)
1496{ return NULL; }
d80d0217
RD		 1497static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1498 unsigned int devfn)
1499{ return NULL; }
1500
2ee546c4
BH		 1501static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1502static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
41e5c0f8 1503static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
12ea6cad 1504
fb8a0d9d
WM		 1505#define dev_is_pci(d) (false)
1506#define dev_is_pf(d) (false)
1507#define dev_num_vf(d) (0)
4352dfd5 1508#endif /* CONFIG_PCI */
1da177e4 1509
4352dfd5
GKH		 1510/* Include architecture-dependent settings and functions */
1511
1512#include <asm/pci.h>
1da177e4 1513
92016ba5
JO		 1514#ifndef pci_root_bus_fwnode
1515#define pci_root_bus_fwnode(bus) NULL
1516#endif
1517
1da177e4
LT		 1518/* these helpers provide future and backwards compatibility
1519 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1520#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1521#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1522#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1523#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1524 ((pci_resource_start((dev), (bar)) == 0 && \
1525 pci_resource_end((dev), (bar)) == \
1526 pci_resource_start((dev), (bar))) ? 0 : \
1527 \
1528 (pci_resource_end((dev), (bar)) - \
1529 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1530
1531/* Similar to the helpers above, these manipulate per-pci_dev
1532 * driver-specific data. They are really just a wrapper around
1533 * the generic device structure functions of these calls.
1534 */
05cca6e5 1535static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1536{
1537 return dev_get_drvdata(&pdev->dev);
1538}
1539
05cca6e5 1540static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1541{
1542 dev_set_drvdata(&pdev->dev, data);
1543}
1544
1545/* If you want to know what to call your pci_dev, ask this function.
1546 * Again, it's a wrapper around the generic device.
1547 */
2fc90f61 1548static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1549{
c6c4f070 1550 return dev_name(&pdev->dev);
1da177e4
LT		 1551}
1552
2311b1f2
ME		 1553
1554/* Some archs don't want to expose struct resource to userland as-is
1555 * in sysfs and /proc
1556 */
1557#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1558static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1559 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1560 resource_size_t *end)
2311b1f2
ME		 1561{
1562 *start = rsrc->start;
1563 *end = rsrc->end;
1564}
1565#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1566
1567
1da177e4
LT		 1568/*
1569 * The world is not perfect and supplies us with broken PCI devices.
1570 * For at least a part of these bugs we need a work-around, so both
1571 * generic (drivers/pci/quirks.c) and per-architecture code can define
1572 * fixup hooks to be called for particular buggy devices.
1573 */
1574
1575struct pci_fixup {
f4ca5c6a
YL		 1576 u16 vendor; /* You can use PCI_ANY_ID here of course */
1577 u16 device; /* You can use PCI_ANY_ID here of course */
1578 u32 class; /* You can use PCI_ANY_ID here too */
1579 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1580 void (*hook)(struct pci_dev *dev);
1581};
1582
1583enum pci_fixup_pass {
1584 pci_fixup_early, /* Before probing BARs */
1585 pci_fixup_header, /* After reading configuration header */
1586 pci_fixup_final, /* Final phase of device fixups */
1587 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1588 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1589 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1590 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1591 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1592};
1593
1594/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1595#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1596 class_shift, hook) \
ecf61c78 1597 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1598 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1599 = { vendor, device, class, class_shift, hook };
1600
1601#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1602 class_shift, hook) \
1603 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1604 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1605#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1606 class_shift, hook) \
1607 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1608 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1609#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1610 class_shift, hook) \
1611 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1612 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1613#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1614 class_shift, hook) \
1615 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1616 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1617#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1618 class_shift, hook) \
1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1620 resume##hook, vendor, device, class, \
f4ca5c6a
YL		 1621 class_shift, hook)
1622#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1623 class_shift, hook) \
1624 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1625 resume_early##hook, vendor, device, \
f4ca5c6a
YL		 1626 class, class_shift, hook)
1627#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1628 class_shift, hook) \
1629 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1630 suspend##hook, vendor, device, class, \
f4ca5c6a 1631 class_shift, hook)
7d2a01b8
AN		 1632#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1633 class_shift, hook) \
1634 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1635 suspend_late##hook, vendor, device, \
1636 class, class_shift, hook)
f4ca5c6a 1637
1da177e4
LT		 1638#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1639 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1640 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1641#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1642 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1643 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1644#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1645 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1646 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1647#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1648 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1649 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1650#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1651 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1652 resume##hook, vendor, device, \
f4ca5c6a 1653 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1654#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1655 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1656 resume_early##hook, vendor, device, \
f4ca5c6a 1657 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1658#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1659 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1660 suspend##hook, vendor, device, \
f4ca5c6a 1661 PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1662#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1663 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1664 suspend_late##hook, vendor, device, \
1665 PCI_ANY_ID, 0, hook)
1da177e4 1666
93177a74 1667#ifdef CONFIG_PCI_QUIRKS
1da177e4 1668void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1669int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1670int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1671#else
1672static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1673 struct pci_dev *dev) { }
ad805758
AW		 1674static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1675 u16 acs_flags)
1676{
1677 return -ENOTTY;
1678}
c1d61c9b
AW		 1679static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1680{
1681 return -ENOTTY;
1682}
93177a74 1683#endif
1da177e4 1684
05cca6e5 1685void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1686void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1687void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1688int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1689int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1690 const char *name);
fb7ebfe4 1691void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1692
1da177e4 1693extern int pci_pci_problems;
236561e5 1694#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1695#define PCIPCI_TRITON 2
1696#define PCIPCI_NATOMA 4
1697#define PCIPCI_VIAETBF 8
1698#define PCIPCI_VSFX 16
236561e5
AC		 1699#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1700#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1701
4516a618
AN		 1702extern unsigned long pci_cardbus_io_size;
1703extern unsigned long pci_cardbus_mem_size;
15856ad5 1704extern u8 pci_dfl_cache_line_size;
ac1aa47b 1705extern u8 pci_cache_line_size;
4516a618 1706
28760489
EB		 1707extern unsigned long pci_hotplug_io_size;
1708extern unsigned long pci_hotplug_mem_size;
1709
f7625980 1710/* Architecture-specific versions may override these (weak) */
19792a08 1711void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1712void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1713int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1714 enum pcie_reset_state state);
eca0d467 1715int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1716void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1717void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1718int pcibios_alloc_irq(struct pci_dev *dev);
1719void pcibios_free_irq(struct pci_dev *dev);
575e3348 1720
699c1985
SO		 1721#ifdef CONFIG_HIBERNATE_CALLBACKS
1722extern struct dev_pm_ops pcibios_pm_ops;
1723#endif
1724
7752d5cf 1725#ifdef CONFIG_PCI_MMCONFIG
f39d5b72
BH		 1726void __init pci_mmcfg_early_init(void);
1727void __init pci_mmcfg_late_init(void);
7752d5cf 1728#else
bb63b421 1729static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1730static inline void pci_mmcfg_late_init(void) { }
1731#endif
1732
642c92da 1733int pci_ext_cfg_avail(void);
0ef5f8f6 1734
1684f5dd 1735void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1736void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1737
dd7cc44d 1738#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1739int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1740int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1741
f39d5b72
BH		 1742int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1743void pci_disable_sriov(struct pci_dev *dev);
c194f7ea
WY		 1744int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1745void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
f39d5b72 1746int pci_num_vf(struct pci_dev *dev);
5a8eb242 1747int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1748int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1749int pci_sriov_get_totalvfs(struct pci_dev *dev);
0e6c9122 1750resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
dd7cc44d 1751#else
b07579c0
WY		 1752static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1753{
1754 return -ENOSYS;
1755}
1756static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1757{
1758 return -ENOSYS;
1759}
dd7cc44d 1760static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1761{ return -ENODEV; }
c194f7ea
WY		 1762static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1763{
1764 return -ENOSYS;
1765}
1766static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1767 int id, int reset) { }
2ee546c4 1768static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1769static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1770static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1771{ return 0; }
bff73156 1772static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1773{ return 0; }
bff73156 1774static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1775{ return 0; }
0e6c9122
WY		 1776static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1777{ return 0; }
dd7cc44d
YZ		 1778#endif
1779
c825bc94 1780#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1781void pci_hp_create_module_link(struct pci_slot *pci_slot);
1782void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 1783#endif
1784
d7b7e605
KK		 1785/**
1786 * pci_pcie_cap - get the saved PCIe capability offset
1787 * @dev: PCI device
1788 *
1789 * PCIe capability offset is calculated at PCI device initialization
1790 * time and saved in the data structure. This function returns saved
1791 * PCIe capability offset. Using this instead of pci_find_capability()
1792 * reduces unnecessary search in the PCI configuration space. If you
1793 * need to calculate PCIe capability offset from raw device for some
1794 * reasons, please use pci_find_capability() instead.
1795 */
1796static inline int pci_pcie_cap(struct pci_dev *dev)
1797{
1798 return dev->pcie_cap;
1799}
1800
7eb776c4
KK		 1801/**
1802 * pci_is_pcie - check if the PCI device is PCI Express capable
1803 * @dev: PCI device
1804 *
a895c28a 1805 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 1806 */
1807static inline bool pci_is_pcie(struct pci_dev *dev)
1808{
a895c28a 1809 return pci_pcie_cap(dev);
7eb776c4
KK		 1810}
1811
7c9c003c
MS		 1812/**
1813 * pcie_caps_reg - get the PCIe Capabilities Register
1814 * @dev: PCI device
1815 */
1816static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1817{
1818 return dev->pcie_flags_reg;
1819}
1820
786e2288
YW		 1821/**
1822 * pci_pcie_type - get the PCIe device/port type
1823 * @dev: PCI device
1824 */
1825static inline int pci_pcie_type(const struct pci_dev *dev)
1826{
1c531d82 1827 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 1828}
1829
5d990b62 1830void pci_request_acs(void);
ad805758
AW		 1831bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1832bool pci_acs_path_enabled(struct pci_dev *start,
1833 struct pci_dev *end, u16 acs_flags);
a2ce7662 1834
7ad506fa 1835#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 1836#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 1837
1838/* Large Resource Data Type Tag Item Names */
1839#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1840#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1841#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1842
1843#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1844#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1845#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1846
1847/* Small Resource Data Type Tag Item Names */
9eb45d5c 1848#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 1849
9eb45d5c 1850#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 1851
1852#define PCI_VPD_SRDT_TIN_MASK 0x78
1853#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 1854#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 1855
1856#define PCI_VPD_LRDT_TAG_SIZE 3
1857#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1858
e1d5bdab
MC		 1859#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1860
4067a854
MC		 1861#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1862#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1863#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1864#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1865
a2ce7662
MC		 1866/**
1867 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1868 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1869 *
1870 * Returns the extracted Large Resource Data Type length.
1871 */
1872static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1873{
1874 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1875}
1876
9eb45d5c
HR		 1877/**
1878 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1879 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1880 *
1881 * Returns the extracted Large Resource Data Type Tag item.
1882 */
1883static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1884{
1885 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1886}
1887
7ad506fa
MC		 1888/**
1889 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1890 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1891 *
1892 * Returns the extracted Small Resource Data Type length.
1893 */
1894static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1895{
1896 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1897}
1898
9eb45d5c
HR		 1899/**
1900 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
1901 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1902 *
1903 * Returns the extracted Small Resource Data Type Tag Item.
1904 */
1905static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
1906{
1907 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
1908}
1909
e1d5bdab
MC		 1910/**
1911 * pci_vpd_info_field_size - Extracts the information field length
1912 * @lrdt: Pointer to the beginning of an information field header
1913 *
1914 * Returns the extracted information field length.
1915 */
1916static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1917{
1918 return info_field[2];
1919}
1920
b55ac1b2
MC		 1921/**
1922 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1923 * @buf: Pointer to buffered vpd data
1924 * @off: The offset into the buffer at which to begin the search
1925 * @len: The length of the vpd buffer
1926 * @rdt: The Resource Data Type to search for
1927 *
1928 * Returns the index where the Resource Data Type was found or
1929 * -ENOENT otherwise.
1930 */
1931int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1932
4067a854
MC		 1933/**
1934 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1935 * @buf: Pointer to buffered vpd data
1936 * @off: The offset into the buffer at which to begin the search
1937 * @len: The length of the buffer area, relative to off, in which to search
1938 * @kw: The keyword to search for
1939 *
1940 * Returns the index where the information field keyword was found or
1941 * -ENOENT otherwise.
1942 */
1943int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1944 unsigned int len, const char *kw);
1945
98d9f30c
BH		 1946/* PCI <-> OF binding helpers */
1947#ifdef CONFIG_OF
1948struct device_node;
b165e2b6 1949struct irq_domain;
f39d5b72
BH		 1950void pci_set_of_node(struct pci_dev *dev);
1951void pci_release_of_node(struct pci_dev *dev);
1952void pci_set_bus_of_node(struct pci_bus *bus);
1953void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 1954struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
98d9f30c
BH		 1955
1956/* Arch may override this (weak) */
723ec4d0 1957struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 1958
3df425f3
JC		 1959static inline struct device_node *
1960pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 1961{
1962 return pdev ? pdev->dev.of_node : NULL;
1963}
1964
ef3b4f8c
BH		 1965static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1966{
1967 return bus ? bus->dev.of_node : NULL;
1968}
1969
98d9f30c
BH		 1970#else /* CONFIG_OF */
1971static inline void pci_set_of_node(struct pci_dev *dev) { }
1972static inline void pci_release_of_node(struct pci_dev *dev) { }
1973static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1974static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
f0b66a2c
KH		 1975static inline struct device_node *
1976pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
b165e2b6
MZ		 1977static inline struct irq_domain *
1978pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
98d9f30c
BH		 1979#endif /* CONFIG_OF */
1980
471036b2
SS		 1981#ifdef CONFIG_ACPI
1982struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
1983
1984void
1985pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
1986#else
1987static inline struct irq_domain *
1988pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
1989#endif
1990
eb740b5f
GS		 1991#ifdef CONFIG_EEH
1992static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1993{
1994 return pdev->dev.archdata.edev;
1995}
1996#endif
1997
f0af9593 1998void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 1999bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2000int pci_for_each_dma_alias(struct pci_dev *pdev,
2001 int (*fn)(struct pci_dev *pdev,
2002 u16 alias, void *data), void *data);
2003
ce052984
EZ		 2004/* helper functions for operation of device flag */
2005static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2006{
2007 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2008}
2009static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2010{
2011 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2012}
2013static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2014{
2015 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2016}
19bdb6e4
AW		 2017
2018/**
2019 * pci_ari_enabled - query ARI forwarding status
2020 * @bus: the PCI bus
2021 *
2022 * Returns true if ARI forwarding is enabled.
2023 */
2024static inline bool pci_ari_enabled(struct pci_bus *bus)
2025{
2026 return bus->self && bus->self->ari_enabled;
2027}
bc4b024a
CH		 2028
2029/* provide the legacy pci_dma_* API */
2030#include <linux/pci-dma-compat.h>
2031
1da177e4 2032#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)