Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * pci.h | |
4 | * | |
5 | * PCI defines and function prototypes | |
6 | * Copyright 1994, Drew Eckhardt | |
7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
8 | * | |
7ce2e76a KW |
9 | * PCI Express ASPM defines and function prototypes |
10 | * Copyright (c) 2007 Intel Corp. | |
11 | * Zhang Yanmin (yanmin.zhang@intel.com) | |
12 | * Shaohua Li (shaohua.li@intel.com) | |
13 | * | |
1da177e4 LT |
14 | * For more information, please consult the following manuals (look at |
15 | * http://www.pcisig.com/ for how to get them): | |
16 | * | |
17 | * PCI BIOS Specification | |
18 | * PCI Local Bus Specification | |
19 | * PCI to PCI Bridge Specification | |
7ce2e76a | 20 | * PCI Express Specification |
1da177e4 LT |
21 | * PCI System Design Guide |
22 | */ | |
1da177e4 LT |
23 | #ifndef LINUX_PCI_H |
24 | #define LINUX_PCI_H | |
25 | ||
1da177e4 | 26 | |
778382e0 DW |
27 | #include <linux/mod_devicetable.h> |
28 | ||
1da177e4 | 29 | #include <linux/types.h> |
98db6f19 | 30 | #include <linux/init.h> |
1da177e4 LT |
31 | #include <linux/ioport.h> |
32 | #include <linux/list.h> | |
4a7fb636 | 33 | #include <linux/compiler.h> |
1da177e4 | 34 | #include <linux/errno.h> |
f46753c5 | 35 | #include <linux/kobject.h> |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <linux/device.h> |
704e8953 | 38 | #include <linux/interrupt.h> |
1388cc96 | 39 | #include <linux/io.h> |
14d76b68 | 40 | #include <linux/resource_ext.h> |
607ca46e | 41 | #include <uapi/linux/pci.h> |
1da177e4 | 42 | |
7e7a43c3 AB |
43 | #include <linux/pci_ids.h> |
44 | ||
d6e055e8 HK |
45 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
46 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | |
47 | PCI_STATUS_REC_MASTER_ABORT | \ | |
48 | PCI_STATUS_REC_TARGET_ABORT | \ | |
49 | PCI_STATUS_SIG_TARGET_ABORT | \ | |
50 | PCI_STATUS_PARITY) | |
51 | ||
e20afa06 | 52 | /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ |
6937b7dd | 53 | #define PCI_NUM_RESET_METHODS 7 |
e20afa06 | 54 | |
9bdc81ce AN |
55 | #define PCI_RESET_PROBE true |
56 | #define PCI_RESET_DO_RESET false | |
57 | ||
85467136 SK |
58 | /* |
59 | * The PCI interface treats multi-function devices as independent | |
60 | * devices. The slot/function address of each device is encoded | |
61 | * in a single byte as follows: | |
62 | * | |
63 | * 7:3 = slot | |
64 | * 2:0 = function | |
f7625980 BH |
65 | * |
66 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 67 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 68 | * the following kernel-only defines are being added here. |
85467136 | 69 | */ |
0aa0f5d1 | 70 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
71 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
72 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
73 | ||
f46753c5 AC |
74 | /* pci_slot represents a physical slot */ |
75 | struct pci_slot { | |
0aa0f5d1 BH |
76 | struct pci_bus *bus; /* Bus this slot is on */ |
77 | struct list_head list; /* Node in list of slots */ | |
78 | struct hotplug_slot *hotplug; /* Hotplug info (move here) */ | |
79 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
80 | struct kobject kobj; | |
f46753c5 AC |
81 | }; |
82 | ||
0ad772ec AC |
83 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
84 | { | |
85 | return kobject_name(&slot->kobj); | |
86 | } | |
87 | ||
1da177e4 LT |
88 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
89 | enum pci_mmap_state { | |
90 | pci_mmap_io, | |
91 | pci_mmap_mem | |
92 | }; | |
93 | ||
0aa0f5d1 | 94 | /* For PCI devices, the region numbers are assigned this way: */ |
fde09c6d YZ |
95 | enum { |
96 | /* #0-5: standard PCI resources */ | |
97 | PCI_STD_RESOURCES, | |
c9c13ba4 | 98 | PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, |
fde09c6d YZ |
99 | |
100 | /* #6: expansion ROM resource */ | |
101 | PCI_ROM_RESOURCE, | |
102 | ||
0aa0f5d1 | 103 | /* Device-specific resources */ |
d1b054da YZ |
104 | #ifdef CONFIG_PCI_IOV |
105 | PCI_IOV_RESOURCES, | |
106 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
107 | #endif | |
108 | ||
6e0688db KW |
109 | /* PCI-to-PCI (P2P) bridge windows */ |
110 | #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
111 | #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
112 | #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
113 | ||
114 | /* CardBus bridge windows */ | |
115 | #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) | |
116 | #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) | |
117 | #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) | |
118 | #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) | |
119 | ||
120 | /* Total number of bridge resources for P2P and CardBus */ | |
fde09c6d YZ |
121 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
122 | ||
6e0688db | 123 | /* Resources assigned to buses behind the bridge */ |
fde09c6d YZ |
124 | PCI_BRIDGE_RESOURCES, |
125 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
126 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
127 | ||
0aa0f5d1 | 128 | /* Total resources associated with a PCI device */ |
fde09c6d YZ |
129 | PCI_NUM_RESOURCES, |
130 | ||
0aa0f5d1 | 131 | /* Preserve this for compatibility */ |
cda57bf9 | 132 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 133 | }; |
1da177e4 | 134 | |
b352baf1 PB |
135 | /** |
136 | * enum pci_interrupt_pin - PCI INTx interrupt values | |
137 | * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt | |
138 | * @PCI_INTERRUPT_INTA: PCI INTA pin | |
139 | * @PCI_INTERRUPT_INTB: PCI INTB pin | |
140 | * @PCI_INTERRUPT_INTC: PCI INTC pin | |
141 | * @PCI_INTERRUPT_INTD: PCI INTD pin | |
142 | * | |
143 | * Corresponds to values for legacy PCI INTx interrupts, as can be found in the | |
144 | * PCI_INTERRUPT_PIN register. | |
145 | */ | |
146 | enum pci_interrupt_pin { | |
147 | PCI_INTERRUPT_UNKNOWN, | |
148 | PCI_INTERRUPT_INTA, | |
149 | PCI_INTERRUPT_INTB, | |
150 | PCI_INTERRUPT_INTC, | |
151 | PCI_INTERRUPT_INTD, | |
152 | }; | |
153 | ||
154 | /* The number of legacy PCI INTx interrupts */ | |
155 | #define PCI_NUM_INTX 4 | |
156 | ||
57bdeef4 NN |
157 | /* |
158 | * Reading from a device that doesn't respond typically returns ~0. A | |
159 | * successful read from a device may also return ~0, so you need additional | |
160 | * information to reliably identify errors. | |
161 | */ | |
162 | #define PCI_ERROR_RESPONSE (~0ULL) | |
163 | #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) | |
164 | #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) | |
165 | ||
224abb67 BH |
166 | /* |
167 | * pci_power_t values must match the bits in the Capabilities PME_Support | |
168 | * and Control/Status PowerState fields in the Power Management capability. | |
169 | */ | |
1da177e4 LT |
170 | typedef int __bitwise pci_power_t; |
171 | ||
4352dfd5 GKH |
172 | #define PCI_D0 ((pci_power_t __force) 0) |
173 | #define PCI_D1 ((pci_power_t __force) 1) | |
174 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
175 | #define PCI_D3hot ((pci_power_t __force) 3) |
176 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 177 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 178 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 179 | |
00240c38 AS |
180 | /* Remember to update this when the list above changes! */ |
181 | extern const char *pci_power_names[]; | |
182 | ||
183 | static inline const char *pci_power_name(pci_power_t state) | |
184 | { | |
9661e783 | 185 | return pci_power_names[1 + (__force int) state]; |
00240c38 AS |
186 | } |
187 | ||
0aa0f5d1 | 188 | /** |
229b4e07 CD |
189 | * typedef pci_channel_state_t |
190 | * | |
0aa0f5d1 BH |
191 | * The pci_channel state describes connectivity between the CPU and |
192 | * the PCI device. If some PCI bus between here and the PCI device | |
193 | * has crashed or locked up, this info is reflected here. | |
392a1ce7 | 194 | */ |
195 | typedef unsigned int __bitwise pci_channel_state_t; | |
196 | ||
16d79cd4 | 197 | enum { |
392a1ce7 | 198 | /* I/O channel is in normal state */ |
199 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
200 | ||
201 | /* I/O to channel is blocked */ | |
202 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
203 | ||
204 | /* PCI card is dead */ | |
205 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
206 | }; | |
207 | ||
f7bdd12d BK |
208 | typedef unsigned int __bitwise pcie_reset_state_t; |
209 | ||
210 | enum pcie_reset_state { | |
211 | /* Reset is NOT asserted (Use to deassert reset) */ | |
212 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
213 | ||
f7625980 | 214 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
215 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
216 | ||
f7625980 | 217 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
218 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
219 | }; | |
220 | ||
ba698ad4 DM |
221 | typedef unsigned short __bitwise pci_dev_flags_t; |
222 | enum pci_dev_flags { | |
0aa0f5d1 | 223 | /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ |
6b121592 | 224 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 225 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 226 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 227 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 228 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 229 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 230 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
c8fe16e3 AW |
231 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
232 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
233 | /* Do not use bus resets for device */ |
234 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
235 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
236 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
932c435c MR |
237 | /* Get VPD from function 0 VPD */ |
238 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), | |
0aa0f5d1 | 239 | /* A non-root bridge where translation occurs, stop alias search here */ |
ffff8858 | 240 | PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), |
f65fd1aa SN |
241 | /* Do not use FLR even if device advertises PCI_AF_CAP */ |
242 | PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), | |
a99b646a | 243 | /* Don't use Relaxed Ordering for TLPs directed at this device */ |
c2eac4d3 | 244 | PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), |
2226667a MZ |
245 | /* Device does honor MSI masking despite saying otherwise */ |
246 | PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), | |
ba698ad4 DM |
247 | }; |
248 | ||
e1d3a908 SA |
249 | enum pci_irq_reroute_variant { |
250 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
251 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
252 | }; | |
253 | ||
6e325a62 MT |
254 | typedef unsigned short __bitwise pci_bus_flags_t; |
255 | enum pci_bus_flags { | |
032c3d86 JD |
256 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
257 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
258 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, | |
17e8f0d4 | 259 | PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, |
6e325a62 MT |
260 | }; |
261 | ||
0aa0f5d1 | 262 | /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ |
59da381e JK |
263 | enum pcie_link_width { |
264 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
265 | PCIE_LNK_X1 = 0x01, | |
266 | PCIE_LNK_X2 = 0x02, | |
267 | PCIE_LNK_X4 = 0x04, | |
268 | PCIE_LNK_X8 = 0x08, | |
0aa0f5d1 | 269 | PCIE_LNK_X12 = 0x0c, |
59da381e JK |
270 | PCIE_LNK_X16 = 0x10, |
271 | PCIE_LNK_X32 = 0x20, | |
0aa0f5d1 | 272 | PCIE_LNK_WIDTH_UNKNOWN = 0xff, |
59da381e JK |
273 | }; |
274 | ||
e56faff5 | 275 | /* See matching string table in pci_speed_string() */ |
536c8cb4 MW |
276 | enum pci_bus_speed { |
277 | PCI_SPEED_33MHz = 0x00, | |
278 | PCI_SPEED_66MHz = 0x01, | |
279 | PCI_SPEED_66MHz_PCIX = 0x02, | |
280 | PCI_SPEED_100MHz_PCIX = 0x03, | |
281 | PCI_SPEED_133MHz_PCIX = 0x04, | |
282 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
283 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
284 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
285 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
286 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
287 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
288 | AGP_UNKNOWN = 0x0c, |
289 | AGP_1X = 0x0d, | |
290 | AGP_2X = 0x0e, | |
291 | AGP_4X = 0x0f, | |
292 | AGP_8X = 0x10, | |
536c8cb4 MW |
293 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
294 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
295 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
296 | PCIE_SPEED_2_5GT = 0x14, | |
297 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 298 | PCIE_SPEED_8_0GT = 0x16, |
1acfb9b7 | 299 | PCIE_SPEED_16_0GT = 0x17, |
de76cda2 | 300 | PCIE_SPEED_32_0GT = 0x18, |
34191749 | 301 | PCIE_SPEED_64_0GT = 0x19, |
536c8cb4 MW |
302 | PCI_SPEED_UNKNOWN = 0xff, |
303 | }; | |
304 | ||
576c7218 AD |
305 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
306 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); | |
307 | ||
fd00faa3 HK |
308 | struct pci_vpd { |
309 | struct mutex lock; | |
310 | unsigned int len; | |
311 | u8 cap; | |
24a4742f AW |
312 | }; |
313 | ||
402723ad | 314 | struct irq_affinity; |
7d715a6c | 315 | struct pcie_link_state; |
d1b054da | 316 | struct pci_sriov; |
52916982 | 317 | struct pci_p2pdma; |
90655631 | 318 | struct rcec_ea; |
ee69439c | 319 | |
0aa0f5d1 | 320 | /* The pci_dev structure describes PCI devices */ |
1da177e4 | 321 | struct pci_dev { |
0aa0f5d1 BH |
322 | struct list_head bus_list; /* Node in per-bus list */ |
323 | struct pci_bus *bus; /* Bus this device is on */ | |
324 | struct pci_bus *subordinate; /* Bus this device bridges to */ | |
1da177e4 | 325 | |
0aa0f5d1 BH |
326 | void *sysdata; /* Hook for sys-specific extension */ |
327 | struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ | |
f46753c5 | 328 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 | 329 | |
0aa0f5d1 | 330 | unsigned int devfn; /* Encoded device & function index */ |
1da177e4 LT |
331 | unsigned short vendor; |
332 | unsigned short device; | |
333 | unsigned short subsystem_vendor; | |
334 | unsigned short subsystem_device; | |
335 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 336 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 337 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
66b80809 KB |
338 | #ifdef CONFIG_PCIEAER |
339 | u16 aer_cap; /* AER capability offset */ | |
db89ccbe | 340 | struct aer_stats *aer_stats; /* AER stats for this device */ |
90655631 SK |
341 | #endif |
342 | #ifdef CONFIG_PCIEPORTBUS | |
343 | struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ | |
507b460f | 344 | struct pci_dev *rcec; /* Associated RCEC device */ |
66b80809 | 345 | #endif |
69139244 | 346 | u32 devcap; /* PCIe Device Capabilities */ |
f7625980 | 347 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
348 | u8 msi_cap; /* MSI capability offset */ |
349 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 350 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
0aa0f5d1 BH |
351 | u8 rom_base_reg; /* Config register controlling ROM */ |
352 | u8 pin; /* Interrupt pin this device uses */ | |
353 | u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ | |
354 | unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ | |
1da177e4 | 355 | |
68da4e0e | 356 | struct pci_driver *driver; /* Driver bound to this device */ |
1da177e4 LT |
357 | u64 dma_mask; /* Mask of the bits of bus address this |
358 | device implements. Normally this is | |
359 | 0xffffffff. You only need to change | |
360 | this if your device has broken DMA | |
361 | or supports 64-bit transfers. */ | |
362 | ||
4d57cdfa FT |
363 | struct device_dma_parameters dma_parms; |
364 | ||
0aa0f5d1 BH |
365 | pci_power_t current_state; /* Current operating state. In ACPI, |
366 | this is D0-D3, D0 being fully | |
367 | functional, and D3 being off. */ | |
d6112f8d | 368 | unsigned int imm_ready:1; /* Supports Immediate Readiness */ |
703860ed | 369 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
370 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
371 | can be generated */ | |
379021d5 | 372 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
373 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
374 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
375 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
376 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
9d26d3a8 | 377 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
448bd857 | 378 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
0aa0f5d1 BH |
379 | unsigned int mmio_always_on:1; /* Disallow turning off io/mem |
380 | decoding during BAR sizing */ | |
e80bb09d | 381 | unsigned int wakeup_prepared:1; |
0aa0f5d1 | 382 | unsigned int runtime_d3cold:1; /* Whether go through runtime |
448bd857 HY |
383 | D3cold, not set for devices |
384 | powered on/off by the | |
385 | corresponding bridge */ | |
d491f2b7 | 386 | unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ |
b440bde7 | 387 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
576243b3 KB |
388 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
389 | controlled exclusively by | |
390 | user sysfs */ | |
4ec73791 SM |
391 | unsigned int clear_retrain_link:1; /* Need to clear Retrain Link |
392 | bit manually */ | |
3789af9a | 393 | unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ |
448bd857 | 394 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 395 | |
7d715a6c | 396 | #ifdef CONFIG_PCIEASPM |
f7625980 | 397 | struct pcie_link_state *link_state; /* ASPM link state */ |
c46fd358 BH |
398 | unsigned int ltr_path:1; /* Latency Tolerance Reporting |
399 | supported from root to here */ | |
ee8b1c47 | 400 | u16 l1ss; /* L1SS Capability pointer */ |
7d715a6c | 401 | #endif |
8c09e896 | 402 | unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ |
7ce3f912 | 403 | unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ |
7d715a6c | 404 | |
0aa0f5d1 BH |
405 | pci_channel_state_t error_state; /* Current connectivity state */ |
406 | struct device dev; /* Generic device interface */ | |
1da177e4 | 407 | |
0aa0f5d1 | 408 | int cfg_size; /* Size of config space */ |
1da177e4 LT |
409 | |
410 | /* | |
411 | * Instead of touching interrupt line and base address registers | |
412 | * directly, use the values stored here. They might be different! | |
413 | */ | |
414 | unsigned int irq; | |
415 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
416 | ||
0aa0f5d1 BH |
417 | bool match_driver; /* Skip attaching driver */ |
418 | ||
419 | unsigned int transparent:1; /* Subtractive decode bridge */ | |
51c48b31 BH |
420 | unsigned int io_window:1; /* Bridge has I/O window */ |
421 | unsigned int pref_window:1; /* Bridge has pref mem window */ | |
422 | unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ | |
0aa0f5d1 BH |
423 | unsigned int multifunction:1; /* Multi-function device */ |
424 | ||
0aa0f5d1 BH |
425 | unsigned int is_busmaster:1; /* Is busmaster */ |
426 | unsigned int no_msi:1; /* May not use MSI */ | |
f6b6aefe | 427 | unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ |
0aa0f5d1 BH |
428 | unsigned int block_cfg_access:1; /* Config space access blocked */ |
429 | unsigned int broken_parity_status:1; /* Generates false positive parity */ | |
430 | unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ | |
f7625980 | 431 | unsigned int msi_enabled:1; |
99dc804d | 432 | unsigned int msix_enabled:1; |
0aa0f5d1 BH |
433 | unsigned int ari_enabled:1; /* ARI forwarding */ |
434 | unsigned int ats_enabled:1; /* Address Translation Svc */ | |
a4f4fa68 JPB |
435 | unsigned int pasid_enabled:1; /* Process Address Space ID */ |
436 | unsigned int pri_enabled:1; /* Page Request Interface */ | |
3f35d2cf TG |
437 | unsigned int is_managed:1; /* Managed via devres */ |
438 | unsigned int is_msi_managed:1; /* MSI release via devres installed */ | |
0aa0f5d1 | 439 | unsigned int needs_freset:1; /* Requires fundamental reset */ |
aa8c6c93 | 440 | unsigned int state_saved:1; |
d1b054da | 441 | unsigned int is_physfn:1; |
dd7cc44d | 442 | unsigned int is_virtfn:1; |
0aa0f5d1 | 443 | unsigned int is_hotplug_bridge:1; |
b03799b0 | 444 | unsigned int shpc_managed:1; /* SHPC owned by shpchp */ |
0aa0f5d1 | 445 | unsigned int is_thunderbolt:1; /* Thunderbolt controller */ |
617654aa MW |
446 | /* |
447 | * Devices marked being untrusted are the ones that can potentially | |
448 | * execute DMA attacks and similar. They are typically connected | |
449 | * through external ports such as Thunderbolt but not limited to | |
450 | * that. When an IOMMU is enabled they should be getting full | |
451 | * mappings to make sure they cannot access arbitrary memory. | |
452 | */ | |
453 | unsigned int untrusted:1; | |
99b50be9 RJ |
454 | /* |
455 | * Info from the platform, e.g., ACPI or device tree, may mark a | |
456 | * device as "external-facing". An external-facing device is | |
457 | * itself internal but devices downstream from it are external. | |
458 | */ | |
459 | unsigned int external_facing:1; | |
0aa0f5d1 BH |
460 | unsigned int broken_intx_masking:1; /* INTx masking can't be used */ |
461 | unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ | |
cffe0a2b | 462 | unsigned int irq_managed:1; |
0aa0f5d1 BH |
463 | unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ |
464 | unsigned int is_probed:1; /* Device probing in progress */ | |
f0157160 | 465 | unsigned int link_active_reporting:1;/* Device capable of reporting link active */ |
aff68a5a | 466 | unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ |
12856e7a | 467 | unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ |
500b55b0 | 468 | unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ |
ba698ad4 | 469 | pci_dev_flags_t dev_flags; |
bae94d02 | 470 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 471 | |
0aa0f5d1 | 472 | u32 saved_config_space[16]; /* Config space saved at suspend time */ |
41017f0c | 473 | struct hlist_head saved_cap_space; |
0aa0f5d1 | 474 | int rom_attr_enabled; /* Display of ROM attribute enabled? */ |
1da177e4 | 475 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
45aec1ae | 476 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
9bb04a0c | 477 | |
d22b3621 BH |
478 | #ifdef CONFIG_HOTPLUG_PCI_PCIE |
479 | unsigned int broken_cmd_compl:1; /* No compl for some cmds */ | |
480 | #endif | |
9bb04a0c JY |
481 | #ifdef CONFIG_PCIE_PTM |
482 | unsigned int ptm_root:1; | |
483 | unsigned int ptm_enabled:1; | |
8b2ec318 | 484 | u8 ptm_granularity; |
9bb04a0c | 485 | #endif |
ded86d8d | 486 | #ifdef CONFIG_PCI_MSI |
85aa607e | 487 | void __iomem *msix_base; |
cd119b09 | 488 | raw_spinlock_t msi_lock; |
ded86d8d | 489 | #endif |
fd00faa3 | 490 | struct pci_vpd vpd; |
be06c1b4 BH |
491 | #ifdef CONFIG_PCIE_DPC |
492 | u16 dpc_cap; | |
493 | unsigned int dpc_rp_extensions:1; | |
494 | u8 dpc_rp_log_size; | |
495 | #endif | |
466b3ddf | 496 | #ifdef CONFIG_PCI_ATS |
dd7cc44d | 497 | union { |
0aa0f5d1 BH |
498 | struct pci_sriov *sriov; /* PF: SR-IOV info */ |
499 | struct pci_dev *physfn; /* VF: related PF */ | |
dd7cc44d | 500 | }; |
67930995 BH |
501 | u16 ats_cap; /* ATS Capability offset */ |
502 | u8 ats_stu; /* ATS Smallest Translation Unit */ | |
4ebeb1ec CT |
503 | #endif |
504 | #ifdef CONFIG_PCI_PRI | |
c065190b | 505 | u16 pri_cap; /* PRI Capability offset */ |
4ebeb1ec | 506 | u32 pri_reqs_alloc; /* Number of PRI requests allocated */ |
e5adf79a | 507 | unsigned int pasid_required:1; /* PRG Response PASID Required */ |
4ebeb1ec CT |
508 | #endif |
509 | #ifdef CONFIG_PCI_PASID | |
751035b8 | 510 | u16 pasid_cap; /* PASID Capability offset */ |
4ebeb1ec | 511 | u16 pasid_features; |
52916982 LG |
512 | #endif |
513 | #ifdef CONFIG_PCI_P2PDMA | |
ae21f835 | 514 | struct pci_p2pdma __rcu *p2pdma; |
d1b054da | 515 | #endif |
52fbf5bd | 516 | u16 acs_cap; /* ACS Capability offset */ |
0aa0f5d1 BH |
517 | phys_addr_t rom; /* Physical address if not from BAR */ |
518 | size_t romlen; /* Length if not from BAR */ | |
519 | char *driver_override; /* Driver name to force a match */ | |
89ee9f76 | 520 | |
0aa0f5d1 | 521 | unsigned long priv_flags; /* Private flags for the PCI driver */ |
e20afa06 AN |
522 | |
523 | /* These methods index pci_reset_fn_methods[] */ | |
524 | u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ | |
1da177e4 LT |
525 | }; |
526 | ||
dda56549 Y |
527 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
528 | { | |
529 | #ifdef CONFIG_PCI_IOV | |
530 | if (dev->is_virtfn) | |
531 | dev = dev->physfn; | |
532 | #endif | |
dda56549 Y |
533 | return dev; |
534 | } | |
535 | ||
3c6e6ae7 | 536 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 537 | |
1da177e4 LT |
538 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
539 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
540 | ||
a7369f1f LV |
541 | static inline int pci_channel_offline(struct pci_dev *pdev) |
542 | { | |
543 | return (pdev->error_state != pci_channel_io_normal); | |
544 | } | |
545 | ||
15d82ca2 BF |
546 | /* |
547 | * Currently in ACPI spec, for each PCI host bridge, PCI Segment | |
548 | * Group number is limited to a 16-bit value, therefore (int)-1 is | |
549 | * not a valid PCI domain number, and can be used as a sentinel | |
550 | * value indicating ->domain_nr is not set by the driver (and | |
551 | * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with | |
552 | * pci_bus_find_domain_nr()). | |
553 | */ | |
554 | #define PCI_DOMAIN_NR_NOT_SET (-1) | |
555 | ||
5a21d70d | 556 | struct pci_host_bridge { |
0aa0f5d1 BH |
557 | struct device dev; |
558 | struct pci_bus *bus; /* Root bus */ | |
559 | struct pci_ops *ops; | |
07e29295 | 560 | struct pci_ops *child_ops; |
0aa0f5d1 BH |
561 | void *sysdata; |
562 | int busnr; | |
15d82ca2 | 563 | int domain_nr; |
14d76b68 | 564 | struct list_head windows; /* resource_entry */ |
e80a91ad | 565 | struct list_head dma_ranges; /* dma ranges resource list */ |
0aa0f5d1 | 566 | u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ |
3aa8a41e | 567 | int (*map_irq)(const struct pci_dev *, u8, u8); |
4fa2649a | 568 | void (*release_fn)(struct pci_host_bridge *); |
0aa0f5d1 | 569 | void *release_data; |
0aa0f5d1 BH |
570 | unsigned int ignore_reset_delay:1; /* For entire hierarchy */ |
571 | unsigned int no_ext_tags:1; /* No Extended Tags */ | |
02bfeb48 | 572 | unsigned int native_aer:1; /* OS may use PCIe AER */ |
9310f0dc | 573 | unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ |
1df81a6d | 574 | unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ |
02bfeb48 | 575 | unsigned int native_pme:1; /* OS may use PCIe PME */ |
af8bb9f8 | 576 | unsigned int native_ltr:1; /* OS may use PCIe LTR */ |
ac1c8e35 | 577 | unsigned int native_dpc:1; /* OS may use PCIe DPC */ |
a78cf965 | 578 | unsigned int preserve_config:1; /* Preserve FW resource setup */ |
2c8d5a2d | 579 | unsigned int size_windows:1; /* Enable root bus sizing */ |
94e89b14 | 580 | unsigned int msi_domain:1; /* Bridge wants MSI domain */ |
a78cf965 | 581 | |
7c7a0e94 GP |
582 | /* Resource alignment requirements */ |
583 | resource_size_t (*align_resource)(struct pci_dev *dev, | |
584 | const struct resource *res, | |
585 | resource_size_t start, | |
586 | resource_size_t size, | |
587 | resource_size_t align); | |
914a1951 | 588 | unsigned long private[] ____cacheline_aligned; |
5a21d70d | 589 | }; |
41017f0c | 590 | |
7b543663 | 591 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
7c7a0e94 | 592 | |
59094065 TR |
593 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
594 | { | |
595 | return (void *)bridge->private; | |
596 | } | |
597 | ||
598 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) | |
599 | { | |
600 | return container_of(priv, struct pci_host_bridge, private); | |
601 | } | |
602 | ||
a52d1443 | 603 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); |
5c3f18cc LP |
604 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
605 | size_t priv); | |
dff79b91 | 606 | void pci_free_host_bridge(struct pci_host_bridge *bridge); |
7c7a0e94 GP |
607 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
608 | ||
4fa2649a | 609 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
0aa0f5d1 BH |
610 | void (*release_fn)(struct pci_host_bridge *), |
611 | void *release_data); | |
7b543663 | 612 | |
6c0cc950 RW |
613 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
614 | ||
2fe2abf8 BH |
615 | /* |
616 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
617 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
618 | * buses below host bridges or subtractive decode bridges) go in the list. | |
619 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
620 | */ | |
621 | ||
622 | /* | |
623 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
624 | * and there's no way to program the bridge with the details of the window. | |
625 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
626 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
627 | */ | |
628 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
629 | ||
630 | struct pci_bus_resource { | |
0aa0f5d1 BH |
631 | struct list_head list; |
632 | struct resource *res; | |
633 | unsigned int flags; | |
2fe2abf8 | 634 | }; |
4352dfd5 GKH |
635 | |
636 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
637 | |
638 | struct pci_bus { | |
0aa0f5d1 BH |
639 | struct list_head node; /* Node in list of buses */ |
640 | struct pci_bus *parent; /* Parent bus this bridge is on */ | |
641 | struct list_head children; /* List of child buses */ | |
642 | struct list_head devices; /* List of devices on this bus */ | |
643 | struct pci_dev *self; /* Bridge device as seen by parent */ | |
644 | struct list_head slots; /* List of slots on this bus; | |
67546762 | 645 | protected by pci_slot_mutex */ |
2fe2abf8 | 646 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
0aa0f5d1 BH |
647 | struct list_head resources; /* Address space routed to this bus */ |
648 | struct resource busn_res; /* Bus numbers routed to this bus */ | |
1da177e4 | 649 | |
0aa0f5d1 | 650 | struct pci_ops *ops; /* Configuration access functions */ |
0aa0f5d1 BH |
651 | void *sysdata; /* Hook for sys-specific extension */ |
652 | struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ | |
1da177e4 | 653 | |
0aa0f5d1 BH |
654 | unsigned char number; /* Bus number */ |
655 | unsigned char primary; /* Number of primary bridge */ | |
3749c51a MW |
656 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
657 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
658 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
659 | int domain_nr; | |
660 | #endif | |
1da177e4 LT |
661 | |
662 | char name[48]; | |
663 | ||
0aa0f5d1 BH |
664 | unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ |
665 | pci_bus_flags_t bus_flags; /* Inherited by child buses */ | |
1da177e4 | 666 | struct device *bridge; |
fd7d1ced | 667 | struct device dev; |
0aa0f5d1 BH |
668 | struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ |
669 | struct bin_attribute *legacy_mem; /* Legacy mem */ | |
cc74d96f | 670 | unsigned int is_added:1; |
1da177e4 LT |
671 | }; |
672 | ||
fd7d1ced | 673 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 674 | |
4e544bac HK |
675 | static inline u16 pci_dev_id(struct pci_dev *dev) |
676 | { | |
677 | return PCI_DEVID(dev->bus->number, dev->devfn); | |
678 | } | |
679 | ||
79af72d7 | 680 | /* |
f7625980 | 681 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 682 | * false otherwise |
77a0dfcd BH |
683 | * |
684 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
685 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
686 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
687 | */ |
688 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
689 | { | |
690 | return !(pbus->parent); | |
691 | } | |
692 | ||
1c86438c YW |
693 | /** |
694 | * pci_is_bridge - check if the PCI device is a bridge | |
695 | * @dev: PCI device | |
696 | * | |
697 | * Return true if the PCI device is bridge whether it has subordinate | |
698 | * or not. | |
699 | */ | |
700 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
701 | { | |
702 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
703 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
704 | } | |
705 | ||
24a0c654 AS |
706 | #define for_each_pci_bridge(dev, bus) \ |
707 | list_for_each_entry(dev, &bus->devices, bus_list) \ | |
708 | if (!pci_is_bridge(dev)) {} else | |
709 | ||
c6bde215 BH |
710 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
711 | { | |
712 | dev = pci_physfn(dev); | |
713 | if (pci_is_root_bus(dev->bus)) | |
714 | return NULL; | |
715 | ||
716 | return dev->bus->self; | |
717 | } | |
718 | ||
16cf0ebc RW |
719 | #ifdef CONFIG_PCI_MSI |
720 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
721 | { | |
722 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
723 | } | |
724 | #else | |
725 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
726 | #endif | |
727 | ||
0aa0f5d1 | 728 | /* Error values that may be returned by PCI functions */ |
1da177e4 LT |
729 | #define PCIBIOS_SUCCESSFUL 0x00 |
730 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
731 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
732 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
733 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
734 | #define PCIBIOS_SET_FAILED 0x88 | |
735 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
736 | ||
0aa0f5d1 | 737 | /* Translate above to generic errno for passing back through non-PCI code */ |
a6961651 AW |
738 | static inline int pcibios_err_to_errno(int err) |
739 | { | |
740 | if (err <= PCIBIOS_SUCCESSFUL) | |
741 | return err; /* Assume already errno */ | |
742 | ||
743 | switch (err) { | |
744 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
745 | return -ENOENT; | |
746 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 747 | return -ENOTTY; |
a6961651 AW |
748 | case PCIBIOS_DEVICE_NOT_FOUND: |
749 | return -ENODEV; | |
750 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
751 | return -EFAULT; | |
752 | case PCIBIOS_SET_FAILED: | |
753 | return -EIO; | |
754 | case PCIBIOS_BUFFER_TOO_SMALL: | |
755 | return -ENOSPC; | |
756 | } | |
757 | ||
d97ffe23 | 758 | return -ERANGE; |
a6961651 AW |
759 | } |
760 | ||
1da177e4 LT |
761 | /* Low-level architecture-dependent routines */ |
762 | ||
763 | struct pci_ops { | |
057bd2e0 TR |
764 | int (*add_bus)(struct pci_bus *bus); |
765 | void (*remove_bus)(struct pci_bus *bus); | |
1f94a94f | 766 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
767 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
768 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
769 | }; | |
770 | ||
b6ce068a MW |
771 | /* |
772 | * ACPI needs to be able to access PCI config space before we've done a | |
773 | * PCI bus scan and created pci_bus structures. | |
774 | */ | |
f39d5b72 BH |
775 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
776 | int reg, int len, u32 *val); | |
777 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
778 | int reg, int len, u32 val); | |
1da177e4 | 779 | |
8e639079 | 780 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
3a9ad0b4 YL |
781 | typedef u64 pci_bus_addr_t; |
782 | #else | |
783 | typedef u32 pci_bus_addr_t; | |
784 | #endif | |
785 | ||
1da177e4 | 786 | struct pci_bus_region { |
0aa0f5d1 BH |
787 | pci_bus_addr_t start; |
788 | pci_bus_addr_t end; | |
1da177e4 LT |
789 | }; |
790 | ||
791 | struct pci_dynids { | |
0aa0f5d1 BH |
792 | spinlock_t lock; /* Protects list, index */ |
793 | struct list_head list; /* For IDs added at runtime */ | |
1da177e4 LT |
794 | }; |
795 | ||
f7625980 BH |
796 | |
797 | /* | |
798 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
799 | * a set of callbacks in struct pci_error_handlers, that device driver | |
800 | * will be notified of PCI bus errors, and will be driven to recovery | |
801 | * when an error occurs. | |
392a1ce7 | 802 | */ |
803 | ||
804 | typedef unsigned int __bitwise pci_ers_result_t; | |
805 | ||
806 | enum pci_ers_result { | |
0aa0f5d1 | 807 | /* No result/none/not supported in device driver */ |
392a1ce7 | 808 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
809 | ||
810 | /* Device driver can recover without slot reset */ | |
811 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
812 | ||
0aa0f5d1 | 813 | /* Device driver wants slot to be reset */ |
392a1ce7 | 814 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
815 | ||
816 | /* Device has completely failed, is unrecoverable */ | |
817 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
818 | ||
819 | /* Device driver is fully recovered and operational */ | |
820 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
821 | |
822 | /* No AER capabilities registered for the driver */ | |
823 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 | 824 | }; |
825 | ||
826 | /* PCI bus error event callbacks */ | |
05cca6e5 | 827 | struct pci_error_handlers { |
392a1ce7 | 828 | /* PCI bus error detected on this device */ |
829 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
16d79cd4 | 830 | pci_channel_state_t error); |
392a1ce7 | 831 | |
832 | /* MMIO has been re-enabled, but not DMA */ | |
833 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
834 | ||
392a1ce7 | 835 | /* PCI slot has been reset */ |
836 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
837 | ||
3ebe7f9f | 838 | /* PCI function reset prepare or completed */ |
775755ed CH |
839 | void (*reset_prepare)(struct pci_dev *dev); |
840 | void (*reset_done)(struct pci_dev *dev); | |
3ebe7f9f | 841 | |
392a1ce7 | 842 | /* Device driver may resume normal operations */ |
843 | void (*resume)(struct pci_dev *dev); | |
844 | }; | |
845 | ||
392a1ce7 | 846 | |
1da177e4 | 847 | struct module; |
229b4e07 CD |
848 | |
849 | /** | |
850 | * struct pci_driver - PCI driver structure | |
851 | * @node: List of driver structures. | |
852 | * @name: Driver name. | |
853 | * @id_table: Pointer to table of device IDs the driver is | |
854 | * interested in. Most drivers should export this | |
855 | * table using MODULE_DEVICE_TABLE(pci,...). | |
856 | * @probe: This probing function gets called (during execution | |
857 | * of pci_register_driver() for already existing | |
858 | * devices or later if a new device gets inserted) for | |
859 | * all PCI devices which match the ID table and are not | |
860 | * "owned" by the other drivers yet. This function gets | |
861 | * passed a "struct pci_dev \*" for each device whose | |
862 | * entry in the ID table matches the device. The probe | |
863 | * function returns zero when the driver chooses to | |
864 | * take "ownership" of the device or an error code | |
865 | * (negative number) otherwise. | |
866 | * The probe function always gets called from process | |
867 | * context, so it can sleep. | |
868 | * @remove: The remove() function gets called whenever a device | |
869 | * being handled by this driver is removed (either during | |
870 | * deregistration of the driver or when it's manually | |
871 | * pulled out of a hot-pluggable slot). | |
872 | * The remove function always gets called from process | |
873 | * context, so it can sleep. | |
874 | * @suspend: Put device into low power state. | |
229b4e07 | 875 | * @resume: Wake device from low power state. |
151f4e2b | 876 | * (Please see Documentation/power/pci.rst for descriptions |
229b4e07 CD |
877 | * of PCI Power Management and the related functions.) |
878 | * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). | |
879 | * Intended to stop any idling DMA operations. | |
880 | * Useful for enabling wake-on-lan (NIC) or changing | |
881 | * the power state of a device before reboot. | |
882 | * e.g. drivers/net/e100.c. | |
883 | * @sriov_configure: Optional driver callback to allow configuration of | |
884 | * number of VFs to enable via sysfs "sriov_numvfs" file. | |
c3d5c2d9 LR |
885 | * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X |
886 | * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". | |
887 | * This will change MSI-X Table Size in the VF Message Control | |
888 | * registers. | |
889 | * @sriov_get_vf_total_msix: PF driver callback to get the total number of | |
890 | * MSI-X vectors available for distribution to the VFs. | |
229b4e07 CD |
891 | * @err_handler: See Documentation/PCI/pci-error-recovery.rst |
892 | * @groups: Sysfs attribute groups. | |
ded13b9c AG |
893 | * @dev_groups: Attributes attached to the device that will be |
894 | * created once it is bound to the driver. | |
229b4e07 CD |
895 | * @driver: Driver model structure. |
896 | * @dynids: List of dynamically added device IDs. | |
897 | */ | |
1da177e4 | 898 | struct pci_driver { |
0aa0f5d1 BH |
899 | struct list_head node; |
900 | const char *name; | |
901 | const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ | |
902 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
903 | void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
904 | int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
7cb30264 BY |
905 | int (*resume)(struct pci_dev *dev); /* Device woken up */ |
906 | void (*shutdown)(struct pci_dev *dev); | |
907 | int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ | |
c3d5c2d9 LR |
908 | int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ |
909 | u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); | |
49453028 | 910 | const struct pci_error_handlers *err_handler; |
92d50fc1 | 911 | const struct attribute_group **groups; |
ded13b9c | 912 | const struct attribute_group **dev_groups; |
1da177e4 | 913 | struct device_driver driver; |
0aa0f5d1 | 914 | struct pci_dynids dynids; |
1da177e4 LT |
915 | }; |
916 | ||
8e9028b3 BH |
917 | static inline struct pci_driver *to_pci_driver(struct device_driver *drv) |
918 | { | |
919 | return drv ? container_of(drv, struct pci_driver, driver) : NULL; | |
920 | } | |
1da177e4 LT |
921 | |
922 | /** | |
0aa0f5d1 | 923 | * PCI_DEVICE - macro used to describe a specific PCI device |
1da177e4 LT |
924 | * @vend: the 16 bit PCI Vendor ID |
925 | * @dev: the 16 bit PCI Device ID | |
926 | * | |
927 | * This macro is used to create a struct pci_device_id that matches a | |
928 | * specific device. The subvendor and subdevice fields will be set to | |
929 | * PCI_ANY_ID. | |
930 | */ | |
931 | #define PCI_DEVICE(vend,dev) \ | |
932 | .vendor = (vend), .device = (dev), \ | |
933 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
934 | ||
343b7258 MG |
935 | /** |
936 | * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with | |
937 | * override_only flags. | |
938 | * @vend: the 16 bit PCI Vendor ID | |
939 | * @dev: the 16 bit PCI Device ID | |
940 | * @driver_override: the 32 bit PCI Device override_only | |
941 | * | |
942 | * This macro is used to create a struct pci_device_id that matches only a | |
943 | * driver_override device. The subvendor and subdevice fields will be set to | |
944 | * PCI_ANY_ID. | |
945 | */ | |
946 | #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ | |
947 | .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ | |
948 | .subdevice = PCI_ANY_ID, .override_only = (driver_override) | |
949 | ||
cc6711b0 MG |
950 | /** |
951 | * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO | |
952 | * "driver_override" PCI device. | |
953 | * @vend: the 16 bit PCI Vendor ID | |
954 | * @dev: the 16 bit PCI Device ID | |
955 | * | |
956 | * This macro is used to create a struct pci_device_id that matches a | |
957 | * specific device. The subvendor and subdevice fields will be set to | |
958 | * PCI_ANY_ID and the driver_override will be set to | |
959 | * PCI_ID_F_VFIO_DRIVER_OVERRIDE. | |
960 | */ | |
961 | #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ | |
962 | PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) | |
963 | ||
3d567e0e | 964 | /** |
0aa0f5d1 | 965 | * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem |
3d567e0e NNS |
966 | * @vend: the 16 bit PCI Vendor ID |
967 | * @dev: the 16 bit PCI Device ID | |
968 | * @subvend: the 16 bit PCI Subvendor ID | |
969 | * @subdev: the 16 bit PCI Subdevice ID | |
970 | * | |
971 | * This macro is used to create a struct pci_device_id that matches a | |
972 | * specific device with subsystem information. | |
973 | */ | |
974 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
975 | .vendor = (vend), .device = (dev), \ | |
976 | .subvendor = (subvend), .subdevice = (subdev) | |
977 | ||
1da177e4 | 978 | /** |
0aa0f5d1 | 979 | * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class |
1da177e4 LT |
980 | * @dev_class: the class, subclass, prog-if triple for this device |
981 | * @dev_class_mask: the class mask for this device | |
982 | * | |
983 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 984 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
985 | * fields will be set to PCI_ANY_ID. |
986 | */ | |
987 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
988 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
989 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
990 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
991 | ||
1597cacb | 992 | /** |
0aa0f5d1 | 993 | * PCI_VDEVICE - macro used to describe a specific PCI device in short form |
c1309040 MR |
994 | * @vend: the vendor name |
995 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
996 | * |
997 | * This macro is used to create a struct pci_device_id that matches a | |
998 | * specific PCI device. The subvendor, and subdevice fields will be set | |
999 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
1000 | * private data. | |
1001 | */ | |
c1309040 MR |
1002 | #define PCI_VDEVICE(vend, dev) \ |
1003 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
1004 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 1005 | |
b72ae8ca AS |
1006 | /** |
1007 | * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form | |
1008 | * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) | |
1009 | * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) | |
1010 | * @data: the driver data to be filled | |
1011 | * | |
1012 | * This macro is used to create a struct pci_device_id that matches a | |
1013 | * specific PCI device. The subvendor, and subdevice fields will be set | |
1014 | * to PCI_ANY_ID. | |
1015 | */ | |
1016 | #define PCI_DEVICE_DATA(vend, dev, data) \ | |
1017 | .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ | |
1018 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ | |
1019 | .driver_data = (kernel_ulong_t)(data) | |
1020 | ||
5bbe029f | 1021 | enum { |
0aa0f5d1 BH |
1022 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ |
1023 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ | |
1024 | PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ | |
1025 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ | |
1026 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ | |
5bbe029f | 1027 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
0aa0f5d1 | 1028 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ |
5bbe029f BH |
1029 | }; |
1030 | ||
0d8006dd HX |
1031 | #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ |
1032 | #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ | |
1033 | #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ | |
1034 | #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ | |
1035 | ||
0aa0f5d1 | 1036 | /* These external functions are only available when PCI support is enabled */ |
1da177e4 LT |
1037 | #ifdef CONFIG_PCI |
1038 | ||
5bbe029f BH |
1039 | extern unsigned int pci_flags; |
1040 | ||
1041 | static inline void pci_set_flags(int flags) { pci_flags = flags; } | |
1042 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } | |
1043 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } | |
1044 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } | |
1045 | ||
a58674ff | 1046 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
1047 | |
1048 | enum pcie_bus_config_types { | |
0aa0f5d1 BH |
1049 | PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ |
1050 | PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ | |
1051 | PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ | |
1052 | PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ | |
1053 | PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ | |
b03e7495 JM |
1054 | }; |
1055 | ||
1056 | extern enum pcie_bus_config_types pcie_bus_config; | |
1057 | ||
1da177e4 LT |
1058 | extern struct bus_type pci_bus_type; |
1059 | ||
f7625980 BH |
1060 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
1061 | * code, or PCI core code. */ | |
0aa0f5d1 | 1062 | extern struct list_head pci_root_buses; /* List of all known PCI buses */ |
f7625980 | 1063 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 1064 | int no_pci_devices(void); |
1da177e4 | 1065 | |
3c449ed0 | 1066 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
7b77061f | 1067 | void pcibios_bus_add_device(struct pci_dev *pdev); |
10a95747 JL |
1068 | void pcibios_add_bus(struct pci_bus *bus); |
1069 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 1070 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 1071 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 1072 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 1073 | char *pcibios_setup(char *str); |
1da177e4 LT |
1074 | |
1075 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 1076 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 1077 | resource_size_t, |
e31dd6e4 | 1078 | resource_size_t); |
1da177e4 | 1079 | |
d1bbf38a | 1080 | /* Weak but can be overridden by arch */ |
2d1c8618 BH |
1081 | void pci_fixup_cardbus(struct pci_bus *); |
1082 | ||
1da177e4 LT |
1083 | /* Generic PCI functions used internally */ |
1084 | ||
fc279850 | 1085 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 1086 | struct resource *res); |
fc279850 | 1087 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 1088 | struct pci_bus_region *region); |
d1fd4fb6 | 1089 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 1090 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 1091 | void pci_bus_add_devices(const struct pci_bus *bus); |
de4b2f76 | 1092 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
1093 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1094 | struct pci_ops *ops, void *sysdata, | |
1095 | struct list_head *resources); | |
49b8e3f3 | 1096 | int pci_host_probe(struct pci_host_bridge *bridge); |
98a35831 YL |
1097 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
1098 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
1099 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 1100 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
0aa0f5d1 BH |
1101 | struct pci_ops *ops, void *sysdata, |
1102 | struct list_head *resources); | |
1228c4b6 | 1103 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); |
05cca6e5 GKH |
1104 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
1105 | int busnr); | |
f46753c5 | 1106 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
1107 | const char *name, |
1108 | struct hotplug_slot *hotplug); | |
f46753c5 | 1109 | void pci_destroy_slot(struct pci_slot *slot); |
017ffe64 YW |
1110 | #ifdef CONFIG_SYSFS |
1111 | void pci_dev_assign_slot(struct pci_dev *dev); | |
1112 | #else | |
1113 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } | |
1114 | #endif | |
1da177e4 | 1115 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 1116 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 1117 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 1118 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 1119 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 1120 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
1121 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
1122 | struct resource *res); | |
3df425f3 | 1123 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 1124 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 1125 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
1126 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
1127 | void pci_dev_put(struct pci_dev *dev); | |
1128 | void pci_remove_bus(struct pci_bus *b); | |
1129 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 1130 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
1131 | void pci_stop_root_bus(struct pci_bus *bus); |
1132 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 1133 | void pci_setup_cardbus(struct pci_bus *bus); |
d366d28c | 1134 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
f39d5b72 | 1135 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
1136 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
1137 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
1da177e4 LT |
1138 | |
1139 | /* Generic PCI functions exported to card drivers */ | |
1140 | ||
f646c2a0 PM |
1141 | u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
1142 | u8 pci_find_capability(struct pci_dev *dev, int cap); | |
1143 | u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
1144 | u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
1145 | u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); | |
ee8b1c47 BH |
1146 | u16 pci_find_ext_capability(struct pci_dev *dev, int cap); |
1147 | u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); | |
29f3eb64 | 1148 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
c124fd9a | 1149 | u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); |
ee122037 | 1150 | u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); |
1da177e4 | 1151 | |
70c0923b JK |
1152 | u64 pci_get_dsn(struct pci_dev *dev); |
1153 | ||
d42552c3 | 1154 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
0aa0f5d1 | 1155 | struct pci_dev *from); |
05cca6e5 | 1156 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
0aa0f5d1 BH |
1157 | unsigned int ss_vendor, unsigned int ss_device, |
1158 | struct pci_dev *from); | |
05cca6e5 | 1159 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
1160 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
1161 | unsigned int devfn); | |
05cca6e5 | 1162 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
1163 | int pci_dev_present(const struct pci_device_id *ids); |
1164 | ||
05cca6e5 GKH |
1165 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
1166 | int where, u8 *val); | |
1167 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
1168 | int where, u16 *val); | |
1169 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1170 | int where, u32 *val); | |
1171 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
1172 | int where, u8 val); | |
1173 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
1174 | int where, u16 val); | |
1175 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1176 | int where, u32 val); | |
1f94a94f RH |
1177 | |
1178 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
1179 | int where, int size, u32 *val); | |
1180 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
1181 | int where, int size, u32 val); | |
1182 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
1183 | int where, int size, u32 *val); | |
1184 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
1185 | int where, int size, u32 val); | |
1186 | ||
a72b46c3 | 1187 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 1188 | |
d3881e50 KB |
1189 | int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); |
1190 | int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); | |
1191 | int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); | |
1192 | int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); | |
1193 | int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); | |
1194 | int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); | |
1da177e4 | 1195 | |
8c0d3a02 JL |
1196 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
1197 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
1198 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
1199 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
1200 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
1201 | u16 clear, u16 set); | |
1202 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
1203 | u32 clear, u32 set); | |
1204 | ||
1205 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
1206 | u16 set) | |
1207 | { | |
1208 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
1209 | } | |
1210 | ||
1211 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
1212 | u32 set) | |
1213 | { | |
1214 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
1215 | } | |
1216 | ||
1217 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
1218 | u16 clear) | |
1219 | { | |
1220 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
1221 | } | |
1222 | ||
1223 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
1224 | u32 clear) | |
1225 | { | |
1226 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
1227 | } | |
1228 | ||
0aa0f5d1 | 1229 | /* User-space driven config access */ |
c63587d7 AW |
1230 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
1231 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
1232 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
1233 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
1234 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
1235 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
1236 | ||
4a7fb636 | 1237 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
1238 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
1239 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 1240 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
1241 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
1242 | void pcim_pin_device(struct pci_dev *pdev); | |
1243 | ||
99b3c58f PG |
1244 | static inline bool pci_intx_mask_supported(struct pci_dev *pdev) |
1245 | { | |
1246 | /* | |
1247 | * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is | |
1248 | * writable and no quirk has marked the feature broken. | |
1249 | */ | |
1250 | return !pdev->broken_intx_masking; | |
1251 | } | |
1252 | ||
296ccb08 YS |
1253 | static inline int pci_is_enabled(struct pci_dev *pdev) |
1254 | { | |
1255 | return (atomic_read(&pdev->enable_cnt) > 0); | |
1256 | } | |
1257 | ||
9ac7849e TH |
1258 | static inline int pci_is_managed(struct pci_dev *pdev) |
1259 | { | |
1260 | return pdev->is_managed; | |
1261 | } | |
1262 | ||
1da177e4 | 1263 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
1264 | |
1265 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 1266 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 1267 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 1268 | |
f7bdd12d | 1269 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 1270 | int pci_set_cacheline_size(struct pci_dev *dev); |
4a7fb636 | 1271 | int __must_check pci_set_mwi(struct pci_dev *dev); |
fc0f9f4d | 1272 | int __must_check pcim_set_mwi(struct pci_dev *dev); |
694625c0 | 1273 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 1274 | void pci_clear_mwi(struct pci_dev *dev); |
1fd3dde5 | 1275 | void pci_disable_parity(struct pci_dev *dev); |
a04ce0ff | 1276 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
1277 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
1278 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
157e876f | 1279 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 1280 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
1281 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
1282 | int pcix_get_mmrbc(struct pci_dev *dev); | |
1283 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 1284 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 1285 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
1286 | int pcie_get_mps(struct pci_dev *dev); |
1287 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
6db79a88 TG |
1288 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, |
1289 | enum pci_bus_speed *speed, | |
1290 | enum pcie_link_width *width); | |
9e506a7b | 1291 | void pcie_print_link_status(struct pci_dev *dev); |
9bdc81ce | 1292 | int pcie_reset_flr(struct pci_dev *dev, bool probe); |
91295d79 | 1293 | int pcie_flr(struct pci_dev *dev); |
a96d627a | 1294 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 1295 | int pci_reset_function(struct pci_dev *dev); |
a477b9cd | 1296 | int pci_reset_function_locked(struct pci_dev *dev); |
61cf16d8 | 1297 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 1298 | int pci_probe_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 1299 | int pci_probe_reset_bus(struct pci_bus *bus); |
c6a44ba9 | 1300 | int pci_reset_bus(struct pci_dev *dev); |
9e33002f GS |
1301 | void pci_reset_secondary_bus(struct pci_dev *dev); |
1302 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
14add80b | 1303 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1304 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1305 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
8bb705e3 | 1306 | void pci_release_resource(struct pci_dev *dev, int resno); |
192f1bf7 ND |
1307 | static inline int pci_rebar_bytes_to_size(u64 bytes) |
1308 | { | |
1309 | bytes = roundup_pow_of_two(bytes); | |
1310 | ||
1311 | /* Return BAR size as defined in the resizable BAR specification */ | |
1312 | return max(ilog2(bytes), 20) - 20; | |
1313 | } | |
1314 | ||
8fbdbb66 | 1315 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
8bb705e3 | 1316 | int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); |
c87deff7 | 1317 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1318 | bool pci_device_is_present(struct pci_dev *pdev); |
08249651 | 1319 | void pci_ignore_hotplug(struct pci_dev *dev); |
2856ba60 | 1320 | struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); |
ec5d9e87 | 1321 | int pci_status_get_and_clear_errors(struct pci_dev *pdev); |
1da177e4 | 1322 | |
704e8953 CH |
1323 | int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, |
1324 | irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, | |
1325 | const char *fmt, ...); | |
1326 | void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); | |
1327 | ||
1da177e4 | 1328 | /* ROM control related routines */ |
e416de5e AC |
1329 | int pci_enable_rom(struct pci_dev *pdev); |
1330 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1331 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1332 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
1da177e4 LT |
1333 | |
1334 | /* Power management related routines */ | |
1335 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1336 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1337 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1338 | int pci_load_saved_state(struct pci_dev *dev, |
1339 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1340 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1341 | struct pci_saved_state **state); | |
d6aa37cd | 1342 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1343 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1344 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1345 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1346 | void pci_pme_active(struct pci_dev *dev, bool enable); |
0847684c | 1347 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 1348 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1349 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1350 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1351 | bool pci_dev_run_wake(struct pci_dev *dev); |
9d26d3a8 MW |
1352 | void pci_d3cold_enable(struct pci_dev *dev); |
1353 | void pci_d3cold_disable(struct pci_dev *dev); | |
a99b646a | 1354 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); |
99efde6c | 1355 | void pci_resume_bus(struct pci_bus *bus); |
2a4d2c42 | 1356 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); |
1da177e4 | 1357 | |
bb209c82 BH |
1358 | /* For use by arch with custom probe code */ |
1359 | void set_pcie_port_type(struct pci_dev *pdev); | |
1360 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1361 | ||
ce5ccdef | 1362 | /* Functions for PCI Hotplug drivers to use */ |
2f320521 | 1363 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1364 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1365 | void pci_lock_rescan_remove(void); |
1366 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1367 | |
0aa0f5d1 | 1368 | /* Vital Product Data routines */ |
287d19ce SH |
1369 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1370 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
bf2928c7 HK |
1371 | ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1372 | ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
287d19ce | 1373 | |
1da177e4 | 1374 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1375 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1376 | void pci_bus_assign_resources(const struct pci_bus *bus); |
765bf9b7 | 1377 | void pci_bus_claim_resources(struct pci_bus *bus); |
1da177e4 LT |
1378 | void pci_bus_size_bridges(struct pci_bus *bus); |
1379 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1380 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1381 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1382 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1383 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1384 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
8bb705e3 | 1385 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); |
1da177e4 | 1386 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1387 | int pci_enable_resources(struct pci_dev *, int mask); |
47a650f2 | 1388 | void pci_assign_irq(struct pci_dev *dev); |
afd29f90 | 1389 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
1da177e4 | 1390 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1391 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1392 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1393 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1394 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 1395 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1396 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1397 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1398 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1399 | |
1400 | /* drivers/pci/bus.c */ | |
45ca9e97 | 1401 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1402 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1403 | resource_size_t offset); | |
45ca9e97 | 1404 | void pci_free_resource_list(struct list_head *resources); |
950334bc BH |
1405 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
1406 | unsigned int flags); | |
2fe2abf8 BH |
1407 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1408 | void pci_bus_remove_resources(struct pci_bus *bus); | |
950334bc BH |
1409 | int devm_request_pci_bus_resources(struct device *dev, |
1410 | struct list_head *resources); | |
2fe2abf8 | 1411 | |
bfc45606 DD |
1412 | /* Temporary until new and working PCI SBR API in place */ |
1413 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); | |
1414 | ||
89a74ecc | 1415 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1416 | for (i = 0; \ |
1417 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1418 | i++) | |
89a74ecc | 1419 | |
4a7fb636 AM |
1420 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1421 | struct resource *res, resource_size_t size, | |
1422 | resource_size_t align, resource_size_t min, | |
664c2848 | 1423 | unsigned long type_mask, |
3b7a17fc DB |
1424 | resource_size_t (*alignf)(void *, |
1425 | const struct resource *, | |
b26b2d49 DB |
1426 | resource_size_t, |
1427 | resource_size_t), | |
4a7fb636 | 1428 | void *alignf_data); |
1da177e4 | 1429 | |
8b921acf | 1430 | |
fcfaab30 GP |
1431 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
1432 | resource_size_t size); | |
c5076cfe TN |
1433 | unsigned long pci_address_to_pio(phys_addr_t addr); |
1434 | phys_addr_t pci_pio_to_address(unsigned long pio); | |
8b921acf | 1435 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
a5fb9fb0 SS |
1436 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, |
1437 | phys_addr_t phys_addr); | |
4d3f1384 | 1438 | void pci_unmap_iospace(struct resource *res); |
490cb6dd LP |
1439 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, |
1440 | resource_size_t offset, | |
1441 | resource_size_t size); | |
1442 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
1443 | struct resource *res); | |
8b921acf | 1444 | |
3a9ad0b4 | 1445 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
06cf56e4 BH |
1446 | { |
1447 | struct pci_bus_region region; | |
1448 | ||
1449 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1450 | return region.start; | |
1451 | } | |
1452 | ||
863b18f4 | 1453 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1454 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1455 | const char *mod_name); | |
bba81165 | 1456 | |
0aa0f5d1 | 1457 | /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ |
bba81165 AM |
1458 | #define pci_register_driver(driver) \ |
1459 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1460 | |
05cca6e5 | 1461 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1462 | |
1463 | /** | |
1464 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1465 | * @__pci_driver: pci_driver struct | |
1466 | * | |
1467 | * Helper macro for PCI drivers which do not do anything special in module | |
1468 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1469 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1470 | */ | |
1471 | #define module_pci_driver(__pci_driver) \ | |
0aa0f5d1 | 1472 | module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) |
aad4f400 | 1473 | |
b4eb6cdb PG |
1474 | /** |
1475 | * builtin_pci_driver() - Helper macro for registering a PCI driver | |
1476 | * @__pci_driver: pci_driver struct | |
1477 | * | |
1478 | * Helper macro for PCI drivers which do not do anything special in their | |
1479 | * init code. This eliminates a lot of boilerplate. Each driver may only | |
1480 | * use this macro once, and calling it replaces device_initcall(...) | |
1481 | */ | |
1482 | #define builtin_pci_driver(__pci_driver) \ | |
1483 | builtin_driver(__pci_driver, pci_register_driver) | |
1484 | ||
05cca6e5 | 1485 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1486 | int pci_add_dynid(struct pci_driver *drv, |
1487 | unsigned int vendor, unsigned int device, | |
1488 | unsigned int subvendor, unsigned int subdevice, | |
1489 | unsigned int class, unsigned int class_mask, | |
1490 | unsigned long driver_data); | |
05cca6e5 GKH |
1491 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1492 | struct pci_dev *dev); | |
1493 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1494 | int pass); | |
1da177e4 | 1495 | |
70298c6e | 1496 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1497 | void *userdata); |
ac7dc65a | 1498 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1499 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1500 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1501 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1502 | unsigned long type); | |
cecf4864 | 1503 | |
3448a19d DA |
1504 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1505 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1506 | ||
deb2d2ec | 1507 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1508 | unsigned int command_bits, u32 flags); |
fe537670 | 1509 | |
d7cc609f LG |
1510 | /* |
1511 | * Virtual interrupts allow for more interrupts to be allocated | |
1512 | * than the device has interrupts for. These are not programmed | |
1513 | * into the device's MSI-X table and must be handled by some | |
1514 | * other driver means. | |
1515 | */ | |
1516 | #define PCI_IRQ_VIRTUAL (1 << 4) | |
1517 | ||
4fe0d154 CH |
1518 | #define PCI_IRQ_ALL_TYPES \ |
1519 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) | |
aff17164 | 1520 | |
1da177e4 LT |
1521 | #include <linux/dmapool.h> |
1522 | ||
1da177e4 | 1523 | struct msix_entry { |
0aa0f5d1 BH |
1524 | u32 vector; /* Kernel uses to write allocated vector */ |
1525 | u16 entry; /* Driver uses to specify entry, OS writes */ | |
1da177e4 LT |
1526 | }; |
1527 | ||
4c859804 BH |
1528 | #ifdef CONFIG_PCI_MSI |
1529 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 | 1530 | void pci_disable_msi(struct pci_dev *dev); |
4c859804 | 1531 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 | 1532 | void pci_disable_msix(struct pci_dev *dev); |
f39d5b72 BH |
1533 | void pci_restore_msi_state(struct pci_dev *dev); |
1534 | int pci_msi_enabled(void); | |
4fe03955 | 1535 | int pci_enable_msi(struct pci_dev *dev); |
4c859804 BH |
1536 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1537 | int minvec, int maxvec); | |
f7fc32cb AG |
1538 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1539 | struct msix_entry *entries, int nvec) | |
1540 | { | |
1541 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1542 | if (rc < 0) | |
1543 | return rc; | |
1544 | return 0; | |
1545 | } | |
402723ad CH |
1546 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1547 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1548 | struct irq_affinity *affd); |
402723ad | 1549 | |
aff17164 CH |
1550 | void pci_free_irq_vectors(struct pci_dev *dev); |
1551 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); | |
ee8d41e5 | 1552 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
aff17164 | 1553 | |
4c859804 | 1554 | #else |
2ee546c4 | 1555 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1556 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
1557 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
2ee546c4 | 1558 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
2ee546c4 BH |
1559 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1560 | static inline int pci_msi_enabled(void) { return 0; } | |
4fe03955 | 1561 | static inline int pci_enable_msi(struct pci_dev *dev) |
f7fc32cb | 1562 | { return -ENOSYS; } |
302a2523 | 1563 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
0aa0f5d1 | 1564 | struct msix_entry *entries, int minvec, int maxvec) |
2ee546c4 | 1565 | { return -ENOSYS; } |
f7fc32cb | 1566 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
0aa0f5d1 | 1567 | struct msix_entry *entries, int nvec) |
f7fc32cb | 1568 | { return -ENOSYS; } |
402723ad CH |
1569 | |
1570 | static inline int | |
1571 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1572 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1573 | struct irq_affinity *aff_desc) |
aff17164 | 1574 | { |
83b4605b CH |
1575 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) |
1576 | return 1; | |
1577 | return -ENOSPC; | |
aff17164 | 1578 | } |
402723ad | 1579 | |
aff17164 CH |
1580 | static inline void pci_free_irq_vectors(struct pci_dev *dev) |
1581 | { | |
1582 | } | |
1583 | ||
1584 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1585 | { | |
1586 | if (WARN_ON_ONCE(nr > 0)) | |
1587 | return -EINVAL; | |
1588 | return dev->irq; | |
1589 | } | |
ee8d41e5 TG |
1590 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
1591 | int vec) | |
1592 | { | |
1593 | return cpu_possible_mask; | |
1594 | } | |
1da177e4 LT |
1595 | #endif |
1596 | ||
0d58e6c1 PB |
1597 | /** |
1598 | * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq | |
1599 | * @d: the INTx IRQ domain | |
1600 | * @node: the DT node for the device whose interrupt we're translating | |
1601 | * @intspec: the interrupt specifier data from the DT | |
1602 | * @intsize: the number of entries in @intspec | |
1603 | * @out_hwirq: pointer at which to write the hwirq number | |
1604 | * @out_type: pointer at which to write the interrupt type | |
1605 | * | |
1606 | * Translate a PCI INTx interrupt number from device tree in the range 1-4, as | |
1607 | * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range | |
1608 | * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the | |
1609 | * INTx value to obtain the hwirq number. | |
1610 | * | |
1611 | * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. | |
1612 | */ | |
1613 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, | |
1614 | struct device_node *node, | |
1615 | const u32 *intspec, | |
1616 | unsigned int intsize, | |
1617 | unsigned long *out_hwirq, | |
1618 | unsigned int *out_type) | |
1619 | { | |
1620 | const u32 intx = intspec[0]; | |
1621 | ||
1622 | if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) | |
1623 | return -EINVAL; | |
1624 | ||
1625 | *out_hwirq = intx - PCI_INTERRUPT_INTA; | |
1626 | return 0; | |
1627 | } | |
1628 | ||
ab0724ff | 1629 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 | 1630 | extern bool pcie_ports_disabled; |
5352a44a | 1631 | extern bool pcie_ports_native; |
ab0724ff MT |
1632 | #else |
1633 | #define pcie_ports_disabled true | |
5352a44a | 1634 | #define pcie_ports_native false |
ab0724ff | 1635 | #endif |
415e12b2 | 1636 | |
aff5d055 HK |
1637 | #define PCIE_LINK_STATE_L0S BIT(0) |
1638 | #define PCIE_LINK_STATE_L1 BIT(1) | |
1639 | #define PCIE_LINK_STATE_CLKPM BIT(2) | |
1640 | #define PCIE_LINK_STATE_L1_1 BIT(3) | |
1641 | #define PCIE_LINK_STATE_L1_2 BIT(4) | |
1642 | #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) | |
1643 | #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) | |
7ce2e76a | 1644 | |
4c859804 | 1645 | #ifdef CONFIG_PCIEASPM |
7ce2e76a KW |
1646 | int pci_disable_link_state(struct pci_dev *pdev, int state); |
1647 | int pci_disable_link_state_locked(struct pci_dev *pdev, int state); | |
1648 | void pcie_no_aspm(void); | |
f39d5b72 | 1649 | bool pcie_aspm_support_enabled(void); |
accd2dd7 | 1650 | bool pcie_aspm_enabled(struct pci_dev *pdev); |
4c859804 | 1651 | #else |
7ce2e76a KW |
1652 | static inline int pci_disable_link_state(struct pci_dev *pdev, int state) |
1653 | { return 0; } | |
1654 | static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
1655 | { return 0; } | |
1656 | static inline void pcie_no_aspm(void) { } | |
4c859804 | 1657 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
accd2dd7 | 1658 | static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } |
3e1b1600 AP |
1659 | #endif |
1660 | ||
415e12b2 | 1661 | #ifdef CONFIG_PCIEAER |
415e12b2 RW |
1662 | bool pci_aer_available(void); |
1663 | #else | |
415e12b2 RW |
1664 | static inline bool pci_aer_available(void) { return false; } |
1665 | #endif | |
1666 | ||
cef74409 GK |
1667 | bool pci_ats_disabled(void); |
1668 | ||
1d71eb53 VCG |
1669 | #ifdef CONFIG_PCIE_PTM |
1670 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); | |
014408cd | 1671 | bool pcie_ptm_enabled(struct pci_dev *dev); |
1d71eb53 VCG |
1672 | #else |
1673 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) | |
1674 | { return -EINVAL; } | |
014408cd VCG |
1675 | static inline bool pcie_ptm_enabled(struct pci_dev *dev) |
1676 | { return false; } | |
1d71eb53 VCG |
1677 | #endif |
1678 | ||
f39d5b72 BH |
1679 | void pci_cfg_access_lock(struct pci_dev *dev); |
1680 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1681 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1682 | |
dfd5bb23 | 1683 | void pci_dev_lock(struct pci_dev *dev); |
e3a9b121 LC |
1684 | int pci_dev_trylock(struct pci_dev *dev); |
1685 | void pci_dev_unlock(struct pci_dev *dev); | |
1686 | ||
4352dfd5 GKH |
1687 | /* |
1688 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1689 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1690 | * configuration space. |
1691 | */ | |
32a2eea7 JG |
1692 | #ifdef CONFIG_PCI_DOMAINS |
1693 | extern int pci_domains_supported; | |
1694 | #else | |
1695 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1696 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1697 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
32a2eea7 | 1698 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1699 | |
670ba0c8 CM |
1700 | /* |
1701 | * Generic implementation for PCI domain support. If your | |
1702 | * architecture does not need custom management of PCI | |
1703 | * domains then this implementation will be used | |
1704 | */ | |
1705 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1706 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1707 | { | |
1708 | return bus->domain_nr; | |
1709 | } | |
2ab51dde TN |
1710 | #ifdef CONFIG_ACPI |
1711 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); | |
670ba0c8 | 1712 | #else |
2ab51dde TN |
1713 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
1714 | { return 0; } | |
1715 | #endif | |
9c7cb891 | 1716 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
670ba0c8 CM |
1717 | #endif |
1718 | ||
0aa0f5d1 | 1719 | /* Some architectures require additional setup to direct VGA traffic */ |
95a8b6ef | 1720 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
0aa0f5d1 | 1721 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1722 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1723 | |
be9d2e89 JT |
1724 | static inline int |
1725 | pci_request_io_regions(struct pci_dev *pdev, const char *name) | |
1726 | { | |
1727 | return pci_request_selected_regions(pdev, | |
1728 | pci_select_bars(pdev, IORESOURCE_IO), name); | |
1729 | } | |
1730 | ||
1731 | static inline void | |
1732 | pci_release_io_regions(struct pci_dev *pdev) | |
1733 | { | |
1734 | return pci_release_selected_regions(pdev, | |
1735 | pci_select_bars(pdev, IORESOURCE_IO)); | |
1736 | } | |
1737 | ||
1738 | static inline int | |
1739 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) | |
1740 | { | |
1741 | return pci_request_selected_regions(pdev, | |
1742 | pci_select_bars(pdev, IORESOURCE_MEM), name); | |
1743 | } | |
1744 | ||
1745 | static inline void | |
1746 | pci_release_mem_regions(struct pci_dev *pdev) | |
1747 | { | |
1748 | return pci_release_selected_regions(pdev, | |
1749 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1750 | } | |
1751 | ||
4352dfd5 | 1752 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 | 1753 | |
5bbe029f BH |
1754 | static inline void pci_set_flags(int flags) { } |
1755 | static inline void pci_add_flags(int flags) { } | |
1756 | static inline void pci_clear_flags(int flags) { } | |
1757 | static inline int pci_has_flag(int flag) { return 0; } | |
1758 | ||
1da177e4 | 1759 | /* |
0aa0f5d1 BH |
1760 | * If the system does not have PCI, clearly these return errors. Define |
1761 | * these as simple inline functions to avoid hair in drivers. | |
1da177e4 | 1762 | */ |
05cca6e5 GKH |
1763 | #define _PCI_NOP(o, s, t) \ |
1764 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1765 | int where, t val) \ | |
1da177e4 | 1766 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1767 | |
1768 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1769 | _PCI_NOP(o, word, u16 x) \ | |
1770 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1771 | _PCI_NOP_ALL(read, *) |
1772 | _PCI_NOP_ALL(write,) | |
1773 | ||
d42552c3 | 1774 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1775 | unsigned int device, |
1776 | struct pci_dev *from) | |
2ee546c4 | 1777 | { return NULL; } |
d42552c3 | 1778 | |
05cca6e5 GKH |
1779 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1780 | unsigned int device, | |
1781 | unsigned int ss_vendor, | |
1782 | unsigned int ss_device, | |
b08508c4 | 1783 | struct pci_dev *from) |
2ee546c4 | 1784 | { return NULL; } |
1da177e4 | 1785 | |
05cca6e5 GKH |
1786 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1787 | struct pci_dev *from) | |
2ee546c4 | 1788 | { return NULL; } |
1da177e4 | 1789 | |
877fee2a HG |
1790 | |
1791 | static inline int pci_dev_present(const struct pci_device_id *ids) | |
1792 | { return 0; } | |
1793 | ||
ed4aaadb | 1794 | #define no_pci_devices() (1) |
1da177e4 LT |
1795 | #define pci_dev_put(dev) do { } while (0) |
1796 | ||
2ee546c4 BH |
1797 | static inline void pci_set_master(struct pci_dev *dev) { } |
1798 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
1799 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
977da073 | 1800 | static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } |
05cca6e5 | 1801 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1802 | { return -EBUSY; } |
817f9916 AS |
1803 | static inline int __must_check __pci_register_driver(struct pci_driver *drv, |
1804 | struct module *owner, | |
1805 | const char *mod_name) | |
2ee546c4 | 1806 | { return 0; } |
05cca6e5 | 1807 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
1808 | { return 0; } |
1809 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
f646c2a0 | 1810 | static inline u8 pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1811 | { return 0; } |
05cca6e5 GKH |
1812 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1813 | int cap) | |
2ee546c4 | 1814 | { return 0; } |
05cca6e5 | 1815 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1816 | { return 0; } |
05cca6e5 | 1817 | |
70c0923b JK |
1818 | static inline u64 pci_get_dsn(struct pci_dev *dev) |
1819 | { return 0; } | |
1820 | ||
1da177e4 | 1821 | /* Power management related routines */ |
2ee546c4 BH |
1822 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
1823 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 1824 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 1825 | { return 0; } |
3449248c | 1826 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 1827 | { return 0; } |
05cca6e5 GKH |
1828 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1829 | pm_message_t state) | |
2ee546c4 | 1830 | { return PCI_D0; } |
05cca6e5 GKH |
1831 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1832 | int enable) | |
2ee546c4 | 1833 | { return 0; } |
48a92a81 | 1834 | |
afd29f90 MW |
1835 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
1836 | struct resource *res) | |
1837 | { return NULL; } | |
05cca6e5 | 1838 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
1839 | { return -EIO; } |
1840 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 1841 | |
00dcc7cf RH |
1842 | static inline int pci_register_io_range(struct fwnode_handle *fwnode, |
1843 | phys_addr_t addr, resource_size_t size) | |
1844 | { return -EINVAL; } | |
1845 | ||
c5076cfe TN |
1846 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
1847 | ||
d80d0217 RD |
1848 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1849 | { return NULL; } | |
d80d0217 RD |
1850 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1851 | unsigned int devfn) | |
1852 | { return NULL; } | |
7912af5c RD |
1853 | static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, |
1854 | unsigned int bus, unsigned int devfn) | |
1855 | { return NULL; } | |
d80d0217 | 1856 | |
2ee546c4 BH |
1857 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1858 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
12ea6cad | 1859 | |
fb8a0d9d WM |
1860 | #define dev_is_pci(d) (false) |
1861 | #define dev_is_pf(d) (false) | |
fe594932 GU |
1862 | static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) |
1863 | { return false; } | |
80db6f08 NC |
1864 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
1865 | struct device_node *node, | |
1866 | const u32 *intspec, | |
1867 | unsigned int intsize, | |
1868 | unsigned long *out_hwirq, | |
1869 | unsigned int *out_type) | |
1870 | { return -EINVAL; } | |
9c212009 LR |
1871 | |
1872 | static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
1873 | struct pci_dev *dev) | |
1874 | { return NULL; } | |
b9ae16d8 | 1875 | static inline bool pci_ats_disabled(void) { return true; } |
0d8006dd HX |
1876 | |
1877 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1878 | { | |
1879 | return -EINVAL; | |
1880 | } | |
1881 | ||
1882 | static inline int | |
1883 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1884 | unsigned int max_vecs, unsigned int flags, | |
1885 | struct irq_affinity *aff_desc) | |
1886 | { | |
1887 | return -ENOSPC; | |
1888 | } | |
4352dfd5 | 1889 | #endif /* CONFIG_PCI */ |
1da177e4 | 1890 | |
0d8006dd HX |
1891 | static inline int |
1892 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1893 | unsigned int max_vecs, unsigned int flags) | |
1894 | { | |
1895 | return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, | |
1896 | NULL); | |
1897 | } | |
1898 | ||
4352dfd5 GKH |
1899 | /* Include architecture-dependent settings and functions */ |
1900 | ||
1901 | #include <asm/pci.h> | |
1da177e4 | 1902 | |
d1bbf38a | 1903 | /* These two functions provide almost identical functionality. Depending |
f7195824 DW |
1904 | * on the architecture, one will be implemented as a wrapper around the |
1905 | * other (in drivers/pci/mmap.c). | |
1906 | * | |
1907 | * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff | |
1908 | * is expected to be an offset within that region. | |
1909 | * | |
1910 | * pci_mmap_page_range() is the legacy architecture-specific interface, | |
1911 | * which accepts a "user visible" resource address converted by | |
1912 | * pci_resource_to_user(), as used in the legacy mmap() interface in | |
1913 | * /proc/bus/pci/. | |
1914 | */ | |
1915 | int pci_mmap_resource_range(struct pci_dev *dev, int bar, | |
1916 | struct vm_area_struct *vma, | |
1917 | enum pci_mmap_state mmap_state, int write_combine); | |
f66e2258 DW |
1918 | int pci_mmap_page_range(struct pci_dev *pdev, int bar, |
1919 | struct vm_area_struct *vma, | |
11df1954 DW |
1920 | enum pci_mmap_state mmap_state, int write_combine); |
1921 | ||
ae749c7a DW |
1922 | #ifndef arch_can_pci_mmap_wc |
1923 | #define arch_can_pci_mmap_wc() 0 | |
1924 | #endif | |
2bea36fd | 1925 | |
e854d8b2 DW |
1926 | #ifndef arch_can_pci_mmap_io |
1927 | #define arch_can_pci_mmap_io() 0 | |
2bea36fd DW |
1928 | #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) |
1929 | #else | |
1930 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); | |
e854d8b2 | 1931 | #endif |
ae749c7a | 1932 | |
92016ba5 JO |
1933 | #ifndef pci_root_bus_fwnode |
1934 | #define pci_root_bus_fwnode(bus) NULL | |
1935 | #endif | |
1936 | ||
0aa0f5d1 BH |
1937 | /* |
1938 | * These helpers provide future and backwards compatibility | |
1939 | * for accessing popular PCI BAR info | |
1940 | */ | |
05cca6e5 GKH |
1941 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1942 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1943 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1944 | #define pci_resource_len(dev,bar) \ |
ca32b531 | 1945 | ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ |
05cca6e5 GKH |
1946 | \ |
1947 | (pci_resource_end((dev), (bar)) - \ | |
1948 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 | 1949 | |
0aa0f5d1 BH |
1950 | /* |
1951 | * Similar to the helpers above, these manipulate per-pci_dev | |
1da177e4 LT |
1952 | * driver-specific data. They are really just a wrapper around |
1953 | * the generic device structure functions of these calls. | |
1954 | */ | |
05cca6e5 | 1955 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1956 | { |
1957 | return dev_get_drvdata(&pdev->dev); | |
1958 | } | |
1959 | ||
05cca6e5 | 1960 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1961 | { |
1962 | dev_set_drvdata(&pdev->dev, data); | |
1963 | } | |
1964 | ||
2fc90f61 | 1965 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1966 | { |
c6c4f070 | 1967 | return dev_name(&pdev->dev); |
1da177e4 LT |
1968 | } |
1969 | ||
8221a013 BH |
1970 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1971 | const struct resource *rsrc, | |
1972 | resource_size_t *start, resource_size_t *end); | |
2311b1f2 | 1973 | |
1da177e4 | 1974 | /* |
0aa0f5d1 BH |
1975 | * The world is not perfect and supplies us with broken PCI devices. |
1976 | * For at least a part of these bugs we need a work-around, so both | |
1977 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1978 | * fixup hooks to be called for particular buggy devices. | |
1da177e4 LT |
1979 | */ |
1980 | ||
1981 | struct pci_fixup { | |
0aa0f5d1 BH |
1982 | u16 vendor; /* Or PCI_ANY_ID */ |
1983 | u16 device; /* Or PCI_ANY_ID */ | |
1984 | u32 class; /* Or PCI_ANY_ID */ | |
f4ca5c6a | 1985 | unsigned int class_shift; /* should be 0, 8, 16 */ |
c9d8b55f AB |
1986 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
1987 | int hook_offset; | |
1988 | #else | |
1da177e4 | 1989 | void (*hook)(struct pci_dev *dev); |
c9d8b55f | 1990 | #endif |
1da177e4 LT |
1991 | }; |
1992 | ||
1993 | enum pci_fixup_pass { | |
1994 | pci_fixup_early, /* Before probing BARs */ | |
1995 | pci_fixup_header, /* After reading configuration header */ | |
1996 | pci_fixup_final, /* Final phase of device fixups */ | |
1997 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 1998 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 1999 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 2000 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 2001 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
2002 | }; |
2003 | ||
c9d8b55f | 2004 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
09a4e4d9 | 2005 | #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ |
c9d8b55f AB |
2006 | class_shift, hook) \ |
2007 | __ADDRESSABLE(hook) \ | |
2008 | asm(".section " #sec ", \"a\" \n" \ | |
2009 | ".balign 16 \n" \ | |
2010 | ".short " #vendor ", " #device " \n" \ | |
2011 | ".long " #class ", " #class_shift " \n" \ | |
2012 | ".long " #hook " - . \n" \ | |
2013 | ".previous \n"); | |
09a4e4d9 ST |
2014 | |
2015 | /* | |
2016 | * Clang's LTO may rename static functions in C, but has no way to | |
2017 | * handle such renamings when referenced from inline asm. To work | |
2018 | * around this, create global C stubs for these cases. | |
2019 | */ | |
2020 | #ifdef CONFIG_LTO_CLANG | |
2021 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2022 | class_shift, hook, stub) \ | |
ff301ceb ST |
2023 | void __cficanonical stub(struct pci_dev *dev); \ |
2024 | void __cficanonical stub(struct pci_dev *dev) \ | |
09a4e4d9 ST |
2025 | { \ |
2026 | hook(dev); \ | |
2027 | } \ | |
2028 | ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2029 | class_shift, stub) | |
2030 | #else | |
2031 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2032 | class_shift, hook, stub) \ | |
2033 | ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
2034 | class_shift, hook) | |
2035 | #endif | |
2036 | ||
c9d8b55f AB |
2037 | #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ |
2038 | class_shift, hook) \ | |
2039 | __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
09a4e4d9 | 2040 | class_shift, hook, __UNIQUE_ID(hook)) |
c9d8b55f | 2041 | #else |
1da177e4 | 2042 | /* Anonymous variables would be nice... */ |
f4ca5c6a YL |
2043 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
2044 | class_shift, hook) \ | |
ecf61c78 | 2045 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
2046 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
2047 | = { vendor, device, class, class_shift, hook }; | |
c9d8b55f | 2048 | #endif |
f4ca5c6a YL |
2049 | |
2050 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
2051 | class_shift, hook) \ | |
2052 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 2053 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2054 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
2055 | class_shift, hook) \ | |
2056 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 2057 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2058 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
2059 | class_shift, hook) \ | |
2060 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 2061 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2062 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
2063 | class_shift, hook) \ | |
2064 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 2065 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2066 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
2067 | class_shift, hook) \ | |
2068 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 2069 | resume##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2070 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
2071 | class_shift, hook) \ | |
2072 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 2073 | resume_early##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
2074 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
2075 | class_shift, hook) \ | |
2076 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 2077 | suspend##hook, vendor, device, class, class_shift, hook) |
7d2a01b8 AN |
2078 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
2079 | class_shift, hook) \ | |
2080 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 2081 | suspend_late##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a | 2082 | |
1da177e4 LT |
2083 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
2084 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 2085 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2086 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
2087 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 2088 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2089 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
2090 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 2091 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
2092 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
2093 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 2094 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
2095 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
2096 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 2097 | resume##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
2098 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
2099 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 2100 | resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
2101 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
2102 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 2103 | suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
2104 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
2105 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 2106 | suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 | 2107 | |
93177a74 | 2108 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 2109 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
2110 | #else |
2111 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 2112 | struct pci_dev *dev) { } |
93177a74 | 2113 | #endif |
1da177e4 | 2114 | |
05cca6e5 | 2115 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 2116 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 2117 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
2118 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
2119 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 2120 | const char *name); |
fb7ebfe4 | 2121 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 2122 | |
1da177e4 | 2123 | extern int pci_pci_problems; |
236561e5 | 2124 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
2125 | #define PCIPCI_TRITON 2 |
2126 | #define PCIPCI_NATOMA 4 | |
2127 | #define PCIPCI_VIAETBF 8 | |
2128 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
2129 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
2130 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 2131 | |
4516a618 AN |
2132 | extern unsigned long pci_cardbus_io_size; |
2133 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 2134 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 2135 | extern u8 pci_cache_line_size; |
4516a618 | 2136 | |
f7625980 | 2137 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 2138 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 2139 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
2140 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2141 | enum pcie_reset_state state); | |
06dc660e | 2142 | int pcibios_device_add(struct pci_dev *dev); |
6ae32c53 | 2143 | void pcibios_release_device(struct pci_dev *dev); |
5d32a665 | 2144 | #ifdef CONFIG_PCI |
a43ae58c | 2145 | void pcibios_penalize_isa_irq(int irq, int active); |
5d32a665 SK |
2146 | #else |
2147 | static inline void pcibios_penalize_isa_irq(int irq, int active) {} | |
2148 | #endif | |
890e4847 JL |
2149 | int pcibios_alloc_irq(struct pci_dev *dev); |
2150 | void pcibios_free_irq(struct pci_dev *dev); | |
619e6f34 | 2151 | resource_size_t pcibios_default_alignment(void); |
575e3348 | 2152 | |
935c760e | 2153 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
f39d5b72 BH |
2154 | void __init pci_mmcfg_early_init(void); |
2155 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 2156 | #else |
bb63b421 | 2157 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
2158 | static inline void pci_mmcfg_late_init(void) { } |
2159 | #endif | |
2160 | ||
642c92da | 2161 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 2162 | |
1684f5dd | 2163 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
c43996f4 | 2164 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 2165 | |
dd7cc44d | 2166 | #ifdef CONFIG_PCI_IOV |
b07579c0 WY |
2167 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
2168 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); | |
2169 | ||
f39d5b72 BH |
2170 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
2171 | void pci_disable_sriov(struct pci_dev *dev); | |
a1ceea67 NS |
2172 | |
2173 | int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); | |
753f6124 JS |
2174 | int pci_iov_add_virtfn(struct pci_dev *dev, int id); |
2175 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id); | |
f39d5b72 | 2176 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 2177 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
2178 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
2179 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
8effc395 | 2180 | int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); |
0e6c9122 | 2181 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
608c0d88 | 2182 | void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); |
619e6f34 MM |
2183 | |
2184 | /* Arch may override these (weak) */ | |
2185 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); | |
2186 | int pcibios_sriov_disable(struct pci_dev *pdev); | |
2187 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); | |
dd7cc44d | 2188 | #else |
b07579c0 WY |
2189 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
2190 | { | |
2191 | return -ENOSYS; | |
2192 | } | |
2193 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) | |
2194 | { | |
2195 | return -ENOSYS; | |
2196 | } | |
dd7cc44d | 2197 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
2ee546c4 | 2198 | { return -ENODEV; } |
a1ceea67 NS |
2199 | |
2200 | static inline int pci_iov_sysfs_link(struct pci_dev *dev, | |
2201 | struct pci_dev *virtfn, int id) | |
2202 | { | |
2203 | return -ENODEV; | |
2204 | } | |
753f6124 | 2205 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) |
c194f7ea WY |
2206 | { |
2207 | return -ENOSYS; | |
2208 | } | |
2209 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, | |
753f6124 | 2210 | int id) { } |
2ee546c4 | 2211 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
2ee546c4 | 2212 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 2213 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 2214 | { return 0; } |
bff73156 | 2215 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 2216 | { return 0; } |
bff73156 | 2217 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 2218 | { return 0; } |
8effc395 | 2219 | #define pci_sriov_configure_simple NULL |
0e6c9122 WY |
2220 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
2221 | { return 0; } | |
608c0d88 | 2222 | static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } |
dd7cc44d YZ |
2223 | #endif |
2224 | ||
c825bc94 | 2225 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
2226 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
2227 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
2228 | #endif |
2229 | ||
d7b7e605 KK |
2230 | /** |
2231 | * pci_pcie_cap - get the saved PCIe capability offset | |
2232 | * @dev: PCI device | |
2233 | * | |
2234 | * PCIe capability offset is calculated at PCI device initialization | |
2235 | * time and saved in the data structure. This function returns saved | |
2236 | * PCIe capability offset. Using this instead of pci_find_capability() | |
2237 | * reduces unnecessary search in the PCI configuration space. If you | |
2238 | * need to calculate PCIe capability offset from raw device for some | |
2239 | * reasons, please use pci_find_capability() instead. | |
2240 | */ | |
2241 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
2242 | { | |
2243 | return dev->pcie_cap; | |
2244 | } | |
2245 | ||
7eb776c4 KK |
2246 | /** |
2247 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
2248 | * @dev: PCI device | |
2249 | * | |
a895c28a | 2250 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
2251 | */ |
2252 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
2253 | { | |
a895c28a | 2254 | return pci_pcie_cap(dev); |
7eb776c4 KK |
2255 | } |
2256 | ||
7c9c003c MS |
2257 | /** |
2258 | * pcie_caps_reg - get the PCIe Capabilities Register | |
2259 | * @dev: PCI device | |
2260 | */ | |
2261 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
2262 | { | |
2263 | return dev->pcie_flags_reg; | |
2264 | } | |
2265 | ||
786e2288 YW |
2266 | /** |
2267 | * pci_pcie_type - get the PCIe device/port type | |
2268 | * @dev: PCI device | |
2269 | */ | |
2270 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
2271 | { | |
1c531d82 | 2272 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
2273 | } |
2274 | ||
6ae72bfa YY |
2275 | /** |
2276 | * pcie_find_root_port - Get the PCIe root port device | |
2277 | * @dev: PCI device | |
2278 | * | |
2279 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
2280 | * for a given PCI/PCIe Device. | |
2281 | */ | |
e784930b JT |
2282 | static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) |
2283 | { | |
5396956c MW |
2284 | while (dev) { |
2285 | if (pci_is_pcie(dev) && | |
2286 | pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2287 | return dev; | |
2288 | dev = pci_upstream_bridge(dev); | |
e784930b | 2289 | } |
6ae72bfa | 2290 | |
e784930b JT |
2291 | return NULL; |
2292 | } | |
2293 | ||
5d990b62 | 2294 | void pci_request_acs(void); |
ad805758 AW |
2295 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
2296 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2297 | struct pci_dev *end, u16 acs_flags); | |
430a2368 | 2298 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); |
a2ce7662 | 2299 | |
7ad506fa | 2300 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 2301 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
2302 | |
2303 | /* Large Resource Data Type Tag Item Names */ | |
2304 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
2305 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
2306 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
2307 | ||
2308 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
2309 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
2310 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
2311 | ||
4067a854 | 2312 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
16efafa3 | 2313 | #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" |
4067a854 MC |
2314 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
2315 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 2316 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 2317 | |
a2ce7662 | 2318 | /** |
76f3c032 HK |
2319 | * pci_vpd_alloc - Allocate buffer and read VPD into it |
2320 | * @dev: PCI device | |
2321 | * @size: pointer to field where VPD length is returned | |
9eb45d5c | 2322 | * |
76f3c032 | 2323 | * Returns pointer to allocated buffer or an ERR_PTR in case of failure |
9eb45d5c | 2324 | */ |
76f3c032 | 2325 | void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); |
9eb45d5c | 2326 | |
e1d5bdab | 2327 | /** |
acfbb1b8 HK |
2328 | * pci_vpd_find_id_string - Locate id string in VPD |
2329 | * @buf: Pointer to buffered VPD data | |
2330 | * @len: The length of the buffer area in which to search | |
2331 | * @size: Pointer to field where length of id string is returned | |
e1d5bdab | 2332 | * |
acfbb1b8 | 2333 | * Returns the index of the id string or -ENOENT if not found. |
e1d5bdab | 2334 | */ |
acfbb1b8 | 2335 | int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); |
e1d5bdab | 2336 | |
b55ac1b2 | 2337 | /** |
9e515c9f HK |
2338 | * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section |
2339 | * @buf: Pointer to buffered VPD data | |
2340 | * @len: The length of the buffer area in which to search | |
2341 | * @kw: The keyword to search for | |
2342 | * @size: Pointer to field where length of found keyword data is returned | |
b55ac1b2 | 2343 | * |
9e515c9f HK |
2344 | * Returns the index of the information field keyword data or -ENOENT if |
2345 | * not found. | |
b55ac1b2 | 2346 | */ |
9e515c9f HK |
2347 | int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, |
2348 | const char *kw, unsigned int *size); | |
b55ac1b2 | 2349 | |
4067a854 | 2350 | /** |
6107e5cb HK |
2351 | * pci_vpd_check_csum - Check VPD checksum |
2352 | * @buf: Pointer to buffered VPD data | |
2353 | * @len: VPD size | |
4067a854 | 2354 | * |
6107e5cb | 2355 | * Returns 1 if VPD has no checksum, otherwise 0 or an errno |
4067a854 | 2356 | */ |
6107e5cb | 2357 | int pci_vpd_check_csum(const void *buf, unsigned int len); |
4067a854 | 2358 | |
98d9f30c BH |
2359 | /* PCI <-> OF binding helpers */ |
2360 | #ifdef CONFIG_OF | |
2361 | struct device_node; | |
b165e2b6 | 2362 | struct irq_domain; |
b165e2b6 | 2363 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
85aabbd7 | 2364 | bool pci_host_of_has_msi_map(struct device *dev); |
98d9f30c BH |
2365 | |
2366 | /* Arch may override this (weak) */ | |
723ec4d0 | 2367 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 2368 | |
0aa0f5d1 | 2369 | #else /* CONFIG_OF */ |
b165e2b6 MZ |
2370 | static inline struct irq_domain * |
2371 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } | |
85aabbd7 | 2372 | static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } |
98d9f30c BH |
2373 | #endif /* CONFIG_OF */ |
2374 | ||
ad32eb2d BM |
2375 | static inline struct device_node * |
2376 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
2377 | { | |
2378 | return pdev ? pdev->dev.of_node : NULL; | |
2379 | } | |
2380 | ||
2381 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) | |
2382 | { | |
2383 | return bus ? bus->dev.of_node : NULL; | |
2384 | } | |
2385 | ||
471036b2 SS |
2386 | #ifdef CONFIG_ACPI |
2387 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); | |
2388 | ||
2389 | void | |
2390 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); | |
52525b7a | 2391 | bool pci_pr3_present(struct pci_dev *pdev); |
471036b2 SS |
2392 | #else |
2393 | static inline struct irq_domain * | |
2394 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } | |
46b4bff6 | 2395 | static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } |
471036b2 SS |
2396 | #endif |
2397 | ||
eb740b5f GS |
2398 | #ifdef CONFIG_EEH |
2399 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
2400 | { | |
2401 | return pdev->dev.archdata.edev; | |
2402 | } | |
2403 | #endif | |
2404 | ||
09298542 | 2405 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); |
338c3149 | 2406 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
c25dc828 AW |
2407 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
2408 | int (*fn)(struct pci_dev *pdev, | |
2409 | u16 alias, void *data), void *data); | |
2410 | ||
0aa0f5d1 | 2411 | /* Helper functions for operation of device flag */ |
ce052984 EZ |
2412 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
2413 | { | |
2414 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
2415 | } | |
2416 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
2417 | { | |
2418 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
2419 | } | |
2420 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
2421 | { | |
2422 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
2423 | } | |
19bdb6e4 AW |
2424 | |
2425 | /** | |
2426 | * pci_ari_enabled - query ARI forwarding status | |
2427 | * @bus: the PCI bus | |
2428 | * | |
2429 | * Returns true if ARI forwarding is enabled. | |
2430 | */ | |
2431 | static inline bool pci_ari_enabled(struct pci_bus *bus) | |
2432 | { | |
2433 | return bus->self && bus->self->ari_enabled; | |
2434 | } | |
bc4b024a | 2435 | |
8531e283 LW |
2436 | /** |
2437 | * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain | |
2438 | * @pdev: PCI device to check | |
2439 | * | |
2440 | * Walk upwards from @pdev and check for each encountered bridge if it's part | |
2441 | * of a Thunderbolt controller. Reaching the host bridge means @pdev is not | |
2442 | * Thunderbolt-attached. (But rather soldered to the mainboard usually.) | |
2443 | */ | |
2444 | static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) | |
2445 | { | |
2446 | struct pci_dev *parent = pdev; | |
2447 | ||
2448 | if (pdev->is_thunderbolt) | |
2449 | return true; | |
2450 | ||
2451 | while ((parent = pci_upstream_bridge(parent))) | |
2452 | if (parent->is_thunderbolt) | |
2453 | return true; | |
2454 | ||
2455 | return false; | |
2456 | } | |
2457 | ||
2e28bc84 | 2458 | #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) |
3ecac020 ME |
2459 | void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); |
2460 | #endif | |
856e1eb9 | 2461 | |
0aa0f5d1 | 2462 | /* Provide the legacy pci_dma_* API */ |
bc4b024a CH |
2463 | #include <linux/pci-dma-compat.h> |
2464 | ||
7506dc79 FL |
2465 | #define pci_printk(level, pdev, fmt, arg...) \ |
2466 | dev_printk(level, &(pdev)->dev, fmt, ##arg) | |
2467 | ||
2468 | #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) | |
2469 | #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) | |
2470 | #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) | |
2471 | #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) | |
2472 | #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) | |
2473 | #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) | |
2474 | #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) | |
2475 | #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) | |
2476 | ||
a88a7b3e BH |
2477 | #define pci_notice_ratelimited(pdev, fmt, arg...) \ |
2478 | dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2479 | ||
7f1c62c4 KW |
2480 | #define pci_info_ratelimited(pdev, fmt, arg...) \ |
2481 | dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2482 | ||
12bcae44 BH |
2483 | #define pci_WARN(pdev, condition, fmt, arg...) \ |
2484 | WARN(condition, "%s %s: " fmt, \ | |
2485 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2486 | ||
2487 | #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ | |
2488 | WARN_ONCE(condition, "%s %s: " fmt, \ | |
2489 | dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) | |
2490 | ||
1da177e4 | 2491 | #endif /* LINUX_PCI_H */ |