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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville...
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
1da177e4
LT		 16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
1da177e4 19
778382e0
DW		 20#include <linux/mod_devicetable.h>
21
1da177e4 22#include <linux/types.h>
98db6f19 23#include <linux/init.h>
1da177e4
LT		 24#include <linux/ioport.h>
25#include <linux/list.h>
4a7fb636 26#include <linux/compiler.h>
1da177e4 27#include <linux/errno.h>
f46753c5 28#include <linux/kobject.h>
60063497 29#include <linux/atomic.h>
1da177e4 30#include <linux/device.h>
1388cc96 31#include <linux/io.h>
74bb1bcc 32#include <linux/irqreturn.h>
607ca46e 33#include <uapi/linux/pci.h>
1da177e4 34
7e7a43c3
AB		 35/* Include the ID list */
36#include <linux/pci_ids.h>
37
f46753c5
AC		 38/* pci_slot represents a physical slot */
39struct pci_slot {
40 struct pci_bus *bus; /* The bus this slot is on */
41 struct list_head list; /* node in list of slots on this bus */
42 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
43 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
44 struct kobject kobj;
45};
46
0ad772ec
AC		 47static inline const char *pci_slot_name(const struct pci_slot *slot)
48{
49 return kobject_name(&slot->kobj);
50}
51
1da177e4
LT		 52/* File state for mmap()s on /proc/bus/pci/X/Y */
53enum pci_mmap_state {
54 pci_mmap_io,
55 pci_mmap_mem
56};
57
58/* This defines the direction arg to the DMA mapping routines. */
59#define PCI_DMA_BIDIRECTIONAL 0
60#define PCI_DMA_TODEVICE 1
61#define PCI_DMA_FROMDEVICE 2
62#define PCI_DMA_NONE 3
63
fde09c6d
YZ		 64/*
65 * For PCI devices, the region numbers are assigned this way:
66 */
67enum {
68 /* #0-5: standard PCI resources */
69 PCI_STD_RESOURCES,
70 PCI_STD_RESOURCE_END = 5,
71
72 /* #6: expansion ROM resource */
73 PCI_ROM_RESOURCE,
74
d1b054da
YZ		 75 /* device specific resources */
76#ifdef CONFIG_PCI_IOV
77 PCI_IOV_RESOURCES,
78 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
79#endif
80
fde09c6d
YZ		 81 /* resources assigned to buses behind the bridge */
82#define PCI_BRIDGE_RESOURCE_NUM 4
83
84 PCI_BRIDGE_RESOURCES,
85 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
86 PCI_BRIDGE_RESOURCE_NUM - 1,
87
88 /* total resources associated with a PCI device */
89 PCI_NUM_RESOURCES,
90
91 /* preserve this for compatibility */
cda57bf9 92 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 93};
1da177e4
LT		 94
95typedef int __bitwise pci_power_t;
96
4352dfd5
GKH		 97#define PCI_D0 ((pci_power_t __force) 0)
98#define PCI_D1 ((pci_power_t __force) 1)
99#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 100#define PCI_D3hot ((pci_power_t __force) 3)
101#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 102#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 103#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 104
00240c38
AS		 105/* Remember to update this when the list above changes! */
106extern const char *pci_power_names[];
107
108static inline const char *pci_power_name(pci_power_t state)
109{
110 return pci_power_names[1 + (int) state];
111}
112
448bd857
HY		 113#define PCI_PM_D2_DELAY 200
114#define PCI_PM_D3_WAIT 10
115#define PCI_PM_D3COLD_WAIT 100
116#define PCI_PM_BUS_WAIT 50
aa8c6c93 117
392a1ce7 118/** The pci_channel state describes connectivity between the CPU and
119 * the pci device. If some PCI bus between here and the pci device
120 * has crashed or locked up, this info is reflected here.
121 */
122typedef unsigned int __bitwise pci_channel_state_t;
123
124enum pci_channel_state {
125 /* I/O channel is in normal state */
126 pci_channel_io_normal = (__force pci_channel_state_t) 1,
127
128 /* I/O to channel is blocked */
129 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
130
131 /* PCI card is dead */
132 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
133};
134
f7bdd12d
BK		 135typedef unsigned int __bitwise pcie_reset_state_t;
136
137enum pcie_reset_state {
138 /* Reset is NOT asserted (Use to deassert reset) */
139 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
140
141 /* Use #PERST to reset PCI-E device */
142 pcie_warm_reset = (__force pcie_reset_state_t) 2,
143
144 /* Use PCI-E Hot Reset to reset device */
145 pcie_hot_reset = (__force pcie_reset_state_t) 3
146};
147
ba698ad4
DM		 148typedef unsigned short __bitwise pci_dev_flags_t;
149enum pci_dev_flags {
150 /* INTX_DISABLE in PCI_COMMAND register disables MSI
151 * generation too.
152 */
153 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 154 /* Device configuration is irrevocably lost if disabled into D3 */
155 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 156 /* Provide indication device is assigned by a Virtual Machine Manager */
157 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 158};
159
e1d3a908
SA		 160enum pci_irq_reroute_variant {
161 INTEL_IRQ_REROUTE_VARIANT = 1,
162 MAX_IRQ_REROUTE_VARIANTS = 3
163};
164
6e325a62
MT		 165typedef unsigned short __bitwise pci_bus_flags_t;
166enum pci_bus_flags {
d556ad4b
PO		 167 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
168 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 169};
170
536c8cb4
MW		 171/* Based on the PCI Hotplug Spec, but some values are made up by us */
172enum pci_bus_speed {
173 PCI_SPEED_33MHz = 0x00,
174 PCI_SPEED_66MHz = 0x01,
175 PCI_SPEED_66MHz_PCIX = 0x02,
176 PCI_SPEED_100MHz_PCIX = 0x03,
177 PCI_SPEED_133MHz_PCIX = 0x04,
178 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
179 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
180 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
181 PCI_SPEED_66MHz_PCIX_266 = 0x09,
182 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
183 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 184 AGP_UNKNOWN = 0x0c,
185 AGP_1X = 0x0d,
186 AGP_2X = 0x0e,
187 AGP_4X = 0x0f,
188 AGP_8X = 0x10,
536c8cb4
MW		 189 PCI_SPEED_66MHz_PCIX_533 = 0x11,
190 PCI_SPEED_100MHz_PCIX_533 = 0x12,
191 PCI_SPEED_133MHz_PCIX_533 = 0x13,
192 PCIE_SPEED_2_5GT = 0x14,
193 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 194 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 195 PCI_SPEED_UNKNOWN = 0xff,
196};
197
24a4742f 198struct pci_cap_saved_data {
41017f0c 199 char cap_nr;
24a4742f 200 unsigned int size;
41017f0c
SL		 201 u32 data[0];
202};
203
24a4742f
AW		 204struct pci_cap_saved_state {
205 struct hlist_node next;
206 struct pci_cap_saved_data cap;
207};
208
7d715a6c 209struct pcie_link_state;
ee69439c 210struct pci_vpd;
d1b054da 211struct pci_sriov;
302b4215 212struct pci_ats;
ee69439c 213
1da177e4
LT		 214/*
215 * The pci_dev structure is used to describe PCI devices.
216 */
217struct pci_dev {
1da177e4
LT		 218 struct list_head bus_list; /* node in per-bus list */
219 struct pci_bus *bus; /* bus this device is on */
220 struct pci_bus *subordinate; /* bus this device bridges to */
221
222 void *sysdata; /* hook for sys-specific extension */
223 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 224 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 225
226 unsigned int devfn; /* encoded device & function index */
227 unsigned short vendor;
228 unsigned short device;
229 unsigned short subsystem_vendor;
230 unsigned short subsystem_device;
231 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 232 u8 revision; /* PCI revision, low byte of class word */
1da177e4 233 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 234 u8 pcie_cap; /* PCI-E capability offset */
b03e7495 235 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 236 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 237 u8 pin; /* which interrupt pin this device uses */
786e2288 238 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
1da177e4
LT		 239
240 struct pci_driver *driver; /* which driver has allocated this device */
241 u64 dma_mask; /* Mask of the bits of bus address this
242 device implements. Normally this is
243 0xffffffff. You only need to change
244 this if your device has broken DMA
245 or supports 64-bit transfers. */
246
4d57cdfa
FT		 247 struct device_dma_parameters dma_parms;
248
1da177e4
LT		 249 pci_power_t current_state; /* Current operating state. In ACPI-speak,
250 this is D0-D3, D0 being fully functional,
251 and D3 being off. */
337001b6
RW		 252 int pm_cap; /* PM capability offset in the
253 configuration space */
254 unsigned int pme_support:5; /* Bitmask of states from which PME#
255 can be generated */
c7f48656 256 unsigned int pme_interrupt:1;
379021d5 257 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 258 unsigned int d1_support:1; /* Low power state D1 is supported */
259 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 260 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
261 unsigned int no_d3cold:1; /* D3cold is forbidden */
262 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 263 unsigned int mmio_always_on:1; /* disallow turning off io/mem
264 decoding during bar sizing */
e80bb09d 265 unsigned int wakeup_prepared:1;
448bd857
HY		 266 unsigned int runtime_d3cold:1; /* whether go through runtime
267 D3cold, not set for devices
268 powered on/off by the
269 corresponding bridge */
1ae861e6 270 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 271 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 272
7d715a6c
SL		 273#ifdef CONFIG_PCIEASPM
274 struct pcie_link_state *link_state; /* ASPM link state. */
275#endif
276
392a1ce7 277 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 278 struct device dev; /* Generic device interface */
279
1da177e4
LT		 280 int cfg_size; /* Size of configuration space */
281
282 /*
283 * Instead of touching interrupt line and base address registers
284 * directly, use the values stored here. They might be different!
285 */
286 unsigned int irq;
287 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
288
58d9a38f 289 bool match_driver; /* Skip attaching driver */
1da177e4
LT		 290 /* These fields are used by common fixups */
291 unsigned int transparent:1; /* Transparent PCI bridge */
292 unsigned int multifunction:1;/* Part of multi-function device */
293 /* keep track of device state */
8a1bc901 294 unsigned int is_added:1;
1da177e4 295 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 296 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 297 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 298 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 299 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 300 unsigned int msi_enabled:1;
301 unsigned int msix_enabled:1;
58c3a727 302 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 303 unsigned int is_managed:1;
6d3be84a
KK		 304 unsigned int is_pcie:1; /* Obsolete. Will be removed.
305 Use pci_is_pcie() instead */
260d703a 306 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 307 unsigned int state_saved:1;
d1b054da 308 unsigned int is_physfn:1;
dd7cc44d 309 unsigned int is_virtfn:1;
711d5779 310 unsigned int reset_fn:1;
28760489 311 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 312 unsigned int __aer_firmware_first_valid:1;
313 unsigned int __aer_firmware_first:1;
fbebb9fd 314 unsigned int broken_intx_masking:1;
2b28ae19 315 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
ba698ad4 316 pci_dev_flags_t dev_flags;
bae94d02 317 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 318
1da177e4 319 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 320 struct hlist_head saved_cap_space;
1da177e4
LT		 321 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
322 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
323 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 324 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 325#ifdef CONFIG_PCI_MSI
4aa9bc95 326 struct list_head msi_list;
da8d1c8b 327 struct kset *msi_kset;
ded86d8d 328#endif
94e61088 329 struct pci_vpd *vpd;
466b3ddf 330#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 331 union {
332 struct pci_sriov *sriov; /* SR-IOV capability related */
333 struct pci_dev *physfn; /* the PF this VF is associated with */
334 };
302b4215 335 struct pci_ats *ats; /* Address Translation Service */
d1b054da 336#endif
dbd3fc33 337 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 338 size_t romlen; /* Length of ROM if it's not from the BAR */
1da177e4
LT		 339};
340
dda56549
Y		 341static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
342{
343#ifdef CONFIG_PCI_IOV
344 if (dev->is_virtfn)
345 dev = dev->physfn;
346#endif
347
348 return dev;
349}
350
65891215
ME		 351extern struct pci_dev *alloc_pci_dev(void);
352
1da177e4
LT		 353#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
354#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
355
a7369f1f
LV		 356static inline int pci_channel_offline(struct pci_dev *pdev)
357{
358 return (pdev->error_state != pci_channel_io_normal);
359}
360
67cdc827
YL		 361extern struct resource busn_resource;
362
0efd5aab
BH		 363struct pci_host_bridge_window {
364 struct list_head list;
365 struct resource *res; /* host bridge aperture (CPU address) */
366 resource_size_t offset; /* bus address + offset = CPU address */
367};
41017f0c 368
5a21d70d 369struct pci_host_bridge {
7b543663 370 struct device dev;
5a21d70d 371 struct pci_bus *bus; /* root bus */
0efd5aab 372 struct list_head windows; /* pci_host_bridge_windows */
4fa2649a
YL		 373 void (*release_fn)(struct pci_host_bridge *);
374 void *release_data;
5a21d70d 375};
41017f0c 376
7b543663 377#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
4fa2649a
YL		 378void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
379 void (*release_fn)(struct pci_host_bridge *),
380 void *release_data);
7b543663 381
6c0cc950
RW		 382int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
383
2fe2abf8
BH		 384/*
385 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
386 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
387 * buses below host bridges or subtractive decode bridges) go in the list.
388 * Use pci_bus_for_each_resource() to iterate through all the resources.
389 */
390
391/*
392 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
393 * and there's no way to program the bridge with the details of the window.
394 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
395 * decode bit set, because they are explicit and can be programmed with _SRS.
396 */
397#define PCI_SUBTRACTIVE_DECODE 0x1
398
399struct pci_bus_resource {
400 struct list_head list;
401 struct resource *res;
402 unsigned int flags;
403};
4352dfd5
GKH		 404
405#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 406
407struct pci_bus {
408 struct list_head node; /* node in list of buses */
409 struct pci_bus *parent; /* parent bus this bridge is on */
410 struct list_head children; /* list of child buses */
411 struct list_head devices; /* list of devices on this bus */
412 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 413 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 414 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
415 struct list_head resources; /* address space routed to this bus */
92f02430 416 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 417
418 struct pci_ops *ops; /* configuration access functions */
419 void *sysdata; /* hook for sys-specific extension */
420 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
421
422 unsigned char number; /* bus number */
423 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 424 unsigned char max_bus_speed; /* enum pci_bus_speed */
425 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 426
427 char name[48];
428
429 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 430 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 431 struct device *bridge;
fd7d1ced 432 struct device dev;
1da177e4
LT		 433 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
434 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 435 unsigned int is_added:1;
1da177e4
LT		 436};
437
438#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 439#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 440
79af72d7
KK		 441/*
442 * Returns true if the pci bus is root (behind host-pci bridge),
443 * false otherwise
444 */
445static inline bool pci_is_root_bus(struct pci_bus *pbus)
446{
447 return !(pbus->parent);
448}
449
16cf0ebc
RW		 450#ifdef CONFIG_PCI_MSI
451static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
452{
453 return pci_dev->msi_enabled || pci_dev->msix_enabled;
454}
455#else
456static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
457#endif
458
1da177e4
LT		 459/*
460 * Error values that may be returned by PCI functions.
461 */
462#define PCIBIOS_SUCCESSFUL 0x00
463#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
464#define PCIBIOS_BAD_VENDOR_ID 0x83
465#define PCIBIOS_DEVICE_NOT_FOUND 0x86
466#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
467#define PCIBIOS_SET_FAILED 0x88
468#define PCIBIOS_BUFFER_TOO_SMALL 0x89
469
a6961651
AW		 470/*
471 * Translate above to generic errno for passing back through non-pci.
472 */
473static inline int pcibios_err_to_errno(int err)
474{
475 if (err <= PCIBIOS_SUCCESSFUL)
476 return err; /* Assume already errno */
477
478 switch (err) {
479 case PCIBIOS_FUNC_NOT_SUPPORTED:
480 return -ENOENT;
481 case PCIBIOS_BAD_VENDOR_ID:
482 return -EINVAL;
483 case PCIBIOS_DEVICE_NOT_FOUND:
484 return -ENODEV;
485 case PCIBIOS_BAD_REGISTER_NUMBER:
486 return -EFAULT;
487 case PCIBIOS_SET_FAILED:
488 return -EIO;
489 case PCIBIOS_BUFFER_TOO_SMALL:
490 return -ENOSPC;
491 }
492
493 return -ENOTTY;
494}
495
1da177e4
LT		 496/* Low-level architecture-dependent routines */
497
498struct pci_ops {
499 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
500 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
501};
502
b6ce068a
MW		 503/*
504 * ACPI needs to be able to access PCI config space before we've done a
505 * PCI bus scan and created pci_bus structures.
506 */
507extern int raw_pci_read(unsigned int domain, unsigned int bus,
508 unsigned int devfn, int reg, int len, u32 *val);
509extern int raw_pci_write(unsigned int domain, unsigned int bus,
510 unsigned int devfn, int reg, int len, u32 val);
1da177e4
LT		 511
512struct pci_bus_region {
c40a22e0
BH		 513 resource_size_t start;
514 resource_size_t end;
1da177e4
LT		 515};
516
517struct pci_dynids {
518 spinlock_t lock; /* protects list, index */
519 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 520};
521
392a1ce7 522/* ---------------------------------------------------------------- */
523/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 524 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7 525 * will be notified of PCI bus errors, and will be driven to recovery
526 * when an error occurs.
527 */
528
529typedef unsigned int __bitwise pci_ers_result_t;
530
531enum pci_ers_result {
532 /* no result/none/not supported in device driver */
533 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
534
535 /* Device driver can recover without slot reset */
536 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
537
538 /* Device driver wants slot to be reset. */
539 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
540
541 /* Device has completely failed, is unrecoverable */
542 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
543
544 /* Device driver is fully recovered and operational */
545 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 546
547 /* No AER capabilities registered for the driver */
548 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 549};
550
551/* PCI bus error event callbacks */
05cca6e5 552struct pci_error_handlers {
392a1ce7 553 /* PCI bus error detected on this device */
554 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 555 enum pci_channel_state error);
392a1ce7 556
557 /* MMIO has been re-enabled, but not DMA */
558 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
559
560 /* PCI Express link has been reset */
561 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
562
563 /* PCI slot has been reset */
564 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
565
566 /* Device driver may resume normal operations */
567 void (*resume)(struct pci_dev *dev);
568};
569
570/* ---------------------------------------------------------------- */
571
1da177e4
LT		 572struct module;
573struct pci_driver {
574 struct list_head node;
42b21932 575 const char *name;
1da177e4
LT		 576 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
577 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
578 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
579 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 580 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
581 int (*resume_early) (struct pci_dev *dev);
1da177e4 582 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 583 void (*shutdown) (struct pci_dev *dev);
1789382a 584 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 585 const struct pci_error_handlers *err_handler;
1da177e4
LT		 586 struct device_driver driver;
587 struct pci_dynids dynids;
588};
589
05cca6e5 590#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 591
90a1ba0c 592/**
9f9351bb 593 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 594 * @_table: device table name
595 *
596 * This macro is used to create a struct pci_device_id array (a device table)
597 * in a generic manner.
598 */
9f9351bb 599#define DEFINE_PCI_DEVICE_TABLE(_table) \
15856ad5 600 const struct pci_device_id _table[]
90a1ba0c 601
1da177e4
LT		 602/**
603 * PCI_DEVICE - macro used to describe a specific pci device
604 * @vend: the 16 bit PCI Vendor ID
605 * @dev: the 16 bit PCI Device ID
606 *
607 * This macro is used to create a struct pci_device_id that matches a
608 * specific device. The subvendor and subdevice fields will be set to
609 * PCI_ANY_ID.
610 */
611#define PCI_DEVICE(vend,dev) \
612 .vendor = (vend), .device = (dev), \
613 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
614
3d567e0e
NNS		 615/**
616 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
617 * @vend: the 16 bit PCI Vendor ID
618 * @dev: the 16 bit PCI Device ID
619 * @subvend: the 16 bit PCI Subvendor ID
620 * @subdev: the 16 bit PCI Subdevice ID
621 *
622 * This macro is used to create a struct pci_device_id that matches a
623 * specific device with subsystem information.
624 */
625#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
626 .vendor = (vend), .device = (dev), \
627 .subvendor = (subvend), .subdevice = (subdev)
628
1da177e4
LT		 629/**
630 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
631 * @dev_class: the class, subclass, prog-if triple for this device
632 * @dev_class_mask: the class mask for this device
633 *
634 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 635 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 636 * fields will be set to PCI_ANY_ID.
637 */
638#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
639 .class = (dev_class), .class_mask = (dev_class_mask), \
640 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
641 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
642
1597cacb
AC		 643/**
644 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 645 * @vendor: the vendor name
646 * @device: the 16 bit PCI Device ID
1597cacb
AC		 647 *
648 * This macro is used to create a struct pci_device_id that matches a
649 * specific PCI device. The subvendor, and subdevice fields will be set
650 * to PCI_ANY_ID. The macro allows the next field to follow as the device
651 * private data.
652 */
653
654#define PCI_VDEVICE(vendor, device) \
655 PCI_VENDOR_ID_##vendor, (device), \
656 PCI_ANY_ID, PCI_ANY_ID, 0, 0
657
1da177e4
LT		 658/* these external functions are only available when PCI support is enabled */
659#ifdef CONFIG_PCI
660
b03e7495
JM		 661extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
662
663enum pcie_bus_config_types {
5f39e670 664 PCIE_BUS_TUNE_OFF,
b03e7495 665 PCIE_BUS_SAFE,
5f39e670 666 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 667 PCIE_BUS_PEER2PEER,
668};
669
670extern enum pcie_bus_config_types pcie_bus_config;
671
1da177e4
LT		 672extern struct bus_type pci_bus_type;
673
674/* Do NOT directly access these two variables, unless you are arch specific pci
675 * code, or pci core code. */
676extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb
ZY		 677/* Some device drivers need know if pci is initiated */
678extern int no_pci_devices(void);
1da177e4 679
3c449ed0 680void pcibios_resource_survey_bus(struct pci_bus *bus);
1da177e4 681void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 682int __must_check pcibios_enable_device(struct pci_dev *, int mask);
2b6f2c35 683/* Architecture specific versions may override this (weak) */
05cca6e5 684char *pcibios_setup(char *str);
1da177e4
LT		 685
686/* Used only when drivers/pci/setup.c is used */
3b7a17fc 687resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 688 resource_size_t,
e31dd6e4 689 resource_size_t);
1da177e4
LT		 690void pcibios_update_irq(struct pci_dev *, int irq);
691
2d1c8618
BH		 692/* Weak but can be overriden by arch */
693void pci_fixup_cardbus(struct pci_bus *);
694
1da177e4
LT		 695/* Generic PCI functions used internally */
696
36a66cd6
BH		 697void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
698 struct resource *res);
699void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
700 struct pci_bus_region *region);
d1fd4fb6 701void pcibios_scan_specific_bus(int busn);
1da177e4 702extern struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 703void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 704struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
705 struct pci_ops *ops, void *sysdata);
de4b2f76 706struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 707struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
708 struct pci_ops *ops, void *sysdata,
709 struct list_head *resources);
98a35831
YL		 710int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
711int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
712void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 713struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 714 struct pci_ops *ops, void *sysdata,
715 struct list_head *resources);
05cca6e5
GKH		 716struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
717 int busnr);
3749c51a 718void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 719struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 720 const char *name,
721 struct hotplug_slot *hotplug);
f46753c5 722void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 723void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 724int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 725struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 726void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 727unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 728int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 729void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 730struct resource *pci_find_parent_resource(const struct pci_dev *dev,
731 struct resource *res);
3df425f3 732u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 733int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 734u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1da177e4
LT		 735extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
736extern void pci_dev_put(struct pci_dev *dev);
737extern void pci_remove_bus(struct pci_bus *b);
210647af 738extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
cdfcc572
YL		 739void pci_stop_root_bus(struct pci_bus *bus);
740void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 741void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 742extern void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 743#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
744#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
745#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 746
747/* Generic PCI functions exported to card drivers */
748
388c8c16
JB		 749enum pci_lost_interrupt_reason {
750 PCI_LOST_IRQ_NO_INFORMATION = 0,
751 PCI_LOST_IRQ_DISABLE_MSI,
752 PCI_LOST_IRQ_DISABLE_MSIX,
753 PCI_LOST_IRQ_DISABLE_ACPI,
754};
755enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 756int pci_find_capability(struct pci_dev *dev, int cap);
757int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
758int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 759int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 760int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
761int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 762struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 763
d42552c3
AM		 764struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
765 struct pci_dev *from);
05cca6e5 766struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 767 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 768 struct pci_dev *from);
05cca6e5 769struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 770struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
771 unsigned int devfn);
772static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
773 unsigned int devfn)
774{
775 return pci_get_domain_bus_and_slot(0, bus, devfn);
776}
05cca6e5 777struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 778int pci_dev_present(const struct pci_device_id *ids);
779
05cca6e5
GKH		 780int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
781 int where, u8 *val);
782int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
783 int where, u16 *val);
784int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
785 int where, u32 *val);
786int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
787 int where, u8 val);
788int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
789 int where, u16 val);
790int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
791 int where, u32 val);
a72b46c3 792struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 793
bf362f75 794static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 795{
05cca6e5 796 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 797}
bf362f75 798static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 799{
05cca6e5 800 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 801}
bf362f75 802static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 803 u32 *val)
1da177e4 804{
05cca6e5 805 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 806}
bf362f75 807static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 808{
05cca6e5 809 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 810}
bf362f75 811static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 812{
05cca6e5 813 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 814}
bf362f75 815static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 816 u32 val)
1da177e4 817{
05cca6e5 818 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 819}
820
8c0d3a02
JL		 821int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
822int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
823int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
824int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
825int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
826 u16 clear, u16 set);
827int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
828 u32 clear, u32 set);
829
830static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
831 u16 set)
832{
833 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
834}
835
836static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
837 u32 set)
838{
839 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
840}
841
842static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
843 u16 clear)
844{
845 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
846}
847
848static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
849 u32 clear)
850{
851 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
852}
853
c63587d7
AW		 854/* user-space driven config access */
855int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
856int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
857int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
858int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
859int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
860int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
861
4a7fb636 862int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 863int __must_check pci_enable_device_io(struct pci_dev *dev);
864int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 865int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 866int __must_check pcim_enable_device(struct pci_dev *pdev);
867void pcim_pin_device(struct pci_dev *pdev);
868
296ccb08
YS		 869static inline int pci_is_enabled(struct pci_dev *pdev)
870{
871 return (atomic_read(&pdev->enable_cnt) > 0);
872}
873
9ac7849e
TH		 874static inline int pci_is_managed(struct pci_dev *pdev)
875{
876 return pdev->is_managed;
877}
878
1da177e4 879void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 880
881extern unsigned int pcibios_max_latency;
1da177e4 882void pci_set_master(struct pci_dev *dev);
6a479079 883void pci_clear_master(struct pci_dev *dev);
96c55900 884
f7bdd12d 885int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 886int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 887#define HAVE_PCI_SET_MWI
4a7fb636 888int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 889int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 890void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 891void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 892bool pci_intx_mask_supported(struct pci_dev *dev);
893bool pci_check_and_mask_intx(struct pci_dev *dev);
894bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 895void pci_msi_off(struct pci_dev *dev);
4d57cdfa 896int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 897int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 898int pcix_get_max_mmrbc(struct pci_dev *dev);
899int pcix_get_mmrbc(struct pci_dev *dev);
900int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 901int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 902int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 903int pcie_get_mps(struct pci_dev *dev);
904int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 905int __pci_reset_function(struct pci_dev *dev);
a96d627a 906int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 907int pci_reset_function(struct pci_dev *dev);
14add80b 908void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 909int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 910int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 911int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 912
913/* ROM control related routines */
e416de5e
AC		 914int pci_enable_rom(struct pci_dev *pdev);
915void pci_disable_rom(struct pci_dev *pdev);
144a50ea 916void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 917void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 918size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 919void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 920
921/* Power management related routines */
922int pci_save_state(struct pci_dev *dev);
1d3c16a8 923void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 924struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
925int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
926int pci_load_and_free_saved_state(struct pci_dev *dev,
927 struct pci_saved_state **state);
0e5dd46b 928int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 929int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
930pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 931bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 932void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 933int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
934 bool runtime, bool enable);
0235c4fc 935int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 936pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 937int pci_prepare_to_sleep(struct pci_dev *dev);
938int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 939bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 940bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 941void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 942
6cbf8214
RW		 943static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
944 bool enable)
945{
946 return __pci_enable_wake(dev, state, false, enable);
947}
1da177e4 948
b48d4425
JB		 949#define PCI_EXP_IDO_REQUEST (1<<0)
950#define PCI_EXP_IDO_COMPLETION (1<<1)
951void pci_enable_ido(struct pci_dev *dev, unsigned long type);
952void pci_disable_ido(struct pci_dev *dev, unsigned long type);
953
48a92a81 954enum pci_obff_signal_type {
688398bb
MS		 955 PCI_EXP_OBFF_SIGNAL_L0 = 0,
956 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 957};
958int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
959void pci_disable_obff(struct pci_dev *dev);
960
51c2e0a7
JB		 961int pci_enable_ltr(struct pci_dev *dev);
962void pci_disable_ltr(struct pci_dev *dev);
963int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
964
bb209c82
BH		 965/* For use by arch with custom probe code */
966void set_pcie_port_type(struct pci_dev *pdev);
967void set_pcie_hotplug_bridge(struct pci_dev *pdev);
968
ce5ccdef 969/* Functions for PCI Hotplug drivers to use */
05cca6e5 970int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 971unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 972unsigned int pci_rescan_bus(struct pci_bus *bus);
ce5ccdef 973
287d19ce
SH		 974/* Vital product data routines */
975ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
976ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 977int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 978
1da177e4 979/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 980resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 981void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 982void pci_bus_size_bridges(struct pci_bus *bus);
983int pci_claim_resource(struct pci_dev *, int);
984void pci_assign_unassigned_resources(void);
6841ec68 985void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 986void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1da177e4 987void pdev_enable_device(struct pci_dev *);
842de40d 988int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 989void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 990 int (*)(const struct pci_dev *, u8, u8));
1da177e4 991#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 992int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 993int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 994void pci_release_regions(struct pci_dev *);
4a7fb636 995int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 996int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 997void pci_release_region(struct pci_dev *, int);
c87deff7 998int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 999int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1000void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1001
1002/* drivers/pci/bus.c */
45ca9e97 1003void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1004void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1005 resource_size_t offset);
45ca9e97 1006void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 1007void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1008struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1009void pci_bus_remove_resources(struct pci_bus *bus);
1010
89a74ecc 1011#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1012 for (i = 0; \
1013 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1014 i++)
89a74ecc 1015
4a7fb636
AM		 1016int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1017 struct resource *res, resource_size_t size,
1018 resource_size_t align, resource_size_t min,
1019 unsigned int type_mask,
3b7a17fc
DB		 1020 resource_size_t (*alignf)(void *,
1021 const struct resource *,
b26b2d49
DB		 1022 resource_size_t,
1023 resource_size_t),
4a7fb636 1024 void *alignf_data);
1da177e4
LT		 1025void pci_enable_bridges(struct pci_bus *bus);
1026
863b18f4 1027/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1028int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1029 const char *mod_name);
bba81165
AM		 1030
1031/*
1032 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1033 */
1034#define pci_register_driver(driver) \
1035 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1036
05cca6e5 1037void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1038
1039/**
1040 * module_pci_driver() - Helper macro for registering a PCI driver
1041 * @__pci_driver: pci_driver struct
1042 *
1043 * Helper macro for PCI drivers which do not do anything special in module
1044 * init/exit. This eliminates a lot of boilerplate. Each module may only
1045 * use this macro once, and calling it replaces module_init() and module_exit()
1046 */
1047#define module_pci_driver(__pci_driver) \
1048 module_driver(__pci_driver, pci_register_driver, \
1049 pci_unregister_driver)
1050
05cca6e5 1051struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1052int pci_add_dynid(struct pci_driver *drv,
1053 unsigned int vendor, unsigned int device,
1054 unsigned int subvendor, unsigned int subdevice,
1055 unsigned int class, unsigned int class_mask,
1056 unsigned long driver_data);
05cca6e5
GKH		 1057const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1058 struct pci_dev *dev);
1059int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1060 int pass);
1da177e4 1061
70298c6e 1062void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1063 void *userdata);
70b9f7dc 1064int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 1065int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1066unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1067void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1068resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1069 unsigned long type);
cecf4864 1070
3448a19d
DA		 1071#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1072#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1073
deb2d2ec 1074int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1075 unsigned int command_bits, u32 flags);
1da177e4
LT		 1076/* kmem_cache style wrapper around pci_alloc_consistent() */
1077
f41b1771 1078#include <linux/pci-dma.h>
1da177e4
LT		 1079#include <linux/dmapool.h>
1080
1081#define pci_pool dma_pool
1082#define pci_pool_create(name, pdev, size, align, allocation) \
1083 dma_pool_create(name, &pdev->dev, size, align, allocation)
1084#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1085#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1086#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1087
e24c2d96
DM		 1088enum pci_dma_burst_strategy {
1089 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1090 strategy_parameter is N/A */
1091 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1092 byte boundaries */
1093 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1094 strategy_parameter byte boundaries */
1095};
1096
1da177e4 1097struct msix_entry {
16dbef4a 1098 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1099 u16 entry; /* driver uses to specify entry, OS writes */
1100};
1101
0366f8f7 1102
1da177e4 1103#ifndef CONFIG_PCI_MSI
1c8d7b0a 1104static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1105{
1106 return -1;
1107}
1108
08261d87
AG		 1109static inline int
1110pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1111{
1112 return -1;
1113}
1114
d52877c7
YL		 1115static inline void pci_msi_shutdown(struct pci_dev *dev)
1116{ }
05cca6e5
GKH		 1117static inline void pci_disable_msi(struct pci_dev *dev)
1118{ }
1119
a52e2e35
RW		 1120static inline int pci_msix_table_size(struct pci_dev *dev)
1121{
1122 return 0;
1123}
05cca6e5
GKH		 1124static inline int pci_enable_msix(struct pci_dev *dev,
1125 struct msix_entry *entries, int nvec)
1126{
1127 return -1;
1128}
1129
d52877c7
YL		 1130static inline void pci_msix_shutdown(struct pci_dev *dev)
1131{ }
05cca6e5
GKH		 1132static inline void pci_disable_msix(struct pci_dev *dev)
1133{ }
1134
1135static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1136{ }
1137
1138static inline void pci_restore_msi_state(struct pci_dev *dev)
1139{ }
07ae95f9
AP		 1140static inline int pci_msi_enabled(void)
1141{
1142 return 0;
1143}
1da177e4 1144#else
1c8d7b0a 1145extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
08261d87 1146extern int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
d52877c7 1147extern void pci_msi_shutdown(struct pci_dev *dev);
1da177e4 1148extern void pci_disable_msi(struct pci_dev *dev);
a52e2e35 1149extern int pci_msix_table_size(struct pci_dev *dev);
05cca6e5 1150extern int pci_enable_msix(struct pci_dev *dev,
1da177e4 1151 struct msix_entry *entries, int nvec);
d52877c7 1152extern void pci_msix_shutdown(struct pci_dev *dev);
1da177e4
LT		 1153extern void pci_disable_msix(struct pci_dev *dev);
1154extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
94688cf2 1155extern void pci_restore_msi_state(struct pci_dev *dev);
07ae95f9 1156extern int pci_msi_enabled(void);
1da177e4
LT		 1157#endif
1158
ab0724ff 1159#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1160extern bool pcie_ports_disabled;
1161extern bool pcie_ports_auto;
ab0724ff
MT		 1162#else
1163#define pcie_ports_disabled true
1164#define pcie_ports_auto false
1165#endif
415e12b2 1166
3e1b1600 1167#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1168static inline int pcie_aspm_enabled(void) { return 0; }
1169static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1170#else
1171extern int pcie_aspm_enabled(void);
8b8bae90 1172extern bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1173#endif
1174
415e12b2
RW		 1175#ifdef CONFIG_PCIEAER
1176void pci_no_aer(void);
1177bool pci_aer_available(void);
1178#else
1179static inline void pci_no_aer(void) { }
1180static inline bool pci_aer_available(void) { return false; }
1181#endif
1182
43c16408
AP		 1183#ifndef CONFIG_PCIE_ECRC
1184static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1185{
1186 return;
1187}
1188static inline void pcie_ecrc_get_policy(char *str) {};
1189#else
1190extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1191extern void pcie_ecrc_get_policy(char *str);
1192#endif
1193
1c8d7b0a
MW		 1194#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1195
8b955b0d 1196#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1197/* The functions a driver should call */
1198int ht_create_irq(struct pci_dev *dev, int idx);
1199void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1200#endif /* CONFIG_HT_IRQ */
1201
fb51ccbf
JK		 1202extern void pci_cfg_access_lock(struct pci_dev *dev);
1203extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1204extern void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1205
4352dfd5
GKH		 1206/*
1207 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1208 * a PCI domain is defined to be a set of PCI busses which share
1209 * configuration space.
1210 */
32a2eea7
JG		 1211#ifdef CONFIG_PCI_DOMAINS
1212extern int pci_domains_supported;
1213#else
1214enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1215static inline int pci_domain_nr(struct pci_bus *bus)
1216{
1217 return 0;
1218}
1219
4352dfd5
GKH		 1220static inline int pci_proc_domain(struct pci_bus *bus)
1221{
1222 return 0;
1223}
32a2eea7 1224#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1225
95a8b6ef
MT		 1226/* some architectures require additional setup to direct VGA traffic */
1227typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1228 unsigned int command_bits, u32 flags);
95a8b6ef
MT		 1229extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1230
4352dfd5 1231#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1232
1233/*
1234 * If the system does not have PCI, clearly these return errors. Define
1235 * these as simple inline functions to avoid hair in drivers.
1236 */
1237
05cca6e5
GKH		 1238#define _PCI_NOP(o, s, t) \
1239 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1240 int where, t val) \
1da177e4 1241 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1242
1243#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1244 _PCI_NOP(o, word, u16 x) \
1245 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1246_PCI_NOP_ALL(read, *)
1247_PCI_NOP_ALL(write,)
1248
d42552c3 1249static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1250 unsigned int device,
1251 struct pci_dev *from)
1252{
1253 return NULL;
1254}
d42552c3 1255
05cca6e5
GKH		 1256static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1257 unsigned int device,
1258 unsigned int ss_vendor,
1259 unsigned int ss_device,
b08508c4 1260 struct pci_dev *from)
05cca6e5
GKH		 1261{
1262 return NULL;
1263}
1da177e4 1264
05cca6e5
GKH		 1265static inline struct pci_dev *pci_get_class(unsigned int class,
1266 struct pci_dev *from)
1267{
1268 return NULL;
1269}
1da177e4
LT		 1270
1271#define pci_dev_present(ids) (0)
ed4aaadb 1272#define no_pci_devices() (1)
1da177e4
LT		 1273#define pci_dev_put(dev) do { } while (0)
1274
05cca6e5
GKH		 1275static inline void pci_set_master(struct pci_dev *dev)
1276{ }
1277
1278static inline int pci_enable_device(struct pci_dev *dev)
1279{
1280 return -EIO;
1281}
1282
1283static inline void pci_disable_device(struct pci_dev *dev)
1284{ }
1285
1286static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1287{
1288 return -EIO;
1289}
1290
80be0385
RD		 1291static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1292{
1293 return -EIO;
1294}
1295
4d57cdfa
FT		 1296static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1297 unsigned int size)
1298{
1299 return -EIO;
1300}
1301
59fc67de
FT		 1302static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1303 unsigned long mask)
1304{
1305 return -EIO;
1306}
1307
05cca6e5
GKH		 1308static inline int pci_assign_resource(struct pci_dev *dev, int i)
1309{
1310 return -EBUSY;
1311}
1312
1313static inline int __pci_register_driver(struct pci_driver *drv,
1314 struct module *owner)
1315{
1316 return 0;
1317}
1318
1319static inline int pci_register_driver(struct pci_driver *drv)
1320{
1321 return 0;
1322}
1323
1324static inline void pci_unregister_driver(struct pci_driver *drv)
1325{ }
1326
1327static inline int pci_find_capability(struct pci_dev *dev, int cap)
1328{
1329 return 0;
1330}
1331
1332static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1333 int cap)
1334{
1335 return 0;
1336}
1337
1338static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1339{
1340 return 0;
1341}
1342
1da177e4 1343/* Power management related routines */
05cca6e5
GKH		 1344static inline int pci_save_state(struct pci_dev *dev)
1345{
1346 return 0;
1347}
1348
1d3c16a8
JM		 1349static inline void pci_restore_state(struct pci_dev *dev)
1350{ }
1da177e4 1351
05cca6e5
GKH		 1352static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1353{
1354 return 0;
1355}
1356
3449248c
RD		 1357static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1358{
1359 return 0;
1360}
1361
05cca6e5
GKH		 1362static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1363 pm_message_t state)
1364{
1365 return PCI_D0;
1366}
1367
1368static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1369 int enable)
1370{
1371 return 0;
1372}
1373
b48d4425
JB		 1374static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1375{
1376}
1377
1378static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1379{
1380}
1381
48a92a81
JB		 1382static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1383{
1384 return 0;
1385}
1386
1387static inline void pci_disable_obff(struct pci_dev *dev)
1388{
1389}
1390
05cca6e5
GKH		 1391static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1392{
1393 return -EIO;
1394}
1395
1396static inline void pci_release_regions(struct pci_dev *dev)
1397{ }
0da0ead9 1398
a46e8126
KG		 1399#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1400
fb51ccbf 1401static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1402{ }
1403
fb51ccbf
JK		 1404static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1405{ return 0; }
1406
1407static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1408{ }
e04b0ea2 1409
d80d0217
RD		 1410static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1411{ return NULL; }
1412
1413static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1414 unsigned int devfn)
1415{ return NULL; }
1416
1417static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1418 unsigned int devfn)
1419{ return NULL; }
1420
92298e66
DA		 1421static inline int pci_domain_nr(struct pci_bus *bus)
1422{ return 0; }
1423
12ea6cad
AW		 1424static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1425{ return NULL; }
1426
fb8a0d9d
WM		 1427#define dev_is_pci(d) (false)
1428#define dev_is_pf(d) (false)
1429#define dev_num_vf(d) (0)
4352dfd5 1430#endif /* CONFIG_PCI */
1da177e4 1431
4352dfd5
GKH		 1432/* Include architecture-dependent settings and functions */
1433
1434#include <asm/pci.h>
1da177e4 1435
1f82de10
YL		 1436#ifndef PCIBIOS_MAX_MEM_32
1437#define PCIBIOS_MAX_MEM_32 (-1)
1438#endif
1439
1da177e4
LT		 1440/* these helpers provide future and backwards compatibility
1441 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1442#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1443#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1444#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1445#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1446 ((pci_resource_start((dev), (bar)) == 0 && \
1447 pci_resource_end((dev), (bar)) == \
1448 pci_resource_start((dev), (bar))) ? 0 : \
1449 \
1450 (pci_resource_end((dev), (bar)) - \
1451 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1452
1453/* Similar to the helpers above, these manipulate per-pci_dev
1454 * driver-specific data. They are really just a wrapper around
1455 * the generic device structure functions of these calls.
1456 */
05cca6e5 1457static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1458{
1459 return dev_get_drvdata(&pdev->dev);
1460}
1461
05cca6e5 1462static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1463{
1464 dev_set_drvdata(&pdev->dev, data);
1465}
1466
1467/* If you want to know what to call your pci_dev, ask this function.
1468 * Again, it's a wrapper around the generic device.
1469 */
2fc90f61 1470static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1471{
c6c4f070 1472 return dev_name(&pdev->dev);
1da177e4
LT		 1473}
1474
2311b1f2
ME		 1475
1476/* Some archs don't want to expose struct resource to userland as-is
1477 * in sysfs and /proc
1478 */
1479#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1480static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1481 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1482 resource_size_t *end)
2311b1f2
ME		 1483{
1484 *start = rsrc->start;
1485 *end = rsrc->end;
1486}
1487#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1488
1489
1da177e4
LT		 1490/*
1491 * The world is not perfect and supplies us with broken PCI devices.
1492 * For at least a part of these bugs we need a work-around, so both
1493 * generic (drivers/pci/quirks.c) and per-architecture code can define
1494 * fixup hooks to be called for particular buggy devices.
1495 */
1496
1497struct pci_fixup {
f4ca5c6a
YL		 1498 u16 vendor; /* You can use PCI_ANY_ID here of course */
1499 u16 device; /* You can use PCI_ANY_ID here of course */
1500 u32 class; /* You can use PCI_ANY_ID here too */
1501 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1502 void (*hook)(struct pci_dev *dev);
1503};
1504
1505enum pci_fixup_pass {
1506 pci_fixup_early, /* Before probing BARs */
1507 pci_fixup_header, /* After reading configuration header */
1508 pci_fixup_final, /* Final phase of device fixups */
1509 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1510 pci_fixup_resume, /* pci_device_resume() */
1511 pci_fixup_suspend, /* pci_device_suspend */
1512 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1513};
1514
1515/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1516#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1517 class_shift, hook) \
769ae543 1518 static const struct pci_fixup __pci_fixup_##name __used \
f4ca5c6a
YL		 1519 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1520 = { vendor, device, class, class_shift, hook };
1521
1522#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1523 class_shift, hook) \
1524 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1525 vendor##device##hook, vendor, device, class, class_shift, hook)
1526#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1527 class_shift, hook) \
1528 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1529 vendor##device##hook, vendor, device, class, class_shift, hook)
1530#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1531 class_shift, hook) \
1532 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1533 vendor##device##hook, vendor, device, class, class_shift, hook)
1534#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1535 class_shift, hook) \
1536 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1537 vendor##device##hook, vendor, device, class, class_shift, hook)
1538#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1539 class_shift, hook) \
1540 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1541 resume##vendor##device##hook, vendor, device, class, \
1542 class_shift, hook)
1543#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1544 class_shift, hook) \
1545 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1546 resume_early##vendor##device##hook, vendor, device, \
1547 class, class_shift, hook)
1548#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1549 class_shift, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1551 suspend##vendor##device##hook, vendor, device, class, \
1552 class_shift, hook)
1553
1da177e4
LT		 1554#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1555 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1556 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1557#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1558 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1559 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1560#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1561 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1562 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1563#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1565 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1566#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1568 resume##vendor##device##hook, vendor, device, \
1569 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1570#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1571 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1572 resume_early##vendor##device##hook, vendor, device, \
1573 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1574#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1576 suspend##vendor##device##hook, vendor, device, \
1577 PCI_ANY_ID, 0, hook)
1da177e4 1578
93177a74 1579#ifdef CONFIG_PCI_QUIRKS
1da177e4 1580void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
12ea6cad 1581struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
ad805758 1582int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
93177a74
RW		 1583#else
1584static inline void pci_fixup_device(enum pci_fixup_pass pass,
1585 struct pci_dev *dev) {}
12ea6cad
AW		 1586static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1587{
1588 return pci_dev_get(dev);
1589}
ad805758
AW		 1590static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1591 u16 acs_flags)
1592{
1593 return -ENOTTY;
1594}
93177a74 1595#endif
1da177e4 1596
05cca6e5 1597void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1598void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1599void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1600int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1601int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1602 const char *name);
fb7ebfe4 1603void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1604
1da177e4 1605extern int pci_pci_problems;
236561e5 1606#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1607#define PCIPCI_TRITON 2
1608#define PCIPCI_NATOMA 4
1609#define PCIPCI_VIAETBF 8
1610#define PCIPCI_VSFX 16
236561e5
AC		 1611#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1612#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1613
4516a618
AN		 1614extern unsigned long pci_cardbus_io_size;
1615extern unsigned long pci_cardbus_mem_size;
15856ad5 1616extern u8 pci_dfl_cache_line_size;
ac1aa47b 1617extern u8 pci_cache_line_size;
4516a618 1618
28760489
EB		 1619extern unsigned long pci_hotplug_io_size;
1620extern unsigned long pci_hotplug_mem_size;
1621
cfce9fb8 1622/* Architecture specific versions may override these (weak) */
19792a08
AB		 1623int pcibios_add_platform_entries(struct pci_dev *dev);
1624void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1625void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1626int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1627 enum pcie_reset_state state);
eca0d467 1628int pcibios_add_device(struct pci_dev *dev);
575e3348 1629
7752d5cf 1630#ifdef CONFIG_PCI_MMCONFIG
bb63b421 1631extern void __init pci_mmcfg_early_init(void);
7752d5cf
RH		 1632extern void __init pci_mmcfg_late_init(void);
1633#else
bb63b421 1634static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1635static inline void pci_mmcfg_late_init(void) { }
1636#endif
1637
642c92da 1638int pci_ext_cfg_avail(void);
0ef5f8f6 1639
1684f5dd 1640void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1641
dd7cc44d
YZ		 1642#ifdef CONFIG_PCI_IOV
1643extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1644extern void pci_disable_sriov(struct pci_dev *dev);
74bb1bcc 1645extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
fb8a0d9d 1646extern int pci_num_vf(struct pci_dev *dev);
bff73156
DD		 1647extern int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1648extern int pci_sriov_get_totalvfs(struct pci_dev *dev);
dd7cc44d
YZ		 1649#else
1650static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1651{
1652 return -ENODEV;
1653}
1654static inline void pci_disable_sriov(struct pci_dev *dev)
1655{
1656}
74bb1bcc
YZ		 1657static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1658{
1659 return IRQ_NONE;
1660}
fb8a0d9d
WM		 1661static inline int pci_num_vf(struct pci_dev *dev)
1662{
1663 return 0;
1664}
bff73156
DD		 1665static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1666{
1667 return 0;
1668}
1669static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1670{
1671 return 0;
1672}
dd7cc44d
YZ		 1673#endif
1674
c825bc94
KK		 1675#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1676extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1677extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1678#endif
1679
d7b7e605
KK		 1680/**
1681 * pci_pcie_cap - get the saved PCIe capability offset
1682 * @dev: PCI device
1683 *
1684 * PCIe capability offset is calculated at PCI device initialization
1685 * time and saved in the data structure. This function returns saved
1686 * PCIe capability offset. Using this instead of pci_find_capability()
1687 * reduces unnecessary search in the PCI configuration space. If you
1688 * need to calculate PCIe capability offset from raw device for some
1689 * reasons, please use pci_find_capability() instead.
1690 */
1691static inline int pci_pcie_cap(struct pci_dev *dev)
1692{
1693 return dev->pcie_cap;
1694}
1695
7eb776c4
KK		 1696/**
1697 * pci_is_pcie - check if the PCI device is PCI Express capable
1698 * @dev: PCI device
1699 *
1700 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1701 */
1702static inline bool pci_is_pcie(struct pci_dev *dev)
1703{
1704 return !!pci_pcie_cap(dev);
1705}
1706
7c9c003c
MS		 1707/**
1708 * pcie_caps_reg - get the PCIe Capabilities Register
1709 * @dev: PCI device
1710 */
1711static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1712{
1713 return dev->pcie_flags_reg;
1714}
1715
786e2288
YW		 1716/**
1717 * pci_pcie_type - get the PCIe device/port type
1718 * @dev: PCI device
1719 */
1720static inline int pci_pcie_type(const struct pci_dev *dev)
1721{
1c531d82 1722 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 1723}
1724
5d990b62 1725void pci_request_acs(void);
ad805758
AW		 1726bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1727bool pci_acs_path_enabled(struct pci_dev *start,
1728 struct pci_dev *end, u16 acs_flags);
a2ce7662 1729
7ad506fa
MC		 1730#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1731#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1732
1733/* Large Resource Data Type Tag Item Names */
1734#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1735#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1736#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1737
1738#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1739#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1740#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1741
1742/* Small Resource Data Type Tag Item Names */
1743#define PCI_VPD_STIN_END 0x78 /* End */
1744
1745#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1746
1747#define PCI_VPD_SRDT_TIN_MASK 0x78
1748#define PCI_VPD_SRDT_LEN_MASK 0x07
1749
1750#define PCI_VPD_LRDT_TAG_SIZE 3
1751#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1752
e1d5bdab
MC		 1753#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1754
4067a854
MC		 1755#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1756#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1757#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1758#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1759
a2ce7662
MC		 1760/**
1761 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1762 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1763 *
1764 * Returns the extracted Large Resource Data Type length.
1765 */
1766static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1767{
1768 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1769}
1770
7ad506fa
MC		 1771/**
1772 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1773 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1774 *
1775 * Returns the extracted Small Resource Data Type length.
1776 */
1777static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1778{
1779 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1780}
1781
e1d5bdab
MC		 1782/**
1783 * pci_vpd_info_field_size - Extracts the information field length
1784 * @lrdt: Pointer to the beginning of an information field header
1785 *
1786 * Returns the extracted information field length.
1787 */
1788static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1789{
1790 return info_field[2];
1791}
1792
b55ac1b2
MC		 1793/**
1794 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1795 * @buf: Pointer to buffered vpd data
1796 * @off: The offset into the buffer at which to begin the search
1797 * @len: The length of the vpd buffer
1798 * @rdt: The Resource Data Type to search for
1799 *
1800 * Returns the index where the Resource Data Type was found or
1801 * -ENOENT otherwise.
1802 */
1803int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1804
4067a854
MC		 1805/**
1806 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1807 * @buf: Pointer to buffered vpd data
1808 * @off: The offset into the buffer at which to begin the search
1809 * @len: The length of the buffer area, relative to off, in which to search
1810 * @kw: The keyword to search for
1811 *
1812 * Returns the index where the information field keyword was found or
1813 * -ENOENT otherwise.
1814 */
1815int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1816 unsigned int len, const char *kw);
1817
98d9f30c
BH		 1818/* PCI <-> OF binding helpers */
1819#ifdef CONFIG_OF
1820struct device_node;
1821extern void pci_set_of_node(struct pci_dev *dev);
1822extern void pci_release_of_node(struct pci_dev *dev);
1823extern void pci_set_bus_of_node(struct pci_bus *bus);
1824extern void pci_release_bus_of_node(struct pci_bus *bus);
1825
1826/* Arch may override this (weak) */
1827extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1828
3df425f3
JC		 1829static inline struct device_node *
1830pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 1831{
1832 return pdev ? pdev->dev.of_node : NULL;
1833}
1834
ef3b4f8c
BH		 1835static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1836{
1837 return bus ? bus->dev.of_node : NULL;
1838}
1839
98d9f30c
BH		 1840#else /* CONFIG_OF */
1841static inline void pci_set_of_node(struct pci_dev *dev) { }
1842static inline void pci_release_of_node(struct pci_dev *dev) { }
1843static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1844static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1845#endif /* CONFIG_OF */
1846
eb740b5f
GS		 1847#ifdef CONFIG_EEH
1848static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1849{
1850 return pdev->dev.archdata.edev;
1851}
1852#endif
1853
166e9278
OBC		 1854/**
1855 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1856 * @pdev: the PCI device
1857 *
1858 * if the device is PCIE, return NULL
1859 * if the device isn't connected to a PCIe bridge (that is its parent is a
1860 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1861 * parent
1862 */
1863struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1864
1da177e4 1865#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)