Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
60063497 | 52 | #include <linux/atomic.h> |
1da177e4 | 53 | #include <linux/device.h> |
1388cc96 | 54 | #include <linux/io.h> |
74bb1bcc | 55 | #include <linux/irqreturn.h> |
1da177e4 | 56 | |
7e7a43c3 AB |
57 | /* Include the ID list */ |
58 | #include <linux/pci_ids.h> | |
59 | ||
f46753c5 AC |
60 | /* pci_slot represents a physical slot */ |
61 | struct pci_slot { | |
62 | struct pci_bus *bus; /* The bus this slot is on */ | |
63 | struct list_head list; /* node in list of slots on this bus */ | |
64 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
65 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
66 | struct kobject kobj; | |
67 | }; | |
68 | ||
0ad772ec AC |
69 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
70 | { | |
71 | return kobject_name(&slot->kobj); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
75 | enum pci_mmap_state { | |
76 | pci_mmap_io, | |
77 | pci_mmap_mem | |
78 | }; | |
79 | ||
80 | /* This defines the direction arg to the DMA mapping routines. */ | |
81 | #define PCI_DMA_BIDIRECTIONAL 0 | |
82 | #define PCI_DMA_TODEVICE 1 | |
83 | #define PCI_DMA_FROMDEVICE 2 | |
84 | #define PCI_DMA_NONE 3 | |
85 | ||
fde09c6d YZ |
86 | /* |
87 | * For PCI devices, the region numbers are assigned this way: | |
88 | */ | |
89 | enum { | |
90 | /* #0-5: standard PCI resources */ | |
91 | PCI_STD_RESOURCES, | |
92 | PCI_STD_RESOURCE_END = 5, | |
93 | ||
94 | /* #6: expansion ROM resource */ | |
95 | PCI_ROM_RESOURCE, | |
96 | ||
d1b054da YZ |
97 | /* device specific resources */ |
98 | #ifdef CONFIG_PCI_IOV | |
99 | PCI_IOV_RESOURCES, | |
100 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
101 | #endif | |
102 | ||
fde09c6d YZ |
103 | /* resources assigned to buses behind the bridge */ |
104 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
105 | ||
106 | PCI_BRIDGE_RESOURCES, | |
107 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
108 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
109 | ||
110 | /* total resources associated with a PCI device */ | |
111 | PCI_NUM_RESOURCES, | |
112 | ||
113 | /* preserve this for compatibility */ | |
114 | DEVICE_COUNT_RESOURCE | |
115 | }; | |
1da177e4 LT |
116 | |
117 | typedef int __bitwise pci_power_t; | |
118 | ||
4352dfd5 GKH |
119 | #define PCI_D0 ((pci_power_t __force) 0) |
120 | #define PCI_D1 ((pci_power_t __force) 1) | |
121 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
122 | #define PCI_D3hot ((pci_power_t __force) 3) |
123 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 124 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 125 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 126 | |
00240c38 AS |
127 | /* Remember to update this when the list above changes! */ |
128 | extern const char *pci_power_names[]; | |
129 | ||
130 | static inline const char *pci_power_name(pci_power_t state) | |
131 | { | |
132 | return pci_power_names[1 + (int) state]; | |
133 | } | |
134 | ||
aa8c6c93 RW |
135 | #define PCI_PM_D2_DELAY 200 |
136 | #define PCI_PM_D3_WAIT 10 | |
137 | #define PCI_PM_BUS_WAIT 50 | |
138 | ||
392a1ce7 | 139 | /** The pci_channel state describes connectivity between the CPU and |
140 | * the pci device. If some PCI bus between here and the pci device | |
141 | * has crashed or locked up, this info is reflected here. | |
142 | */ | |
143 | typedef unsigned int __bitwise pci_channel_state_t; | |
144 | ||
145 | enum pci_channel_state { | |
146 | /* I/O channel is in normal state */ | |
147 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
148 | ||
149 | /* I/O to channel is blocked */ | |
150 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
151 | ||
152 | /* PCI card is dead */ | |
153 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
154 | }; | |
155 | ||
f7bdd12d BK |
156 | typedef unsigned int __bitwise pcie_reset_state_t; |
157 | ||
158 | enum pcie_reset_state { | |
159 | /* Reset is NOT asserted (Use to deassert reset) */ | |
160 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
161 | ||
162 | /* Use #PERST to reset PCI-E device */ | |
163 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
164 | ||
165 | /* Use PCI-E Hot Reset to reset device */ | |
166 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
167 | }; | |
168 | ||
ba698ad4 DM |
169 | typedef unsigned short __bitwise pci_dev_flags_t; |
170 | enum pci_dev_flags { | |
171 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
172 | * generation too. | |
173 | */ | |
174 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
175 | /* Device configuration is irrevocably lost if disabled into D3 */ |
176 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
6777829c GR |
177 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
178 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, | |
ba698ad4 DM |
179 | }; |
180 | ||
e1d3a908 SA |
181 | enum pci_irq_reroute_variant { |
182 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
183 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
184 | }; | |
185 | ||
6e325a62 MT |
186 | typedef unsigned short __bitwise pci_bus_flags_t; |
187 | enum pci_bus_flags { | |
d556ad4b PO |
188 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
189 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
190 | }; |
191 | ||
536c8cb4 MW |
192 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
193 | enum pci_bus_speed { | |
194 | PCI_SPEED_33MHz = 0x00, | |
195 | PCI_SPEED_66MHz = 0x01, | |
196 | PCI_SPEED_66MHz_PCIX = 0x02, | |
197 | PCI_SPEED_100MHz_PCIX = 0x03, | |
198 | PCI_SPEED_133MHz_PCIX = 0x04, | |
199 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
200 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
201 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
202 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
203 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
204 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
205 | AGP_UNKNOWN = 0x0c, |
206 | AGP_1X = 0x0d, | |
207 | AGP_2X = 0x0e, | |
208 | AGP_4X = 0x0f, | |
209 | AGP_8X = 0x10, | |
536c8cb4 MW |
210 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
211 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
212 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
213 | PCIE_SPEED_2_5GT = 0x14, | |
214 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 215 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
216 | PCI_SPEED_UNKNOWN = 0xff, |
217 | }; | |
218 | ||
24a4742f | 219 | struct pci_cap_saved_data { |
41017f0c | 220 | char cap_nr; |
24a4742f | 221 | unsigned int size; |
41017f0c SL |
222 | u32 data[0]; |
223 | }; | |
224 | ||
24a4742f AW |
225 | struct pci_cap_saved_state { |
226 | struct hlist_node next; | |
227 | struct pci_cap_saved_data cap; | |
228 | }; | |
229 | ||
7d715a6c | 230 | struct pcie_link_state; |
ee69439c | 231 | struct pci_vpd; |
d1b054da | 232 | struct pci_sriov; |
302b4215 | 233 | struct pci_ats; |
ee69439c | 234 | |
1da177e4 LT |
235 | /* |
236 | * The pci_dev structure is used to describe PCI devices. | |
237 | */ | |
238 | struct pci_dev { | |
1da177e4 LT |
239 | struct list_head bus_list; /* node in per-bus list */ |
240 | struct pci_bus *bus; /* bus this device is on */ | |
241 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
242 | ||
243 | void *sysdata; /* hook for sys-specific extension */ | |
244 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 245 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
246 | |
247 | unsigned int devfn; /* encoded device & function index */ | |
248 | unsigned short vendor; | |
249 | unsigned short device; | |
250 | unsigned short subsystem_vendor; | |
251 | unsigned short subsystem_device; | |
252 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 253 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 254 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
0efea000 | 255 | u8 pcie_cap; /* PCI-E capability offset */ |
b03e7495 JM |
256 | u8 pcie_type:4; /* PCI-E device/port type */ |
257 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ | |
1da177e4 | 258 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 259 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
260 | |
261 | struct pci_driver *driver; /* which driver has allocated this device */ | |
262 | u64 dma_mask; /* Mask of the bits of bus address this | |
263 | device implements. Normally this is | |
264 | 0xffffffff. You only need to change | |
265 | this if your device has broken DMA | |
266 | or supports 64-bit transfers. */ | |
267 | ||
4d57cdfa FT |
268 | struct device_dma_parameters dma_parms; |
269 | ||
1da177e4 LT |
270 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
271 | this is D0-D3, D0 being fully functional, | |
272 | and D3 being off. */ | |
337001b6 RW |
273 | int pm_cap; /* PM capability offset in the |
274 | configuration space */ | |
275 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
276 | can be generated */ | |
c7f48656 | 277 | unsigned int pme_interrupt:1; |
379021d5 | 278 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
279 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
280 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
281 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
253d2e54 JP |
282 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
283 | decoding during bar sizing */ | |
e80bb09d | 284 | unsigned int wakeup_prepared:1; |
1ae861e6 | 285 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
1da177e4 | 286 | |
7d715a6c SL |
287 | #ifdef CONFIG_PCIEASPM |
288 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
289 | #endif | |
290 | ||
392a1ce7 | 291 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
292 | struct device dev; /* Generic device interface */ |
293 | ||
1da177e4 LT |
294 | int cfg_size; /* Size of configuration space */ |
295 | ||
296 | /* | |
297 | * Instead of touching interrupt line and base address registers | |
298 | * directly, use the values stored here. They might be different! | |
299 | */ | |
300 | unsigned int irq; | |
301 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
58c84eda | 302 | resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
1da177e4 LT |
303 | |
304 | /* These fields are used by common fixups */ | |
305 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
306 | unsigned int multifunction:1;/* Part of multi-function device */ | |
307 | /* keep track of device state */ | |
8a1bc901 | 308 | unsigned int is_added:1; |
1da177e4 | 309 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 310 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 311 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 312 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 313 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
314 | unsigned int msi_enabled:1; |
315 | unsigned int msix_enabled:1; | |
58c3a727 | 316 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 317 | unsigned int is_managed:1; |
6d3be84a KK |
318 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
319 | Use pci_is_pcie() instead */ | |
260d703a | 320 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 321 | unsigned int state_saved:1; |
d1b054da | 322 | unsigned int is_physfn:1; |
dd7cc44d | 323 | unsigned int is_virtfn:1; |
711d5779 | 324 | unsigned int reset_fn:1; |
28760489 | 325 | unsigned int is_hotplug_bridge:1; |
affb72c3 HY |
326 | unsigned int __aer_firmware_first_valid:1; |
327 | unsigned int __aer_firmware_first:1; | |
ba698ad4 | 328 | pci_dev_flags_t dev_flags; |
bae94d02 | 329 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 330 | |
1da177e4 | 331 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 332 | struct hlist_head saved_cap_space; |
1da177e4 LT |
333 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
334 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
335 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 336 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 337 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 338 | struct list_head msi_list; |
ded86d8d | 339 | #endif |
94e61088 | 340 | struct pci_vpd *vpd; |
d1b054da | 341 | #ifdef CONFIG_PCI_IOV |
dd7cc44d YZ |
342 | union { |
343 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
344 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
345 | }; | |
302b4215 | 346 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 347 | #endif |
1da177e4 LT |
348 | }; |
349 | ||
dda56549 Y |
350 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
351 | { | |
352 | #ifdef CONFIG_PCI_IOV | |
353 | if (dev->is_virtfn) | |
354 | dev = dev->physfn; | |
355 | #endif | |
356 | ||
357 | return dev; | |
358 | } | |
359 | ||
65891215 ME |
360 | extern struct pci_dev *alloc_pci_dev(void); |
361 | ||
1da177e4 LT |
362 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
363 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
364 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
365 | ||
a7369f1f LV |
366 | static inline int pci_channel_offline(struct pci_dev *pdev) |
367 | { | |
368 | return (pdev->error_state != pci_channel_io_normal); | |
369 | } | |
370 | ||
41017f0c | 371 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 372 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
373 | { |
374 | struct pci_cap_saved_state *tmp; | |
375 | struct hlist_node *pos; | |
376 | ||
377 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
24a4742f | 378 | if (tmp->cap.cap_nr == cap) |
41017f0c SL |
379 | return tmp; |
380 | } | |
381 | return NULL; | |
382 | } | |
383 | ||
384 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
385 | struct pci_cap_saved_state *new_cap) | |
386 | { | |
387 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
388 | } | |
389 | ||
2fe2abf8 BH |
390 | /* |
391 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
392 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
393 | * buses below host bridges or subtractive decode bridges) go in the list. | |
394 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
395 | */ | |
396 | ||
397 | /* | |
398 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
399 | * and there's no way to program the bridge with the details of the window. | |
400 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
401 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
402 | */ | |
403 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
404 | ||
405 | struct pci_bus_resource { | |
406 | struct list_head list; | |
407 | struct resource *res; | |
408 | unsigned int flags; | |
409 | }; | |
4352dfd5 GKH |
410 | |
411 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
412 | |
413 | struct pci_bus { | |
414 | struct list_head node; /* node in list of buses */ | |
415 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
416 | struct list_head children; /* list of child buses */ | |
417 | struct list_head devices; /* list of devices on this bus */ | |
418 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 419 | struct list_head slots; /* list of slots on this bus */ |
2fe2abf8 BH |
420 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
421 | struct list_head resources; /* address space routed to this bus */ | |
1da177e4 LT |
422 | |
423 | struct pci_ops *ops; /* configuration access functions */ | |
424 | void *sysdata; /* hook for sys-specific extension */ | |
425 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
426 | ||
427 | unsigned char number; /* bus number */ | |
428 | unsigned char primary; /* number of primary bridge */ | |
429 | unsigned char secondary; /* number of secondary bridge */ | |
430 | unsigned char subordinate; /* max number of subordinate buses */ | |
3749c51a MW |
431 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
432 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
1da177e4 LT |
433 | |
434 | char name[48]; | |
435 | ||
436 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 437 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 438 | struct device *bridge; |
fd7d1ced | 439 | struct device dev; |
1da177e4 LT |
440 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
441 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 442 | unsigned int is_added:1; |
1da177e4 LT |
443 | }; |
444 | ||
445 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 446 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 447 | |
79af72d7 KK |
448 | /* |
449 | * Returns true if the pci bus is root (behind host-pci bridge), | |
450 | * false otherwise | |
451 | */ | |
452 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
453 | { | |
454 | return !(pbus->parent); | |
455 | } | |
456 | ||
16cf0ebc RW |
457 | #ifdef CONFIG_PCI_MSI |
458 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
459 | { | |
460 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
461 | } | |
462 | #else | |
463 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
464 | #endif | |
465 | ||
1da177e4 LT |
466 | /* |
467 | * Error values that may be returned by PCI functions. | |
468 | */ | |
469 | #define PCIBIOS_SUCCESSFUL 0x00 | |
470 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
471 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
472 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
473 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
474 | #define PCIBIOS_SET_FAILED 0x88 | |
475 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
476 | ||
477 | /* Low-level architecture-dependent routines */ | |
478 | ||
479 | struct pci_ops { | |
480 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
481 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
482 | }; | |
483 | ||
b6ce068a MW |
484 | /* |
485 | * ACPI needs to be able to access PCI config space before we've done a | |
486 | * PCI bus scan and created pci_bus structures. | |
487 | */ | |
488 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
489 | unsigned int devfn, int reg, int len, u32 *val); | |
490 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
491 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
492 | |
493 | struct pci_bus_region { | |
c40a22e0 BH |
494 | resource_size_t start; |
495 | resource_size_t end; | |
1da177e4 LT |
496 | }; |
497 | ||
498 | struct pci_dynids { | |
499 | spinlock_t lock; /* protects list, index */ | |
500 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
501 | }; |
502 | ||
392a1ce7 | 503 | /* ---------------------------------------------------------------- */ |
504 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 505 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 506 | * will be notified of PCI bus errors, and will be driven to recovery |
507 | * when an error occurs. | |
508 | */ | |
509 | ||
510 | typedef unsigned int __bitwise pci_ers_result_t; | |
511 | ||
512 | enum pci_ers_result { | |
513 | /* no result/none/not supported in device driver */ | |
514 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
515 | ||
516 | /* Device driver can recover without slot reset */ | |
517 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
518 | ||
519 | /* Device driver wants slot to be reset. */ | |
520 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
521 | ||
522 | /* Device has completely failed, is unrecoverable */ | |
523 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
524 | ||
525 | /* Device driver is fully recovered and operational */ | |
526 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
527 | }; | |
528 | ||
529 | /* PCI bus error event callbacks */ | |
05cca6e5 | 530 | struct pci_error_handlers { |
392a1ce7 | 531 | /* PCI bus error detected on this device */ |
532 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 533 | enum pci_channel_state error); |
392a1ce7 | 534 | |
535 | /* MMIO has been re-enabled, but not DMA */ | |
536 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
537 | ||
538 | /* PCI Express link has been reset */ | |
539 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
540 | ||
541 | /* PCI slot has been reset */ | |
542 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
543 | ||
544 | /* Device driver may resume normal operations */ | |
545 | void (*resume)(struct pci_dev *dev); | |
546 | }; | |
547 | ||
548 | /* ---------------------------------------------------------------- */ | |
549 | ||
1da177e4 LT |
550 | struct module; |
551 | struct pci_driver { | |
552 | struct list_head node; | |
42b21932 | 553 | const char *name; |
1da177e4 LT |
554 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
555 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
556 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
557 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
558 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
559 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 560 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 561 | void (*shutdown) (struct pci_dev *dev); |
392a1ce7 | 562 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
563 | struct device_driver driver; |
564 | struct pci_dynids dynids; | |
565 | }; | |
566 | ||
05cca6e5 | 567 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 568 | |
90a1ba0c | 569 | /** |
9f9351bb | 570 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
571 | * @_table: device table name |
572 | * | |
573 | * This macro is used to create a struct pci_device_id array (a device table) | |
574 | * in a generic manner. | |
575 | */ | |
9f9351bb | 576 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
577 | const struct pci_device_id _table[] __devinitconst |
578 | ||
1da177e4 LT |
579 | /** |
580 | * PCI_DEVICE - macro used to describe a specific pci device | |
581 | * @vend: the 16 bit PCI Vendor ID | |
582 | * @dev: the 16 bit PCI Device ID | |
583 | * | |
584 | * This macro is used to create a struct pci_device_id that matches a | |
585 | * specific device. The subvendor and subdevice fields will be set to | |
586 | * PCI_ANY_ID. | |
587 | */ | |
588 | #define PCI_DEVICE(vend,dev) \ | |
589 | .vendor = (vend), .device = (dev), \ | |
590 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
591 | ||
592 | /** | |
593 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
594 | * @dev_class: the class, subclass, prog-if triple for this device | |
595 | * @dev_class_mask: the class mask for this device | |
596 | * | |
597 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 598 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
599 | * fields will be set to PCI_ANY_ID. |
600 | */ | |
601 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
602 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
603 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
604 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
605 | ||
1597cacb AC |
606 | /** |
607 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
608 | * @vendor: the vendor name |
609 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
610 | * |
611 | * This macro is used to create a struct pci_device_id that matches a | |
612 | * specific PCI device. The subvendor, and subdevice fields will be set | |
613 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
614 | * private data. | |
615 | */ | |
616 | ||
617 | #define PCI_VDEVICE(vendor, device) \ | |
618 | PCI_VENDOR_ID_##vendor, (device), \ | |
619 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
620 | ||
1da177e4 LT |
621 | /* these external functions are only available when PCI support is enabled */ |
622 | #ifdef CONFIG_PCI | |
623 | ||
b03e7495 JM |
624 | extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss); |
625 | ||
626 | enum pcie_bus_config_types { | |
5f39e670 | 627 | PCIE_BUS_TUNE_OFF, |
b03e7495 | 628 | PCIE_BUS_SAFE, |
5f39e670 | 629 | PCIE_BUS_PERFORMANCE, |
b03e7495 JM |
630 | PCIE_BUS_PEER2PEER, |
631 | }; | |
632 | ||
633 | extern enum pcie_bus_config_types pcie_bus_config; | |
634 | ||
1da177e4 LT |
635 | extern struct bus_type pci_bus_type; |
636 | ||
637 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
638 | * code, or pci core code. */ | |
639 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
640 | /* Some device drivers need know if pci is initiated */ |
641 | extern int no_pci_devices(void); | |
1da177e4 LT |
642 | |
643 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 644 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 645 | char *pcibios_setup(char *str); |
1da177e4 LT |
646 | |
647 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 648 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 649 | resource_size_t, |
e31dd6e4 | 650 | resource_size_t); |
1da177e4 LT |
651 | void pcibios_update_irq(struct pci_dev *, int irq); |
652 | ||
2d1c8618 BH |
653 | /* Weak but can be overriden by arch */ |
654 | void pci_fixup_cardbus(struct pci_bus *); | |
655 | ||
1da177e4 LT |
656 | /* Generic PCI functions used internally */ |
657 | ||
d1fd4fb6 | 658 | void pcibios_scan_specific_bus(int busn); |
1da177e4 | 659 | extern struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 660 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
661 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
662 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 663 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 664 | void *sysdata) |
1da177e4 | 665 | { |
c431ada4 RS |
666 | struct pci_bus *root_bus; |
667 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
668 | if (root_bus) | |
669 | pci_bus_add_devices(root_bus); | |
670 | return root_bus; | |
1da177e4 | 671 | } |
05cca6e5 GKH |
672 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
673 | struct pci_ops *ops, void *sysdata); | |
674 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
675 | int busnr); | |
3749c51a | 676 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 677 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
678 | const char *name, |
679 | struct hotplug_slot *hotplug); | |
f46753c5 | 680 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 681 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 682 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 683 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 684 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 685 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 686 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 687 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
688 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
689 | struct resource *res); | |
57c2cf71 | 690 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
1da177e4 | 691 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 692 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
1da177e4 LT |
693 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
694 | extern void pci_dev_put(struct pci_dev *dev); | |
695 | extern void pci_remove_bus(struct pci_bus *b); | |
696 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 697 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 698 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 699 | extern void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
700 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
701 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
702 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) | |
1da177e4 LT |
703 | |
704 | /* Generic PCI functions exported to card drivers */ | |
705 | ||
388c8c16 JB |
706 | enum pci_lost_interrupt_reason { |
707 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
708 | PCI_LOST_IRQ_DISABLE_MSI, | |
709 | PCI_LOST_IRQ_DISABLE_MSIX, | |
710 | PCI_LOST_IRQ_DISABLE_ACPI, | |
711 | }; | |
712 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
713 | int pci_find_capability(struct pci_dev *dev, int cap); |
714 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
715 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
cf4c43dd JB |
716 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
717 | int cap); | |
05cca6e5 GKH |
718 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
719 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 720 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 721 | |
d42552c3 AM |
722 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
723 | struct pci_dev *from); | |
05cca6e5 | 724 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 725 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 726 | struct pci_dev *from); |
05cca6e5 | 727 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
728 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
729 | unsigned int devfn); | |
730 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
731 | unsigned int devfn) | |
732 | { | |
733 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
734 | } | |
05cca6e5 | 735 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
736 | int pci_dev_present(const struct pci_device_id *ids); |
737 | ||
05cca6e5 GKH |
738 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
739 | int where, u8 *val); | |
740 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
741 | int where, u16 *val); | |
742 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
743 | int where, u32 *val); | |
744 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
745 | int where, u8 val); | |
746 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
747 | int where, u16 val); | |
748 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
749 | int where, u32 val); | |
a72b46c3 | 750 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 LT |
751 | |
752 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
753 | { | |
05cca6e5 | 754 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
755 | } |
756 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
757 | { | |
05cca6e5 | 758 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 759 | } |
05cca6e5 GKH |
760 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
761 | u32 *val) | |
1da177e4 | 762 | { |
05cca6e5 | 763 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
764 | } |
765 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
766 | { | |
05cca6e5 | 767 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
768 | } |
769 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
770 | { | |
05cca6e5 | 771 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 772 | } |
05cca6e5 GKH |
773 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
774 | u32 val) | |
1da177e4 | 775 | { |
05cca6e5 | 776 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
777 | } |
778 | ||
4a7fb636 | 779 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
780 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
781 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 782 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
783 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
784 | void pcim_pin_device(struct pci_dev *pdev); | |
785 | ||
296ccb08 YS |
786 | static inline int pci_is_enabled(struct pci_dev *pdev) |
787 | { | |
788 | return (atomic_read(&pdev->enable_cnt) > 0); | |
789 | } | |
790 | ||
9ac7849e TH |
791 | static inline int pci_is_managed(struct pci_dev *pdev) |
792 | { | |
793 | return pdev->is_managed; | |
794 | } | |
795 | ||
1da177e4 LT |
796 | void pci_disable_device(struct pci_dev *dev); |
797 | void pci_set_master(struct pci_dev *dev); | |
6a479079 | 798 | void pci_clear_master(struct pci_dev *dev); |
f7bdd12d | 799 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 800 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 801 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 802 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 803 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 804 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 805 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 806 | void pci_msi_off(struct pci_dev *dev); |
4d57cdfa | 807 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 808 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
809 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
810 | int pcix_get_mmrbc(struct pci_dev *dev); | |
811 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 812 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 813 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
814 | int pcie_get_mps(struct pci_dev *dev); |
815 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
8c1c699f | 816 | int __pci_reset_function(struct pci_dev *dev); |
8dd7f803 | 817 | int pci_reset_function(struct pci_dev *dev); |
14add80b | 818 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 819 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 820 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
c87deff7 | 821 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
822 | |
823 | /* ROM control related routines */ | |
e416de5e AC |
824 | int pci_enable_rom(struct pci_dev *pdev); |
825 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 826 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 827 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 828 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
1da177e4 LT |
829 | |
830 | /* Power management related routines */ | |
831 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 832 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 AW |
833 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
834 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); | |
835 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
836 | struct pci_saved_state **state); | |
0e5dd46b | 837 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
838 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
839 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 840 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 841 | void pci_pme_active(struct pci_dev *dev, bool enable); |
6cbf8214 RW |
842 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
843 | bool runtime, bool enable); | |
0235c4fc | 844 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 845 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
846 | int pci_prepare_to_sleep(struct pci_dev *dev); |
847 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 848 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 849 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 850 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
1da177e4 | 851 | |
6cbf8214 RW |
852 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
853 | bool enable) | |
854 | { | |
855 | return __pci_enable_wake(dev, state, false, enable); | |
856 | } | |
1da177e4 | 857 | |
b48d4425 JB |
858 | #define PCI_EXP_IDO_REQUEST (1<<0) |
859 | #define PCI_EXP_IDO_COMPLETION (1<<1) | |
860 | void pci_enable_ido(struct pci_dev *dev, unsigned long type); | |
861 | void pci_disable_ido(struct pci_dev *dev, unsigned long type); | |
862 | ||
48a92a81 | 863 | enum pci_obff_signal_type { |
688398bb MS |
864 | PCI_EXP_OBFF_SIGNAL_L0 = 0, |
865 | PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, | |
48a92a81 JB |
866 | }; |
867 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); | |
868 | void pci_disable_obff(struct pci_dev *dev); | |
869 | ||
51c2e0a7 JB |
870 | bool pci_ltr_supported(struct pci_dev *dev); |
871 | int pci_enable_ltr(struct pci_dev *dev); | |
872 | void pci_disable_ltr(struct pci_dev *dev); | |
873 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); | |
874 | ||
bb209c82 BH |
875 | /* For use by arch with custom probe code */ |
876 | void set_pcie_port_type(struct pci_dev *pdev); | |
877 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
878 | ||
ce5ccdef | 879 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 880 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
3ed4fd96 AC |
881 | #ifdef CONFIG_HOTPLUG |
882 | unsigned int pci_rescan_bus(struct pci_bus *bus); | |
883 | #endif | |
ce5ccdef | 884 | |
287d19ce SH |
885 | /* Vital product data routines */ |
886 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
887 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 888 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 889 | |
1da177e4 | 890 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
ea741551 | 891 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
892 | void pci_bus_size_bridges(struct pci_bus *bus); |
893 | int pci_claim_resource(struct pci_dev *, int); | |
894 | void pci_assign_unassigned_resources(void); | |
6841ec68 | 895 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
1da177e4 LT |
896 | void pdev_enable_device(struct pci_dev *); |
897 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 898 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 | 899 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
d5341942 | 900 | int (*)(const struct pci_dev *, u8, u8)); |
1da177e4 | 901 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 902 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 903 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 904 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 905 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 906 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 907 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 908 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 909 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 910 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
911 | |
912 | /* drivers/pci/bus.c */ | |
2fe2abf8 BH |
913 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
914 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); | |
915 | void pci_bus_remove_resources(struct pci_bus *bus); | |
916 | ||
89a74ecc | 917 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
918 | for (i = 0; \ |
919 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
920 | i++) | |
89a74ecc | 921 | |
4a7fb636 AM |
922 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
923 | struct resource *res, resource_size_t size, | |
924 | resource_size_t align, resource_size_t min, | |
925 | unsigned int type_mask, | |
3b7a17fc DB |
926 | resource_size_t (*alignf)(void *, |
927 | const struct resource *, | |
b26b2d49 DB |
928 | resource_size_t, |
929 | resource_size_t), | |
4a7fb636 | 930 | void *alignf_data); |
1da177e4 LT |
931 | void pci_enable_bridges(struct pci_bus *bus); |
932 | ||
863b18f4 | 933 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
934 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
935 | const char *mod_name); | |
bba81165 AM |
936 | |
937 | /* | |
938 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
939 | */ | |
940 | #define pci_register_driver(driver) \ | |
941 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 942 | |
05cca6e5 GKH |
943 | void pci_unregister_driver(struct pci_driver *dev); |
944 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
945 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
9dba910e TH |
946 | int pci_add_dynid(struct pci_driver *drv, |
947 | unsigned int vendor, unsigned int device, | |
948 | unsigned int subvendor, unsigned int subdevice, | |
949 | unsigned int class, unsigned int class_mask, | |
950 | unsigned long driver_data); | |
05cca6e5 GKH |
951 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
952 | struct pci_dev *dev); | |
953 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
954 | int pass); | |
1da177e4 | 955 | |
70298c6e | 956 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 957 | void *userdata); |
70b9f7dc | 958 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 959 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 960 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 961 | void pci_setup_bridge(struct pci_bus *bus); |
cecf4864 | 962 | |
3448a19d DA |
963 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
964 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
965 | ||
deb2d2ec | 966 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 967 | unsigned int command_bits, u32 flags); |
1da177e4 LT |
968 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
969 | ||
f41b1771 | 970 | #include <linux/pci-dma.h> |
1da177e4 LT |
971 | #include <linux/dmapool.h> |
972 | ||
973 | #define pci_pool dma_pool | |
974 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
975 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
976 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
977 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
978 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
979 | ||
e24c2d96 DM |
980 | enum pci_dma_burst_strategy { |
981 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
982 | strategy_parameter is N/A */ | |
983 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
984 | byte boundaries */ | |
985 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
986 | strategy_parameter byte boundaries */ | |
987 | }; | |
988 | ||
1da177e4 | 989 | struct msix_entry { |
16dbef4a | 990 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
991 | u16 entry; /* driver uses to specify entry, OS writes */ |
992 | }; | |
993 | ||
0366f8f7 | 994 | |
1da177e4 | 995 | #ifndef CONFIG_PCI_MSI |
1c8d7b0a | 996 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
05cca6e5 GKH |
997 | { |
998 | return -1; | |
999 | } | |
1000 | ||
d52877c7 YL |
1001 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
1002 | { } | |
05cca6e5 GKH |
1003 | static inline void pci_disable_msi(struct pci_dev *dev) |
1004 | { } | |
1005 | ||
a52e2e35 RW |
1006 | static inline int pci_msix_table_size(struct pci_dev *dev) |
1007 | { | |
1008 | return 0; | |
1009 | } | |
05cca6e5 GKH |
1010 | static inline int pci_enable_msix(struct pci_dev *dev, |
1011 | struct msix_entry *entries, int nvec) | |
1012 | { | |
1013 | return -1; | |
1014 | } | |
1015 | ||
d52877c7 YL |
1016 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
1017 | { } | |
05cca6e5 GKH |
1018 | static inline void pci_disable_msix(struct pci_dev *dev) |
1019 | { } | |
1020 | ||
1021 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
1022 | { } | |
1023 | ||
1024 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
1025 | { } | |
07ae95f9 AP |
1026 | static inline int pci_msi_enabled(void) |
1027 | { | |
1028 | return 0; | |
1029 | } | |
1da177e4 | 1030 | #else |
1c8d7b0a | 1031 | extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
d52877c7 | 1032 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 1033 | extern void pci_disable_msi(struct pci_dev *dev); |
a52e2e35 | 1034 | extern int pci_msix_table_size(struct pci_dev *dev); |
05cca6e5 | 1035 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 1036 | struct msix_entry *entries, int nvec); |
d52877c7 | 1037 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
1038 | extern void pci_disable_msix(struct pci_dev *dev); |
1039 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 1040 | extern void pci_restore_msi_state(struct pci_dev *dev); |
07ae95f9 | 1041 | extern int pci_msi_enabled(void); |
1da177e4 LT |
1042 | #endif |
1043 | ||
ab0724ff | 1044 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 RW |
1045 | extern bool pcie_ports_disabled; |
1046 | extern bool pcie_ports_auto; | |
ab0724ff MT |
1047 | #else |
1048 | #define pcie_ports_disabled true | |
1049 | #define pcie_ports_auto false | |
1050 | #endif | |
415e12b2 | 1051 | |
3e1b1600 | 1052 | #ifndef CONFIG_PCIEASPM |
8b8bae90 RW |
1053 | static inline int pcie_aspm_enabled(void) { return 0; } |
1054 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 AP |
1055 | #else |
1056 | extern int pcie_aspm_enabled(void); | |
8b8bae90 | 1057 | extern bool pcie_aspm_support_enabled(void); |
3e1b1600 AP |
1058 | #endif |
1059 | ||
415e12b2 RW |
1060 | #ifdef CONFIG_PCIEAER |
1061 | void pci_no_aer(void); | |
1062 | bool pci_aer_available(void); | |
1063 | #else | |
1064 | static inline void pci_no_aer(void) { } | |
1065 | static inline bool pci_aer_available(void) { return false; } | |
1066 | #endif | |
1067 | ||
43c16408 AP |
1068 | #ifndef CONFIG_PCIE_ECRC |
1069 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) | |
1070 | { | |
1071 | return; | |
1072 | } | |
1073 | static inline void pcie_ecrc_get_policy(char *str) {}; | |
1074 | #else | |
1075 | extern void pcie_set_ecrc_checking(struct pci_dev *dev); | |
1076 | extern void pcie_ecrc_get_policy(char *str); | |
1077 | #endif | |
1078 | ||
1c8d7b0a MW |
1079 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
1080 | ||
8b955b0d | 1081 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
1082 | /* The functions a driver should call */ |
1083 | int ht_create_irq(struct pci_dev *dev, int idx); | |
1084 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
1085 | #endif /* CONFIG_HT_IRQ */ |
1086 | ||
e04b0ea2 BK |
1087 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
1088 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
1089 | ||
4352dfd5 GKH |
1090 | /* |
1091 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
1092 | * a PCI domain is defined to be a set of PCI busses which share | |
1093 | * configuration space. | |
1094 | */ | |
32a2eea7 JG |
1095 | #ifdef CONFIG_PCI_DOMAINS |
1096 | extern int pci_domains_supported; | |
1097 | #else | |
1098 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
1099 | static inline int pci_domain_nr(struct pci_bus *bus) |
1100 | { | |
1101 | return 0; | |
1102 | } | |
1103 | ||
4352dfd5 GKH |
1104 | static inline int pci_proc_domain(struct pci_bus *bus) |
1105 | { | |
1106 | return 0; | |
1107 | } | |
32a2eea7 | 1108 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1109 | |
95a8b6ef MT |
1110 | /* some architectures require additional setup to direct VGA traffic */ |
1111 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, | |
3448a19d | 1112 | unsigned int command_bits, u32 flags); |
95a8b6ef MT |
1113 | extern void pci_register_set_vga_state(arch_set_vga_state_t func); |
1114 | ||
4352dfd5 | 1115 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
1116 | |
1117 | /* | |
1118 | * If the system does not have PCI, clearly these return errors. Define | |
1119 | * these as simple inline functions to avoid hair in drivers. | |
1120 | */ | |
1121 | ||
05cca6e5 GKH |
1122 | #define _PCI_NOP(o, s, t) \ |
1123 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1124 | int where, t val) \ | |
1da177e4 | 1125 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1126 | |
1127 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1128 | _PCI_NOP(o, word, u16 x) \ | |
1129 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1130 | _PCI_NOP_ALL(read, *) |
1131 | _PCI_NOP_ALL(write,) | |
1132 | ||
d42552c3 | 1133 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1134 | unsigned int device, |
1135 | struct pci_dev *from) | |
1136 | { | |
1137 | return NULL; | |
1138 | } | |
d42552c3 | 1139 | |
05cca6e5 GKH |
1140 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1141 | unsigned int device, | |
1142 | unsigned int ss_vendor, | |
1143 | unsigned int ss_device, | |
b08508c4 | 1144 | struct pci_dev *from) |
05cca6e5 GKH |
1145 | { |
1146 | return NULL; | |
1147 | } | |
1da177e4 | 1148 | |
05cca6e5 GKH |
1149 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1150 | struct pci_dev *from) | |
1151 | { | |
1152 | return NULL; | |
1153 | } | |
1da177e4 LT |
1154 | |
1155 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1156 | #define no_pci_devices() (1) |
1da177e4 LT |
1157 | #define pci_dev_put(dev) do { } while (0) |
1158 | ||
05cca6e5 GKH |
1159 | static inline void pci_set_master(struct pci_dev *dev) |
1160 | { } | |
1161 | ||
1162 | static inline int pci_enable_device(struct pci_dev *dev) | |
1163 | { | |
1164 | return -EIO; | |
1165 | } | |
1166 | ||
1167 | static inline void pci_disable_device(struct pci_dev *dev) | |
1168 | { } | |
1169 | ||
1170 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1171 | { | |
1172 | return -EIO; | |
1173 | } | |
1174 | ||
80be0385 RD |
1175 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1176 | { | |
1177 | return -EIO; | |
1178 | } | |
1179 | ||
4d57cdfa FT |
1180 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1181 | unsigned int size) | |
1182 | { | |
1183 | return -EIO; | |
1184 | } | |
1185 | ||
59fc67de FT |
1186 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1187 | unsigned long mask) | |
1188 | { | |
1189 | return -EIO; | |
1190 | } | |
1191 | ||
05cca6e5 GKH |
1192 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1193 | { | |
1194 | return -EBUSY; | |
1195 | } | |
1196 | ||
1197 | static inline int __pci_register_driver(struct pci_driver *drv, | |
1198 | struct module *owner) | |
1199 | { | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static inline int pci_register_driver(struct pci_driver *drv) | |
1204 | { | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
1209 | { } | |
1210 | ||
1211 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
1212 | { | |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
1217 | int cap) | |
1218 | { | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
1223 | { | |
1224 | return 0; | |
1225 | } | |
1226 | ||
1da177e4 | 1227 | /* Power management related routines */ |
05cca6e5 GKH |
1228 | static inline int pci_save_state(struct pci_dev *dev) |
1229 | { | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1d3c16a8 JM |
1233 | static inline void pci_restore_state(struct pci_dev *dev) |
1234 | { } | |
1da177e4 | 1235 | |
05cca6e5 GKH |
1236 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1237 | { | |
1238 | return 0; | |
1239 | } | |
1240 | ||
3449248c RD |
1241 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
1242 | { | |
1243 | return 0; | |
1244 | } | |
1245 | ||
05cca6e5 GKH |
1246 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1247 | pm_message_t state) | |
1248 | { | |
1249 | return PCI_D0; | |
1250 | } | |
1251 | ||
1252 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1253 | int enable) | |
1254 | { | |
1255 | return 0; | |
1256 | } | |
1257 | ||
b48d4425 JB |
1258 | static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
1259 | { | |
1260 | } | |
1261 | ||
1262 | static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |
1263 | { | |
1264 | } | |
1265 | ||
48a92a81 JB |
1266 | static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) |
1267 | { | |
1268 | return 0; | |
1269 | } | |
1270 | ||
1271 | static inline void pci_disable_obff(struct pci_dev *dev) | |
1272 | { | |
1273 | } | |
1274 | ||
05cca6e5 GKH |
1275 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
1276 | { | |
1277 | return -EIO; | |
1278 | } | |
1279 | ||
1280 | static inline void pci_release_regions(struct pci_dev *dev) | |
1281 | { } | |
0da0ead9 | 1282 | |
a46e8126 KG |
1283 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1284 | ||
05cca6e5 GKH |
1285 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
1286 | { } | |
1287 | ||
1288 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
1289 | { } | |
e04b0ea2 | 1290 | |
d80d0217 RD |
1291 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1292 | { return NULL; } | |
1293 | ||
1294 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1295 | unsigned int devfn) | |
1296 | { return NULL; } | |
1297 | ||
1298 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1299 | unsigned int devfn) | |
1300 | { return NULL; } | |
1301 | ||
92298e66 DA |
1302 | static inline int pci_domain_nr(struct pci_bus *bus) |
1303 | { return 0; } | |
1304 | ||
fb8a0d9d WM |
1305 | #define dev_is_pci(d) (false) |
1306 | #define dev_is_pf(d) (false) | |
1307 | #define dev_num_vf(d) (0) | |
4352dfd5 | 1308 | #endif /* CONFIG_PCI */ |
1da177e4 | 1309 | |
4352dfd5 GKH |
1310 | /* Include architecture-dependent settings and functions */ |
1311 | ||
1312 | #include <asm/pci.h> | |
1da177e4 | 1313 | |
1f82de10 YL |
1314 | #ifndef PCIBIOS_MAX_MEM_32 |
1315 | #define PCIBIOS_MAX_MEM_32 (-1) | |
1316 | #endif | |
1317 | ||
1da177e4 LT |
1318 | /* these helpers provide future and backwards compatibility |
1319 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1320 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1321 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1322 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1323 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1324 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1325 | pci_resource_end((dev), (bar)) == \ | |
1326 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1327 | \ | |
1328 | (pci_resource_end((dev), (bar)) - \ | |
1329 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1330 | |
1331 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1332 | * driver-specific data. They are really just a wrapper around | |
1333 | * the generic device structure functions of these calls. | |
1334 | */ | |
05cca6e5 | 1335 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1336 | { |
1337 | return dev_get_drvdata(&pdev->dev); | |
1338 | } | |
1339 | ||
05cca6e5 | 1340 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1341 | { |
1342 | dev_set_drvdata(&pdev->dev, data); | |
1343 | } | |
1344 | ||
1345 | /* If you want to know what to call your pci_dev, ask this function. | |
1346 | * Again, it's a wrapper around the generic device. | |
1347 | */ | |
2fc90f61 | 1348 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1349 | { |
c6c4f070 | 1350 | return dev_name(&pdev->dev); |
1da177e4 LT |
1351 | } |
1352 | ||
2311b1f2 ME |
1353 | |
1354 | /* Some archs don't want to expose struct resource to userland as-is | |
1355 | * in sysfs and /proc | |
1356 | */ | |
1357 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1358 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1359 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1360 | resource_size_t *end) |
2311b1f2 ME |
1361 | { |
1362 | *start = rsrc->start; | |
1363 | *end = rsrc->end; | |
1364 | } | |
1365 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1366 | ||
1367 | ||
1da177e4 LT |
1368 | /* |
1369 | * The world is not perfect and supplies us with broken PCI devices. | |
1370 | * For at least a part of these bugs we need a work-around, so both | |
1371 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1372 | * fixup hooks to be called for particular buggy devices. | |
1373 | */ | |
1374 | ||
1375 | struct pci_fixup { | |
1376 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1377 | void (*hook)(struct pci_dev *dev); | |
1378 | }; | |
1379 | ||
1380 | enum pci_fixup_pass { | |
1381 | pci_fixup_early, /* Before probing BARs */ | |
1382 | pci_fixup_header, /* After reading configuration header */ | |
1383 | pci_fixup_final, /* Final phase of device fixups */ | |
1384 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1385 | pci_fixup_resume, /* pci_device_resume() */ |
1386 | pci_fixup_suspend, /* pci_device_suspend */ | |
1387 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1388 | }; |
1389 | ||
1390 | /* Anonymous variables would be nice... */ | |
1391 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1392 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1393 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1394 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1395 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1396 | vendor##device##hook, vendor, device, hook) | |
1397 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1398 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1399 | vendor##device##hook, vendor, device, hook) | |
1400 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1401 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1402 | vendor##device##hook, vendor, device, hook) | |
1403 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1404 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1405 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1406 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1407 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1408 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1409 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1410 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1411 | resume_early##vendor##device##hook, vendor, device, hook) | |
1412 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1413 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1414 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 | 1415 | |
93177a74 | 1416 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1417 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
1418 | #else |
1419 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
1420 | struct pci_dev *dev) {} | |
1421 | #endif | |
1da177e4 | 1422 | |
05cca6e5 | 1423 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1424 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1425 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1426 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1427 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1428 | const char *name); | |
ec04b075 | 1429 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1430 | |
1da177e4 | 1431 | extern int pci_pci_problems; |
236561e5 | 1432 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1433 | #define PCIPCI_TRITON 2 |
1434 | #define PCIPCI_NATOMA 4 | |
1435 | #define PCIPCI_VIAETBF 8 | |
1436 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1437 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1438 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1439 | |
4516a618 AN |
1440 | extern unsigned long pci_cardbus_io_size; |
1441 | extern unsigned long pci_cardbus_mem_size; | |
491424c0 | 1442 | extern u8 __devinitdata pci_dfl_cache_line_size; |
ac1aa47b | 1443 | extern u8 pci_cache_line_size; |
4516a618 | 1444 | |
28760489 EB |
1445 | extern unsigned long pci_hotplug_io_size; |
1446 | extern unsigned long pci_hotplug_mem_size; | |
1447 | ||
19792a08 AB |
1448 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1449 | void pcibios_disable_device(struct pci_dev *dev); | |
1450 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1451 | enum pcie_reset_state state); | |
575e3348 | 1452 | |
7752d5cf | 1453 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1454 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1455 | extern void __init pci_mmcfg_late_init(void); |
1456 | #else | |
bb63b421 | 1457 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1458 | static inline void pci_mmcfg_late_init(void) { } |
1459 | #endif | |
1460 | ||
0ef5f8f6 AP |
1461 | int pci_ext_cfg_avail(struct pci_dev *dev); |
1462 | ||
1684f5dd | 1463 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1464 | |
dd7cc44d YZ |
1465 | #ifdef CONFIG_PCI_IOV |
1466 | extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); | |
1467 | extern void pci_disable_sriov(struct pci_dev *dev); | |
74bb1bcc | 1468 | extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
fb8a0d9d | 1469 | extern int pci_num_vf(struct pci_dev *dev); |
dd7cc44d YZ |
1470 | #else |
1471 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
1472 | { | |
1473 | return -ENODEV; | |
1474 | } | |
1475 | static inline void pci_disable_sriov(struct pci_dev *dev) | |
1476 | { | |
1477 | } | |
74bb1bcc YZ |
1478 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1479 | { | |
1480 | return IRQ_NONE; | |
1481 | } | |
fb8a0d9d WM |
1482 | static inline int pci_num_vf(struct pci_dev *dev) |
1483 | { | |
1484 | return 0; | |
1485 | } | |
dd7cc44d YZ |
1486 | #endif |
1487 | ||
c825bc94 KK |
1488 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
1489 | extern void pci_hp_create_module_link(struct pci_slot *pci_slot); | |
1490 | extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
1491 | #endif | |
1492 | ||
d7b7e605 KK |
1493 | /** |
1494 | * pci_pcie_cap - get the saved PCIe capability offset | |
1495 | * @dev: PCI device | |
1496 | * | |
1497 | * PCIe capability offset is calculated at PCI device initialization | |
1498 | * time and saved in the data structure. This function returns saved | |
1499 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1500 | * reduces unnecessary search in the PCI configuration space. If you | |
1501 | * need to calculate PCIe capability offset from raw device for some | |
1502 | * reasons, please use pci_find_capability() instead. | |
1503 | */ | |
1504 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1505 | { | |
1506 | return dev->pcie_cap; | |
1507 | } | |
1508 | ||
7eb776c4 KK |
1509 | /** |
1510 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1511 | * @dev: PCI device | |
1512 | * | |
1513 | * Retrun true if the PCI device is PCI Express capable, false otherwise. | |
1514 | */ | |
1515 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1516 | { | |
1517 | return !!pci_pcie_cap(dev); | |
1518 | } | |
1519 | ||
5d990b62 CW |
1520 | void pci_request_acs(void); |
1521 | ||
a2ce7662 | 1522 | |
7ad506fa MC |
1523 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
1524 | #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) | |
1525 | ||
1526 | /* Large Resource Data Type Tag Item Names */ | |
1527 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
1528 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
1529 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
1530 | ||
1531 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
1532 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
1533 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
1534 | ||
1535 | /* Small Resource Data Type Tag Item Names */ | |
1536 | #define PCI_VPD_STIN_END 0x78 /* End */ | |
1537 | ||
1538 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END | |
1539 | ||
1540 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
1541 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
1542 | ||
1543 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
1544 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 1545 | |
e1d5bdab MC |
1546 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1547 | ||
4067a854 MC |
1548 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1549 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
1550 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 1551 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 1552 | |
a2ce7662 MC |
1553 | /** |
1554 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
1555 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1556 | * | |
1557 | * Returns the extracted Large Resource Data Type length. | |
1558 | */ | |
1559 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
1560 | { | |
1561 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
1562 | } | |
1563 | ||
7ad506fa MC |
1564 | /** |
1565 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
1566 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
1567 | * | |
1568 | * Returns the extracted Small Resource Data Type length. | |
1569 | */ | |
1570 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
1571 | { | |
1572 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
1573 | } | |
1574 | ||
e1d5bdab MC |
1575 | /** |
1576 | * pci_vpd_info_field_size - Extracts the information field length | |
1577 | * @lrdt: Pointer to the beginning of an information field header | |
1578 | * | |
1579 | * Returns the extracted information field length. | |
1580 | */ | |
1581 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
1582 | { | |
1583 | return info_field[2]; | |
1584 | } | |
1585 | ||
b55ac1b2 MC |
1586 | /** |
1587 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
1588 | * @buf: Pointer to buffered vpd data | |
1589 | * @off: The offset into the buffer at which to begin the search | |
1590 | * @len: The length of the vpd buffer | |
1591 | * @rdt: The Resource Data Type to search for | |
1592 | * | |
1593 | * Returns the index where the Resource Data Type was found or | |
1594 | * -ENOENT otherwise. | |
1595 | */ | |
1596 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
1597 | ||
4067a854 MC |
1598 | /** |
1599 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
1600 | * @buf: Pointer to buffered vpd data | |
1601 | * @off: The offset into the buffer at which to begin the search | |
1602 | * @len: The length of the buffer area, relative to off, in which to search | |
1603 | * @kw: The keyword to search for | |
1604 | * | |
1605 | * Returns the index where the information field keyword was found or | |
1606 | * -ENOENT otherwise. | |
1607 | */ | |
1608 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
1609 | unsigned int len, const char *kw); | |
1610 | ||
98d9f30c BH |
1611 | /* PCI <-> OF binding helpers */ |
1612 | #ifdef CONFIG_OF | |
1613 | struct device_node; | |
1614 | extern void pci_set_of_node(struct pci_dev *dev); | |
1615 | extern void pci_release_of_node(struct pci_dev *dev); | |
1616 | extern void pci_set_bus_of_node(struct pci_bus *bus); | |
1617 | extern void pci_release_bus_of_node(struct pci_bus *bus); | |
1618 | ||
1619 | /* Arch may override this (weak) */ | |
1620 | extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus); | |
1621 | ||
64099d98 BH |
1622 | static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1623 | { | |
1624 | return pdev ? pdev->dev.of_node : NULL; | |
1625 | } | |
1626 | ||
ef3b4f8c BH |
1627 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
1628 | { | |
1629 | return bus ? bus->dev.of_node : NULL; | |
1630 | } | |
1631 | ||
98d9f30c BH |
1632 | #else /* CONFIG_OF */ |
1633 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
1634 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
1635 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
1636 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
1637 | #endif /* CONFIG_OF */ | |
1638 | ||
166e9278 OBC |
1639 | /** |
1640 | * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device | |
1641 | * @pdev: the PCI device | |
1642 | * | |
1643 | * if the device is PCIE, return NULL | |
1644 | * if the device isn't connected to a PCIe bridge (that is its parent is a | |
1645 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its | |
1646 | * parent | |
1647 | */ | |
1648 | struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); | |
1649 | ||
1da177e4 LT |
1650 | #endif /* __KERNEL__ */ |
1651 | #endif /* LINUX_PCI_H */ |