projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: pnv_php: Add missing of_node_put()
[linux-2.6-block.git] / include / linux / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
1da177e4
LT		 17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
1da177e4 20
778382e0
DW		 21#include <linux/mod_devicetable.h>
22
1da177e4 23#include <linux/types.h>
98db6f19 24#include <linux/init.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/list.h>
4a7fb636 27#include <linux/compiler.h>
1da177e4 28#include <linux/errno.h>
f46753c5 29#include <linux/kobject.h>
60063497 30#include <linux/atomic.h>
1da177e4 31#include <linux/device.h>
704e8953 32#include <linux/interrupt.h>
1388cc96 33#include <linux/io.h>
14d76b68 34#include <linux/resource_ext.h>
607ca46e 35#include <uapi/linux/pci.h>
1da177e4 36
7e7a43c3
AB		 37#include <linux/pci_ids.h>
38
85467136
SK		 39/*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
f7625980
BH		 46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 48 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 49 * the following kernel-only defines are being added here.
85467136 50 */
0aa0f5d1 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
f46753c5
AC		 55/* pci_slot represents a physical slot */
56struct pci_slot {
0aa0f5d1
BH		 57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
f46753c5
AC		 62};
63
0ad772ec
AC		 64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
1da177e4
LT		 69/* File state for mmap()s on /proc/bus/pci/X/Y */
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
0aa0f5d1 75/* For PCI devices, the region numbers are assigned this way: */
fde09c6d
YZ		 76enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
0aa0f5d1 84 /* Device-specific resources */
d1b054da
YZ		 85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
0aa0f5d1 90 /* Resources assigned to buses behind the bridge */
fde09c6d
YZ		 91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
0aa0f5d1 97 /* Total resources associated with a PCI device */
fde09c6d
YZ		 98 PCI_NUM_RESOURCES,
99
0aa0f5d1 100 /* Preserve this for compatibility */
cda57bf9 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 102};
1da177e4 103
b352baf1
PB		 104/**
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
111 *
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
114 */
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123/* The number of legacy PCI INTx interrupts */
124#define PCI_NUM_INTX 4
125
224abb67
BH		 126/*
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
129 */
1da177e4
LT		 130typedef int __bitwise pci_power_t;
131
4352dfd5
GKH		 132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 137#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 139
00240c38
AS		 140/* Remember to update this when the list above changes! */
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
9661e783 145 return pci_power_names[1 + (__force int) state];
00240c38
AS		 146}
147
448bd857
HY		 148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
aa8c6c93 152
0aa0f5d1
BH		 153/**
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
392a1ce7 157 */
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
f7bdd12d
BK		 171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
f7625980 177 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
f7625980 180 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
ba698ad4
DM		 184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
0aa0f5d1 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
6b121592 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 188 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 190 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
0aa0f5d1 202 /* A non-root bridge where translation occurs, stop alias search here */
ffff8858 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 206 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 208};
209
e1d3a908
SA		 210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
6e325a62
MT		 215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
032c3d86
JD		 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
6e325a62
MT		 220};
221
0aa0f5d1 222/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
59da381e
JK		 223enum pcie_link_width {
224 PCIE_LNK_WIDTH_RESRV = 0x00,
225 PCIE_LNK_X1 = 0x01,
226 PCIE_LNK_X2 = 0x02,
227 PCIE_LNK_X4 = 0x04,
228 PCIE_LNK_X8 = 0x08,
0aa0f5d1 229 PCIE_LNK_X12 = 0x0c,
59da381e
JK		 230 PCIE_LNK_X16 = 0x10,
231 PCIE_LNK_X32 = 0x20,
0aa0f5d1 232 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
59da381e
JK		 233};
234
536c8cb4
MW		 235/* Based on the PCI Hotplug Spec, but some values are made up by us */
236enum pci_bus_speed {
237 PCI_SPEED_33MHz = 0x00,
238 PCI_SPEED_66MHz = 0x01,
239 PCI_SPEED_66MHz_PCIX = 0x02,
240 PCI_SPEED_100MHz_PCIX = 0x03,
241 PCI_SPEED_133MHz_PCIX = 0x04,
242 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
243 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
244 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
245 PCI_SPEED_66MHz_PCIX_266 = 0x09,
246 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
247 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 248 AGP_UNKNOWN = 0x0c,
249 AGP_1X = 0x0d,
250 AGP_2X = 0x0e,
251 AGP_4X = 0x0f,
252 AGP_8X = 0x10,
536c8cb4
MW		 253 PCI_SPEED_66MHz_PCIX_533 = 0x11,
254 PCI_SPEED_100MHz_PCIX_533 = 0x12,
255 PCI_SPEED_133MHz_PCIX_533 = 0x13,
256 PCIE_SPEED_2_5GT = 0x14,
257 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 258 PCIE_SPEED_8_0GT = 0x16,
1acfb9b7 259 PCIE_SPEED_16_0GT = 0x17,
536c8cb4
MW		 260 PCI_SPEED_UNKNOWN = 0xff,
261};
262
24a4742f 263struct pci_cap_saved_data {
0aa0f5d1
BH		 264 u16 cap_nr;
265 bool cap_extended;
266 unsigned int size;
267 u32 data[0];
41017f0c
SL		 268};
269
24a4742f 270struct pci_cap_saved_state {
0aa0f5d1
BH		 271 struct hlist_node next;
272 struct pci_cap_saved_data cap;
24a4742f
AW		 273};
274
402723ad 275struct irq_affinity;
7d715a6c 276struct pcie_link_state;
ee69439c 277struct pci_vpd;
d1b054da 278struct pci_sriov;
302b4215 279struct pci_ats;
ee69439c 280
0aa0f5d1 281/* The pci_dev structure describes PCI devices */
1da177e4 282struct pci_dev {
0aa0f5d1
BH		 283 struct list_head bus_list; /* Node in per-bus list */
284 struct pci_bus *bus; /* Bus this device is on */
285 struct pci_bus *subordinate; /* Bus this device bridges to */
1da177e4 286
0aa0f5d1
BH		 287 void *sysdata; /* Hook for sys-specific extension */
288 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
f46753c5 289 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4 290
0aa0f5d1 291 unsigned int devfn; /* Encoded device & function index */
1da177e4
LT		 292 unsigned short vendor;
293 unsigned short device;
294 unsigned short subsystem_vendor;
295 unsigned short subsystem_device;
296 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 297 u8 revision; /* PCI revision, low byte of class word */
1da177e4 298 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 299#ifdef CONFIG_PCIEAER
300 u16 aer_cap; /* AER capability offset */
301#endif
f7625980 302 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 303 u8 msi_cap; /* MSI capability offset */
304 u8 msix_cap; /* MSI-X capability offset */
f7625980 305 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
0aa0f5d1
BH		 306 u8 rom_base_reg; /* Config register controlling ROM */
307 u8 pin; /* Interrupt pin this device uses */
308 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
309 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
1da177e4 310
0aa0f5d1 311 struct pci_driver *driver; /* Driver bound to this device */
1da177e4
LT		 312 u64 dma_mask; /* Mask of the bits of bus address this
313 device implements. Normally this is
314 0xffffffff. You only need to change
315 this if your device has broken DMA
316 or supports 64-bit transfers. */
317
4d57cdfa
FT		 318 struct device_dma_parameters dma_parms;
319
0aa0f5d1
BH		 320 pci_power_t current_state; /* Current operating state. In ACPI,
321 this is D0-D3, D0 being fully
322 functional, and D3 being off. */
703860ed 323 u8 pm_cap; /* PM capability offset */
337001b6
RW		 324 unsigned int pme_support:5; /* Bitmask of states from which PME#
325 can be generated */
379021d5 326 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 327 unsigned int d1_support:1; /* Low power state D1 is supported */
328 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 329 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
330 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 331 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 332 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
0aa0f5d1
BH		 333 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
334 decoding during BAR sizing */
e80bb09d 335 unsigned int wakeup_prepared:1;
0aa0f5d1 336 unsigned int runtime_d3cold:1; /* Whether go through runtime
448bd857
HY		 337 D3cold, not set for devices
338 powered on/off by the
339 corresponding bridge */
b440bde7 340 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 341 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
342 controlled exclusively by
343 user sysfs */
1ae861e6 344 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 345 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 346
7d715a6c 347#ifdef CONFIG_PCIEASPM
f7625980 348 struct pcie_link_state *link_state; /* ASPM link state */
c46fd358
BH		 349 unsigned int ltr_path:1; /* Latency Tolerance Reporting
350 supported from root to here */
7d715a6c
SL		 351#endif
352
0aa0f5d1
BH		 353 pci_channel_state_t error_state; /* Current connectivity state */
354 struct device dev; /* Generic device interface */
1da177e4 355
0aa0f5d1 356 int cfg_size; /* Size of config space */
1da177e4
LT		 357
358 /*
359 * Instead of touching interrupt line and base address registers
360 * directly, use the values stored here. They might be different!
361 */
362 unsigned int irq;
363 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
364
0aa0f5d1
BH		 365 bool match_driver; /* Skip attaching driver */
366
367 unsigned int transparent:1; /* Subtractive decode bridge */
368 unsigned int multifunction:1; /* Multi-function device */
369
8a1bc901 370 unsigned int is_added:1;
0aa0f5d1
BH		 371 unsigned int is_busmaster:1; /* Is busmaster */
372 unsigned int no_msi:1; /* May not use MSI */
373 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
374 unsigned int block_cfg_access:1; /* Config space access blocked */
375 unsigned int broken_parity_status:1; /* Generates false positive parity */
376 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
f7625980 377 unsigned int msi_enabled:1;
99dc804d 378 unsigned int msix_enabled:1;
0aa0f5d1
BH		 379 unsigned int ari_enabled:1; /* ARI forwarding */
380 unsigned int ats_enabled:1; /* Address Translation Svc */
a4f4fa68
JPB		 381 unsigned int pasid_enabled:1; /* Process Address Space ID */
382 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 383 unsigned int is_managed:1;
0aa0f5d1 384 unsigned int needs_freset:1; /* Requires fundamental reset */
aa8c6c93 385 unsigned int state_saved:1;
d1b054da 386 unsigned int is_physfn:1;
dd7cc44d 387 unsigned int is_virtfn:1;
711d5779 388 unsigned int reset_fn:1;
0aa0f5d1
BH		 389 unsigned int is_hotplug_bridge:1;
390 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
391 unsigned int __aer_firmware_first_valid:1;
affb72c3 392 unsigned int __aer_firmware_first:1;
0aa0f5d1
BH		 393 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
394 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
cffe0a2b 395 unsigned int irq_managed:1;
d0751b98 396 unsigned int has_secondary_link:1;
0aa0f5d1
BH		 397 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
398 unsigned int is_probed:1; /* Device probing in progress */
ba698ad4 399 pci_dev_flags_t dev_flags;
bae94d02 400 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 401
0aa0f5d1 402 u32 saved_config_space[16]; /* Config space saved at suspend time */
41017f0c 403 struct hlist_head saved_cap_space;
0aa0f5d1
BH		 404 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
405 int rom_attr_enabled; /* Display of ROM attribute enabled? */
1da177e4 406 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 407 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c 408
d22b3621
BH		 409#ifdef CONFIG_HOTPLUG_PCI_PCIE
410 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
411#endif
9bb04a0c
JY		 412#ifdef CONFIG_PCIE_PTM
413 unsigned int ptm_root:1;
414 unsigned int ptm_enabled:1;
8b2ec318 415 u8 ptm_granularity;
9bb04a0c 416#endif
ded86d8d 417#ifdef CONFIG_PCI_MSI
1c51b50c 418 const struct attribute_group **msi_irq_groups;
ded86d8d 419#endif
94e61088 420 struct pci_vpd *vpd;
466b3ddf 421#ifdef CONFIG_PCI_ATS
dd7cc44d 422 union {
0aa0f5d1
BH		 423 struct pci_sriov *sriov; /* PF: SR-IOV info */
424 struct pci_dev *physfn; /* VF: related PF */
dd7cc44d 425 };
67930995
BH		 426 u16 ats_cap; /* ATS Capability offset */
427 u8 ats_stu; /* ATS Smallest Translation Unit */
0aa0f5d1 428 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
4ebeb1ec
CT		 429#endif
430#ifdef CONFIG_PCI_PRI
431 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
432#endif
433#ifdef CONFIG_PCI_PASID
434 u16 pasid_features;
d1b054da 435#endif
0aa0f5d1
BH		 436 phys_addr_t rom; /* Physical address if not from BAR */
437 size_t romlen; /* Length if not from BAR */
438 char *driver_override; /* Driver name to force a match */
89ee9f76 439
0aa0f5d1 440 unsigned long priv_flags; /* Private flags for the PCI driver */
1da177e4
LT		 441};
442
dda56549
Y		 443static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
444{
445#ifdef CONFIG_PCI_IOV
446 if (dev->is_virtfn)
447 dev = dev->physfn;
448#endif
dda56549
Y		 449 return dev;
450}
451
3c6e6ae7 452struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 453
1da177e4
LT		 454#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
455#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
456
a7369f1f
LV		 457static inline int pci_channel_offline(struct pci_dev *pdev)
458{
459 return (pdev->error_state != pci_channel_io_normal);
460}
461
5a21d70d 462struct pci_host_bridge {
0aa0f5d1
BH		 463 struct device dev;
464 struct pci_bus *bus; /* Root bus */
465 struct pci_ops *ops;
466 void *sysdata;
467 int busnr;
14d76b68 468 struct list_head windows; /* resource_entry */
0aa0f5d1 469 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
3aa8a41e 470 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a 471 void (*release_fn)(struct pci_host_bridge *);
0aa0f5d1 472 void *release_data;
37d6a0a6 473 struct msi_controller *msi;
0aa0f5d1
BH		 474 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
475 unsigned int no_ext_tags:1; /* No Extended Tags */
02bfeb48
BH		 476 unsigned int native_aer:1; /* OS may use PCIe AER */
477 unsigned int native_hotplug:1; /* OS may use PCIe hotplug */
478 unsigned int native_pme:1; /* OS may use PCIe PME */
7c7a0e94
GP		 479 /* Resource alignment requirements */
480 resource_size_t (*align_resource)(struct pci_dev *dev,
481 const struct resource *res,
482 resource_size_t start,
483 resource_size_t size,
484 resource_size_t align);
0aa0f5d1 485 unsigned long private[0] ____cacheline_aligned;
5a21d70d 486};
41017f0c 487
7b543663 488#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 489
59094065
TR		 490static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
491{
492 return (void *)bridge->private;
493}
494
495static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
496{
497 return container_of(priv, struct pci_host_bridge, private);
498}
499
a52d1443 500struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 501struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
502 size_t priv);
dff79b91 503void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 504struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
505
4fa2649a 506void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
0aa0f5d1
BH		 507 void (*release_fn)(struct pci_host_bridge *),
508 void *release_data);
7b543663 509
6c0cc950
RW		 510int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
511
2fe2abf8
BH		 512/*
513 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
514 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
515 * buses below host bridges or subtractive decode bridges) go in the list.
516 * Use pci_bus_for_each_resource() to iterate through all the resources.
517 */
518
519/*
520 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
521 * and there's no way to program the bridge with the details of the window.
522 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
523 * decode bit set, because they are explicit and can be programmed with _SRS.
524 */
525#define PCI_SUBTRACTIVE_DECODE 0x1
526
527struct pci_bus_resource {
0aa0f5d1
BH		 528 struct list_head list;
529 struct resource *res;
530 unsigned int flags;
2fe2abf8 531};
4352dfd5
GKH		 532
533#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 534
535struct pci_bus {
0aa0f5d1
BH		 536 struct list_head node; /* Node in list of buses */
537 struct pci_bus *parent; /* Parent bus this bridge is on */
538 struct list_head children; /* List of child buses */
539 struct list_head devices; /* List of devices on this bus */
540 struct pci_dev *self; /* Bridge device as seen by parent */
541 struct list_head slots; /* List of slots on this bus;
67546762 542 protected by pci_slot_mutex */
2fe2abf8 543 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
0aa0f5d1
BH		 544 struct list_head resources; /* Address space routed to this bus */
545 struct resource busn_res; /* Bus numbers routed to this bus */
1da177e4 546
0aa0f5d1 547 struct pci_ops *ops; /* Configuration access functions */
c2791b80 548 struct msi_controller *msi; /* MSI controller */
0aa0f5d1
BH		 549 void *sysdata; /* Hook for sys-specific extension */
550 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
1da177e4 551
0aa0f5d1
BH		 552 unsigned char number; /* Bus number */
553 unsigned char primary; /* Number of primary bridge */
3749c51a
MW		 554 unsigned char max_bus_speed; /* enum pci_bus_speed */
555 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 556#ifdef CONFIG_PCI_DOMAINS_GENERIC
557 int domain_nr;
558#endif
1da177e4
LT		 559
560 char name[48];
561
0aa0f5d1
BH		 562 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
563 pci_bus_flags_t bus_flags; /* Inherited by child buses */
1da177e4 564 struct device *bridge;
fd7d1ced 565 struct device dev;
0aa0f5d1
BH		 566 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
567 struct bin_attribute *legacy_mem; /* Legacy mem */
cc74d96f 568 unsigned int is_added:1;
1da177e4
LT		 569};
570
fd7d1ced 571#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 572
79af72d7 573/*
f7625980 574 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 575 * false otherwise
77a0dfcd
BH		 576 *
577 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
578 * This is incorrect because "virtual" buses added for SR-IOV (via
579 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 580 */
581static inline bool pci_is_root_bus(struct pci_bus *pbus)
582{
583 return !(pbus->parent);
584}
585
1c86438c
YW		 586/**
587 * pci_is_bridge - check if the PCI device is a bridge
588 * @dev: PCI device
589 *
590 * Return true if the PCI device is bridge whether it has subordinate
591 * or not.
592 */
593static inline bool pci_is_bridge(struct pci_dev *dev)
594{
595 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
596 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
597}
598
24a0c654
AS		 599#define for_each_pci_bridge(dev, bus) \
600 list_for_each_entry(dev, &bus->devices, bus_list) \
601 if (!pci_is_bridge(dev)) {} else
602
c6bde215
BH		 603static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
604{
605 dev = pci_physfn(dev);
606 if (pci_is_root_bus(dev->bus))
607 return NULL;
608
609 return dev->bus->self;
610}
611
6675a601
MK		 612struct device *pci_get_host_bridge_device(struct pci_dev *dev);
613void pci_put_host_bridge_device(struct device *dev);
614
16cf0ebc
RW		 615#ifdef CONFIG_PCI_MSI
616static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
617{
618 return pci_dev->msi_enabled || pci_dev->msix_enabled;
619}
620#else
621static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
622#endif
623
0aa0f5d1 624/* Error values that may be returned by PCI functions */
1da177e4
LT		 625#define PCIBIOS_SUCCESSFUL 0x00
626#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
627#define PCIBIOS_BAD_VENDOR_ID 0x83
628#define PCIBIOS_DEVICE_NOT_FOUND 0x86
629#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
630#define PCIBIOS_SET_FAILED 0x88
631#define PCIBIOS_BUFFER_TOO_SMALL 0x89
632
0aa0f5d1 633/* Translate above to generic errno for passing back through non-PCI code */
a6961651
AW		 634static inline int pcibios_err_to_errno(int err)
635{
636 if (err <= PCIBIOS_SUCCESSFUL)
637 return err; /* Assume already errno */
638
639 switch (err) {
640 case PCIBIOS_FUNC_NOT_SUPPORTED:
641 return -ENOENT;
642 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 643 return -ENOTTY;
a6961651
AW		 644 case PCIBIOS_DEVICE_NOT_FOUND:
645 return -ENODEV;
646 case PCIBIOS_BAD_REGISTER_NUMBER:
647 return -EFAULT;
648 case PCIBIOS_SET_FAILED:
649 return -EIO;
650 case PCIBIOS_BUFFER_TOO_SMALL:
651 return -ENOSPC;
652 }
653
d97ffe23 654 return -ERANGE;
a6961651
AW		 655}
656
1da177e4
LT		 657/* Low-level architecture-dependent routines */
658
659struct pci_ops {
057bd2e0
TR		 660 int (*add_bus)(struct pci_bus *bus);
661 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 662 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 663 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
664 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
665};
666
b6ce068a
MW		 667/*
668 * ACPI needs to be able to access PCI config space before we've done a
669 * PCI bus scan and created pci_bus structures.
670 */
f39d5b72
BH		 671int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
672 int reg, int len, u32 *val);
673int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
674 int reg, int len, u32 val);
1da177e4 675
3a9ad0b4
YL		 676#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
677typedef u64 pci_bus_addr_t;
678#else
679typedef u32 pci_bus_addr_t;
680#endif
681
1da177e4 682struct pci_bus_region {
0aa0f5d1
BH		 683 pci_bus_addr_t start;
684 pci_bus_addr_t end;
1da177e4
LT		 685};
686
687struct pci_dynids {
0aa0f5d1
BH		 688 spinlock_t lock; /* Protects list, index */
689 struct list_head list; /* For IDs added at runtime */
1da177e4
LT		 690};
691
f7625980
BH		 692
693/*
694 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
695 * a set of callbacks in struct pci_error_handlers, that device driver
696 * will be notified of PCI bus errors, and will be driven to recovery
697 * when an error occurs.
392a1ce7 698 */
699
700typedef unsigned int __bitwise pci_ers_result_t;
701
702enum pci_ers_result {
0aa0f5d1 703 /* No result/none/not supported in device driver */
392a1ce7 704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
705
706 /* Device driver can recover without slot reset */
707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
708
0aa0f5d1 709 /* Device driver wants slot to be reset */
392a1ce7 710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
711
712 /* Device has completely failed, is unrecoverable */
713 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
714
715 /* Device driver is fully recovered and operational */
716 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 717
718 /* No AER capabilities registered for the driver */
719 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7 720};
721
722/* PCI bus error event callbacks */
05cca6e5 723struct pci_error_handlers {
392a1ce7 724 /* PCI bus error detected on this device */
725 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 726 enum pci_channel_state error);
392a1ce7 727
728 /* MMIO has been re-enabled, but not DMA */
729 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
730
392a1ce7 731 /* PCI slot has been reset */
732 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
733
3ebe7f9f 734 /* PCI function reset prepare or completed */
775755ed
CH		 735 void (*reset_prepare)(struct pci_dev *dev);
736 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 737
392a1ce7 738 /* Device driver may resume normal operations */
739 void (*resume)(struct pci_dev *dev);
740};
741
392a1ce7 742
1da177e4
LT		 743struct module;
744struct pci_driver {
0aa0f5d1
BH		 745 struct list_head node;
746 const char *name;
747 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
748 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
749 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
750 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
751 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
752 int (*resume_early)(struct pci_dev *dev);
753 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 754 void (*shutdown) (struct pci_dev *dev);
0aa0f5d1 755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
49453028 756 const struct pci_error_handlers *err_handler;
92d50fc1 757 const struct attribute_group **groups;
1da177e4 758 struct device_driver driver;
0aa0f5d1 759 struct pci_dynids dynids;
1da177e4
LT		 760};
761
05cca6e5 762#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 763
764/**
0aa0f5d1 765 * PCI_DEVICE - macro used to describe a specific PCI device
1da177e4
LT		 766 * @vend: the 16 bit PCI Vendor ID
767 * @dev: the 16 bit PCI Device ID
768 *
769 * This macro is used to create a struct pci_device_id that matches a
770 * specific device. The subvendor and subdevice fields will be set to
771 * PCI_ANY_ID.
772 */
773#define PCI_DEVICE(vend,dev) \
774 .vendor = (vend), .device = (dev), \
775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
776
3d567e0e 777/**
0aa0f5d1 778 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
3d567e0e
NNS		 779 * @vend: the 16 bit PCI Vendor ID
780 * @dev: the 16 bit PCI Device ID
781 * @subvend: the 16 bit PCI Subvendor ID
782 * @subdev: the 16 bit PCI Subdevice ID
783 *
784 * This macro is used to create a struct pci_device_id that matches a
785 * specific device with subsystem information.
786 */
787#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
788 .vendor = (vend), .device = (dev), \
789 .subvendor = (subvend), .subdevice = (subdev)
790
1da177e4 791/**
0aa0f5d1 792 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1da177e4
LT		 793 * @dev_class: the class, subclass, prog-if triple for this device
794 * @dev_class_mask: the class mask for this device
795 *
796 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 797 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 798 * fields will be set to PCI_ANY_ID.
799 */
800#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
801 .class = (dev_class), .class_mask = (dev_class_mask), \
802 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
804
1597cacb 805/**
0aa0f5d1 806 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
c1309040
MR		 807 * @vend: the vendor name
808 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 809 *
810 * This macro is used to create a struct pci_device_id that matches a
811 * specific PCI device. The subvendor, and subdevice fields will be set
812 * to PCI_ANY_ID. The macro allows the next field to follow as the device
813 * private data.
814 */
c1309040
MR		 815#define PCI_VDEVICE(vend, dev) \
816 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
817 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 818
5bbe029f 819enum {
0aa0f5d1
BH		 820 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
821 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
822 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
823 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
824 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
5bbe029f 825 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
0aa0f5d1 826 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
5bbe029f
BH		 827};
828
0aa0f5d1 829/* These external functions are only available when PCI support is enabled */
1da177e4
LT		 830#ifdef CONFIG_PCI
831
5bbe029f
BH		 832extern unsigned int pci_flags;
833
834static inline void pci_set_flags(int flags) { pci_flags = flags; }
835static inline void pci_add_flags(int flags) { pci_flags |= flags; }
836static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
837static inline int pci_has_flag(int flag) { return pci_flags & flag; }
838
a58674ff 839void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 840
841enum pcie_bus_config_types {
0aa0f5d1
BH		 842 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
843 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
844 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
845 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
846 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
b03e7495
JM		 847};
848
849extern enum pcie_bus_config_types pcie_bus_config;
850
1da177e4
LT		 851extern struct bus_type pci_bus_type;
852
f7625980
BH		 853/* Do NOT directly access these two variables, unless you are arch-specific PCI
854 * code, or PCI core code. */
0aa0f5d1 855extern struct list_head pci_root_buses; /* List of all known PCI buses */
f7625980 856/* Some device drivers need know if PCI is initiated */
f39d5b72 857int no_pci_devices(void);
1da177e4 858
3c449ed0 859void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 860void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 861void pcibios_add_bus(struct pci_bus *bus);
862void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 863void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 864int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 865/* Architecture-specific versions may override this (weak) */
05cca6e5 866char *pcibios_setup(char *str);
1da177e4
LT		 867
868/* Used only when drivers/pci/setup.c is used */
3b7a17fc 869resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 870 resource_size_t,
e31dd6e4 871 resource_size_t);
1da177e4 872
2d1c8618
BH		 873/* Weak but can be overriden by arch */
874void pci_fixup_cardbus(struct pci_bus *);
875
1da177e4
LT		 876/* Generic PCI functions used internally */
877
fc279850 878void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 879 struct resource *res);
fc279850 880void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 881 struct pci_bus_region *region);
d1fd4fb6 882void pcibios_scan_specific_bus(int busn);
f39d5b72 883struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 884void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 885struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 886struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
887 struct pci_ops *ops, void *sysdata,
888 struct list_head *resources);
49b8e3f3 889int pci_host_probe(struct pci_host_bridge *bridge);
98a35831
YL		 890int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
891int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
892void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 893struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
0aa0f5d1
BH		 894 struct pci_ops *ops, void *sysdata,
895 struct list_head *resources);
1228c4b6 896int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 897struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
898 int busnr);
3749c51a 899void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 900struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 901 const char *name,
902 struct hotplug_slot *hotplug);
f46753c5 903void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 904#ifdef CONFIG_SYSFS
905void pci_dev_assign_slot(struct pci_dev *dev);
906#else
907static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
908#endif
1da177e4 909int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 910struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 911void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 912unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 913void pci_bus_add_device(struct pci_dev *dev);
1da177e4 914void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 915struct resource *pci_find_parent_resource(const struct pci_dev *dev,
916 struct resource *res);
c56d4450 917struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 918u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 919int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 920u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 921struct pci_dev *pci_dev_get(struct pci_dev *dev);
922void pci_dev_put(struct pci_dev *dev);
923void pci_remove_bus(struct pci_bus *b);
924void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 925void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 926void pci_stop_root_bus(struct pci_bus *bus);
927void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 928void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 929void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 930void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 931#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
932#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 933
934/* Generic PCI functions exported to card drivers */
935
388c8c16
JB		 936enum pci_lost_interrupt_reason {
937 PCI_LOST_IRQ_NO_INFORMATION = 0,
938 PCI_LOST_IRQ_DISABLE_MSI,
939 PCI_LOST_IRQ_DISABLE_MSIX,
940 PCI_LOST_IRQ_DISABLE_ACPI,
941};
942enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 943int pci_find_capability(struct pci_dev *dev, int cap);
944int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
945int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 946int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 947int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
948int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 949struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 950
d42552c3 951struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
0aa0f5d1 952 struct pci_dev *from);
05cca6e5 953struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
0aa0f5d1
BH		 954 unsigned int ss_vendor, unsigned int ss_device,
955 struct pci_dev *from);
05cca6e5 956struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 957struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
958 unsigned int devfn);
05cca6e5 959struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 960int pci_dev_present(const struct pci_device_id *ids);
961
05cca6e5
GKH		 962int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
963 int where, u8 *val);
964int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
965 int where, u16 *val);
966int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
967 int where, u32 *val);
968int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
969 int where, u8 val);
970int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
971 int where, u16 val);
972int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
973 int where, u32 val);
1f94a94f
RH		 974
975int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
976 int where, int size, u32 *val);
977int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
978 int where, int size, u32 val);
979int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
980 int where, int size, u32 *val);
981int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
982 int where, int size, u32 val);
983
a72b46c3 984struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 985
d3881e50
KB		 986int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
987int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
988int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
989int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
990int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
991int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 992
8c0d3a02
JL		 993int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
994int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
995int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
996int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
997int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
998 u16 clear, u16 set);
999int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1000 u32 clear, u32 set);
1001
1002static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1003 u16 set)
1004{
1005 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1006}
1007
1008static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1009 u32 set)
1010{
1011 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1012}
1013
1014static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1015 u16 clear)
1016{
1017 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1018}
1019
1020static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1021 u32 clear)
1022{
1023 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1024}
1025
0aa0f5d1 1026/* User-space driven config access */
c63587d7
AW		 1027int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1028int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1029int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1030int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1031int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1032int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1033
4a7fb636 1034int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1035int __must_check pci_enable_device_io(struct pci_dev *dev);
1036int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1037int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1038int __must_check pcim_enable_device(struct pci_dev *pdev);
1039void pcim_pin_device(struct pci_dev *pdev);
1040
99b3c58f
PG		 1041static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1042{
1043 /*
1044 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1045 * writable and no quirk has marked the feature broken.
1046 */
1047 return !pdev->broken_intx_masking;
1048}
1049
296ccb08
YS		 1050static inline int pci_is_enabled(struct pci_dev *pdev)
1051{
1052 return (atomic_read(&pdev->enable_cnt) > 0);
1053}
1054
9ac7849e
TH		 1055static inline int pci_is_managed(struct pci_dev *pdev)
1056{
1057 return pdev->is_managed;
1058}
1059
1da177e4 1060void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1061
1062extern unsigned int pcibios_max_latency;
1da177e4 1063void pci_set_master(struct pci_dev *dev);
6a479079 1064void pci_clear_master(struct pci_dev *dev);
96c55900 1065
f7bdd12d 1066int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1067int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1068#define HAVE_PCI_SET_MWI
4a7fb636 1069int __must_check pci_set_mwi(struct pci_dev *dev);
fc0f9f4d 1070int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1071int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1072void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1073void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1074bool pci_check_and_mask_intx(struct pci_dev *dev);
1075bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1076int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1077int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1078int pcix_get_max_mmrbc(struct pci_dev *dev);
1079int pcix_get_mmrbc(struct pci_dev *dev);
1080int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1081int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1082int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1083int pcie_get_mps(struct pci_dev *dev);
1084int pcie_set_mps(struct pci_dev *dev, int mps);
81377c8d
JK		 1085int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1086 enum pcie_link_width *width);
6db79a88
TG		 1087u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1088 enum pci_bus_speed *speed,
1089 enum pcie_link_width *width);
9e506a7b 1090void pcie_print_link_status(struct pci_dev *dev);
91295d79 1091int pcie_flr(struct pci_dev *dev);
a96d627a 1092int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1093int pci_reset_function(struct pci_dev *dev);
a477b9cd 1094int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1095int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1096int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1097int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1098int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1099int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1100int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1101int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1102void pci_reset_secondary_bus(struct pci_dev *dev);
1103void pcibios_reset_secondary_bus(struct pci_dev *dev);
01fd61c0 1104int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1105void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1106int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1107int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1108void pci_release_resource(struct pci_dev *dev, int resno);
1109int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1110int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1111bool pci_device_is_present(struct pci_dev *pdev);
08249651 1112void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1113
704e8953
CH		 1114int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1116 const char *fmt, ...);
1117void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1118
1da177e4 1119/* ROM control related routines */
e416de5e
AC		 1120int pci_enable_rom(struct pci_dev *pdev);
1121void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1122void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1123void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1124size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1125void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1126
1127/* Power management related routines */
1128int pci_save_state(struct pci_dev *dev);
1d3c16a8 1129void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1130struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1131int pci_load_saved_state(struct pci_dev *dev,
1132 struct pci_saved_state *state);
ffbdd3f7
AW		 1133int pci_load_and_free_saved_state(struct pci_dev *dev,
1134 struct pci_saved_state **state);
fd0f7f73
AW		 1135struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1136struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1137 u16 cap);
1138int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1139int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1140 u16 cap, unsigned int size);
0e5dd46b 1141int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1142int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1143pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1144bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1145void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1146int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1147int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1148int pci_prepare_to_sleep(struct pci_dev *dev);
1149int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1150bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1151bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1152void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1153void pci_d3cold_enable(struct pci_dev *dev);
1154void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1155bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
2a4d2c42
LW		 1156void pci_wakeup_bus(struct pci_bus *bus);
1157void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1da177e4 1158
425c1b22
AW		 1159/* PCI Virtual Channel */
1160int pci_save_vc_state(struct pci_dev *dev);
1161void pci_restore_vc_state(struct pci_dev *dev);
1162void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1163
bb209c82
BH		 1164/* For use by arch with custom probe code */
1165void set_pcie_port_type(struct pci_dev *pdev);
1166void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1167
ce5ccdef 1168/* Functions for PCI Hotplug drivers to use */
05cca6e5 1169int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1170unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1171unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1172void pci_lock_rescan_remove(void);
1173void pci_unlock_rescan_remove(void);
ce5ccdef 1174
0aa0f5d1 1175/* Vital Product Data routines */
287d19ce
SH		 1176ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1177ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1178int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1179
1da177e4 1180/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1181resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1182void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1183void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1184void pci_bus_size_bridges(struct pci_bus *bus);
1185int pci_claim_resource(struct pci_dev *, int);
8505e729 1186int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1187void pci_assign_unassigned_resources(void);
6841ec68 1188void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1189void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1190void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1191int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1192void pdev_enable_device(struct pci_dev *);
842de40d 1193int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1194void pci_assign_irq(struct pci_dev *dev);
afd29f90 1195struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1196#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1197int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1198int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1199void pci_release_regions(struct pci_dev *);
4a7fb636 1200int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1201int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1202void pci_release_region(struct pci_dev *, int);
c87deff7 1203int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1204int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1205void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1206
1207/* drivers/pci/bus.c */
fe830ef6
JL		 1208struct pci_bus *pci_bus_get(struct pci_bus *bus);
1209void pci_bus_put(struct pci_bus *bus);
45ca9e97 1210void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1211void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1212 resource_size_t offset);
45ca9e97 1213void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1214void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1215 unsigned int flags);
2fe2abf8
BH		 1216struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1217void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1218int devm_request_pci_bus_resources(struct device *dev,
1219 struct list_head *resources);
2fe2abf8 1220
89a74ecc 1221#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1222 for (i = 0; \
1223 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1224 i++)
89a74ecc 1225
4a7fb636
AM		 1226int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1227 struct resource *res, resource_size_t size,
1228 resource_size_t align, resource_size_t min,
664c2848 1229 unsigned long type_mask,
3b7a17fc
DB		 1230 resource_size_t (*alignf)(void *,
1231 const struct resource *,
b26b2d49
DB		 1232 resource_size_t,
1233 resource_size_t),
4a7fb636 1234 void *alignf_data);
1da177e4 1235
8b921acf 1236
fcfaab30
GP		 1237int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1238 resource_size_t size);
c5076cfe
TN		 1239unsigned long pci_address_to_pio(phys_addr_t addr);
1240phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1241int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
4d3f1384 1242void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1243void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1244 resource_size_t offset,
1245 resource_size_t size);
1246void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1247 struct resource *res);
8b921acf 1248
3a9ad0b4 1249static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1250{
1251 struct pci_bus_region region;
1252
1253 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1254 return region.start;
1255}
1256
863b18f4 1257/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1258int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1259 const char *mod_name);
bba81165 1260
0aa0f5d1 1261/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
bba81165
AM		 1262#define pci_register_driver(driver) \
1263 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1264
05cca6e5 1265void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1266
1267/**
1268 * module_pci_driver() - Helper macro for registering a PCI driver
1269 * @__pci_driver: pci_driver struct
1270 *
1271 * Helper macro for PCI drivers which do not do anything special in module
1272 * init/exit. This eliminates a lot of boilerplate. Each module may only
1273 * use this macro once, and calling it replaces module_init() and module_exit()
1274 */
1275#define module_pci_driver(__pci_driver) \
0aa0f5d1 1276 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
aad4f400 1277
b4eb6cdb
PG		 1278/**
1279 * builtin_pci_driver() - Helper macro for registering a PCI driver
1280 * @__pci_driver: pci_driver struct
1281 *
1282 * Helper macro for PCI drivers which do not do anything special in their
1283 * init code. This eliminates a lot of boilerplate. Each driver may only
1284 * use this macro once, and calling it replaces device_initcall(...)
1285 */
1286#define builtin_pci_driver(__pci_driver) \
1287 builtin_driver(__pci_driver, pci_register_driver)
1288
05cca6e5 1289struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1290int pci_add_dynid(struct pci_driver *drv,
1291 unsigned int vendor, unsigned int device,
1292 unsigned int subvendor, unsigned int subdevice,
1293 unsigned int class, unsigned int class_mask,
1294 unsigned long driver_data);
05cca6e5
GKH		 1295const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1296 struct pci_dev *dev);
1297int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1298 int pass);
1da177e4 1299
70298c6e 1300void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1301 void *userdata);
ac7dc65a 1302int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1303unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1304void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1305resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1306 unsigned long type);
cecf4864 1307
3448a19d
DA		 1308#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1309#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1310
deb2d2ec 1311int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1312 unsigned int command_bits, u32 flags);
fe537670 1313
0aa0f5d1
BH		 1314#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1315#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1316#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1317#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
4fe0d154
CH		 1318#define PCI_IRQ_ALL_TYPES \
1319 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1320
1da177e4
LT		 1321/* kmem_cache style wrapper around pci_alloc_consistent() */
1322
f41b1771 1323#include <linux/pci-dma.h>
1da177e4
LT		 1324#include <linux/dmapool.h>
1325
1326#define pci_pool dma_pool
1327#define pci_pool_create(name, pdev, size, align, allocation) \
1328 dma_pool_create(name, &pdev->dev, size, align, allocation)
1329#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1330#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1331#define pci_pool_zalloc(pool, flags, handle) \
1332 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1333#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1334
1da177e4 1335struct msix_entry {
0aa0f5d1
BH		 1336 u32 vector; /* Kernel uses to write allocated vector */
1337 u16 entry; /* Driver uses to specify entry, OS writes */
1da177e4
LT		 1338};
1339
4c859804
BH		 1340#ifdef CONFIG_PCI_MSI
1341int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1342void pci_disable_msi(struct pci_dev *dev);
4c859804 1343int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1344void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1345void pci_restore_msi_state(struct pci_dev *dev);
1346int pci_msi_enabled(void);
4fe03955 1347int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1348int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1349 int minvec, int maxvec);
f7fc32cb
AG		 1350static inline int pci_enable_msix_exact(struct pci_dev *dev,
1351 struct msix_entry *entries, int nvec)
1352{
1353 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1354 if (rc < 0)
1355 return rc;
1356 return 0;
1357}
402723ad
CH		 1358int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1359 unsigned int max_vecs, unsigned int flags,
1360 const struct irq_affinity *affd);
1361
aff17164
CH		 1362void pci_free_irq_vectors(struct pci_dev *dev);
1363int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1364const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1365int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1366
4c859804 1367#else
2ee546c4 1368static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1369static inline void pci_disable_msi(struct pci_dev *dev) { }
1370static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1371static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1372static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1373static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1374static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1375{ return -ENOSYS; }
302a2523 1376static inline int pci_enable_msix_range(struct pci_dev *dev,
0aa0f5d1 1377 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1378{ return -ENOSYS; }
f7fc32cb 1379static inline int pci_enable_msix_exact(struct pci_dev *dev,
0aa0f5d1 1380 struct msix_entry *entries, int nvec)
f7fc32cb 1381{ return -ENOSYS; }
402723ad
CH		 1382
1383static inline int
1384pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1385 unsigned int max_vecs, unsigned int flags,
1386 const struct irq_affinity *aff_desc)
aff17164 1387{
83b4605b
CH		 1388 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1389 return 1;
1390 return -ENOSPC;
aff17164 1391}
402723ad 1392
aff17164
CH		 1393static inline void pci_free_irq_vectors(struct pci_dev *dev)
1394{
1395}
1396
1397static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1398{
1399 if (WARN_ON_ONCE(nr > 0))
1400 return -EINVAL;
1401 return dev->irq;
1402}
ee8d41e5
TG		 1403static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1404 int vec)
1405{
1406 return cpu_possible_mask;
1407}
27ddb689
SL		 1408
1409static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1410{
1411 return first_online_node;
1412}
1da177e4
LT		 1413#endif
1414
402723ad
CH		 1415static inline int
1416pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1417 unsigned int max_vecs, unsigned int flags)
1418{
1419 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1420 NULL);
1421}
1422
0d58e6c1
PB		 1423/**
1424 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1425 * @d: the INTx IRQ domain
1426 * @node: the DT node for the device whose interrupt we're translating
1427 * @intspec: the interrupt specifier data from the DT
1428 * @intsize: the number of entries in @intspec
1429 * @out_hwirq: pointer at which to write the hwirq number
1430 * @out_type: pointer at which to write the interrupt type
1431 *
1432 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1433 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1434 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1435 * INTx value to obtain the hwirq number.
1436 *
1437 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1438 */
1439static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1440 struct device_node *node,
1441 const u32 *intspec,
1442 unsigned int intsize,
1443 unsigned long *out_hwirq,
1444 unsigned int *out_type)
1445{
1446 const u32 intx = intspec[0];
1447
1448 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1449 return -EINVAL;
1450
1451 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1452 return 0;
1453}
1454
ab0724ff 1455#ifdef CONFIG_PCIEPORTBUS
415e12b2 1456extern bool pcie_ports_disabled;
ab0724ff
MT		 1457#else
1458#define pcie_ports_disabled true
ab0724ff 1459#endif
415e12b2 1460
4c859804 1461#ifdef CONFIG_PCIEASPM
f39d5b72 1462bool pcie_aspm_support_enabled(void);
4c859804
BH		 1463#else
1464static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1465#endif
1466
415e12b2
RW		 1467#ifdef CONFIG_PCIEAER
1468void pci_no_aer(void);
1469bool pci_aer_available(void);
66b80809 1470int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1471#else
1472static inline void pci_no_aer(void) { }
1473static inline bool pci_aer_available(void) { return false; }
66b80809 1474static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1475#endif
1476
4c859804 1477#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1478void pcie_set_ecrc_checking(struct pci_dev *dev);
1479void pcie_ecrc_get_policy(char *str);
4c859804 1480#else
2ee546c4
BH		 1481static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1482static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1483#endif
1484
edc90fee
BH		 1485#ifdef CONFIG_PCI_ATS
1486/* Address Translation Service */
1487void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1488int pci_enable_ats(struct pci_dev *dev, int ps);
1489void pci_disable_ats(struct pci_dev *dev);
1490int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1491#else
ff9bee89
BH		 1492static inline void pci_ats_init(struct pci_dev *d) { }
1493static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1494static inline void pci_disable_ats(struct pci_dev *d) { }
1495static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1496#endif
1497
eec097d4
BH		 1498#ifdef CONFIG_PCIE_PTM
1499int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1500#else
1501static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1502{ return -EINVAL; }
1503#endif
1504
f39d5b72
BH		 1505void pci_cfg_access_lock(struct pci_dev *dev);
1506bool pci_cfg_access_trylock(struct pci_dev *dev);
1507void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1508
4352dfd5
GKH		 1509/*
1510 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1511 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1512 * configuration space.
1513 */
32a2eea7
JG		 1514#ifdef CONFIG_PCI_DOMAINS
1515extern int pci_domains_supported;
41e5c0f8 1516int pci_get_new_domain_nr(void);
32a2eea7
JG		 1517#else
1518enum { pci_domains_supported = 0 };
2ee546c4
BH		 1519static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1520static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
41e5c0f8 1521static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
32a2eea7 1522#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1523
670ba0c8
CM		 1524/*
1525 * Generic implementation for PCI domain support. If your
1526 * architecture does not need custom management of PCI
1527 * domains then this implementation will be used
1528 */
1529#ifdef CONFIG_PCI_DOMAINS_GENERIC
1530static inline int pci_domain_nr(struct pci_bus *bus)
1531{
1532 return bus->domain_nr;
1533}
2ab51dde
TN		 1534#ifdef CONFIG_ACPI
1535int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1536#else
2ab51dde
TN		 1537static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1538{ return 0; }
1539#endif
9c7cb891 1540int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1541#endif
1542
0aa0f5d1 1543/* Some architectures require additional setup to direct VGA traffic */
95a8b6ef 1544typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
0aa0f5d1 1545 unsigned int command_bits, u32 flags);
f39d5b72 1546void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1547
be9d2e89
JT		 1548static inline int
1549pci_request_io_regions(struct pci_dev *pdev, const char *name)
1550{
1551 return pci_request_selected_regions(pdev,
1552 pci_select_bars(pdev, IORESOURCE_IO), name);
1553}
1554
1555static inline void
1556pci_release_io_regions(struct pci_dev *pdev)
1557{
1558 return pci_release_selected_regions(pdev,
1559 pci_select_bars(pdev, IORESOURCE_IO));
1560}
1561
1562static inline int
1563pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1564{
1565 return pci_request_selected_regions(pdev,
1566 pci_select_bars(pdev, IORESOURCE_MEM), name);
1567}
1568
1569static inline void
1570pci_release_mem_regions(struct pci_dev *pdev)
1571{
1572 return pci_release_selected_regions(pdev,
1573 pci_select_bars(pdev, IORESOURCE_MEM));
1574}
1575
4352dfd5 1576#else /* CONFIG_PCI is not enabled */
1da177e4 1577
5bbe029f
BH		 1578static inline void pci_set_flags(int flags) { }
1579static inline void pci_add_flags(int flags) { }
1580static inline void pci_clear_flags(int flags) { }
1581static inline int pci_has_flag(int flag) { return 0; }
1582
1da177e4 1583/*
0aa0f5d1
BH		 1584 * If the system does not have PCI, clearly these return errors. Define
1585 * these as simple inline functions to avoid hair in drivers.
1da177e4 1586 */
05cca6e5
GKH		 1587#define _PCI_NOP(o, s, t) \
1588 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1589 int where, t val) \
1da177e4 1590 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1591
1592#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1593 _PCI_NOP(o, word, u16 x) \
1594 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1595_PCI_NOP_ALL(read, *)
1596_PCI_NOP_ALL(write,)
1597
d42552c3 1598static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1599 unsigned int device,
1600 struct pci_dev *from)
2ee546c4 1601{ return NULL; }
d42552c3 1602
05cca6e5
GKH		 1603static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1604 unsigned int device,
1605 unsigned int ss_vendor,
1606 unsigned int ss_device,
b08508c4 1607 struct pci_dev *from)
2ee546c4 1608{ return NULL; }
1da177e4 1609
05cca6e5
GKH		 1610static inline struct pci_dev *pci_get_class(unsigned int class,
1611 struct pci_dev *from)
2ee546c4 1612{ return NULL; }
1da177e4
LT		 1613
1614#define pci_dev_present(ids) (0)
ed4aaadb 1615#define no_pci_devices() (1)
1da177e4
LT		 1616#define pci_dev_put(dev) do { } while (0)
1617
2ee546c4
BH		 1618static inline void pci_set_master(struct pci_dev *dev) { }
1619static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1620static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1621static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1622{ return -EBUSY; }
05cca6e5
GKH		 1623static inline int __pci_register_driver(struct pci_driver *drv,
1624 struct module *owner)
2ee546c4 1625{ return 0; }
05cca6e5 1626static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1627{ return 0; }
1628static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1629static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1630{ return 0; }
05cca6e5
GKH		 1631static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1632 int cap)
2ee546c4 1633{ return 0; }
05cca6e5 1634static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1635{ return 0; }
05cca6e5 1636
1da177e4 1637/* Power management related routines */
2ee546c4
BH		 1638static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1639static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1640static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1641{ return 0; }
3449248c 1642static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1643{ return 0; }
05cca6e5
GKH		 1644static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1645 pm_message_t state)
2ee546c4 1646{ return PCI_D0; }
05cca6e5
GKH		 1647static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1648 int enable)
2ee546c4 1649{ return 0; }
48a92a81 1650
afd29f90
MW		 1651static inline struct resource *pci_find_resource(struct pci_dev *dev,
1652 struct resource *res)
1653{ return NULL; }
05cca6e5 1654static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1655{ return -EIO; }
1656static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1657
c5076cfe
TN		 1658static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1659
2ee546c4 1660static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1661static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1662{ return 0; }
2ee546c4 1663static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1664
d80d0217
RD		 1665static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1666{ return NULL; }
d80d0217
RD		 1667static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1668 unsigned int devfn)
1669{ return NULL; }
7912af5c
RD		 1670static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1671 unsigned int bus, unsigned int devfn)
1672{ return NULL; }
d80d0217 1673
2ee546c4
BH		 1674static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1675static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
41e5c0f8 1676static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
12ea6cad 1677
fb8a0d9d
WM		 1678#define dev_is_pci(d) (false)
1679#define dev_is_pf(d) (false)
fe594932
GU		 1680static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1681{ return false; }
80db6f08
NC		 1682static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1683 struct device_node *node,
1684 const u32 *intspec,
1685 unsigned int intsize,
1686 unsigned long *out_hwirq,
1687 unsigned int *out_type)
1688{ return -EINVAL; }
4352dfd5 1689#endif /* CONFIG_PCI */
1da177e4 1690
4352dfd5
GKH		 1691/* Include architecture-dependent settings and functions */
1692
1693#include <asm/pci.h>
1da177e4 1694
f7195824
DW		 1695/* These two functions provide almost identical functionality. Depennding
1696 * on the architecture, one will be implemented as a wrapper around the
1697 * other (in drivers/pci/mmap.c).
1698 *
1699 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1700 * is expected to be an offset within that region.
1701 *
1702 * pci_mmap_page_range() is the legacy architecture-specific interface,
1703 * which accepts a "user visible" resource address converted by
1704 * pci_resource_to_user(), as used in the legacy mmap() interface in
1705 * /proc/bus/pci/.
1706 */
1707int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1708 struct vm_area_struct *vma,
1709 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1710int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1711 struct vm_area_struct *vma,
11df1954
DW		 1712 enum pci_mmap_state mmap_state, int write_combine);
1713
ae749c7a
DW		 1714#ifndef arch_can_pci_mmap_wc
1715#define arch_can_pci_mmap_wc() 0
1716#endif
2bea36fd 1717
e854d8b2
DW		 1718#ifndef arch_can_pci_mmap_io
1719#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1720#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1721#else
1722int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1723#endif
ae749c7a 1724
92016ba5
JO		 1725#ifndef pci_root_bus_fwnode
1726#define pci_root_bus_fwnode(bus) NULL
1727#endif
1728
0aa0f5d1
BH		 1729/*
1730 * These helpers provide future and backwards compatibility
1731 * for accessing popular PCI BAR info
1732 */
05cca6e5
GKH		 1733#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1734#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1735#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1736#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1737 ((pci_resource_start((dev), (bar)) == 0 && \
1738 pci_resource_end((dev), (bar)) == \
1739 pci_resource_start((dev), (bar))) ? 0 : \
1740 \
1741 (pci_resource_end((dev), (bar)) - \
1742 pci_resource_start((dev), (bar)) + 1))
1da177e4 1743
0aa0f5d1
BH		 1744/*
1745 * Similar to the helpers above, these manipulate per-pci_dev
1da177e4
LT		 1746 * driver-specific data. They are really just a wrapper around
1747 * the generic device structure functions of these calls.
1748 */
05cca6e5 1749static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1750{
1751 return dev_get_drvdata(&pdev->dev);
1752}
1753
05cca6e5 1754static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1755{
1756 dev_set_drvdata(&pdev->dev, data);
1757}
1758
2fc90f61 1759static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1760{
c6c4f070 1761 return dev_name(&pdev->dev);
1da177e4
LT		 1762}
1763
2311b1f2 1764
0aa0f5d1
BH		 1765/*
1766 * Some archs don't want to expose struct resource to userland as-is
2311b1f2
ME		 1767 * in sysfs and /proc
1768 */
8221a013
BH		 1769#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1770void pci_resource_to_user(const struct pci_dev *dev, int bar,
1771 const struct resource *rsrc,
1772 resource_size_t *start, resource_size_t *end);
1773#else
2311b1f2 1774static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1775 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1776 resource_size_t *end)
2311b1f2
ME		 1777{
1778 *start = rsrc->start;
1779 *end = rsrc->end;
1780}
1781#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1782
1783
1da177e4 1784/*
0aa0f5d1
BH		 1785 * The world is not perfect and supplies us with broken PCI devices.
1786 * For at least a part of these bugs we need a work-around, so both
1787 * generic (drivers/pci/quirks.c) and per-architecture code can define
1788 * fixup hooks to be called for particular buggy devices.
1da177e4
LT		 1789 */
1790
1791struct pci_fixup {
0aa0f5d1
BH		 1792 u16 vendor; /* Or PCI_ANY_ID */
1793 u16 device; /* Or PCI_ANY_ID */
1794 u32 class; /* Or PCI_ANY_ID */
f4ca5c6a 1795 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1796 void (*hook)(struct pci_dev *dev);
1797};
1798
1799enum pci_fixup_pass {
1800 pci_fixup_early, /* Before probing BARs */
1801 pci_fixup_header, /* After reading configuration header */
1802 pci_fixup_final, /* Final phase of device fixups */
1803 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1804 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1805 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1806 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1807 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1808};
1809
1810/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1811#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1812 class_shift, hook) \
ecf61c78 1813 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1814 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1815 = { vendor, device, class, class_shift, hook };
1816
1817#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1818 class_shift, hook) \
1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1820 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1821#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1822 class_shift, hook) \
1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1824 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1825#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1826 class_shift, hook) \
1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1828 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1829#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1830 class_shift, hook) \
1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1832 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1833#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1834 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1836 resume##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1837#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1838 class_shift, hook) \
1839 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1840 resume_early##hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1841#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1842 class_shift, hook) \
1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1844 suspend##hook, vendor, device, class, class_shift, hook)
7d2a01b8
AN		 1845#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1846 class_shift, hook) \
1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1848 suspend_late##hook, vendor, device, class, class_shift, hook)
f4ca5c6a 1849
1da177e4
LT		 1850#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1852 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1853#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1854 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1855 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1856#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1858 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1859#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1861 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1862#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
0aa0f5d1 1864 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1865#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
0aa0f5d1 1867 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1868#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
0aa0f5d1 1870 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1871#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
0aa0f5d1 1873 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4 1874
93177a74 1875#ifdef CONFIG_PCI_QUIRKS
1da177e4 1876void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1877int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1878int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1879#else
1880static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1881 struct pci_dev *dev) { }
ad805758
AW		 1882static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1883 u16 acs_flags)
1884{
1885 return -ENOTTY;
1886}
c1d61c9b
AW		 1887static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1888{
1889 return -ENOTTY;
1890}
93177a74 1891#endif
1da177e4 1892
05cca6e5 1893void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1894void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1895void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1896int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1897int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1898 const char *name);
fb7ebfe4 1899void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1900
1da177e4 1901extern int pci_pci_problems;
236561e5 1902#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1903#define PCIPCI_TRITON 2
1904#define PCIPCI_NATOMA 4
1905#define PCIPCI_VIAETBF 8
1906#define PCIPCI_VSFX 16
236561e5
AC		 1907#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1908#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1909
4516a618
AN		 1910extern unsigned long pci_cardbus_io_size;
1911extern unsigned long pci_cardbus_mem_size;
15856ad5 1912extern u8 pci_dfl_cache_line_size;
ac1aa47b 1913extern u8 pci_cache_line_size;
4516a618 1914
28760489
EB		 1915extern unsigned long pci_hotplug_io_size;
1916extern unsigned long pci_hotplug_mem_size;
e16b4660 1917extern unsigned long pci_hotplug_bus_size;
28760489 1918
f7625980 1919/* Architecture-specific versions may override these (weak) */
19792a08 1920void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1921void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1922int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1923 enum pcie_reset_state state);
eca0d467 1924int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1925void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1926void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1927int pcibios_alloc_irq(struct pci_dev *dev);
1928void pcibios_free_irq(struct pci_dev *dev);
619e6f34 1929resource_size_t pcibios_default_alignment(void);
575e3348 1930
699c1985
SO		 1931#ifdef CONFIG_HIBERNATE_CALLBACKS
1932extern struct dev_pm_ops pcibios_pm_ops;
1933#endif
1934
935c760e 1935#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1936void __init pci_mmcfg_early_init(void);
1937void __init pci_mmcfg_late_init(void);
7752d5cf 1938#else
bb63b421 1939static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1940static inline void pci_mmcfg_late_init(void) { }
1941#endif
1942
642c92da 1943int pci_ext_cfg_avail(void);
0ef5f8f6 1944
1684f5dd 1945void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1946void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1947
dd7cc44d 1948#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1949int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1950int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1951
f39d5b72
BH		 1952int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1953void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 1954int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1955void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 1956int pci_num_vf(struct pci_dev *dev);
5a8eb242 1957int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1958int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1959int pci_sriov_get_totalvfs(struct pci_dev *dev);
0e6c9122 1960resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
608c0d88 1961void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
619e6f34
MM		 1962
1963/* Arch may override these (weak) */
1964int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1965int pcibios_sriov_disable(struct pci_dev *pdev);
1966resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
dd7cc44d 1967#else
b07579c0
WY		 1968static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1969{
1970 return -ENOSYS;
1971}
1972static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1973{
1974 return -ENOSYS;
1975}
dd7cc44d 1976static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1977{ return -ENODEV; }
753f6124 1978static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 1979{
1980 return -ENOSYS;
1981}
1982static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 1983 int id) { }
2ee546c4 1984static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1985static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1986static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1987{ return 0; }
bff73156 1988static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1989{ return 0; }
bff73156 1990static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1991{ return 0; }
0e6c9122
WY		 1992static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1993{ return 0; }
608c0d88 1994static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
dd7cc44d
YZ		 1995#endif
1996
c825bc94 1997#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1998void pci_hp_create_module_link(struct pci_slot *pci_slot);
1999void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2000#endif
2001
d7b7e605
KK		 2002/**
2003 * pci_pcie_cap - get the saved PCIe capability offset
2004 * @dev: PCI device
2005 *
2006 * PCIe capability offset is calculated at PCI device initialization
2007 * time and saved in the data structure. This function returns saved
2008 * PCIe capability offset. Using this instead of pci_find_capability()
2009 * reduces unnecessary search in the PCI configuration space. If you
2010 * need to calculate PCIe capability offset from raw device for some
2011 * reasons, please use pci_find_capability() instead.
2012 */
2013static inline int pci_pcie_cap(struct pci_dev *dev)
2014{
2015 return dev->pcie_cap;
2016}
2017
7eb776c4
KK		 2018/**
2019 * pci_is_pcie - check if the PCI device is PCI Express capable
2020 * @dev: PCI device
2021 *
a895c28a 2022 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2023 */
2024static inline bool pci_is_pcie(struct pci_dev *dev)
2025{
a895c28a 2026 return pci_pcie_cap(dev);
7eb776c4
KK		 2027}
2028
7c9c003c
MS		 2029/**
2030 * pcie_caps_reg - get the PCIe Capabilities Register
2031 * @dev: PCI device
2032 */
2033static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2034{
2035 return dev->pcie_flags_reg;
2036}
2037
786e2288
YW		 2038/**
2039 * pci_pcie_type - get the PCIe device/port type
2040 * @dev: PCI device
2041 */
2042static inline int pci_pcie_type(const struct pci_dev *dev)
2043{
1c531d82 2044 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2045}
2046
e784930b
JT		 2047static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2048{
2049 while (1) {
2050 if (!pci_is_pcie(dev))
2051 break;
2052 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2053 return dev;
2054 if (!dev->bus->self)
2055 break;
2056 dev = dev->bus->self;
2057 }
2058 return NULL;
2059}
2060
5d990b62 2061void pci_request_acs(void);
ad805758
AW		 2062bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2063bool pci_acs_path_enabled(struct pci_dev *start,
2064 struct pci_dev *end, u16 acs_flags);
430a2368 2065int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
a2ce7662 2066
7ad506fa 2067#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2068#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2069
2070/* Large Resource Data Type Tag Item Names */
2071#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2072#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2073#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2074
2075#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2076#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2077#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2078
2079/* Small Resource Data Type Tag Item Names */
9eb45d5c 2080#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2081
9eb45d5c 2082#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2083
2084#define PCI_VPD_SRDT_TIN_MASK 0x78
2085#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2086#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2087
2088#define PCI_VPD_LRDT_TAG_SIZE 3
2089#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2090
e1d5bdab
MC		 2091#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2092
4067a854
MC		 2093#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2094#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2095#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2096#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2097
a2ce7662
MC		 2098/**
2099 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2100 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2101 *
2102 * Returns the extracted Large Resource Data Type length.
2103 */
2104static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2105{
2106 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2107}
2108
9eb45d5c
HR		 2109/**
2110 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2111 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2112 *
2113 * Returns the extracted Large Resource Data Type Tag item.
2114 */
2115static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2116{
0aa0f5d1 2117 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
9eb45d5c
HR		 2118}
2119
7ad506fa
MC		 2120/**
2121 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2122 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2123 *
2124 * Returns the extracted Small Resource Data Type length.
2125 */
2126static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2127{
2128 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2129}
2130
9eb45d5c
HR		 2131/**
2132 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2133 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2134 *
2135 * Returns the extracted Small Resource Data Type Tag Item.
2136 */
2137static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2138{
2139 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2140}
2141
e1d5bdab
MC		 2142/**
2143 * pci_vpd_info_field_size - Extracts the information field length
2144 * @lrdt: Pointer to the beginning of an information field header
2145 *
2146 * Returns the extracted information field length.
2147 */
2148static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2149{
2150 return info_field[2];
2151}
2152
b55ac1b2
MC		 2153/**
2154 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2155 * @buf: Pointer to buffered vpd data
2156 * @off: The offset into the buffer at which to begin the search
2157 * @len: The length of the vpd buffer
2158 * @rdt: The Resource Data Type to search for
2159 *
2160 * Returns the index where the Resource Data Type was found or
2161 * -ENOENT otherwise.
2162 */
2163int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2164
4067a854
MC		 2165/**
2166 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2167 * @buf: Pointer to buffered vpd data
2168 * @off: The offset into the buffer at which to begin the search
2169 * @len: The length of the buffer area, relative to off, in which to search
2170 * @kw: The keyword to search for
2171 *
2172 * Returns the index where the information field keyword was found or
2173 * -ENOENT otherwise.
2174 */
2175int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2176 unsigned int len, const char *kw);
2177
98d9f30c
BH		 2178/* PCI <-> OF binding helpers */
2179#ifdef CONFIG_OF
2180struct device_node;
b165e2b6 2181struct irq_domain;
f39d5b72
BH		 2182void pci_set_of_node(struct pci_dev *dev);
2183void pci_release_of_node(struct pci_dev *dev);
2184void pci_set_bus_of_node(struct pci_bus *bus);
2185void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2186struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
3a8f77e4
CP		 2187int pci_parse_request_of_pci_ranges(struct device *dev,
2188 struct list_head *resources,
2189 struct resource **bus_range);
98d9f30c
BH		 2190
2191/* Arch may override this (weak) */
723ec4d0 2192struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2193
0aa0f5d1 2194#else /* CONFIG_OF */
98d9f30c
BH		 2195static inline void pci_set_of_node(struct pci_dev *dev) { }
2196static inline void pci_release_of_node(struct pci_dev *dev) { }
2197static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2198static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
b165e2b6
MZ		 2199static inline struct irq_domain *
2200pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
3a8f77e4
CP		 2201static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2202 struct list_head *resources,
2203 struct resource **bus_range)
2204{
2205 return -EINVAL;
2206}
98d9f30c
BH		 2207#endif /* CONFIG_OF */
2208
ad32eb2d
BM		 2209static inline struct device_node *
2210pci_device_to_OF_node(const struct pci_dev *pdev)
2211{
2212 return pdev ? pdev->dev.of_node : NULL;
2213}
2214
2215static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2216{
2217 return bus ? bus->dev.of_node : NULL;
2218}
2219
471036b2
SS		 2220#ifdef CONFIG_ACPI
2221struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2222
2223void
2224pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2225#else
2226static inline struct irq_domain *
2227pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2228#endif
2229
eb740b5f
GS		 2230#ifdef CONFIG_EEH
2231static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2232{
2233 return pdev->dev.archdata.edev;
2234}
2235#endif
2236
f0af9593 2237void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2238bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2239int pci_for_each_dma_alias(struct pci_dev *pdev,
2240 int (*fn)(struct pci_dev *pdev,
2241 u16 alias, void *data), void *data);
2242
0aa0f5d1 2243/* Helper functions for operation of device flag */
ce052984
EZ		 2244static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2245{
2246 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2247}
2248static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2249{
2250 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2251}
2252static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2253{
2254 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2255}
19bdb6e4
AW		 2256
2257/**
2258 * pci_ari_enabled - query ARI forwarding status
2259 * @bus: the PCI bus
2260 *
2261 * Returns true if ARI forwarding is enabled.
2262 */
2263static inline bool pci_ari_enabled(struct pci_bus *bus)
2264{
2265 return bus->self && bus->self->ari_enabled;
2266}
bc4b024a 2267
8531e283
LW		 2268/**
2269 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2270 * @pdev: PCI device to check
2271 *
2272 * Walk upwards from @pdev and check for each encountered bridge if it's part
2273 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2274 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2275 */
2276static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2277{
2278 struct pci_dev *parent = pdev;
2279
2280 if (pdev->is_thunderbolt)
2281 return true;
2282
2283 while ((parent = pci_upstream_bridge(parent)))
2284 if (parent->is_thunderbolt)
2285 return true;
2286
2287 return false;
2288}
2289
3ecac020
ME		 2290#if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH)
2291void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2292#endif
856e1eb9 2293
0aa0f5d1 2294/* Provide the legacy pci_dma_* API */
bc4b024a
CH		 2295#include <linux/pci-dma-compat.h>
2296
7506dc79
FL		 2297#define pci_printk(level, pdev, fmt, arg...) \
2298 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2299
2300#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2301#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2302#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2303#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2304#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2305#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2306#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2307#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2308
1da177e4 2309#endif /* LINUX_PCI_H */
Linux 6.x block layer and io_uring tree(s)