[linux-block.git] / include / linux / pci-epc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * PCI Endpoint *Controller* (EPC) header file
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H

#include <linux/pci-epf.h>

struct pci_epc;

enum pci_epc_interface_type {
	UNKNOWN_INTERFACE = -1,
	PRIMARY_INTERFACE,
	SECONDARY_INTERFACE,
};

enum pci_epc_irq_type {
	PCI_EPC_IRQ_UNKNOWN,
	PCI_EPC_IRQ_LEGACY,
	PCI_EPC_IRQ_MSI,
	PCI_EPC_IRQ_MSIX,
};

static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)
{
	switch (type) {
	case PRIMARY_INTERFACE:
		return "primary";
	case SECONDARY_INTERFACE:
		return "secondary";
	default:
		return "UNKNOWN interface";
	}
}

/**
 * struct pci_epc_ops - set of function pointers for performing EPC operations
 * @write_header: ops to populate configuration space header
 * @set_bar: ops to configure the BAR
 * @clear_bar: ops to reset the BAR
 * @map_addr: ops to map CPU address to PCI address
 * @unmap_addr: ops to unmap CPU address and PCI address
 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 *	     capability register
 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 *	     the MSI capability register
 * @set_msix: ops to set the requested number of MSI-X interrupts in the
 *	     MSI-X capability register
 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
 *	     from the MSI-X capability register
 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
 * @map_msi_irq: ops to map physical address to MSI address and return MSI data
 * @start: ops to start the PCI link
 * @stop: ops to stop the PCI link
 * @get_features: ops to get the features supported by the EPC
 * @owner: the module owner containing the ops
 */
struct pci_epc_ops {
	int	(*write_header)(struct pci_epc *epc, u8 func_no,
				struct pci_epf_header *hdr);
	int	(*set_bar)(struct pci_epc *epc, u8 func_no,
			   struct pci_epf_bar *epf_bar);
	void	(*clear_bar)(struct pci_epc *epc, u8 func_no,
			     struct pci_epf_bar *epf_bar);
	int	(*map_addr)(struct pci_epc *epc, u8 func_no,
			    phys_addr_t addr, u64 pci_addr, size_t size);
	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no,
			      phys_addr_t addr);
	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts,
			    enum pci_barno, u32 offset);
	int	(*get_msix)(struct pci_epc *epc, u8 func_no);
	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
			     enum pci_epc_irq_type type, u16 interrupt_num);
	int	(*map_msi_irq)(struct pci_epc *epc, u8 func_no,
			       phys_addr_t phys_addr, u8 interrupt_num,
			       u32 entry_size, u32 *msi_data,
			       u32 *msi_addr_offset);
	int	(*start)(struct pci_epc *epc);
	void	(*stop)(struct pci_epc *epc);
	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
						       u8 func_no);
	struct module *owner;
};

/**
 * struct pci_epc_mem_window - address window of the endpoint controller
 * @phys_base: physical base address of the PCI address window
 * @size: the size of the PCI address window
 * @page_size: size of each page
 */
struct pci_epc_mem_window {
	phys_addr_t	phys_base;
	size_t		size;
	size_t		page_size;
};

/**
 * struct pci_epc_mem - address space of the endpoint controller
 * @window: address window of the endpoint controller
 * @bitmap: bitmap to manage the PCI address space
 * @pages: number of bits representing the address region
 * @lock: mutex to protect bitmap
 */
struct pci_epc_mem {
	struct pci_epc_mem_window window;
	unsigned long	*bitmap;
	int		pages;
	/* mutex to protect against concurrent access for memory allocation*/
	struct mutex	lock;
};

/**
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * @ops: function pointers for performing endpoint operations
 * @windows: array of address space of the endpoint controller
 * @mem: first window of the endpoint controller, which corresponds to
 *       default address space of the endpoint controller supporting
 *       single window.
 * @num_windows: number of windows supported by device
 * @max_functions: max number of functions that can be configured in this EPC
 * @group: configfs group representing the PCI EPC device
 * @lock: mutex to protect pci_epc ops
 * @function_num_map: bitmap to manage physical function number
 * @notifier: used to notify EPF of any EPC events (like linkup)
 */
struct pci_epc {
	struct device			dev;
	struct list_head		pci_epf;
	const struct pci_epc_ops	*ops;
	struct pci_epc_mem		**windows;
	struct pci_epc_mem		*mem;
	unsigned int			num_windows;
	u8				max_functions;
	struct config_group		*group;
	/* mutex to protect against concurrent access of EP controller */
	struct mutex			lock;
	unsigned long			function_num_map;
	struct atomic_notifier_head	notifier;
};

/**
 * struct pci_epc_features - features supported by a EPC device per function
 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
 * @core_init_notifier: indicate cores that can notify about their availability
 *			for initialization
 * @msi_capable: indicate if the endpoint function has MSI capability
 * @msix_capable: indicate if the endpoint function has MSI-X capability
 * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
 * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
 * @bar_fixed_size: Array specifying the size supported by each BAR
 * @align: alignment size required for BAR buffer allocation
 */
struct pci_epc_features {
	unsigned int	linkup_notifier : 1;
	unsigned int	core_init_notifier : 1;
	unsigned int	msi_capable : 1;
	unsigned int	msix_capable : 1;
	u8	reserved_bar;
	u8	bar_fixed_64bit;
	u64	bar_fixed_size[PCI_STD_NUM_BARS];
	size_t	align;
};

#define to_pci_epc(device) container_of((device), struct pci_epc, dev)

#define pci_epc_create(dev, ops)    \
		__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops)    \
		__devm_pci_epc_create((dev), (ops), THIS_MODULE)

static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
	dev_set_drvdata(&epc->dev, data);
}

static inline void *epc_get_drvdata(struct pci_epc *epc)
{
	return dev_get_drvdata(&epc->dev);
}

static inline int
pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb)
{
	return atomic_notifier_chain_register(&epc->notifier, nb);
}

struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		      struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		 struct module *owner);
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
		    enum pci_epc_interface_type type);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_init_notify(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
			enum pci_epc_interface_type type);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
			 struct pci_epf_header *hdr);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
		    struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
		       struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
		     phys_addr_t phys_addr,
		     u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
			phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
		     enum pci_barno, u32 offset);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no,
			phys_addr_t phys_addr, u8 interrupt_num,
			u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
		      enum pci_epc_irq_type type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
						    u8 func_no);
enum pci_barno
pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
					 *epc_features, enum pci_barno bar);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);

int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
		     size_t size, size_t page_size);
int pci_epc_multi_mem_init(struct pci_epc *epc,
			   struct pci_epc_mem_window *window,
			   unsigned int num_windows);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
				     phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
			   void __iomem *virt_addr, size_t size);
#endif /* __LINUX_PCI_EPC_H */
Commit	Line	Data
8cfab3cf	1	/* SPDX-License-Identifier: GPL-2.0 */
347269c1	2	/*
5e8cb403 KVA	3	* PCI Endpoint Controller (EPC) header file
	4	*
	5	* Copyright (C) 2017 Texas Instruments
	6	* Author: Kishon Vijay Abraham I <kishon@ti.com>
5e8cb403 KVA	7	*/
	8
	9	#ifndef __LINUX_PCI_EPC_H
	10	#define __LINUX_PCI_EPC_H
	11
	12	#include <linux/pci-epf.h>
	13
	14	struct pci_epc;
	15
63840ff5 KVA	16	enum pci_epc_interface_type {
	17	UNKNOWN_INTERFACE = -1,
	18	PRIMARY_INTERFACE,
	19	SECONDARY_INTERFACE,
	20	};
	21
5e8cb403 KVA	22	enum pci_epc_irq_type {
	23	PCI_EPC_IRQ_UNKNOWN,
	24	PCI_EPC_IRQ_LEGACY,
	25	PCI_EPC_IRQ_MSI,
8963106e	26	PCI_EPC_IRQ_MSIX,
5e8cb403 KVA	27	};
5e8cb403 KVA	28
63840ff5 KVA	29	static inline const char *
	30	pci_epc_interface_string(enum pci_epc_interface_type type)
	31	{
	32	switch (type) {
	33	case PRIMARY_INTERFACE:
	34	return "primary";
	35	case SECONDARY_INTERFACE:
	36	return "secondary";
	37	default:
	38	return "UNKNOWN interface";
	39	}
	40	}
	41
5e8cb403 KVA	42	/**
	43	* struct pci_epc_ops - set of function pointers for performing EPC operations
	44	* @write_header: ops to populate configuration space header
	45	* @set_bar: ops to configure the BAR
	46	* @clear_bar: ops to reset the BAR
	47	* @map_addr: ops to map CPU address to PCI address
	48	* @unmap_addr: ops to unmap CPU address and PCI address
	49	* @set_msi: ops to set the requested number of MSI interrupts in the MSI
	50	* capability register
	51	* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
	52	* the MSI capability register
8963106e GP	53	* @set_msix: ops to set the requested number of MSI-X interrupts in the
	54	* MSI-X capability register
	55	* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
	56	* from the MSI-X capability register
d3c70a98	57	* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
87d5972e	58	* @map_msi_irq: ops to map physical address to MSI address and return MSI data
5e8cb403 KVA	59	* @start: ops to start the PCI link
5e8cb403 KVA	60	* @stop: ops to stop the PCI link
347269c1	61	* @get_features: ops to get the features supported by the EPC
5e8cb403 KVA	62	* @owner: the module owner containing the ops
	63	*/
	64	struct pci_epc_ops {
4494738d	65	int (write_header)(struct pci_epc epc, u8 func_no,
5e8cb403	66	struct pci_epf_header *hdr);
4494738d	67	int (set_bar)(struct pci_epc epc, u8 func_no,
bc4a4897	68	struct pci_epf_bar *epf_bar);
4494738d	69	void (clear_bar)(struct pci_epc epc, u8 func_no,
77d08dbd	70	struct pci_epf_bar *epf_bar);
4494738d CP	71	int (map_addr)(struct pci_epc epc, u8 func_no,
	72	phys_addr_t addr, u64 pci_addr, size_t size);
	73	void (unmap_addr)(struct pci_epc epc, u8 func_no,
	74	phys_addr_t addr);
	75	int (set_msi)(struct pci_epc epc, u8 func_no, u8 interrupts);
	76	int (get_msi)(struct pci_epc epc, u8 func_no);
83153d9f KVA	77	int (set_msix)(struct pci_epc epc, u8 func_no, u16 interrupts,
83153d9f KVA	78	enum pci_barno, u32 offset);
8963106e	79	int (get_msix)(struct pci_epc epc, u8 func_no);
4494738d	80	int (raise_irq)(struct pci_epc epc, u8 func_no,
d3c70a98	81	enum pci_epc_irq_type type, u16 interrupt_num);
87d5972e KVA	82	int (map_msi_irq)(struct pci_epc epc, u8 func_no,
	83	phys_addr_t phys_addr, u8 interrupt_num,
	84	u32 entry_size, u32 *msi_data,
	85	u32 *msi_addr_offset);
5e8cb403 KVA	86	int (start)(struct pci_epc epc);
5e8cb403 KVA	87	void (stop)(struct pci_epc epc);
41cb8d18 KVA	88	const struct pci_epc_features* (get_features)(struct pci_epc epc,
41cb8d18 KVA	89	u8 func_no);
5e8cb403 KVA	90	struct module *owner;
	91	};
	92
d45e3c1a LP	93	/**
	94	* struct pci_epc_mem_window - address window of the endpoint controller
	95	* @phys_base: physical base address of the PCI address window
	96	* @size: the size of the PCI address window
	97	* @page_size: size of each page
	98	*/
	99	struct pci_epc_mem_window {
	100	phys_addr_t phys_base;
	101	size_t size;
	102	size_t page_size;
	103	};
	104
5e8cb403 KVA	105	/**
5e8cb403 KVA	106	* struct pci_epc_mem - address space of the endpoint controller
d45e3c1a	107	* @window: address window of the endpoint controller
5e8cb403 KVA	108	* @bitmap: bitmap to manage the PCI address space
5e8cb403 KVA	109	* @pages: number of bits representing the address region
04e046ca	110	* @lock: mutex to protect bitmap
5e8cb403 KVA	111	*/
5e8cb403 KVA	112	struct pci_epc_mem {
d45e3c1a	113	struct pci_epc_mem_window window;
5e8cb403 KVA	114	unsigned long *bitmap;
5e8cb403 KVA	115	int pages;
04e046ca KVA	116	/* mutex to protect against concurrent access for memory allocation*/
04e046ca KVA	117	struct mutex lock;
5e8cb403 KVA	118	};
	119
	120	/**
	121	* struct pci_epc - represents the PCI EPC device
	122	* @dev: PCI EPC device
	123	* @pci_epf: list of endpoint functions present in this EPC device
	124	* @ops: function pointers for performing endpoint operations
d45e3c1a LP	125	* @windows: array of address space of the endpoint controller
	126	* @mem: first window of the endpoint controller, which corresponds to
	127	* default address space of the endpoint controller supporting
	128	* single window.
	129	* @num_windows: number of windows supported by device
5e8cb403	130	* @max_functions: max number of functions that can be configured in this EPC
3a401a2c	131	* @group: configfs group representing the PCI EPC device
3d3248db	132	* @lock: mutex to protect pci_epc ops
2499ee84	133	* @function_num_map: bitmap to manage physical function number
5779dd0a	134	* @notifier: used to notify EPF of any EPC events (like linkup)
5e8cb403 KVA	135	*/
	136	struct pci_epc {
	137	struct device dev;
	138	struct list_head pci_epf;
	139	const struct pci_epc_ops *ops;
d45e3c1a	140	struct pci_epc_mem **windows;
5e8cb403	141	struct pci_epc_mem *mem;
d45e3c1a	142	unsigned int num_windows;
5e8cb403	143	u8 max_functions;
3a401a2c	144	struct config_group *group;
3d3248db KVA	145	/* mutex to protect against concurrent access of EP controller */
3d3248db KVA	146	struct mutex lock;
2499ee84	147	unsigned long function_num_map;
5779dd0a	148	struct atomic_notifier_head notifier;
5e8cb403 KVA	149	};
5e8cb403 KVA	150
41cb8d18 KVA	151	/**
	152	* struct pci_epc_features - features supported by a EPC device per function
	153	* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
347269c1 KW	154	* @core_init_notifier: indicate cores that can notify about their availability
347269c1 KW	155	* for initialization
41cb8d18 KVA	156	* @msi_capable: indicate if the endpoint function has MSI capability
	157	* @msix_capable: indicate if the endpoint function has MSI-X capability
	158	* @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
	159	* @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
	160	* @bar_fixed_size: Array specifying the size supported by each BAR
2a9a8016	161	* @align: alignment size required for BAR buffer allocation
41cb8d18 KVA	162	*/
	163	struct pci_epc_features {
	164	unsigned int linkup_notifier : 1;
3d5f7d9f	165	unsigned int core_init_notifier : 1;
41cb8d18 KVA	166	unsigned int msi_capable : 1;
	167	unsigned int msix_capable : 1;
	168	u8 reserved_bar;
	169	u8 bar_fixed_64bit;
c9c13ba4	170	u64 bar_fixed_size[PCI_STD_NUM_BARS];
2a9a8016	171	size_t align;
41cb8d18 KVA	172	};
41cb8d18 KVA	173
5e8cb403 KVA	174	#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
	175
	176	#define pci_epc_create(dev, ops) \
	177	__pci_epc_create((dev), (ops), THIS_MODULE)
	178	#define devm_pci_epc_create(dev, ops) \
	179	__devm_pci_epc_create((dev), (ops), THIS_MODULE)
	180
	181	static inline void epc_set_drvdata(struct pci_epc epc, void data)
	182	{
	183	dev_set_drvdata(&epc->dev, data);
	184	}
	185
	186	static inline void epc_get_drvdata(struct pci_epc epc)
	187	{
	188	return dev_get_drvdata(&epc->dev);
	189	}
	190
5779dd0a KVA	191	static inline int
	192	pci_epc_register_notifier(struct pci_epc epc, struct notifier_block nb)
	193	{
	194	return atomic_notifier_chain_register(&epc->notifier, nb);
	195	}
	196
5e8cb403 KVA	197	struct pci_epc *
	198	__devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	199	struct module *owner);
	200	struct pci_epc *
	201	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	202	struct module *owner);
	203	void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
	204	void pci_epc_destroy(struct pci_epc *epc);
63840ff5 KVA	205	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf,
63840ff5 KVA	206	enum pci_epc_interface_type type);
5e8cb403	207	void pci_epc_linkup(struct pci_epc *epc);
0ef22dcf	208	void pci_epc_init_notify(struct pci_epc *epc);
63840ff5 KVA	209	void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf,
63840ff5 KVA	210	enum pci_epc_interface_type type);
4494738d CP	211	int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
	212	struct pci_epf_header *hdr);
	213	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
bc4a4897	214	struct pci_epf_bar *epf_bar);
77d08dbd NC	215	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
77d08dbd NC	216	struct pci_epf_bar *epf_bar);
4494738d CP	217	int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
4494738d CP	218	phys_addr_t phys_addr,
5e8cb403	219	u64 pci_addr, size_t size);
4494738d CP	220	void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
	221	phys_addr_t phys_addr);
	222	int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
	223	int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
83153d9f KVA	224	int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
83153d9f KVA	225	enum pci_barno, u32 offset);
8963106e	226	int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
87d5972e KVA	227	int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no,
	228	phys_addr_t phys_addr, u8 interrupt_num,
	229	u32 entry_size, u32 msi_data, u32 msi_addr_offset);
4494738d	230	int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
d3c70a98	231	enum pci_epc_irq_type type, u16 interrupt_num);
5e8cb403 KVA	232	int pci_epc_start(struct pci_epc *epc);
5e8cb403 KVA	233	void pci_epc_stop(struct pci_epc *epc);
41cb8d18 KVA	234	const struct pci_epc_features pci_epc_get_features(struct pci_epc epc,
41cb8d18 KVA	235	u8 func_no);
0e27aecc KVA	236	enum pci_barno
	237	pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
	238	enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
	239	*epc_features, enum pci_barno bar);
5e8cb403 KVA	240	struct pci_epc pci_epc_get(const char epc_name);
	241	void pci_epc_put(struct pci_epc *epc);
	242
975cf23e LP	243	int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
975cf23e LP	244	size_t size, size_t page_size);
d45e3c1a LP	245	int pci_epc_multi_mem_init(struct pci_epc *epc,
	246	struct pci_epc_mem_window *window,
	247	unsigned int num_windows);
5e8cb403 KVA	248	void pci_epc_mem_exit(struct pci_epc *epc);
	249	void __iomem pci_epc_mem_alloc_addr(struct pci_epc epc,
	250	phys_addr_t *phys_addr, size_t size);
	251	void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
	252	void __iomem *virt_addr, size_t size);
	253	#endif /* __LINUX_PCI_EPC_H */