[linux-2.6-block.git] / include / linux / pci-epc.h

/* SPDX-License-Identifier: GPL-2.0 */
/**
 * PCI Endpoint *Controller* (EPC) header file
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H

#include <linux/pci-epf.h>

struct pci_epc;

enum pci_epc_irq_type {
	PCI_EPC_IRQ_UNKNOWN,
	PCI_EPC_IRQ_LEGACY,
	PCI_EPC_IRQ_MSI,
};

/**
 * struct pci_epc_ops - set of function pointers for performing EPC operations
 * @write_header: ops to populate configuration space header
 * @set_bar: ops to configure the BAR
 * @clear_bar: ops to reset the BAR
 * @map_addr: ops to map CPU address to PCI address
 * @unmap_addr: ops to unmap CPU address and PCI address
 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 *	     capability register
 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 *	     the MSI capability register
 * @raise_irq: ops to raise a legacy or MSI interrupt
 * @start: ops to start the PCI link
 * @stop: ops to stop the PCI link
 * @owner: the module owner containing the ops
 */
struct pci_epc_ops {
	int	(*write_header)(struct pci_epc *epc, u8 func_no,
				struct pci_epf_header *hdr);
	int	(*set_bar)(struct pci_epc *epc, u8 func_no,
			   struct pci_epf_bar *epf_bar);
	void	(*clear_bar)(struct pci_epc *epc, u8 func_no,
			     struct pci_epf_bar *epf_bar);
	int	(*map_addr)(struct pci_epc *epc, u8 func_no,
			    phys_addr_t addr, u64 pci_addr, size_t size);
	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no,
			      phys_addr_t addr);
	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
			     enum pci_epc_irq_type type, u8 interrupt_num);
	int	(*start)(struct pci_epc *epc);
	void	(*stop)(struct pci_epc *epc);
	struct module *owner;
};

/**
 * struct pci_epc_mem - address space of the endpoint controller
 * @phys_base: physical base address of the PCI address space
 * @size: the size of the PCI address space
 * @bitmap: bitmap to manage the PCI address space
 * @pages: number of bits representing the address region
 * @page_size: size of each page
 */
struct pci_epc_mem {
	phys_addr_t	phys_base;
	size_t		size;
	unsigned long	*bitmap;
	size_t		page_size;
	int		pages;
};

/**
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * @ops: function pointers for performing endpoint operations
 * @mem: address space of the endpoint controller
 * @max_functions: max number of functions that can be configured in this EPC
 * @group: configfs group representing the PCI EPC device
 * @lock: spinlock to protect pci_epc ops
 */
struct pci_epc {
	struct device			dev;
	struct list_head		pci_epf;
	const struct pci_epc_ops	*ops;
	struct pci_epc_mem		*mem;
	u8				max_functions;
	struct config_group		*group;
	/* spinlock to protect against concurrent access of EP controller */
	spinlock_t			lock;
};

#define to_pci_epc(device) container_of((device), struct pci_epc, dev)

#define pci_epc_create(dev, ops)    \
		__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops)    \
		__devm_pci_epc_create((dev), (ops), THIS_MODULE)

#define pci_epc_mem_init(epc, phys_addr, size)	\
		__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)

static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
	dev_set_drvdata(&epc->dev, data);
}

static inline void *epc_get_drvdata(struct pci_epc *epc)
{
	return dev_get_drvdata(&epc->dev);
}

struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		      struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		 struct module *owner);
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
			 struct pci_epf_header *hdr);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
		    struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
		       struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
		     phys_addr_t phys_addr,
		     u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
			phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
		      enum pci_epc_irq_type type, u8 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);

int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
		       size_t page_size);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
				     phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
			   void __iomem *virt_addr, size_t size);
#endif /* __LINUX_PCI_EPC_H */
Commit	Line	Data
8cfab3cf	1	/* SPDX-License-Identifier: GPL-2.0 */
5e8cb403 KVA	2	/**
	3	* PCI Endpoint Controller (EPC) header file
	4	*
	5	* Copyright (C) 2017 Texas Instruments
	6	* Author: Kishon Vijay Abraham I <kishon@ti.com>
5e8cb403 KVA	7	*/
	8
	9	#ifndef __LINUX_PCI_EPC_H
	10	#define __LINUX_PCI_EPC_H
	11
	12	#include <linux/pci-epf.h>
	13
	14	struct pci_epc;
	15
	16	enum pci_epc_irq_type {
	17	PCI_EPC_IRQ_UNKNOWN,
	18	PCI_EPC_IRQ_LEGACY,
	19	PCI_EPC_IRQ_MSI,
	20	};
	21
	22	/**
	23	* struct pci_epc_ops - set of function pointers for performing EPC operations
	24	* @write_header: ops to populate configuration space header
	25	* @set_bar: ops to configure the BAR
	26	* @clear_bar: ops to reset the BAR
	27	* @map_addr: ops to map CPU address to PCI address
	28	* @unmap_addr: ops to unmap CPU address and PCI address
	29	* @set_msi: ops to set the requested number of MSI interrupts in the MSI
	30	* capability register
	31	* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
	32	* the MSI capability register
	33	* @raise_irq: ops to raise a legacy or MSI interrupt
	34	* @start: ops to start the PCI link
	35	* @stop: ops to stop the PCI link
	36	* @owner: the module owner containing the ops
	37	*/
	38	struct pci_epc_ops {
4494738d	39	int (write_header)(struct pci_epc epc, u8 func_no,
5e8cb403	40	struct pci_epf_header *hdr);
4494738d	41	int (set_bar)(struct pci_epc epc, u8 func_no,
bc4a4897	42	struct pci_epf_bar *epf_bar);
4494738d	43	void (clear_bar)(struct pci_epc epc, u8 func_no,
77d08dbd	44	struct pci_epf_bar *epf_bar);
4494738d CP	45	int (map_addr)(struct pci_epc epc, u8 func_no,
	46	phys_addr_t addr, u64 pci_addr, size_t size);
	47	void (unmap_addr)(struct pci_epc epc, u8 func_no,
	48	phys_addr_t addr);
	49	int (set_msi)(struct pci_epc epc, u8 func_no, u8 interrupts);
	50	int (get_msi)(struct pci_epc epc, u8 func_no);
	51	int (raise_irq)(struct pci_epc epc, u8 func_no,
5e8cb403 KVA	52	enum pci_epc_irq_type type, u8 interrupt_num);
	53	int (start)(struct pci_epc epc);
	54	void (stop)(struct pci_epc epc);
	55	struct module *owner;
	56	};
	57
	58	/**
	59	* struct pci_epc_mem - address space of the endpoint controller
	60	* @phys_base: physical base address of the PCI address space
	61	* @size: the size of the PCI address space
	62	* @bitmap: bitmap to manage the PCI address space
	63	* @pages: number of bits representing the address region
52c9285d	64	* @page_size: size of each page
5e8cb403 KVA	65	*/
	66	struct pci_epc_mem {
	67	phys_addr_t phys_base;
	68	size_t size;
	69	unsigned long *bitmap;
52c9285d	70	size_t page_size;
5e8cb403 KVA	71	int pages;
	72	};
	73
	74	/**
	75	* struct pci_epc - represents the PCI EPC device
	76	* @dev: PCI EPC device
	77	* @pci_epf: list of endpoint functions present in this EPC device
	78	* @ops: function pointers for performing endpoint operations
	79	* @mem: address space of the endpoint controller
	80	* @max_functions: max number of functions that can be configured in this EPC
3a401a2c	81	* @group: configfs group representing the PCI EPC device
5e8cb403 KVA	82	* @lock: spinlock to protect pci_epc ops
	83	*/
	84	struct pci_epc {
	85	struct device dev;
	86	struct list_head pci_epf;
	87	const struct pci_epc_ops *ops;
	88	struct pci_epc_mem *mem;
	89	u8 max_functions;
3a401a2c	90	struct config_group *group;
5e8cb403 KVA	91	/* spinlock to protect against concurrent access of EP controller */
	92	spinlock_t lock;
	93	};
	94
	95	#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
	96
	97	#define pci_epc_create(dev, ops) \
	98	__pci_epc_create((dev), (ops), THIS_MODULE)
	99	#define devm_pci_epc_create(dev, ops) \
	100	__devm_pci_epc_create((dev), (ops), THIS_MODULE)
	101
52c9285d KVA	102	#define pci_epc_mem_init(epc, phys_addr, size) \
	103	__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)
	104
5e8cb403 KVA	105	static inline void epc_set_drvdata(struct pci_epc epc, void data)
	106	{
	107	dev_set_drvdata(&epc->dev, data);
	108	}
	109
	110	static inline void epc_get_drvdata(struct pci_epc epc)
	111	{
	112	return dev_get_drvdata(&epc->dev);
	113	}
	114
	115	struct pci_epc *
	116	__devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	117	struct module *owner);
	118	struct pci_epc *
	119	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	120	struct module *owner);
	121	void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
	122	void pci_epc_destroy(struct pci_epc *epc);
	123	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf);
	124	void pci_epc_linkup(struct pci_epc *epc);
	125	void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf);
4494738d CP	126	int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
	127	struct pci_epf_header *hdr);
	128	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
bc4a4897	129	struct pci_epf_bar *epf_bar);
77d08dbd NC	130	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
77d08dbd NC	131	struct pci_epf_bar *epf_bar);
4494738d CP	132	int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
4494738d CP	133	phys_addr_t phys_addr,
5e8cb403	134	u64 pci_addr, size_t size);
4494738d CP	135	void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
	136	phys_addr_t phys_addr);
	137	int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
	138	int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
	139	int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
	140	enum pci_epc_irq_type type, u8 interrupt_num);
5e8cb403 KVA	141	int pci_epc_start(struct pci_epc *epc);
	142	void pci_epc_stop(struct pci_epc *epc);
	143	struct pci_epc pci_epc_get(const char epc_name);
	144	void pci_epc_put(struct pci_epc *epc);
	145
52c9285d KVA	146	int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
52c9285d KVA	147	size_t page_size);
5e8cb403 KVA	148	void pci_epc_mem_exit(struct pci_epc *epc);
	149	void __iomem pci_epc_mem_alloc_addr(struct pci_epc epc,
	150	phys_addr_t *phys_addr, size_t size);
	151	void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
	152	void __iomem *virt_addr, size_t size);
	153	#endif /* __LINUX_PCI_EPC_H */