[linux-2.6-block.git] / include / linux / pci-epc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * PCI Endpoint *Controller* (EPC) header file
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H

#include <linux/pci-epf.h>

struct pci_epc;

enum pci_epc_interface_type {
	UNKNOWN_INTERFACE = -1,
	PRIMARY_INTERFACE,
	SECONDARY_INTERFACE,
};

static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)
{
	switch (type) {
	case PRIMARY_INTERFACE:
		return "primary";
	case SECONDARY_INTERFACE:
		return "secondary";
	default:
		return "UNKNOWN interface";
	}
}

/**
 * struct pci_epc_ops - set of function pointers for performing EPC operations
 * @write_header: ops to populate configuration space header
 * @set_bar: ops to configure the BAR
 * @clear_bar: ops to reset the BAR
 * @map_addr: ops to map CPU address to PCI address
 * @unmap_addr: ops to unmap CPU address and PCI address
 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 *	     capability register
 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 *	     the MSI capability register
 * @set_msix: ops to set the requested number of MSI-X interrupts in the
 *	     MSI-X capability register
 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
 *	     from the MSI-X capability register
 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
 * @map_msi_irq: ops to map physical address to MSI address and return MSI data
 * @start: ops to start the PCI link
 * @stop: ops to stop the PCI link
 * @get_features: ops to get the features supported by the EPC
 * @owner: the module owner containing the ops
 */
struct pci_epc_ops {
	int	(*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
				struct pci_epf_header *hdr);
	int	(*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			   struct pci_epf_bar *epf_bar);
	void	(*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			     struct pci_epf_bar *epf_bar);
	int	(*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			    phys_addr_t addr, u64 pci_addr, size_t size);
	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			      phys_addr_t addr);
	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			   u8 interrupts);
	int	(*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			    u16 interrupts, enum pci_barno, u32 offset);
	int	(*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
	int	(*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			     unsigned int type, u16 interrupt_num);
	int	(*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			       phys_addr_t phys_addr, u8 interrupt_num,
			       u32 entry_size, u32 *msi_data,
			       u32 *msi_addr_offset);
	int	(*start)(struct pci_epc *epc);
	void	(*stop)(struct pci_epc *epc);
	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
						       u8 func_no, u8 vfunc_no);
	struct module *owner;
};

/**
 * struct pci_epc_mem_window - address window of the endpoint controller
 * @phys_base: physical base address of the PCI address window
 * @size: the size of the PCI address window
 * @page_size: size of each page
 */
struct pci_epc_mem_window {
	phys_addr_t	phys_base;
	size_t		size;
	size_t		page_size;
};

/**
 * struct pci_epc_mem - address space of the endpoint controller
 * @window: address window of the endpoint controller
 * @bitmap: bitmap to manage the PCI address space
 * @pages: number of bits representing the address region
 * @lock: mutex to protect bitmap
 */
struct pci_epc_mem {
	struct pci_epc_mem_window window;
	unsigned long	*bitmap;
	int		pages;
	/* mutex to protect against concurrent access for memory allocation*/
	struct mutex	lock;
};

/**
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * @list_lock: Mutex for protecting pci_epf list
 * @ops: function pointers for performing endpoint operations
 * @windows: array of address space of the endpoint controller
 * @mem: first window of the endpoint controller, which corresponds to
 *       default address space of the endpoint controller supporting
 *       single window.
 * @num_windows: number of windows supported by device
 * @max_functions: max number of functions that can be configured in this EPC
 * @max_vfs: Array indicating the maximum number of virtual functions that can
 *   be associated with each physical function
 * @group: configfs group representing the PCI EPC device
 * @lock: mutex to protect pci_epc ops
 * @function_num_map: bitmap to manage physical function number
 * @init_complete: flag to indicate whether the EPC initialization is complete
 *                 or not
 */
struct pci_epc {
	struct device			dev;
	struct list_head		pci_epf;
	struct mutex			list_lock;
	const struct pci_epc_ops	*ops;
	struct pci_epc_mem		**windows;
	struct pci_epc_mem		*mem;
	unsigned int			num_windows;
	u8				max_functions;
	u8				*max_vfs;
	struct config_group		*group;
	/* mutex to protect against concurrent access of EP controller */
	struct mutex			lock;
	unsigned long			function_num_map;
	bool				init_complete;
};

/**
 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
 * @BAR_FIXED: The BAR mask is fixed by the hardware.
 * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
 */
enum pci_epc_bar_type {
	BAR_PROGRAMMABLE = 0,
	BAR_FIXED,
	BAR_RESERVED,
};

/**
 * struct pci_epc_bar_desc - hardware description for a BAR
 * @type: the type of the BAR
 * @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
 * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
 *		should be configured as 32-bit or 64-bit, the EPF driver must
 *		configure this BAR as 64-bit. Additionally, the BAR succeeding
 *		this BAR must be set to type BAR_RESERVED.
 *
 *		only_64bit should not be set on a BAR of type BAR_RESERVED.
 *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
 *		touch, then both BARx and BARx+1 must be set to type
 *		BAR_RESERVED.)
 */
struct pci_epc_bar_desc {
	enum pci_epc_bar_type type;
	u64 fixed_size;
	bool only_64bit;
};

/**
 * struct pci_epc_features - features supported by a EPC device per function
 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
 * @msi_capable: indicate if the endpoint function has MSI capability
 * @msix_capable: indicate if the endpoint function has MSI-X capability
 * @bar: array specifying the hardware description for each BAR
 * @align: alignment size required for BAR buffer allocation
 */
struct pci_epc_features {
	unsigned int	linkup_notifier : 1;
	unsigned int	msi_capable : 1;
	unsigned int	msix_capable : 1;
	struct	pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
	size_t	align;
};

#define to_pci_epc(device) container_of((device), struct pci_epc, dev)

#ifdef CONFIG_PCI_ENDPOINT

#define pci_epc_create(dev, ops)    \
		__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops)    \
		__devm_pci_epc_create((dev), (ops), THIS_MODULE)

static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
	dev_set_drvdata(&epc->dev, data);
}

static inline void *epc_get_drvdata(struct pci_epc *epc)
{
	return dev_get_drvdata(&epc->dev);
}

struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		      struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		 struct module *owner);
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
		    enum pci_epc_interface_type type);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_linkdown(struct pci_epc *epc);
void pci_epc_init_notify(struct pci_epc *epc);
void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
void pci_epc_deinit_notify(struct pci_epc *epc);
void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
			enum pci_epc_interface_type type);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			 struct pci_epf_header *hdr);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		    struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		       struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		     phys_addr_t phys_addr,
		     u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		    u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		     u16 interrupts, enum pci_barno, u32 offset);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
			phys_addr_t phys_addr, u8 interrupt_num,
			u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
		      unsigned int type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
						    u8 func_no, u8 vfunc_no);
enum pci_barno
pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
					 *epc_features, enum pci_barno bar);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);

int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
		     size_t size, size_t page_size);
int pci_epc_multi_mem_init(struct pci_epc *epc,
			   struct pci_epc_mem_window *window,
			   unsigned int num_windows);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
				     phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
			   void __iomem *virt_addr, size_t size);

#else
static inline void pci_epc_init_notify(struct pci_epc *epc)
{
}

static inline void pci_epc_deinit_notify(struct pci_epc *epc)
{
}
#endif /* CONFIG_PCI_ENDPOINT */
#endif /* __LINUX_PCI_EPC_H */
Commit	Line	Data
8cfab3cf	1	/* SPDX-License-Identifier: GPL-2.0 */
347269c1	2	/*
5e8cb403 KVA	3	* PCI Endpoint Controller (EPC) header file
	4	*
	5	* Copyright (C) 2017 Texas Instruments
	6	* Author: Kishon Vijay Abraham I <kishon@ti.com>
5e8cb403 KVA	7	*/
	8
	9	#ifndef __LINUX_PCI_EPC_H
	10	#define __LINUX_PCI_EPC_H
	11
	12	#include <linux/pci-epf.h>
	13
	14	struct pci_epc;
	15
63840ff5 KVA	16	enum pci_epc_interface_type {
	17	UNKNOWN_INTERFACE = -1,
	18	PRIMARY_INTERFACE,
	19	SECONDARY_INTERFACE,
	20	};
	21
63840ff5 KVA	22	static inline const char *
	23	pci_epc_interface_string(enum pci_epc_interface_type type)
	24	{
	25	switch (type) {
	26	case PRIMARY_INTERFACE:
	27	return "primary";
	28	case SECONDARY_INTERFACE:
	29	return "secondary";
	30	default:
	31	return "UNKNOWN interface";
	32	}
	33	}
	34
5e8cb403 KVA	35	/**
	36	* struct pci_epc_ops - set of function pointers for performing EPC operations
	37	* @write_header: ops to populate configuration space header
	38	* @set_bar: ops to configure the BAR
	39	* @clear_bar: ops to reset the BAR
	40	* @map_addr: ops to map CPU address to PCI address
	41	* @unmap_addr: ops to unmap CPU address and PCI address
	42	* @set_msi: ops to set the requested number of MSI interrupts in the MSI
	43	* capability register
	44	* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
	45	* the MSI capability register
8963106e GP	46	* @set_msix: ops to set the requested number of MSI-X interrupts in the
	47	* MSI-X capability register
	48	* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
	49	* from the MSI-X capability register
d3c70a98	50	* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
87d5972e	51	* @map_msi_irq: ops to map physical address to MSI address and return MSI data
5e8cb403 KVA	52	* @start: ops to start the PCI link
5e8cb403 KVA	53	* @stop: ops to stop the PCI link
347269c1	54	* @get_features: ops to get the features supported by the EPC
5e8cb403 KVA	55	* @owner: the module owner containing the ops
	56	*/
	57	struct pci_epc_ops {
53fd3cbe	58	int (write_header)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
5e8cb403	59	struct pci_epf_header *hdr);
53fd3cbe	60	int (set_bar)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
bc4a4897	61	struct pci_epf_bar *epf_bar);
53fd3cbe	62	void (clear_bar)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
77d08dbd	63	struct pci_epf_bar *epf_bar);
53fd3cbe	64	int (map_addr)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
4494738d	65	phys_addr_t addr, u64 pci_addr, size_t size);
53fd3cbe	66	void (unmap_addr)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
4494738d	67	phys_addr_t addr);
53fd3cbe KVA	68	int (set_msi)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
	69	u8 interrupts);
	70	int (get_msi)(struct pci_epc epc, u8 func_no, u8 vfunc_no);
	71	int (set_msix)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
	72	u16 interrupts, enum pci_barno, u32 offset);
	73	int (get_msix)(struct pci_epc epc, u8 func_no, u8 vfunc_no);
	74	int (raise_irq)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
74955cb8	75	unsigned int type, u16 interrupt_num);
53fd3cbe	76	int (map_msi_irq)(struct pci_epc epc, u8 func_no, u8 vfunc_no,
87d5972e KVA	77	phys_addr_t phys_addr, u8 interrupt_num,
	78	u32 entry_size, u32 *msi_data,
	79	u32 *msi_addr_offset);
5e8cb403 KVA	80	int (start)(struct pci_epc epc);
5e8cb403 KVA	81	void (stop)(struct pci_epc epc);
41cb8d18	82	const struct pci_epc_features* (get_features)(struct pci_epc epc,
53fd3cbe	83	u8 func_no, u8 vfunc_no);
5e8cb403 KVA	84	struct module *owner;
	85	};
	86
d45e3c1a LP	87	/**
	88	* struct pci_epc_mem_window - address window of the endpoint controller
	89	* @phys_base: physical base address of the PCI address window
	90	* @size: the size of the PCI address window
	91	* @page_size: size of each page
	92	*/
	93	struct pci_epc_mem_window {
	94	phys_addr_t phys_base;
	95	size_t size;
	96	size_t page_size;
	97	};
	98
5e8cb403 KVA	99	/**
5e8cb403 KVA	100	* struct pci_epc_mem - address space of the endpoint controller
d45e3c1a	101	* @window: address window of the endpoint controller
5e8cb403 KVA	102	* @bitmap: bitmap to manage the PCI address space
5e8cb403 KVA	103	* @pages: number of bits representing the address region
04e046ca	104	* @lock: mutex to protect bitmap
5e8cb403 KVA	105	*/
5e8cb403 KVA	106	struct pci_epc_mem {
d45e3c1a	107	struct pci_epc_mem_window window;
5e8cb403 KVA	108	unsigned long *bitmap;
5e8cb403 KVA	109	int pages;
04e046ca KVA	110	/* mutex to protect against concurrent access for memory allocation*/
04e046ca KVA	111	struct mutex lock;
5e8cb403 KVA	112	};
	113
	114	/**
	115	* struct pci_epc - represents the PCI EPC device
	116	* @dev: PCI EPC device
	117	* @pci_epf: list of endpoint functions present in this EPC device
2db6b72c	118	* @list_lock: Mutex for protecting pci_epf list
5e8cb403	119	* @ops: function pointers for performing endpoint operations
d45e3c1a LP	120	* @windows: array of address space of the endpoint controller
	121	* @mem: first window of the endpoint controller, which corresponds to
	122	* default address space of the endpoint controller supporting
	123	* single window.
	124	* @num_windows: number of windows supported by device
5e8cb403	125	* @max_functions: max number of functions that can be configured in this EPC
53fd3cbe KVA	126	* @max_vfs: Array indicating the maximum number of virtual functions that can
53fd3cbe KVA	127	* be associated with each physical function
3a401a2c	128	* @group: configfs group representing the PCI EPC device
3d3248db	129	* @lock: mutex to protect pci_epc ops
2499ee84	130	* @function_num_map: bitmap to manage physical function number
a01e7214 MS	131	* @init_complete: flag to indicate whether the EPC initialization is complete
a01e7214 MS	132	* or not
5e8cb403 KVA	133	*/
	134	struct pci_epc {
	135	struct device dev;
	136	struct list_head pci_epf;
d6dd5baf	137	struct mutex list_lock;
5e8cb403	138	const struct pci_epc_ops *ops;
d45e3c1a	139	struct pci_epc_mem **windows;
5e8cb403	140	struct pci_epc_mem *mem;
d45e3c1a	141	unsigned int num_windows;
5e8cb403	142	u8 max_functions;
53fd3cbe	143	u8 *max_vfs;
3a401a2c	144	struct config_group *group;
3d3248db KVA	145	/* mutex to protect against concurrent access of EP controller */
3d3248db KVA	146	struct mutex lock;
2499ee84	147	unsigned long function_num_map;
a01e7214	148	bool init_complete;
5e8cb403 KVA	149	};
5e8cb403 KVA	150
e01c9797 NC	151	/**
	152	* @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
	153	* @BAR_FIXED: The BAR mask is fixed by the hardware.
	154	* @BAR_RESERVED: The BAR should not be touched by an EPF driver.
	155	*/
	156	enum pci_epc_bar_type {
	157	BAR_PROGRAMMABLE = 0,
	158	BAR_FIXED,
	159	BAR_RESERVED,
	160	};
	161
	162	/**
	163	* struct pci_epc_bar_desc - hardware description for a BAR
	164	* @type: the type of the BAR
	165	* @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
	166	* @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
	167	* should be configured as 32-bit or 64-bit, the EPF driver must
	168	* configure this BAR as 64-bit. Additionally, the BAR succeeding
	169	* this BAR must be set to type BAR_RESERVED.
92665146 NC	170	*
	171	* only_64bit should not be set on a BAR of type BAR_RESERVED.
	172	* (If BARx is a 64-bit BAR that an EPF driver is not allowed to
	173	* touch, then both BARx and BARx+1 must be set to type
	174	* BAR_RESERVED.)
e01c9797 NC	175	*/
	176	struct pci_epc_bar_desc {
	177	enum pci_epc_bar_type type;
	178	u64 fixed_size;
	179	bool only_64bit;
	180	};
	181
41cb8d18 KVA	182	/**
	183	* struct pci_epc_features - features supported by a EPC device per function
	184	* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
	185	* @msi_capable: indicate if the endpoint function has MSI capability
	186	* @msix_capable: indicate if the endpoint function has MSI-X capability
e01c9797	187	* @bar: array specifying the hardware description for each BAR
2a9a8016	188	* @align: alignment size required for BAR buffer allocation
41cb8d18 KVA	189	*/
	190	struct pci_epc_features {
	191	unsigned int linkup_notifier : 1;
	192	unsigned int msi_capable : 1;
	193	unsigned int msix_capable : 1;
e01c9797	194	struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
2a9a8016	195	size_t align;
41cb8d18 KVA	196	};
41cb8d18 KVA	197
5e8cb403 KVA	198	#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
5e8cb403 KVA	199
473b2cf9 MS	200	#ifdef CONFIG_PCI_ENDPOINT
473b2cf9 MS	201
5e8cb403 KVA	202	#define pci_epc_create(dev, ops) \
	203	__pci_epc_create((dev), (ops), THIS_MODULE)
	204	#define devm_pci_epc_create(dev, ops) \
	205	__devm_pci_epc_create((dev), (ops), THIS_MODULE)
	206
	207	static inline void epc_set_drvdata(struct pci_epc epc, void data)
	208	{
	209	dev_set_drvdata(&epc->dev, data);
	210	}
	211
	212	static inline void epc_get_drvdata(struct pci_epc epc)
	213	{
	214	return dev_get_drvdata(&epc->dev);
	215	}
	216
	217	struct pci_epc *
	218	__devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	219	struct module *owner);
	220	struct pci_epc *
	221	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	222	struct module *owner);
	223	void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
	224	void pci_epc_destroy(struct pci_epc *epc);
63840ff5 KVA	225	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf,
63840ff5 KVA	226	enum pci_epc_interface_type type);
5e8cb403	227	void pci_epc_linkup(struct pci_epc *epc);
a1f6c3d7	228	void pci_epc_linkdown(struct pci_epc *epc);
0ef22dcf	229	void pci_epc_init_notify(struct pci_epc *epc);
a01e7214	230	void pci_epc_notify_pending_init(struct pci_epc epc, struct pci_epf epf);
473b2cf9	231	void pci_epc_deinit_notify(struct pci_epc *epc);
f58838d7	232	void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
63840ff5 KVA	233	void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf,
63840ff5 KVA	234	enum pci_epc_interface_type type);
53fd3cbe	235	int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
4494738d	236	struct pci_epf_header *hdr);
53fd3cbe	237	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
bc4a4897	238	struct pci_epf_bar *epf_bar);
53fd3cbe	239	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
77d08dbd	240	struct pci_epf_bar *epf_bar);
53fd3cbe	241	int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
4494738d	242	phys_addr_t phys_addr,
5e8cb403	243	u64 pci_addr, size_t size);
53fd3cbe	244	void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
4494738d	245	phys_addr_t phys_addr);
53fd3cbe KVA	246	int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
	247	u8 interrupts);
	248	int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
	249	int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
	250	u16 interrupts, enum pci_barno, u32 offset);
	251	int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
	252	int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
87d5972e KVA	253	phys_addr_t phys_addr, u8 interrupt_num,
87d5972e KVA	254	u32 entry_size, u32 msi_data, u32 msi_addr_offset);
53fd3cbe	255	int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
74955cb8	256	unsigned int type, u16 interrupt_num);
5e8cb403 KVA	257	int pci_epc_start(struct pci_epc *epc);
5e8cb403 KVA	258	void pci_epc_stop(struct pci_epc *epc);
41cb8d18	259	const struct pci_epc_features pci_epc_get_features(struct pci_epc epc,
53fd3cbe	260	u8 func_no, u8 vfunc_no);
0e27aecc KVA	261	enum pci_barno
	262	pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
	263	enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
	264	*epc_features, enum pci_barno bar);
5e8cb403 KVA	265	struct pci_epc pci_epc_get(const char epc_name);
	266	void pci_epc_put(struct pci_epc *epc);
	267
975cf23e LP	268	int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
975cf23e LP	269	size_t size, size_t page_size);
d45e3c1a LP	270	int pci_epc_multi_mem_init(struct pci_epc *epc,
	271	struct pci_epc_mem_window *window,
	272	unsigned int num_windows);
5e8cb403 KVA	273	void pci_epc_mem_exit(struct pci_epc *epc);
	274	void __iomem pci_epc_mem_alloc_addr(struct pci_epc epc,
	275	phys_addr_t *phys_addr, size_t size);
	276	void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
	277	void __iomem *virt_addr, size_t size);
473b2cf9 MS	278
	279	#else
	280	static inline void pci_epc_init_notify(struct pci_epc *epc)
	281	{
	282	}
	283
	284	static inline void pci_epc_deinit_notify(struct pci_epc *epc)
	285	{
	286	}
	287	#endif /* CONFIG_PCI_ENDPOINT */
5e8cb403	288	#endif /* __LINUX_PCI_EPC_H */