[linux-2.6-block.git] / include / linux / pci-epc.h

/* SPDX-License-Identifier: GPL-2.0 */
/**
 * PCI Endpoint *Controller* (EPC) header file
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H

#include <linux/pci-epf.h>

struct pci_epc;

enum pci_epc_irq_type {
	PCI_EPC_IRQ_UNKNOWN,
	PCI_EPC_IRQ_LEGACY,
	PCI_EPC_IRQ_MSI,
	PCI_EPC_IRQ_MSIX,
};

/**
 * struct pci_epc_ops - set of function pointers for performing EPC operations
 * @write_header: ops to populate configuration space header
 * @set_bar: ops to configure the BAR
 * @clear_bar: ops to reset the BAR
 * @map_addr: ops to map CPU address to PCI address
 * @unmap_addr: ops to unmap CPU address and PCI address
 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 *	     capability register
 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 *	     the MSI capability register
 * @set_msix: ops to set the requested number of MSI-X interrupts in the
 *	     MSI-X capability register
 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
 *	     from the MSI-X capability register
 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
 * @start: ops to start the PCI link
 * @stop: ops to stop the PCI link
 * @owner: the module owner containing the ops
 */
struct pci_epc_ops {
	int	(*write_header)(struct pci_epc *epc, u8 func_no,
				struct pci_epf_header *hdr);
	int	(*set_bar)(struct pci_epc *epc, u8 func_no,
			   struct pci_epf_bar *epf_bar);
	void	(*clear_bar)(struct pci_epc *epc, u8 func_no,
			     struct pci_epf_bar *epf_bar);
	int	(*map_addr)(struct pci_epc *epc, u8 func_no,
			    phys_addr_t addr, u64 pci_addr, size_t size);
	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no,
			      phys_addr_t addr);
	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
	int	(*get_msix)(struct pci_epc *epc, u8 func_no);
	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
			     enum pci_epc_irq_type type, u16 interrupt_num);
	int	(*start)(struct pci_epc *epc);
	void	(*stop)(struct pci_epc *epc);
	struct module *owner;
};

/**
 * struct pci_epc_mem - address space of the endpoint controller
 * @phys_base: physical base address of the PCI address space
 * @size: the size of the PCI address space
 * @bitmap: bitmap to manage the PCI address space
 * @pages: number of bits representing the address region
 * @page_size: size of each page
 */
struct pci_epc_mem {
	phys_addr_t	phys_base;
	size_t		size;
	unsigned long	*bitmap;
	size_t		page_size;
	int		pages;
};

/**
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * @ops: function pointers for performing endpoint operations
 * @mem: address space of the endpoint controller
 * @max_functions: max number of functions that can be configured in this EPC
 * @group: configfs group representing the PCI EPC device
 * @lock: spinlock to protect pci_epc ops
 */
struct pci_epc {
	struct device			dev;
	struct list_head		pci_epf;
	const struct pci_epc_ops	*ops;
	struct pci_epc_mem		*mem;
	u8				max_functions;
	struct config_group		*group;
	/* spinlock to protect against concurrent access of EP controller */
	spinlock_t			lock;
	unsigned int			features;
};

#define EPC_FEATURE_NO_LINKUP_NOTIFIER		BIT(0)
#define EPC_FEATURE_BAR_MASK			(BIT(1) | BIT(2) | BIT(3))
#define EPC_FEATURE_MSIX_AVAILABLE		BIT(4)
#define EPC_FEATURE_SET_BAR(features, bar)	\
		(features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
#define EPC_FEATURE_GET_BAR(features)		\
		((features & EPC_FEATURE_BAR_MASK) >> 1)

#define to_pci_epc(device) container_of((device), struct pci_epc, dev)

#define pci_epc_create(dev, ops)    \
		__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops)    \
		__devm_pci_epc_create((dev), (ops), THIS_MODULE)

#define pci_epc_mem_init(epc, phys_addr, size)	\
		__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)

static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
	dev_set_drvdata(&epc->dev, data);
}

static inline void *epc_get_drvdata(struct pci_epc *epc)
{
	return dev_get_drvdata(&epc->dev);
}

struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		      struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		 struct module *owner);
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
			 struct pci_epf_header *hdr);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
		    struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
		       struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
		     phys_addr_t phys_addr,
		     u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
			phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
		      enum pci_epc_irq_type type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);

int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
		       size_t page_size);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
				     phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
			   void __iomem *virt_addr, size_t size);
#endif /* __LINUX_PCI_EPC_H */
Commit	Line	Data
8cfab3cf	1	/* SPDX-License-Identifier: GPL-2.0 */
5e8cb403 KVA	2	/**
	3	* PCI Endpoint Controller (EPC) header file
	4	*
	5	* Copyright (C) 2017 Texas Instruments
	6	* Author: Kishon Vijay Abraham I <kishon@ti.com>
5e8cb403 KVA	7	*/
	8
	9	#ifndef __LINUX_PCI_EPC_H
	10	#define __LINUX_PCI_EPC_H
	11
	12	#include <linux/pci-epf.h>
	13
	14	struct pci_epc;
	15
	16	enum pci_epc_irq_type {
	17	PCI_EPC_IRQ_UNKNOWN,
	18	PCI_EPC_IRQ_LEGACY,
	19	PCI_EPC_IRQ_MSI,
8963106e	20	PCI_EPC_IRQ_MSIX,
5e8cb403 KVA	21	};
	22
	23	/**
	24	* struct pci_epc_ops - set of function pointers for performing EPC operations
	25	* @write_header: ops to populate configuration space header
	26	* @set_bar: ops to configure the BAR
	27	* @clear_bar: ops to reset the BAR
	28	* @map_addr: ops to map CPU address to PCI address
	29	* @unmap_addr: ops to unmap CPU address and PCI address
	30	* @set_msi: ops to set the requested number of MSI interrupts in the MSI
	31	* capability register
	32	* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
	33	* the MSI capability register
8963106e GP	34	* @set_msix: ops to set the requested number of MSI-X interrupts in the
	35	* MSI-X capability register
	36	* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
	37	* from the MSI-X capability register
d3c70a98	38	* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
5e8cb403 KVA	39	* @start: ops to start the PCI link
	40	* @stop: ops to stop the PCI link
	41	* @owner: the module owner containing the ops
	42	*/
	43	struct pci_epc_ops {
4494738d	44	int (write_header)(struct pci_epc epc, u8 func_no,
5e8cb403	45	struct pci_epf_header *hdr);
4494738d	46	int (set_bar)(struct pci_epc epc, u8 func_no,
bc4a4897	47	struct pci_epf_bar *epf_bar);
4494738d	48	void (clear_bar)(struct pci_epc epc, u8 func_no,
77d08dbd	49	struct pci_epf_bar *epf_bar);
4494738d CP	50	int (map_addr)(struct pci_epc epc, u8 func_no,
	51	phys_addr_t addr, u64 pci_addr, size_t size);
	52	void (unmap_addr)(struct pci_epc epc, u8 func_no,
	53	phys_addr_t addr);
	54	int (set_msi)(struct pci_epc epc, u8 func_no, u8 interrupts);
	55	int (get_msi)(struct pci_epc epc, u8 func_no);
8963106e GP	56	int (set_msix)(struct pci_epc epc, u8 func_no, u16 interrupts);
8963106e GP	57	int (get_msix)(struct pci_epc epc, u8 func_no);
4494738d	58	int (raise_irq)(struct pci_epc epc, u8 func_no,
d3c70a98	59	enum pci_epc_irq_type type, u16 interrupt_num);
5e8cb403 KVA	60	int (start)(struct pci_epc epc);
	61	void (stop)(struct pci_epc epc);
	62	struct module *owner;
	63	};
	64
	65	/**
	66	* struct pci_epc_mem - address space of the endpoint controller
	67	* @phys_base: physical base address of the PCI address space
	68	* @size: the size of the PCI address space
	69	* @bitmap: bitmap to manage the PCI address space
	70	* @pages: number of bits representing the address region
52c9285d	71	* @page_size: size of each page
5e8cb403 KVA	72	*/
	73	struct pci_epc_mem {
	74	phys_addr_t phys_base;
	75	size_t size;
	76	unsigned long *bitmap;
52c9285d	77	size_t page_size;
5e8cb403 KVA	78	int pages;
	79	};
	80
	81	/**
	82	* struct pci_epc - represents the PCI EPC device
	83	* @dev: PCI EPC device
	84	* @pci_epf: list of endpoint functions present in this EPC device
	85	* @ops: function pointers for performing endpoint operations
	86	* @mem: address space of the endpoint controller
	87	* @max_functions: max number of functions that can be configured in this EPC
3a401a2c	88	* @group: configfs group representing the PCI EPC device
5e8cb403 KVA	89	* @lock: spinlock to protect pci_epc ops
	90	*/
	91	struct pci_epc {
	92	struct device dev;
	93	struct list_head pci_epf;
	94	const struct pci_epc_ops *ops;
	95	struct pci_epc_mem *mem;
	96	u8 max_functions;
3a401a2c	97	struct config_group *group;
5e8cb403 KVA	98	/* spinlock to protect against concurrent access of EP controller */
5e8cb403 KVA	99	spinlock_t lock;
1d906b22	100	unsigned int features;
5e8cb403 KVA	101	};
5e8cb403 KVA	102
1d906b22 GP	103	#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
1d906b22 GP	104	#define EPC_FEATURE_BAR_MASK (BIT(1) \| BIT(2) \| BIT(3))
c2e00e31	105	#define EPC_FEATURE_MSIX_AVAILABLE BIT(4)
1d906b22 GP	106	#define EPC_FEATURE_SET_BAR(features, bar) \
	107	(features \|= (EPC_FEATURE_BAR_MASK & (bar << 1)))
	108	#define EPC_FEATURE_GET_BAR(features) \
	109	((features & EPC_FEATURE_BAR_MASK) >> 1)
	110
5e8cb403 KVA	111	#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
	112
	113	#define pci_epc_create(dev, ops) \
	114	__pci_epc_create((dev), (ops), THIS_MODULE)
	115	#define devm_pci_epc_create(dev, ops) \
	116	__devm_pci_epc_create((dev), (ops), THIS_MODULE)
	117
52c9285d KVA	118	#define pci_epc_mem_init(epc, phys_addr, size) \
	119	__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)
	120
5e8cb403 KVA	121	static inline void epc_set_drvdata(struct pci_epc epc, void data)
	122	{
	123	dev_set_drvdata(&epc->dev, data);
	124	}
	125
	126	static inline void epc_get_drvdata(struct pci_epc epc)
	127	{
	128	return dev_get_drvdata(&epc->dev);
	129	}
	130
	131	struct pci_epc *
	132	__devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	133	struct module *owner);
	134	struct pci_epc *
	135	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	136	struct module *owner);
	137	void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
	138	void pci_epc_destroy(struct pci_epc *epc);
	139	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf);
	140	void pci_epc_linkup(struct pci_epc *epc);
	141	void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf);
4494738d CP	142	int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
	143	struct pci_epf_header *hdr);
	144	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
bc4a4897	145	struct pci_epf_bar *epf_bar);
77d08dbd NC	146	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
77d08dbd NC	147	struct pci_epf_bar *epf_bar);
4494738d CP	148	int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
4494738d CP	149	phys_addr_t phys_addr,
5e8cb403	150	u64 pci_addr, size_t size);
4494738d CP	151	void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
	152	phys_addr_t phys_addr);
	153	int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
	154	int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
8963106e GP	155	int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
8963106e GP	156	int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
4494738d	157	int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
d3c70a98	158	enum pci_epc_irq_type type, u16 interrupt_num);
5e8cb403 KVA	159	int pci_epc_start(struct pci_epc *epc);
	160	void pci_epc_stop(struct pci_epc *epc);
	161	struct pci_epc pci_epc_get(const char epc_name);
	162	void pci_epc_put(struct pci_epc *epc);
	163
52c9285d KVA	164	int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
52c9285d KVA	165	size_t page_size);
5e8cb403 KVA	166	void pci_epc_mem_exit(struct pci_epc *epc);
	167	void __iomem pci_epc_mem_alloc_addr(struct pci_epc epc,
	168	phys_addr_t *phys_addr, size_t size);
	169	void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
	170	void __iomem *virt_addr, size_t size);
	171	#endif /* __LINUX_PCI_EPC_H */