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8cfab3cf | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
35ff9477 J |
2 | /* |
3 | * Copyright 2016 Broadcom | |
35ff9477 J |
4 | */ |
5 | #ifndef DRIVERS_PCI_ECAM_H | |
6 | #define DRIVERS_PCI_ECAM_H | |
7 | ||
41334f54 | 8 | #include <linux/pci.h> |
35ff9477 J |
9 | #include <linux/kernel.h> |
10 | #include <linux/platform_device.h> | |
11 | ||
12 | /* | |
13 | * struct to hold pci ops and bus shift of the config window | |
14 | * for a PCI controller. | |
15 | */ | |
16 | struct pci_config_window; | |
17 | struct pci_ecam_ops { | |
18 | unsigned int bus_shift; | |
19 | struct pci_ops pci_ops; | |
5c3d14f7 | 20 | int (*init)(struct pci_config_window *); |
35ff9477 J |
21 | }; |
22 | ||
23 | /* | |
24 | * struct to hold the mappings of a config space window. This | |
25 | * is expected to be used as sysdata for PCI controllers that | |
26 | * use ECAM. | |
27 | */ | |
28 | struct pci_config_window { | |
29 | struct resource res; | |
30 | struct resource busr; | |
31 | void *priv; | |
0b104773 | 32 | const struct pci_ecam_ops *ops; |
35ff9477 J |
33 | union { |
34 | void __iomem *win; /* 64-bit single mapping */ | |
35 | void __iomem **winp; /* 32-bit per-bus mapping */ | |
36 | }; | |
5c3d14f7 | 37 | struct device *parent;/* ECAM res was from this dev */ |
35ff9477 J |
38 | }; |
39 | ||
40 | /* create and free pci_config_window */ | |
41 | struct pci_config_window *pci_ecam_create(struct device *dev, | |
42 | struct resource *cfgres, struct resource *busr, | |
0b104773 | 43 | const struct pci_ecam_ops *ops); |
35ff9477 J |
44 | void pci_ecam_free(struct pci_config_window *cfg); |
45 | ||
46 | /* map_bus when ->sysdata is an instance of pci_config_window */ | |
47 | void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, | |
48 | int where); | |
49 | /* default ECAM ops */ | |
0b104773 | 50 | extern const struct pci_ecam_ops pci_generic_ecam_ops; |
35ff9477 | 51 | |
2ca5b8dd | 52 | #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) |
0b104773 RH |
53 | extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */ |
54 | extern const struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */ | |
55 | extern const struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */ | |
56 | extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */ | |
57 | extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */ | |
58 | extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ | |
59 | extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */ | |
2ca5b8dd CC |
60 | #endif |
61 | ||
0c59c06a | 62 | #if IS_ENABLED(CONFIG_PCI_HOST_COMMON) |
1958e717 J |
63 | /* for DT-based PCI controllers that support ECAM */ |
64 | int pci_host_common_probe(struct platform_device *pdev, | |
0b104773 | 65 | const struct pci_ecam_ops *ops); |
01fcb7f7 | 66 | int pci_host_common_remove(struct platform_device *pdev); |
1958e717 | 67 | #endif |
35ff9477 | 68 | #endif |