[linux-2.6-block.git] / include / linux / omap-gpmc.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  OMAP GPMC (General Purpose Memory Controller) defines
 */

#include <linux/platform_data/gpmc-omap.h>

#define GPMC_CONFIG_WP		0x00000005

/* IRQ numbers in GPMC IRQ domain for legacy boot use */
#define GPMC_IRQ_FIFOEVENTENABLE	0
#define GPMC_IRQ_COUNT_EVENT		1

/**
 * gpmc_nand_ops - Interface between NAND and GPMC
 * @nand_write_buffer_empty: get the NAND write buffer empty status.
 */
struct gpmc_nand_ops {
	bool (*nand_writebuffer_empty)(void);
};

struct gpmc_nand_regs;

struct gpmc_onenand_info {
	bool sync_read;
	bool sync_write;
	int burst_len;
};

#if IS_ENABLED(CONFIG_OMAP_GPMC)
struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
					     int cs);
/**
 * gpmc_omap_onenand_set_timings - set optimized sync timings.
 * @cs:      Chip Select Region
 * @freq:    Chip frequency
 * @latency: Burst latency cycle count
 * @info:    Structure describing parameters used
 *
 * Sets optimized timings for the @cs region based on @freq and @latency.
 * Updates the @info structure based on the GPMC settings.
 */
int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
				  int latency,
				  struct gpmc_onenand_info *info);

#else
static inline struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
							   int cs)
{
	return NULL;
}

static inline
int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
				  int latency,
				  struct gpmc_onenand_info *info)
{
	return -EINVAL;
}
#endif /* CONFIG_OMAP_GPMC */

extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
			     struct gpmc_settings *gpmc_s,
			     struct gpmc_device_timings *dev_t);

struct device_node;

extern int gpmc_get_client_irq(unsigned irq_config);

extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);

extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
extern int gpmc_calc_divider(unsigned int sync_clk);
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
			       const struct gpmc_settings *s);
extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
extern void gpmc_cs_free(int cs);
extern int gpmc_configure(int cmd, int wval);
extern void gpmc_read_settings_dt(struct device_node *np,
				  struct gpmc_settings *p);

struct gpmc_timings;
struct omap_nand_platform_data;
struct omap_onenand_platform_data;

#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern int gpmc_onenand_init(struct omap_onenand_platform_data *d);
#else
#define board_onenand_data	NULL
static inline int gpmc_onenand_init(struct omap_onenand_platform_data *d)
{
	return 0;
}
#endif
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
e639cd5b TL	2	/*
e639cd5b TL	3	* OMAP GPMC (General Purpose Memory Controller) defines
e639cd5b TL	4	*/
e639cd5b TL	5
58bc67fc	6	#include <linux/platform_data/gpmc-omap.h>
e639cd5b TL	7
	8	#define GPMC_CONFIG_WP 0x00000005
	9
384258f2 RQ	10	/* IRQ numbers in GPMC IRQ domain for legacy boot use */
	11	#define GPMC_IRQ_FIFOEVENTENABLE 0
	12	#define GPMC_IRQ_COUNT_EVENT 1
e639cd5b	13
f47fcad6 RQ	14	/**
	15	* gpmc_nand_ops - Interface between NAND and GPMC
	16	* @nand_write_buffer_empty: get the NAND write buffer empty status.
	17	*/
	18	struct gpmc_nand_ops {
	19	bool (*nand_writebuffer_empty)(void);
	20	};
	21
	22	struct gpmc_nand_regs;
	23
a758f50f LM	24	struct gpmc_onenand_info {
	25	bool sync_read;
	26	bool sync_write;
	27	int burst_len;
	28	};
	29
f47fcad6 RQ	30	#if IS_ENABLED(CONFIG_OMAP_GPMC)
	31	struct gpmc_nand_ops gpmc_omap_get_nand_ops(struct gpmc_nand_regs regs,
	32	int cs);
a758f50f LM	33	/**
	34	* gpmc_omap_onenand_set_timings - set optimized sync timings.
	35	* @cs: Chip Select Region
	36	* @freq: Chip frequency
	37	* @latency: Burst latency cycle count
	38	* @info: Structure describing parameters used
	39	*
	40	* Sets optimized timings for the @cs region based on @freq and @latency.
	41	* Updates the @info structure based on the GPMC settings.
	42	*/
	43	int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
	44	int latency,
	45	struct gpmc_onenand_info *info);
	46
f47fcad6	47	#else
0680b0ca RQ	48	static inline struct gpmc_nand_ops gpmc_omap_get_nand_ops(struct gpmc_nand_regs regs,
0680b0ca RQ	49	int cs)
f47fcad6 RQ	50	{
	51	return NULL;
	52	}
a758f50f LM	53
	54	static inline
	55	int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
	56	int latency,
	57	struct gpmc_onenand_info *info)
	58	{
	59	return -EINVAL;
	60	}
f47fcad6 RQ	61	#endif /* CONFIG_OMAP_GPMC */
f47fcad6 RQ	62
e639cd5b TL	63	extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
	64	struct gpmc_settings *gpmc_s,
	65	struct gpmc_device_timings *dev_t);
	66
e639cd5b TL	67	struct device_node;
e639cd5b TL	68
e639cd5b TL	69	extern int gpmc_get_client_irq(unsigned irq_config);
	70
	71	extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
	72
	73	extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
	74	extern int gpmc_calc_divider(unsigned int sync_clk);
2e676901 RA	75	extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
2e676901 RA	76	const struct gpmc_settings *s);
e639cd5b TL	77	extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
	78	extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
	79	extern void gpmc_cs_free(int cs);
	80	extern int gpmc_configure(int cmd, int wval);
	81	extern void gpmc_read_settings_dt(struct device_node *np,
	82	struct gpmc_settings *p);
	83
e639cd5b TL	84	struct gpmc_timings;
	85	struct omap_nand_platform_data;
	86	struct omap_onenand_platform_data;
	87
e639cd5b	88	#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
7807e086	89	extern int gpmc_onenand_init(struct omap_onenand_platform_data *d);
e639cd5b TL	90	#else
e639cd5b TL	91	#define board_onenand_data NULL
7807e086	92	static inline int gpmc_onenand_init(struct omap_onenand_platform_data *d)
e639cd5b	93	{
7807e086	94	return 0;
e639cd5b TL	95	}
e639cd5b TL	96	#endif