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nvmet: unify aer type enum
[linux-2.6-block.git] / include / linux / nvme.h
CommitLineData
fadccd8f 1/* SPDX-License-Identifier: GPL-2.0 */
b60503ba
MW		 2/*
3 * Definitions for the NVM Express interface
8757ad65 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
685e6311 10#include <linux/bits.h>
2812dfe3 11#include <linux/types.h>
8e412263 12#include <linux/uuid.h>
eb793e2c
CH		 13
14/* NQN names in commands fields specified one size */
15#define NVMF_NQN_FIELD_LEN 256
16
17/* However the max length of a qualified name is another size */
18#define NVMF_NQN_SIZE 223
19
20#define NVMF_TRSVCID_SIZE 32
21#define NVMF_TRADDR_SIZE 256
22#define NVMF_TSAS_SIZE 256
23
24#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26#define NVME_RDMA_IP_PORT 4420
27
62346eae
AD		 28#define NVME_NSID_ALL 0xffffffff
29
eb793e2c 30enum nvme_subsys_type {
785d584c
HR		 31 /* Referral to another discovery type target subsystem */
32 NVME_NQN_DISC = 1,
33
34 /* NVME type target subsystem */
35 NVME_NQN_NVME = 2,
36
37 /* Current discovery type target subsystem */
38 NVME_NQN_CURR = 3,
eb793e2c
CH		 39};
40
e15a8a97
HR		 41enum nvme_ctrl_type {
42 NVME_CTRL_IO = 1, /* I/O controller */
43 NVME_CTRL_DISC = 2, /* Discovery controller */
44 NVME_CTRL_ADMIN = 3, /* Administrative controller */
45};
46
86c2457a
MB		 47enum nvme_dctype {
48 NVME_DCTYPE_NOT_REPORTED = 0,
49 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
50 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
51};
52
eb793e2c
CH		 53/* Address Family codes for Discovery Log Page entry ADRFAM field */
54enum {
55 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
56 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
57 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
58 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
59 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
d02abd19
CK		 60 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
61 NVMF_ADDR_FAMILY_MAX,
eb793e2c
CH		 62};
63
64/* Transport Type codes for Discovery Log Page entry TRTYPE field */
65enum {
66 NVMF_TRTYPE_RDMA = 1, /* RDMA */
67 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
fc221d05 68 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
eb793e2c
CH		 69 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
70 NVMF_TRTYPE_MAX,
71};
72
73/* Transport Requirements codes for Discovery Log Page entry TREQ field */
74enum {
9b95d2fb
SG		 75 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
76 NVMF_TREQ_REQUIRED = 1, /* Required */
77 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 78#define NVME_TREQ_SECURE_CHANNEL_MASK \
79 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
9b95d2fb
SG		 80
81 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
eb793e2c
CH		 82};
83
84/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
85 * RDMA_QPTYPE field
86 */
87enum {
bf17aa36
RD		 88 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
89 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 90};
91
92/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
93 * RDMA_QPTYPE field
94 */
95enum {
bf17aa36
RD		 96 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
97 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
98 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
99 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
100 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 101};
102
103/* RDMA Connection Management Service Type codes for Discovery Log Page
104 * entry TSAS RDMA_CMS field
105 */
106enum {
bf17aa36 107 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 108};
109
646f45b2
HR		 110/* TSAS SECTYPE for TCP transport */
111enum {
112 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
113 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
114 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
115};
116
7aa1f427 117#define NVME_AQ_DEPTH 32
38dabe21
KB		 118#define NVME_NR_AEN_COMMANDS 1
119#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
120
121/*
122 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
123 * NVM-Express 1.2 specification, section 4.1.2.
124 */
125#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 126
7a67cbea
CH		 127enum {
128 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
129 NVME_REG_VS = 0x0008, /* Version */
130 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 131 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 132 NVME_REG_CC = 0x0014, /* Controller Configuration */
133 NVME_REG_CSTS = 0x001c, /* Controller Status */
134 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
135 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
136 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 137 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
48c9e85b 138 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea 139 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
48c9e85b
RR		 140 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
141 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
142 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
143 * Location
144 */
20d3bb92
KJ		 145 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
146 * Space Control
147 */
354201c5 148 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
48c9e85b
RR		 149 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
150 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
151 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
152 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
153 * Buffer Size
154 */
155 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
156 * Write Throughput
157 */
97f6ef64 158 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 159};
160
a0cadb85 161#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 162#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 163#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 164#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
71010c30 165#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
8fc23e03 166#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 167#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
20d3bb92 168#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
22605f96 169
8ffaadf7
JD		 170#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
171#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598 172
354201c5
CH		 173#define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
174#define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
175
88de4598
CH		 176enum {
177 NVME_CMBSZ_SQS = 1 << 0,
178 NVME_CMBSZ_CQS = 1 << 1,
179 NVME_CMBSZ_LISTS = 1 << 2,
180 NVME_CMBSZ_RDS = 1 << 3,
181 NVME_CMBSZ_WDS = 1 << 4,
182
183 NVME_CMBSZ_SZ_SHIFT = 12,
184 NVME_CMBSZ_SZ_MASK = 0xfffff,
185
186 NVME_CMBSZ_SZU_SHIFT = 8,
187 NVME_CMBSZ_SZU_MASK = 0xf,
188};
8ffaadf7 189
69cd27e2
CH		 190/*
191 * Submission and Completion Queue Entry Sizes for the NVM command set.
192 * (In bytes and specified as a power of two (2^n)).
193 */
c1e0cc7e 194#define NVME_ADM_SQES 6
69cd27e2
CH		 195#define NVME_NVM_IOSQES 6
196#define NVME_NVM_IOCQES 4
197
b60503ba
MW		 198enum {
199 NVME_CC_ENABLE = 1 << 0,
ad4e05b2
MG		 200 NVME_CC_EN_SHIFT = 0,
201 NVME_CC_CSS_SHIFT = 4,
b60503ba 202 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 203 NVME_CC_AMS_SHIFT = 11,
204 NVME_CC_SHN_SHIFT = 14,
205 NVME_CC_IOSQES_SHIFT = 16,
206 NVME_CC_IOCQES_SHIFT = 20,
71010c30
NC		 207 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
208 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
209 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
60b43f62
MG		 210 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
211 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
212 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 213 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
214 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
215 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
216 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
217 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
218 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
354201c5 219 NVME_CC_CRIME = 1 << 24,
e626f37e
CH		 220};
221
222enum {
b60503ba
MW		 223 NVME_CSTS_RDY = 1 << 0,
224 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 225 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 226 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 227 NVME_CSTS_SHST_NORMAL = 0 << 2,
228 NVME_CSTS_SHST_OCCUR = 1 << 2,
229 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 230 NVME_CSTS_SHST_MASK = 3 << 2,
e626f37e
CH		 231};
232
233enum {
20d3bb92
KJ		 234 NVME_CMBMSC_CRE = 1 << 0,
235 NVME_CMBMSC_CMSE = 1 << 1,
b60503ba
MW		 236};
237
e626f37e
CH		 238enum {
239 NVME_CAP_CSS_NVM = 1 << 0,
240 NVME_CAP_CSS_CSI = 1 << 6,
241};
242
354201c5 243enum {
23c9cd56
JG		 244 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
245 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
354201c5
CH		 246};
247
9d99a8dd
CH		 248struct nvme_id_power_state {
249 __le16 max_power; /* centiwatts */
250 __u8 rsvd2;
251 __u8 flags;
252 __le32 entry_lat; /* microseconds */
253 __le32 exit_lat; /* microseconds */
254 __u8 read_tput;
255 __u8 read_lat;
256 __u8 write_tput;
257 __u8 write_lat;
258 __le16 idle_power;
259 __u8 idle_scale;
260 __u8 rsvd19;
261 __le16 active_power;
262 __u8 active_work_scale;
263 __u8 rsvd23[9];
264};
265
266enum {
267 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
268 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
269};
270
12b21171
SG		 271enum nvme_ctrl_attr {
272 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 273 NVME_CTRL_ATTR_TBKAS = (1 << 6),
4020aad8 274 NVME_CTRL_ATTR_ELBAS = (1 << 15),
12b21171
SG		 275};
276
9d99a8dd
CH		 277struct nvme_id_ctrl {
278 __le16 vid;
279 __le16 ssvid;
280 char sn[20];
281 char mn[40];
282 char fr[8];
283 __u8 rab;
284 __u8 ieee[3];
a446c084 285 __u8 cmic;
9d99a8dd 286 __u8 mdts;
08c69640
CH		 287 __le16 cntlid;
288 __le32 ver;
14e974a8
CH		 289 __le32 rtd3r;
290 __le32 rtd3e;
291 __le32 oaes;
eb793e2c 292 __le32 ctratt;
e15a8a97
HR		 293 __u8 rsvd100[11];
294 __u8 cntrltype;
295 __u8 fguid[16];
49cd84b6
KB		 296 __le16 crdt1;
297 __le16 crdt2;
298 __le16 crdt3;
299 __u8 rsvd134[122];
9d99a8dd
CH		 300 __le16 oacs;
301 __u8 acl;
302 __u8 aerl;
303 __u8 frmw;
304 __u8 lpa;
305 __u8 elpe;
306 __u8 npss;
307 __u8 avscc;
308 __u8 apsta;
309 __le16 wctemp;
310 __le16 cctemp;
a446c084
CH		 311 __le16 mtfa;
312 __le32 hmpre;
313 __le32 hmmin;
314 __u8 tnvmcap[16];
315 __u8 unvmcap[16];
316 __le32 rpmbs;
435e8090
GJ		 317 __le16 edstt;
318 __u8 dsto;
319 __u8 fwug;
7b89eae2 320 __le16 kas;
435e8090
GJ		 321 __le16 hctma;
322 __le16 mntmt;
323 __le16 mxtmt;
324 __le32 sanicap;
044a9df1
CH		 325 __le32 hmminds;
326 __le16 hmmaxd;
1a376216
CH		 327 __u8 rsvd338[4];
328 __u8 anatt;
329 __u8 anacap;
330 __le32 anagrpmax;
331 __le32 nanagrpid;
332 __u8 rsvd352[160];
9d99a8dd
CH		 333 __u8 sqes;
334 __u8 cqes;
eb793e2c 335 __le16 maxcmd;
9d99a8dd
CH		 336 __le32 nn;
337 __le16 oncs;
338 __le16 fuses;
339 __u8 fna;
340 __u8 vwc;
341 __le16 awun;
342 __le16 awupf;
343 __u8 nvscc;
93045d59 344 __u8 nwpc;
9d99a8dd
CH		 345 __le16 acwu;
346 __u8 rsvd534[2];
347 __le32 sgls;
1a376216
CH		 348 __le32 mnan;
349 __u8 rsvd544[224];
eb793e2c
CH		 350 char subnqn[256];
351 __u8 rsvd1024[768];
352 __le32 ioccsz;
353 __le32 iorcsz;
354 __le16 icdoff;
355 __u8 ctrattr;
356 __u8 msdbd;
86c2457a
MB		 357 __u8 rsvd1804[2];
358 __u8 dctype;
359 __u8 rsvd1807[241];
9d99a8dd
CH		 360 struct nvme_id_power_state psd[32];
361 __u8 vs[1024];
362};
363
364enum {
d56ae18f 365 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
92decf11
KB		 366 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
367 NVME_CTRL_CMIC_ANA = 1 << 3,
9d99a8dd
CH		 368 NVME_CTRL_ONCS_COMPARE = 1 << 0,
369 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
370 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 371 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
c1fef73f 372 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
dbf86b39 373 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 374 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 375 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
5974ea7c 376 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
f5d11840 377 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 378 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 379 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
48c9e85b
RR		 380 NVME_CTRL_CTRATT_128_ID = 1 << 0,
381 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
382 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
383 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
384 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
385 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
386 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
387 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
9d99a8dd
CH		 388};
389
390struct nvme_lbaf {
391 __le16 ms;
392 __u8 ds;
393 __u8 rp;
394};
395
396struct nvme_id_ns {
397 __le64 nsze;
398 __le64 ncap;
399 __le64 nuse;
400 __u8 nsfeat;
401 __u8 nlbaf;
402 __u8 flbas;
403 __u8 mc;
404 __u8 dpc;
405 __u8 dps;
406 __u8 nmic;
407 __u8 rescap;
408 __u8 fpi;
6605bdd5 409 __u8 dlfeat;
9d99a8dd
CH		 410 __le16 nawun;
411 __le16 nawupf;
412 __le16 nacwu;
413 __le16 nabsn;
414 __le16 nabo;
415 __le16 nabspf;
6b8190d6 416 __le16 noiob;
a446c084 417 __u8 nvmcap[16];
6605bdd5
BVA		 418 __le16 npwg;
419 __le16 npwa;
420 __le16 npdg;
421 __le16 npda;
422 __le16 nows;
423 __u8 rsvd74[18];
1a376216 424 __le32 anagrpid;
93045d59
CK		 425 __u8 rsvd96[3];
426 __u8 nsattr;
6605bdd5
BVA		 427 __le16 nvmsetid;
428 __le16 endgid;
9d99a8dd
CH		 429 __u8 nguid[16];
430 __u8 eui64[8];
4020aad8 431 struct nvme_lbaf lbaf[64];
9d99a8dd
CH		 432 __u8 vs[3712];
433};
434
354201c5
CH		 435/* I/O Command Set Independent Identify Namespace Data Structure */
436struct nvme_id_ns_cs_indep {
437 __u8 nsfeat;
438 __u8 nmic;
439 __u8 rescap;
440 __u8 fpi;
441 __le32 anagrpid;
442 __u8 nsattr;
443 __u8 rsvd9;
444 __le16 nvmsetid;
445 __le16 endgid;
446 __u8 nstat;
447 __u8 rsvd15[4081];
448};
449
240e6ee2
KB		 450struct nvme_zns_lbafe {
451 __le64 zsze;
452 __u8 zdes;
453 __u8 rsvd9[7];
454};
455
456struct nvme_id_ns_zns {
457 __le16 zoc;
458 __le16 ozcs;
459 __le32 mar;
460 __le32 mor;
461 __le32 rrl;
462 __le32 frl;
463 __u8 rsvd20[2796];
4020aad8 464 struct nvme_zns_lbafe lbafe[64];
240e6ee2
KB		 465 __u8 vs[256];
466};
467
468struct nvme_id_ctrl_zns {
469 __u8 zasl;
470 __u8 rsvd1[4095];
471};
472
4020aad8
KB		 473struct nvme_id_ns_nvm {
474 __le64 lbstm;
475 __u8 pic;
476 __u8 rsvd9[3];
477 __le32 elbaf[64];
478 __u8 rsvd268[3828];
479};
480
481enum {
b938e660 482 NVME_ID_NS_NVM_STS_MASK = 0x7f,
4020aad8
KB		 483 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
484 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
485};
486
487static inline __u8 nvme_elbaf_sts(__u32 elbaf)
488{
489 return elbaf & NVME_ID_NS_NVM_STS_MASK;
490}
491
492static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
493{
494 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
495}
496
5befc7c2
KB		 497struct nvme_id_ctrl_nvm {
498 __u8 vsl;
499 __u8 wzsl;
500 __u8 wusl;
501 __u8 dmrl;
502 __le32 dmrsl;
503 __le64 dmsl;
504 __u8 rsvd16[4080];
505};
506
329dd768
CH		 507enum {
508 NVME_ID_CNS_NS = 0x00,
509 NVME_ID_CNS_CTRL = 0x01,
510 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 511 NVME_ID_CNS_NS_DESC_LIST = 0x03,
71010c30
NC		 512 NVME_ID_CNS_CS_NS = 0x05,
513 NVME_ID_CNS_CS_CTRL = 0x06,
354201c5 514 NVME_ID_CNS_NS_CS_INDEP = 0x08,
329dd768
CH		 515 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
516 NVME_ID_CNS_NS_PRESENT = 0x11,
517 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
518 NVME_ID_CNS_CTRL_LIST = 0x13,
48c9e85b
RR		 519 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
520 NVME_ID_CNS_NS_GRANULARITY = 0x16,
521 NVME_ID_CNS_UUID_LIST = 0x17,
329dd768
CH		 522};
523
71010c30
NC		 524enum {
525 NVME_CSI_NVM = 0,
240e6ee2 526 NVME_CSI_ZNS = 2,
71010c30
NC		 527};
528
f5d11840
JA		 529enum {
530 NVME_DIR_IDENTIFY = 0x00,
531 NVME_DIR_STREAMS = 0x01,
532 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
533 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
534 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
535 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
536 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
537 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
538 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
539 NVME_DIR_ENDIR = 0x01,
540};
541
9d99a8dd
CH		 542enum {
543 NVME_NS_FEAT_THIN = 1 << 0,
92decf11
KB		 544 NVME_NS_FEAT_ATOMICS = 1 << 1,
545 NVME_NS_FEAT_IO_OPT = 1 << 4,
546 NVME_NS_ATTR_RO = 1 << 0,
9d99a8dd 547 NVME_NS_FLBAS_LBA_MASK = 0xf,
4020aad8
KB		 548 NVME_NS_FLBAS_LBA_UMASK = 0x60,
549 NVME_NS_FLBAS_LBA_SHIFT = 1,
9d99a8dd 550 NVME_NS_FLBAS_META_EXT = 0x10,
92decf11 551 NVME_NS_NMIC_SHARED = 1 << 0,
9d99a8dd
CH		 552 NVME_LBAF_RP_BEST = 0,
553 NVME_LBAF_RP_BETTER = 1,
554 NVME_LBAF_RP_GOOD = 2,
555 NVME_LBAF_RP_DEGRADED = 3,
556 NVME_NS_DPC_PI_LAST = 1 << 4,
557 NVME_NS_DPC_PI_FIRST = 1 << 3,
558 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
559 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
560 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
561 NVME_NS_DPS_PI_FIRST = 1 << 3,
562 NVME_NS_DPS_PI_MASK = 0x7,
563 NVME_NS_DPS_PI_TYPE1 = 1,
564 NVME_NS_DPS_PI_TYPE2 = 2,
565 NVME_NS_DPS_PI_TYPE3 = 3,
566};
567
354201c5
CH		 568enum {
569 NVME_NSTAT_NRDY = 1 << 0,
570};
571
4020aad8
KB		 572enum {
573 NVME_NVM_NS_16B_GUARD = 0,
574 NVME_NVM_NS_32B_GUARD = 1,
575 NVME_NVM_NS_64B_GUARD = 2,
576};
577
578static inline __u8 nvme_lbaf_index(__u8 flbas)
579{
580 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
581 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
582}
583
39481fbd
IR		 584/* Identify Namespace Metadata Capabilities (MC): */
585enum {
586 NVME_MC_EXTENDED_LBA = (1 << 0),
587 NVME_MC_METADATA_PTR = (1 << 1),
588};
589
af8b86e9
JT		 590struct nvme_ns_id_desc {
591 __u8 nidt;
592 __u8 nidl;
593 __le16 reserved;
594};
595
596#define NVME_NIDT_EUI64_LEN 8
597#define NVME_NIDT_NGUID_LEN 16
598#define NVME_NIDT_UUID_LEN 16
71010c30 599#define NVME_NIDT_CSI_LEN 1
af8b86e9
JT		 600
601enum {
602 NVME_NIDT_EUI64 = 0x01,
603 NVME_NIDT_NGUID = 0x02,
604 NVME_NIDT_UUID = 0x03,
71010c30 605 NVME_NIDT_CSI = 0x04,
af8b86e9
JT		 606};
607
9d99a8dd
CH		 608struct nvme_smart_log {
609 __u8 critical_warning;
610 __u8 temperature[2];
611 __u8 avail_spare;
612 __u8 spare_thresh;
613 __u8 percent_used;
48c9e85b
RR		 614 __u8 endu_grp_crit_warn_sumry;
615 __u8 rsvd7[25];
9d99a8dd
CH		 616 __u8 data_units_read[16];
617 __u8 data_units_written[16];
618 __u8 host_reads[16];
619 __u8 host_writes[16];
620 __u8 ctrl_busy_time[16];
621 __u8 power_cycles[16];
622 __u8 power_on_hours[16];
623 __u8 unsafe_shutdowns[16];
624 __u8 media_errors[16];
625 __u8 num_err_log_entries[16];
626 __le32 warning_temp_time;
627 __le32 critical_comp_time;
628 __le16 temp_sensor[8];
48c9e85b
RR		 629 __le32 thm_temp1_trans_count;
630 __le32 thm_temp2_trans_count;
631 __le32 thm_temp1_total_time;
632 __le32 thm_temp2_total_time;
633 __u8 rsvd232[280];
9d99a8dd
CH		 634};
635
b6dccf7f
AD		 636struct nvme_fw_slot_info_log {
637 __u8 afi;
638 __u8 rsvd1[7];
639 __le64 frs[7];
640 __u8 rsvd64[448];
641};
642
84fef62d
KB		 643enum {
644 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
645 NVME_CMD_EFFECTS_LBCC = 1 << 1,
646 NVME_CMD_EFFECTS_NCC = 1 << 2,
647 NVME_CMD_EFFECTS_NIC = 1 << 3,
648 NVME_CMD_EFFECTS_CCC = 1 << 4,
685e6311 649 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
48c9e85b 650 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
6f99ac04 651 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
84fef62d
KB		 652};
653
654struct nvme_effects_log {
655 __le32 acs[256];
656 __le32 iocs[256];
657 __u8 resv[2048];
658};
659
1a376216
CH		 660enum nvme_ana_state {
661 NVME_ANA_OPTIMIZED = 0x01,
662 NVME_ANA_NONOPTIMIZED = 0x02,
663 NVME_ANA_INACCESSIBLE = 0x03,
664 NVME_ANA_PERSISTENT_LOSS = 0x04,
665 NVME_ANA_CHANGE = 0x0f,
666};
667
668struct nvme_ana_group_desc {
669 __le32 grpid;
670 __le32 nnsids;
671 __le64 chgcnt;
672 __u8 state;
8b92d0e3 673 __u8 rsvd17[15];
1a376216
CH		 674 __le32 nsids[];
675};
676
677/* flag for the log specific field of the ANA log */
678#define NVME_ANA_LOG_RGO (1 << 0)
679
680struct nvme_ana_rsp_hdr {
681 __le64 chgcnt;
682 __le16 ngrps;
683 __le16 rsvd10[3];
684};
685
240e6ee2
KB		 686struct nvme_zone_descriptor {
687 __u8 zt;
688 __u8 zs;
689 __u8 za;
690 __u8 rsvd3[5];
691 __le64 zcap;
692 __le64 zslba;
693 __le64 wp;
694 __u8 rsvd32[32];
695};
696
697enum {
698 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
699};
700
701struct nvme_zone_report {
702 __le64 nr_zones;
703 __u8 resv8[56];
704 struct nvme_zone_descriptor entries[];
705};
706
9d99a8dd
CH		 707enum {
708 NVME_SMART_CRIT_SPARE = 1 << 0,
709 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
710 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
711 NVME_SMART_CRIT_MEDIA = 1 << 3,
712 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
713};
714
715enum {
e3d7874d
KB		 716 NVME_AER_ERROR = 0,
717 NVME_AER_SMART = 1,
868c2392 718 NVME_AER_NOTICE = 2,
e3d7874d
KB		 719 NVME_AER_CSS = 6,
720 NVME_AER_VS = 7,
868c2392
CH		 721};
722
2c61c97f
MK		 723enum {
724 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
725};
726
868c2392
CH		 727enum {
728 NVME_AER_NOTICE_NS_CHANGED = 0x00,
729 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 730 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 731 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 732};
733
aafd3afe 734enum {
7114ddeb
JS		 735 NVME_AEN_BIT_NS_ATTR = 8,
736 NVME_AEN_BIT_FW_ACT = 9,
737 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 738 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 739};
740
741enum {
742 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
743 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
744 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 745 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 746};
747
9d99a8dd
CH		 748struct nvme_lba_range_type {
749 __u8 type;
750 __u8 attributes;
751 __u8 rsvd2[14];
8cf486e1
WS		 752 __le64 slba;
753 __le64 nlb;
9d99a8dd
CH		 754 __u8 guid[16];
755 __u8 rsvd48[16];
756};
757
758enum {
759 NVME_LBART_TYPE_FS = 0x01,
760 NVME_LBART_TYPE_RAID = 0x02,
761 NVME_LBART_TYPE_CACHE = 0x03,
762 NVME_LBART_TYPE_SWAP = 0x04,
763
764 NVME_LBART_ATTRIB_TEMP = 1 << 0,
765 NVME_LBART_ATTRIB_HIDE = 1 << 1,
766};
767
be1a7cd2
MC		 768enum nvme_pr_type {
769 NVME_PR_WRITE_EXCLUSIVE = 1,
770 NVME_PR_EXCLUSIVE_ACCESS = 2,
771 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
772 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
773 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
774 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
775};
776
5fd96a4e
MC		 777enum nvme_eds {
778 NVME_EXTENDED_DATA_STRUCT = 0x1,
779};
780
f2bf2e7e
MC		 781struct nvme_registered_ctrl {
782 __le16 cntlid;
783 __u8 rcsts;
784 __u8 rsvd3[5];
785 __le64 hostid;
786 __le64 rkey;
787};
788
9d99a8dd
CH		 789struct nvme_reservation_status {
790 __le32 gen;
791 __u8 rtype;
792 __u8 regctl[2];
793 __u8 resv5[2];
794 __u8 ptpls;
f2bf2e7e
MC		 795 __u8 resv10[14];
796 struct nvme_registered_ctrl regctl_ds[];
797};
798
799struct nvme_registered_ctrl_ext {
800 __le16 cntlid;
801 __u8 rcsts;
802 __u8 rsvd3[5];
803 __le64 rkey;
804 __u8 hostid[16];
805 __u8 rsvd32[32];
806};
807
808struct nvme_reservation_status_ext {
809 __le32 gen;
810 __u8 rtype;
811 __u8 regctl[2];
812 __u8 resv5[2];
813 __u8 ptpls;
814 __u8 resv10[14];
815 __u8 rsvd24[40];
816 struct nvme_registered_ctrl_ext regctl_eds[];
9d99a8dd
CH		 817};
818
819/* I/O commands */
820
821enum nvme_opcode {
822 nvme_cmd_flush = 0x00,
823 nvme_cmd_write = 0x01,
824 nvme_cmd_read = 0x02,
825 nvme_cmd_write_uncor = 0x04,
826 nvme_cmd_compare = 0x05,
827 nvme_cmd_write_zeroes = 0x08,
828 nvme_cmd_dsm = 0x09,
48c9e85b 829 nvme_cmd_verify = 0x0c,
9d99a8dd
CH		 830 nvme_cmd_resv_register = 0x0d,
831 nvme_cmd_resv_report = 0x0e,
832 nvme_cmd_resv_acquire = 0x11,
833 nvme_cmd_resv_release = 0x15,
240e6ee2
KB		 834 nvme_cmd_zone_mgmt_send = 0x79,
835 nvme_cmd_zone_mgmt_recv = 0x7a,
836 nvme_cmd_zone_append = 0x7d,
855b7717 837 nvme_cmd_vendor_start = 0x80,
9d99a8dd
CH		 838};
839
26f2990d
MI		 840#define nvme_opcode_name(opcode) { opcode, #opcode }
841#define show_nvm_opcode_name(val) \
842 __print_symbolic(val, \
843 nvme_opcode_name(nvme_cmd_flush), \
844 nvme_opcode_name(nvme_cmd_write), \
845 nvme_opcode_name(nvme_cmd_read), \
846 nvme_opcode_name(nvme_cmd_write_uncor), \
847 nvme_opcode_name(nvme_cmd_compare), \
848 nvme_opcode_name(nvme_cmd_write_zeroes), \
849 nvme_opcode_name(nvme_cmd_dsm), \
8e19b87c 850 nvme_opcode_name(nvme_cmd_verify), \
26f2990d
MI		 851 nvme_opcode_name(nvme_cmd_resv_register), \
852 nvme_opcode_name(nvme_cmd_resv_report), \
853 nvme_opcode_name(nvme_cmd_resv_acquire), \
4a407d5e
JT		 854 nvme_opcode_name(nvme_cmd_resv_release), \
855 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
856 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
857 nvme_opcode_name(nvme_cmd_zone_append))
858
26f2990d
MI		 859
860
eb793e2c
CH		 861/*
862 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
863 *
864 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
865 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 866 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 867 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
868 * request subtype
869 */
870enum {
871 NVME_SGL_FMT_ADDRESS = 0x00,
872 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 873 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 874 NVME_SGL_FMT_INVALIDATE = 0x0f,
875};
876
877/*
878 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
879 *
880 * For struct nvme_sgl_desc:
881 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
882 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
883 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
884 *
885 * For struct nvme_keyed_sgl_desc:
886 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 887 *
888 * Transport-specific SGL types:
889 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 890 */
891enum {
892 NVME_SGL_FMT_DATA_DESC = 0x00,
893 NVME_SGL_FMT_SEG_DESC = 0x02,
894 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
895 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 896 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 897};
898
899struct nvme_sgl_desc {
900 __le64 addr;
901 __le32 length;
902 __u8 rsvd[3];
903 __u8 type;
904};
905
906struct nvme_keyed_sgl_desc {
907 __le64 addr;
908 __u8 length[3];
909 __u8 key[4];
910 __u8 type;
911};
912
913union nvme_data_ptr {
914 struct {
915 __le64 prp1;
916 __le64 prp2;
917 };
918 struct nvme_sgl_desc sgl;
919 struct nvme_keyed_sgl_desc ksgl;
920};
921
3972be23
JS		 922/*
923 * Lowest two bits of our flags field (FUSE field in the spec):
924 *
925 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
926 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
927 *
928 * Highest two bits in our flags field (PSDT field in the spec):
929 *
930 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
931 * If used, MPTR contains addr of single physical buffer (byte aligned).
932 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
933 * If used, MPTR contains an address of an SGL segment containing
934 * exactly 1 SGL descriptor (qword aligned).
935 */
936enum {
937 NVME_CMD_FUSE_FIRST = (1 << 0),
938 NVME_CMD_FUSE_SECOND = (1 << 1),
939
940 NVME_CMD_SGL_METABUF = (1 << 6),
941 NVME_CMD_SGL_METASEG = (1 << 7),
942 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
943};
944
9d99a8dd
CH		 945struct nvme_common_command {
946 __u8 opcode;
947 __u8 flags;
948 __u16 command_id;
949 __le32 nsid;
950 __le32 cdw2[2];
951 __le64 metadata;
eb793e2c 952 union nvme_data_ptr dptr;
5c629dc9 953 struct_group(cdws,
b7c8f366
CK		 954 __le32 cdw10;
955 __le32 cdw11;
956 __le32 cdw12;
957 __le32 cdw13;
958 __le32 cdw14;
959 __le32 cdw15;
5c629dc9 960 );
9d99a8dd
CH		 961};
962
963struct nvme_rw_command {
964 __u8 opcode;
965 __u8 flags;
966 __u16 command_id;
967 __le32 nsid;
4020aad8
KB		 968 __le32 cdw2;
969 __le32 cdw3;
9d99a8dd 970 __le64 metadata;
eb793e2c 971 union nvme_data_ptr dptr;
9d99a8dd
CH		 972 __le64 slba;
973 __le16 length;
974 __le16 control;
975 __le32 dsmgmt;
976 __le32 reftag;
977 __le16 apptag;
978 __le16 appmask;
979};
980
981enum {
982 NVME_RW_LR = 1 << 15,
983 NVME_RW_FUA = 1 << 14,
240e6ee2 984 NVME_RW_APPEND_PIREMAP = 1 << 9,
9d99a8dd
CH		 985 NVME_RW_DSM_FREQ_UNSPEC = 0,
986 NVME_RW_DSM_FREQ_TYPICAL = 1,
987 NVME_RW_DSM_FREQ_RARE = 2,
988 NVME_RW_DSM_FREQ_READS = 3,
989 NVME_RW_DSM_FREQ_WRITES = 4,
990 NVME_RW_DSM_FREQ_RW = 5,
991 NVME_RW_DSM_FREQ_ONCE = 6,
992 NVME_RW_DSM_FREQ_PREFETCH = 7,
993 NVME_RW_DSM_FREQ_TEMP = 8,
994 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
995 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
996 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
997 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
998 NVME_RW_DSM_SEQ_REQ = 1 << 6,
999 NVME_RW_DSM_COMPRESSED = 1 << 7,
1000 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1001 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1002 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1003 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 1004 NVME_RW_DTYPE_STREAMS = 1 << 4,
1b96f862 1005 NVME_WZ_DEAC = 1 << 9,
9d99a8dd
CH		 1006};
1007
1008struct nvme_dsm_cmd {
1009 __u8 opcode;
1010 __u8 flags;
1011 __u16 command_id;
1012 __le32 nsid;
1013 __u64 rsvd2[2];
eb793e2c 1014 union nvme_data_ptr dptr;
9d99a8dd
CH		 1015 __le32 nr;
1016 __le32 attributes;
1017 __u32 rsvd12[4];
1018};
1019
1020enum {
1021 NVME_DSMGMT_IDR = 1 << 0,
1022 NVME_DSMGMT_IDW = 1 << 1,
1023 NVME_DSMGMT_AD = 1 << 2,
1024};
1025
b35ba01e
CH		 1026#define NVME_DSM_MAX_RANGES 256
1027
9d99a8dd
CH		 1028struct nvme_dsm_range {
1029 __le32 cattr;
1030 __le32 nlb;
1031 __le64 slba;
1032};
1033
3b7c33b2
CK		 1034struct nvme_write_zeroes_cmd {
1035 __u8 opcode;
1036 __u8 flags;
1037 __u16 command_id;
1038 __le32 nsid;
1039 __u64 rsvd2;
1040 __le64 metadata;
1041 union nvme_data_ptr dptr;
1042 __le64 slba;
1043 __le16 length;
1044 __le16 control;
1045 __le32 dsmgmt;
1046 __le32 reftag;
1047 __le16 apptag;
1048 __le16 appmask;
1049};
1050
240e6ee2
KB		 1051enum nvme_zone_mgmt_action {
1052 NVME_ZONE_CLOSE = 0x1,
1053 NVME_ZONE_FINISH = 0x2,
1054 NVME_ZONE_OPEN = 0x3,
1055 NVME_ZONE_RESET = 0x4,
1056 NVME_ZONE_OFFLINE = 0x5,
1057 NVME_ZONE_SET_DESC_EXT = 0x10,
1058};
1059
1060struct nvme_zone_mgmt_send_cmd {
1061 __u8 opcode;
1062 __u8 flags;
1063 __u16 command_id;
1064 __le32 nsid;
1065 __le32 cdw2[2];
1066 __le64 metadata;
1067 union nvme_data_ptr dptr;
1068 __le64 slba;
1069 __le32 cdw12;
1070 __u8 zsa;
1071 __u8 select_all;
1072 __u8 rsvd13[2];
1073 __le32 cdw14[2];
1074};
1075
1076struct nvme_zone_mgmt_recv_cmd {
1077 __u8 opcode;
1078 __u8 flags;
1079 __u16 command_id;
1080 __le32 nsid;
1081 __le64 rsvd2[2];
1082 union nvme_data_ptr dptr;
1083 __le64 slba;
1084 __le32 numd;
1085 __u8 zra;
1086 __u8 zrasf;
1087 __u8 pr;
1088 __u8 rsvd13;
1089 __le32 cdw14[2];
1090};
1091
1092enum {
1093 NVME_ZRA_ZONE_REPORT = 0,
1094 NVME_ZRASF_ZONE_REPORT_ALL = 0,
aaf2e048
CK		 1095 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1096 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1097 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1098 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1099 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1100 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1101 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
240e6ee2
KB		 1102 NVME_REPORT_ZONE_PARTIAL = 1,
1103};
1104
c5552fde
AL		 1105/* Features */
1106
52deba0f
AM		 1107enum {
1108 NVME_TEMP_THRESH_MASK = 0xffff,
1109 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1110 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1111};
1112
c5552fde
AL		 1113struct nvme_feat_auto_pst {
1114 __le64 entries[32];
1115};
1116
39673e19
CH		 1117enum {
1118 NVME_HOST_MEM_ENABLE = (1 << 0),
1119 NVME_HOST_MEM_RETURN = (1 << 1),
1120};
1121
49cd84b6
KB		 1122struct nvme_feat_host_behavior {
1123 __u8 acre;
4020aad8
KB		 1124 __u8 etdas;
1125 __u8 lbafee;
1126 __u8 resv1[509];
49cd84b6
KB		 1127};
1128
1129enum {
1130 NVME_ENABLE_ACRE = 1,
4020aad8 1131 NVME_ENABLE_LBAFEE = 1,
49cd84b6
KB		 1132};
1133
9d99a8dd
CH		 1134/* Admin commands */
1135
1136enum nvme_admin_opcode {
1137 nvme_admin_delete_sq = 0x00,
1138 nvme_admin_create_sq = 0x01,
1139 nvme_admin_get_log_page = 0x02,
1140 nvme_admin_delete_cq = 0x04,
1141 nvme_admin_create_cq = 0x05,
1142 nvme_admin_identify = 0x06,
1143 nvme_admin_abort_cmd = 0x08,
1144 nvme_admin_set_features = 0x09,
1145 nvme_admin_get_features = 0x0a,
1146 nvme_admin_async_event = 0x0c,
a446c084 1147 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 1148 nvme_admin_activate_fw = 0x10,
1149 nvme_admin_download_fw = 0x11,
48c9e85b 1150 nvme_admin_dev_self_test = 0x14,
a446c084 1151 nvme_admin_ns_attach = 0x15,
7b89eae2 1152 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 1153 nvme_admin_directive_send = 0x19,
1154 nvme_admin_directive_recv = 0x1a,
48c9e85b
RR		 1155 nvme_admin_virtual_mgmt = 0x1c,
1156 nvme_admin_nvme_mi_send = 0x1d,
1157 nvme_admin_nvme_mi_recv = 0x1e,
f9f38e33 1158 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 1159 nvme_admin_format_nvm = 0x80,
1160 nvme_admin_security_send = 0x81,
1161 nvme_admin_security_recv = 0x82,
84fef62d 1162 nvme_admin_sanitize_nvm = 0x84,
c6389845 1163 nvme_admin_get_lba_status = 0x86,
c1fef73f 1164 nvme_admin_vendor_start = 0xC0,
9d99a8dd
CH		 1165};
1166
26f2990d
MI		 1167#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1168#define show_admin_opcode_name(val) \
1169 __print_symbolic(val, \
1170 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1171 nvme_admin_opcode_name(nvme_admin_create_sq), \
1172 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1173 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1174 nvme_admin_opcode_name(nvme_admin_create_cq), \
1175 nvme_admin_opcode_name(nvme_admin_identify), \
1176 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1177 nvme_admin_opcode_name(nvme_admin_set_features), \
1178 nvme_admin_opcode_name(nvme_admin_get_features), \
1179 nvme_admin_opcode_name(nvme_admin_async_event), \
1180 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1181 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1182 nvme_admin_opcode_name(nvme_admin_download_fw), \
8e19b87c 1183 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
26f2990d
MI		 1184 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1185 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1186 nvme_admin_opcode_name(nvme_admin_directive_send), \
1187 nvme_admin_opcode_name(nvme_admin_directive_recv), \
8e19b87c
MI		 1188 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1189 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1190 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
26f2990d
MI		 1191 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1192 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1193 nvme_admin_opcode_name(nvme_admin_security_send), \
1194 nvme_admin_opcode_name(nvme_admin_security_recv), \
a5ef7572
MI		 1195 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1196 nvme_admin_opcode_name(nvme_admin_get_lba_status))
26f2990d 1197
9d99a8dd
CH		 1198enum {
1199 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1200 NVME_CQ_IRQ_ENABLED = (1 << 1),
1201 NVME_SQ_PRIO_URGENT = (0 << 1),
1202 NVME_SQ_PRIO_HIGH = (1 << 1),
1203 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1204 NVME_SQ_PRIO_LOW = (3 << 1),
1205 NVME_FEAT_ARBITRATION = 0x01,
1206 NVME_FEAT_POWER_MGMT = 0x02,
1207 NVME_FEAT_LBA_RANGE = 0x03,
1208 NVME_FEAT_TEMP_THRESH = 0x04,
1209 NVME_FEAT_ERR_RECOVERY = 0x05,
1210 NVME_FEAT_VOLATILE_WC = 0x06,
1211 NVME_FEAT_NUM_QUEUES = 0x07,
1212 NVME_FEAT_IRQ_COALESCE = 0x08,
1213 NVME_FEAT_IRQ_CONFIG = 0x09,
1214 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1215 NVME_FEAT_ASYNC_EVENT = 0x0b,
1216 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 1217 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 1218 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 1219 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 1220 NVME_FEAT_HCTM = 0x10,
1221 NVME_FEAT_NOPSC = 0x11,
1222 NVME_FEAT_RRL = 0x12,
1223 NVME_FEAT_PLM_CONFIG = 0x13,
1224 NVME_FEAT_PLM_WINDOW = 0x14,
49cd84b6 1225 NVME_FEAT_HOST_BEHAVIOR = 0x16,
48c9e85b 1226 NVME_FEAT_SANITIZE = 0x17,
9d99a8dd
CH		 1227 NVME_FEAT_SW_PROGRESS = 0x80,
1228 NVME_FEAT_HOST_ID = 0x81,
1229 NVME_FEAT_RESV_MASK = 0x82,
1230 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 1231 NVME_FEAT_WRITE_PROTECT = 0x84,
c1fef73f
LG		 1232 NVME_FEAT_VENDOR_START = 0xC0,
1233 NVME_FEAT_VENDOR_END = 0xFF,
9d99a8dd
CH		 1234 NVME_LOG_ERROR = 0x01,
1235 NVME_LOG_SMART = 0x02,
1236 NVME_LOG_FW_SLOT = 0x03,
b3984e06 1237 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 1238 NVME_LOG_CMD_EFFECTS = 0x05,
48c9e85b
RR		 1239 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1240 NVME_LOG_TELEMETRY_HOST = 0x07,
1241 NVME_LOG_TELEMETRY_CTRL = 0x08,
1242 NVME_LOG_ENDURANCE_GROUP = 0x09,
1a376216 1243 NVME_LOG_ANA = 0x0c,
eb793e2c 1244 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 1245 NVME_LOG_RESERVATION = 0x80,
1246 NVME_FWACT_REPL = (0 << 3),
1247 NVME_FWACT_REPL_ACTV = (1 << 3),
1248 NVME_FWACT_ACTV = (2 << 3),
1249};
1250
93045d59
CK		 1251/* NVMe Namespace Write Protect State */
1252enum {
1253 NVME_NS_NO_WRITE_PROTECT = 0,
1254 NVME_NS_WRITE_PROTECT,
1255 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1256 NVME_NS_WRITE_PROTECT_PERMANENT,
1257};
1258
b3984e06
CH		 1259#define NVME_MAX_CHANGED_NAMESPACES 1024
1260
9d99a8dd
CH		 1261struct nvme_identify {
1262 __u8 opcode;
1263 __u8 flags;
1264 __u16 command_id;
1265 __le32 nsid;
1266 __u64 rsvd2[2];
eb793e2c 1267 union nvme_data_ptr dptr;
986994a2
PP		 1268 __u8 cns;
1269 __u8 rsvd3;
1270 __le16 ctrlid;
71010c30
NC		 1271 __u8 rsvd11[3];
1272 __u8 csi;
1273 __u32 rsvd12[4];
9d99a8dd
CH		 1274};
1275
0add5e8e
JT		 1276#define NVME_IDENTIFY_DATA_SIZE 4096
1277
9d99a8dd
CH		 1278struct nvme_features {
1279 __u8 opcode;
1280 __u8 flags;
1281 __u16 command_id;
1282 __le32 nsid;
1283 __u64 rsvd2[2];
eb793e2c 1284 union nvme_data_ptr dptr;
9d99a8dd
CH		 1285 __le32 fid;
1286 __le32 dword11;
b85cf734
AD		 1287 __le32 dword12;
1288 __le32 dword13;
1289 __le32 dword14;
1290 __le32 dword15;
9d99a8dd
CH		 1291};
1292
39673e19
CH		 1293struct nvme_host_mem_buf_desc {
1294 __le64 addr;
1295 __le32 size;
1296 __u32 rsvd;
1297};
1298
9d99a8dd
CH		 1299struct nvme_create_cq {
1300 __u8 opcode;
1301 __u8 flags;
1302 __u16 command_id;
1303 __u32 rsvd1[5];
1304 __le64 prp1;
1305 __u64 rsvd8;
1306 __le16 cqid;
1307 __le16 qsize;
1308 __le16 cq_flags;
1309 __le16 irq_vector;
1310 __u32 rsvd12[4];
1311};
1312
1313struct nvme_create_sq {
1314 __u8 opcode;
1315 __u8 flags;
1316 __u16 command_id;
1317 __u32 rsvd1[5];
1318 __le64 prp1;
1319 __u64 rsvd8;
1320 __le16 sqid;
1321 __le16 qsize;
1322 __le16 sq_flags;
1323 __le16 cqid;
1324 __u32 rsvd12[4];
1325};
1326
1327struct nvme_delete_queue {
1328 __u8 opcode;
1329 __u8 flags;
1330 __u16 command_id;
1331 __u32 rsvd1[9];
1332 __le16 qid;
1333 __u16 rsvd10;
1334 __u32 rsvd11[5];
1335};
1336
1337struct nvme_abort_cmd {
1338 __u8 opcode;
1339 __u8 flags;
1340 __u16 command_id;
1341 __u32 rsvd1[9];
1342 __le16 sqid;
1343 __u16 cid;
1344 __u32 rsvd11[5];
1345};
1346
1347struct nvme_download_firmware {
1348 __u8 opcode;
1349 __u8 flags;
1350 __u16 command_id;
1351 __u32 rsvd1[5];
eb793e2c 1352 union nvme_data_ptr dptr;
9d99a8dd
CH		 1353 __le32 numd;
1354 __le32 offset;
1355 __u32 rsvd12[4];
1356};
1357
1358struct nvme_format_cmd {
1359 __u8 opcode;
1360 __u8 flags;
1361 __u16 command_id;
1362 __le32 nsid;
1363 __u64 rsvd2[4];
1364 __le32 cdw10;
1365 __u32 rsvd11[5];
1366};
1367
725b3588
AB		 1368struct nvme_get_log_page_command {
1369 __u8 opcode;
1370 __u8 flags;
1371 __u16 command_id;
1372 __le32 nsid;
1373 __u64 rsvd2[2];
eb793e2c 1374 union nvme_data_ptr dptr;
725b3588 1375 __u8 lid;
9b89bc38 1376 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 1377 __le16 numdl;
1378 __le16 numdu;
1379 __u16 rsvd11;
d808b7f7
KB		 1380 union {
1381 struct {
1382 __le32 lpol;
1383 __le32 lpou;
1384 };
1385 __le64 lpo;
1386 };
be93e87e
KB		 1387 __u8 rsvd14[3];
1388 __u8 csi;
1389 __u32 rsvd15;
725b3588
AB		 1390};
1391
f5d11840
JA		 1392struct nvme_directive_cmd {
1393 __u8 opcode;
1394 __u8 flags;
1395 __u16 command_id;
1396 __le32 nsid;
1397 __u64 rsvd2[2];
1398 union nvme_data_ptr dptr;
1399 __le32 numd;
1400 __u8 doper;
1401 __u8 dtype;
1402 __le16 dspec;
1403 __u8 endir;
1404 __u8 tdtype;
1405 __u16 rsvd15;
1406
1407 __u32 rsvd16[3];
1408};
1409
eb793e2c
CH		 1410/*
1411 * Fabrics subcommands.
1412 */
1413enum nvmf_fabrics_opcode {
1414 nvme_fabrics_command = 0x7f,
1415};
1416
1417enum nvmf_capsule_command {
1418 nvme_fabrics_type_property_set = 0x00,
1419 nvme_fabrics_type_connect = 0x01,
1420 nvme_fabrics_type_property_get = 0x04,
88b140fe
HR		 1421 nvme_fabrics_type_auth_send = 0x05,
1422 nvme_fabrics_type_auth_receive = 0x06,
eb793e2c
CH		 1423};
1424
ad795e47
MI		 1425#define nvme_fabrics_type_name(type) { type, #type }
1426#define show_fabrics_type_name(type) \
1427 __print_symbolic(type, \
1428 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1429 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
88b140fe
HR		 1430 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1431 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1432 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
ad795e47
MI		 1433
1434/*
1435 * If not fabrics command, fctype will be ignored.
1436 */
1437#define show_opcode_name(qid, opcode, fctype) \
1438 ((opcode) == nvme_fabrics_command ? \
1439 show_fabrics_type_name(fctype) : \
1440 ((qid) ? \
1441 show_nvm_opcode_name(opcode) : \
1442 show_admin_opcode_name(opcode)))
1443
eb793e2c
CH		 1444struct nvmf_common_command {
1445 __u8 opcode;
1446 __u8 resv1;
1447 __u16 command_id;
1448 __u8 fctype;
1449 __u8 resv2[35];
1450 __u8 ts[24];
1451};
1452
1453/*
1454 * The legal cntlid range a NVMe Target will provide.
1455 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1456 * Devices based on earlier specs did not have the subsystem concept;
1457 * therefore, those devices had their cntlid value set to 0 as a result.
1458 */
1459#define NVME_CNTLID_MIN 1
1460#define NVME_CNTLID_MAX 0xffef
1461#define NVME_CNTLID_DYNAMIC 0xffff
1462
1463#define MAX_DISC_LOGS 255
1464
785d584c
HR		 1465/* Discovery log page entry flags (EFLAGS): */
1466enum {
1467 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1468 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1469};
1470
eb793e2c
CH		 1471/* Discovery log page entry */
1472struct nvmf_disc_rsp_page_entry {
1473 __u8 trtype;
1474 __u8 adrfam;
a446c084 1475 __u8 subtype;
eb793e2c
CH		 1476 __u8 treq;
1477 __le16 portid;
1478 __le16 cntlid;
1479 __le16 asqsz;
785d584c
HR		 1480 __le16 eflags;
1481 __u8 resv10[20];
eb793e2c
CH		 1482 char trsvcid[NVMF_TRSVCID_SIZE];
1483 __u8 resv64[192];
1484 char subnqn[NVMF_NQN_FIELD_LEN];
1485 char traddr[NVMF_TRADDR_SIZE];
1486 union tsas {
1487 char common[NVMF_TSAS_SIZE];
1488 struct rdma {
1489 __u8 qptype;
1490 __u8 prtype;
1491 __u8 cms;
1492 __u8 resv3[5];
1493 __u16 pkey;
1494 __u8 resv10[246];
1495 } rdma;
646f45b2
HR		 1496 struct tcp {
1497 __u8 sectype;
1498 } tcp;
eb793e2c
CH		 1499 } tsas;
1500};
1501
1502/* Discovery log page header */
1503struct nvmf_disc_rsp_page_hdr {
1504 __le64 genctr;
1505 __le64 numrec;
1506 __le16 recfmt;
1507 __u8 resv14[1006];
f1e71d75 1508 struct nvmf_disc_rsp_page_entry entries[];
eb793e2c
CH		 1509};
1510
e6a622fd
SG		 1511enum {
1512 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1513};
1514
eb793e2c
CH		 1515struct nvmf_connect_command {
1516 __u8 opcode;
1517 __u8 resv1;
1518 __u16 command_id;
1519 __u8 fctype;
1520 __u8 resv2[19];
1521 union nvme_data_ptr dptr;
1522 __le16 recfmt;
1523 __le16 qid;
1524 __le16 sqsize;
1525 __u8 cattr;
1526 __u8 resv3;
1527 __le32 kato;
1528 __u8 resv4[12];
1529};
1530
88b140fe 1531enum {
1c32a801
CH		 1532 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1533 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
88b140fe
HR		 1534};
1535
eb793e2c 1536struct nvmf_connect_data {
8e412263 1537 uuid_t hostid;
eb793e2c
CH		 1538 __le16 cntlid;
1539 char resv4[238];
1540 char subsysnqn[NVMF_NQN_FIELD_LEN];
1541 char hostnqn[NVMF_NQN_FIELD_LEN];
1542 char resv5[256];
1543};
1544
1545struct nvmf_property_set_command {
1546 __u8 opcode;
1547 __u8 resv1;
1548 __u16 command_id;
1549 __u8 fctype;
1550 __u8 resv2[35];
1551 __u8 attrib;
1552 __u8 resv3[3];
1553 __le32 offset;
1554 __le64 value;
1555 __u8 resv4[8];
1556};
1557
1558struct nvmf_property_get_command {
1559 __u8 opcode;
1560 __u8 resv1;
1561 __u16 command_id;
1562 __u8 fctype;
1563 __u8 resv2[35];
1564 __u8 attrib;
1565 __u8 resv3[3];
1566 __le32 offset;
1567 __u8 resv4[16];
1568};
1569
88b140fe
HR		 1570struct nvmf_auth_common_command {
1571 __u8 opcode;
1572 __u8 resv1;
1573 __u16 command_id;
1574 __u8 fctype;
1575 __u8 resv2[19];
1576 union nvme_data_ptr dptr;
1577 __u8 resv3;
1578 __u8 spsp0;
1579 __u8 spsp1;
1580 __u8 secp;
1581 __le32 al_tl;
1582 __u8 resv4[16];
1583};
1584
1585struct nvmf_auth_send_command {
1586 __u8 opcode;
1587 __u8 resv1;
1588 __u16 command_id;
1589 __u8 fctype;
1590 __u8 resv2[19];
1591 union nvme_data_ptr dptr;
1592 __u8 resv3;
1593 __u8 spsp0;
1594 __u8 spsp1;
1595 __u8 secp;
1596 __le32 tl;
1597 __u8 resv4[16];
1598};
1599
1600struct nvmf_auth_receive_command {
1601 __u8 opcode;
1602 __u8 resv1;
1603 __u16 command_id;
1604 __u8 fctype;
1605 __u8 resv2[19];
1606 union nvme_data_ptr dptr;
1607 __u8 resv3;
1608 __u8 spsp0;
1609 __u8 spsp1;
1610 __u8 secp;
1611 __le32 al;
1612 __u8 resv4[16];
1613};
1614
1615/* Value for secp */
1616enum {
1617 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1618};
1619
1620/* Defined value for auth_type */
1621enum {
1622 NVME_AUTH_COMMON_MESSAGES = 0x00,
1623 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1624};
1625
1626/* Defined messages for auth_id */
1627enum {
1628 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1629 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1630 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1631 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1632 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1633 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1634 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1635};
1636
1637struct nvmf_auth_dhchap_protocol_descriptor {
1638 __u8 authid;
1639 __u8 rsvd;
1640 __u8 halen;
1641 __u8 dhlen;
1642 __u8 idlist[60];
1643};
1644
1645enum {
1646 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1647};
1648
1649/* Defined hash functions for DH-HMAC-CHAP authentication */
1650enum {
1651 NVME_AUTH_HASH_SHA256 = 0x01,
1652 NVME_AUTH_HASH_SHA384 = 0x02,
1653 NVME_AUTH_HASH_SHA512 = 0x03,
1654 NVME_AUTH_HASH_INVALID = 0xff,
1655};
1656
1657/* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1658enum {
1659 NVME_AUTH_DHGROUP_NULL = 0x00,
1660 NVME_AUTH_DHGROUP_2048 = 0x01,
1661 NVME_AUTH_DHGROUP_3072 = 0x02,
1662 NVME_AUTH_DHGROUP_4096 = 0x03,
1663 NVME_AUTH_DHGROUP_6144 = 0x04,
1664 NVME_AUTH_DHGROUP_8192 = 0x05,
1665 NVME_AUTH_DHGROUP_INVALID = 0xff,
1666};
1667
1668union nvmf_auth_protocol {
1669 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1670};
1671
1672struct nvmf_auth_dhchap_negotiate_data {
1673 __u8 auth_type;
1674 __u8 auth_id;
1675 __le16 rsvd;
1676 __le16 t_id;
1677 __u8 sc_c;
1678 __u8 napd;
1679 union nvmf_auth_protocol auth_protocol[];
1680};
1681
1682struct nvmf_auth_dhchap_challenge_data {
1683 __u8 auth_type;
1684 __u8 auth_id;
1685 __u16 rsvd1;
1686 __le16 t_id;
1687 __u8 hl;
1688 __u8 rsvd2;
1689 __u8 hashid;
1690 __u8 dhgid;
1691 __le16 dhvlen;
1692 __le32 seqnum;
1693 /* 'hl' bytes of challenge value */
1694 __u8 cval[];
1695 /* followed by 'dhvlen' bytes of DH value */
1696};
1697
1698struct nvmf_auth_dhchap_reply_data {
1699 __u8 auth_type;
1700 __u8 auth_id;
1701 __le16 rsvd1;
1702 __le16 t_id;
1703 __u8 hl;
1704 __u8 rsvd2;
1705 __u8 cvalid;
1706 __u8 rsvd3;
1707 __le16 dhvlen;
1708 __le32 seqnum;
1709 /* 'hl' bytes of response data */
1710 __u8 rval[];
1711 /* followed by 'hl' bytes of Challenge value */
1712 /* followed by 'dhvlen' bytes of DH value */
1713};
1714
1715enum {
1716 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1717};
1718
1719struct nvmf_auth_dhchap_success1_data {
1720 __u8 auth_type;
1721 __u8 auth_id;
1722 __le16 rsvd1;
1723 __le16 t_id;
1724 __u8 hl;
1725 __u8 rsvd2;
1726 __u8 rvalid;
1727 __u8 rsvd3[7];
75276847 1728 /* 'hl' bytes of response value */
88b140fe
HR		 1729 __u8 rval[];
1730};
1731
1732struct nvmf_auth_dhchap_success2_data {
1733 __u8 auth_type;
1734 __u8 auth_id;
1735 __le16 rsvd1;
1736 __le16 t_id;
1737 __u8 rsvd2[10];
1738};
1739
1740struct nvmf_auth_dhchap_failure_data {
1741 __u8 auth_type;
1742 __u8 auth_id;
1743 __le16 rsvd1;
1744 __le16 t_id;
1745 __u8 rescode;
1746 __u8 rescode_exp;
1747};
1748
1749enum {
1750 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1751};
1752
1753enum {
1754 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1755 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1756 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1757 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1758 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1759 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1760 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1761};
1762
1763
f9f38e33
HK		 1764struct nvme_dbbuf {
1765 __u8 opcode;
1766 __u8 flags;
1767 __u16 command_id;
1768 __u32 rsvd1[5];
1769 __le64 prp1;
1770 __le64 prp2;
1771 __u32 rsvd12[6];
1772};
1773
f5d11840 1774struct streams_directive_params {
dc1a0afb
CH		 1775 __le16 msl;
1776 __le16 nssa;
1777 __le16 nsso;
f5d11840 1778 __u8 rsvd[10];
dc1a0afb
CH		 1779 __le32 sws;
1780 __le16 sgs;
1781 __le16 nsa;
1782 __le16 nso;
f5d11840
JA		 1783 __u8 rsvd2[6];
1784};
1785
9d99a8dd
CH		 1786struct nvme_command {
1787 union {
1788 struct nvme_common_command common;
1789 struct nvme_rw_command rw;
1790 struct nvme_identify identify;
1791 struct nvme_features features;
1792 struct nvme_create_cq create_cq;
1793 struct nvme_create_sq create_sq;
1794 struct nvme_delete_queue delete_queue;
1795 struct nvme_download_firmware dlfw;
1796 struct nvme_format_cmd format;
1797 struct nvme_dsm_cmd dsm;
3b7c33b2 1798 struct nvme_write_zeroes_cmd write_zeroes;
240e6ee2
KB		 1799 struct nvme_zone_mgmt_send_cmd zms;
1800 struct nvme_zone_mgmt_recv_cmd zmr;
9d99a8dd 1801 struct nvme_abort_cmd abort;
725b3588 1802 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1803 struct nvmf_common_command fabrics;
1804 struct nvmf_connect_command connect;
1805 struct nvmf_property_set_command prop_set;
1806 struct nvmf_property_get_command prop_get;
88b140fe
HR		 1807 struct nvmf_auth_common_command auth_common;
1808 struct nvmf_auth_send_command auth_send;
1809 struct nvmf_auth_receive_command auth_receive;
f9f38e33 1810 struct nvme_dbbuf dbbuf;
f5d11840 1811 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1812 };
1813};
1814
7a1f46e3
MI		 1815static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1816{
1817 return cmd->common.opcode == nvme_fabrics_command;
1818}
1819
b34de7ce
CK		 1820struct nvme_error_slot {
1821 __le64 error_count;
1822 __le16 sqid;
1823 __le16 cmdid;
1824 __le16 status_field;
1825 __le16 param_error_location;
1826 __le64 lba;
1827 __le32 nsid;
1828 __u8 vs;
1829 __u8 resv[3];
1830 __le64 cs;
1831 __u8 resv2[24];
1832};
1833
7a5abb4b
CH		 1834static inline bool nvme_is_write(struct nvme_command *cmd)
1835{
eb793e2c
CH		 1836 /*
1837 * What a mess...
1838 *
1839 * Why can't we simply have a Fabrics In and Fabrics out command?
1840 */
7a1f46e3 1841 if (unlikely(nvme_is_fabrics(cmd)))
2fd4167f 1842 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1843 return cmd->common.opcode & 1;
1844}
1845
9d99a8dd 1846enum {
eb793e2c
CH		 1847 /*
1848 * Generic Command Status:
1849 */
9d99a8dd
CH		 1850 NVME_SC_SUCCESS = 0x0,
1851 NVME_SC_INVALID_OPCODE = 0x1,
1852 NVME_SC_INVALID_FIELD = 0x2,
1853 NVME_SC_CMDID_CONFLICT = 0x3,
1854 NVME_SC_DATA_XFER_ERROR = 0x4,
1855 NVME_SC_POWER_LOSS = 0x5,
1856 NVME_SC_INTERNAL = 0x6,
1857 NVME_SC_ABORT_REQ = 0x7,
1858 NVME_SC_ABORT_QUEUE = 0x8,
1859 NVME_SC_FUSED_FAIL = 0x9,
1860 NVME_SC_FUSED_MISSING = 0xa,
1861 NVME_SC_INVALID_NS = 0xb,
1862 NVME_SC_CMD_SEQ_ERROR = 0xc,
1863 NVME_SC_SGL_INVALID_LAST = 0xd,
1864 NVME_SC_SGL_INVALID_COUNT = 0xe,
1865 NVME_SC_SGL_INVALID_DATA = 0xf,
1866 NVME_SC_SGL_INVALID_METADATA = 0x10,
1867 NVME_SC_SGL_INVALID_TYPE = 0x11,
3254899e
MG		 1868 NVME_SC_CMB_INVALID_USE = 0x12,
1869 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1870 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1871 NVME_SC_OP_DENIED = 0x15,
eb793e2c 1872 NVME_SC_SGL_INVALID_OFFSET = 0x16,
3254899e
MG		 1873 NVME_SC_RESERVED = 0x17,
1874 NVME_SC_HOST_ID_INCONSIST = 0x18,
1875 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1876 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1877 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
48c9e85b
RR		 1878 NVME_SC_SANITIZE_FAILED = 0x1C,
1879 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
3254899e
MG		 1880 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1881 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
93045d59 1882 NVME_SC_NS_WRITE_PROTECTED = 0x20,
48c9e85b 1883 NVME_SC_CMD_INTERRUPTED = 0x21,
3254899e 1884 NVME_SC_TRANSIENT_TR_ERR = 0x22,
354201c5 1885 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
ab5d0b38 1886 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
93045d59 1887
9d99a8dd
CH		 1888 NVME_SC_LBA_RANGE = 0x80,
1889 NVME_SC_CAP_EXCEEDED = 0x81,
1890 NVME_SC_NS_NOT_READY = 0x82,
1891 NVME_SC_RESERVATION_CONFLICT = 0x83,
3254899e 1892 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
eb793e2c
CH		 1893
1894 /*
1895 * Command Specific Status:
1896 */
9d99a8dd
CH		 1897 NVME_SC_CQ_INVALID = 0x100,
1898 NVME_SC_QID_INVALID = 0x101,
1899 NVME_SC_QUEUE_SIZE = 0x102,
1900 NVME_SC_ABORT_LIMIT = 0x103,
1901 NVME_SC_ABORT_MISSING = 0x104,
1902 NVME_SC_ASYNC_LIMIT = 0x105,
1903 NVME_SC_FIRMWARE_SLOT = 0x106,
1904 NVME_SC_FIRMWARE_IMAGE = 0x107,
1905 NVME_SC_INVALID_VECTOR = 0x108,
1906 NVME_SC_INVALID_LOG_PAGE = 0x109,
1907 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1908 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1909 NVME_SC_INVALID_QUEUE = 0x10c,
1910 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1911 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1912 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1913 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1914 NVME_SC_FW_NEEDS_RESET = 0x111,
1915 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
9581ae4f 1916 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
a446c084 1917 NVME_SC_OVERLAPPING_RANGE = 0x114,
9581ae4f 1918 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
a446c084
CH		 1919 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1920 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1921 NVME_SC_NS_IS_PRIVATE = 0x119,
1922 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1923 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1924 NVME_SC_CTRL_LIST_INVALID = 0x11c,
3254899e 1925 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
48c9e85b 1926 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
3254899e
MG		 1927 NVME_SC_CTRL_ID_INVALID = 0x11f,
1928 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1929 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1930 NVME_SC_RES_ID_INVALID = 0x122,
48c9e85b 1931 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
3254899e
MG		 1932 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1933 NVME_SC_ANA_ATTACH_FAILED = 0x125,
eb793e2c
CH		 1934
1935 /*
1936 * I/O Command Set Specific - NVM commands:
1937 */
9d99a8dd
CH		 1938 NVME_SC_BAD_ATTRIBUTES = 0x180,
1939 NVME_SC_INVALID_PI = 0x181,
1940 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1941 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1942
1943 /*
1944 * I/O Command Set Specific - Fabrics commands:
1945 */
1946 NVME_SC_CONNECT_FORMAT = 0x180,
1947 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1948 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1949 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1950 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1951
1952 NVME_SC_DISCOVERY_RESTART = 0x190,
1953 NVME_SC_AUTH_REQUIRED = 0x191,
1954
240e6ee2
KB		 1955 /*
1956 * I/O Command Set Specific - Zoned commands:
1957 */
1958 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1959 NVME_SC_ZONE_FULL = 0x1b9,
1960 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1961 NVME_SC_ZONE_OFFLINE = 0x1bb,
1962 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1963 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1964 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1965 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1966
eb793e2c
CH		 1967 /*
1968 * Media and Data Integrity Errors:
1969 */
9d99a8dd
CH		 1970 NVME_SC_WRITE_FAULT = 0x280,
1971 NVME_SC_READ_ERROR = 0x281,
1972 NVME_SC_GUARD_CHECK = 0x282,
1973 NVME_SC_APPTAG_CHECK = 0x283,
1974 NVME_SC_REFTAG_CHECK = 0x284,
1975 NVME_SC_COMPARE_FAILED = 0x285,
1976 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1977 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1978
1a376216
CH		 1979 /*
1980 * Path-related Errors:
1981 */
ca2d8992 1982 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1a376216
CH		 1983 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1984 NVME_SC_ANA_INACCESSIBLE = 0x302,
1985 NVME_SC_ANA_TRANSITION = 0x303,
ca2d8992 1986 NVME_SC_CTRL_PATH_ERROR = 0x360,
783f4a44 1987 NVME_SC_HOST_PATH_ERROR = 0x370,
2dc3947b 1988 NVME_SC_HOST_ABORTED_CMD = 0x371,
1a376216 1989
49cd84b6 1990 NVME_SC_CRD = 0x1800,
bd83fe6f 1991 NVME_SC_MORE = 0x2000,
9d99a8dd
CH		 1992 NVME_SC_DNR = 0x4000,
1993};
1994
1995struct nvme_completion {
eb793e2c
CH		 1996 /*
1997 * Used by Admin and Fabrics commands to return data:
1998 */
d49187e9
CH		 1999 union nvme_result {
2000 __le16 u16;
2001 __le32 u32;
2002 __le64 u64;
2003 } result;
9d99a8dd
CH		 2004 __le16 sq_head; /* how much of this queue may be reclaimed */
2005 __le16 sq_id; /* submission queue that generated this entry */
2006 __u16 command_id; /* of the command which completed */
2007 __le16 status; /* did the command fail, and if so, why? */
2008};
2009
8ef2074d
GKB		 2010#define NVME_VS(major, minor, tertiary) \
2011 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 2012
c61d788b
JT		 2013#define NVME_MAJOR(ver) ((ver) >> 16)
2014#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2015#define NVME_TERTIARY(ver) ((ver) & 0xff)
2016
b60503ba 2017#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)