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nvme.h: add struct nvme_host_mem_buf_desc and HMB flags
[linux-2.6-block.git] / include / linux / nvme.h
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b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
8e412263 19#include <linux/uuid.h>
eb793e2c
CH		 20
21/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256
23
24/* However the max length of a qualified name is another size */
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
35enum nvme_subsys_type {
36 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
37 NVME_NQN_NVME = 2, /* NVME type target subsystem */
38};
39
40/* Address Family codes for Discovery Log Page entry ADRFAM field */
41enum {
42 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
43 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
44 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
45 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
46 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
47};
48
49/* Transport Type codes for Discovery Log Page entry TRTYPE field */
50enum {
51 NVMF_TRTYPE_RDMA = 1, /* RDMA */
52 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
53 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
54 NVMF_TRTYPE_MAX,
55};
56
57/* Transport Requirements codes for Discovery Log Page entry TREQ field */
58enum {
59 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
60 NVMF_TREQ_REQUIRED = 1, /* Required */
61 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
62};
63
64/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
65 * RDMA_QPTYPE field
66 */
67enum {
bf17aa36
RD		 68 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
69 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 70};
71
72/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
73 * RDMA_QPTYPE field
74 */
75enum {
bf17aa36
RD		 76 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
77 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
78 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
79 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
80 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 81};
82
83/* RDMA Connection Management Service Type codes for Discovery Log Page
84 * entry TSAS RDMA_CMS field
85 */
86enum {
bf17aa36 87 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 88};
89
90#define NVMF_AQ_DEPTH 32
2812dfe3 91
7a67cbea
CH		 92enum {
93 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
94 NVME_REG_VS = 0x0008, /* Version */
95 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 96 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 97 NVME_REG_CC = 0x0014, /* Controller Configuration */
98 NVME_REG_CSTS = 0x001c, /* Controller Status */
99 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
100 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
101 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 102 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 103 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
104 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
b60503ba
MW		 105};
106
a0cadb85 107#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 108#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 109#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 110#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 111#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 112#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 113
8ffaadf7
JD		 114#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
115#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
116#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
117#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
118
119#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
120#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
121#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
122#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
123#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
124
69cd27e2
CH		 125/*
126 * Submission and Completion Queue Entry Sizes for the NVM command set.
127 * (In bytes and specified as a power of two (2^n)).
128 */
129#define NVME_NVM_IOSQES 6
130#define NVME_NVM_IOCQES 4
131
b60503ba
MW		 132enum {
133 NVME_CC_ENABLE = 1 << 0,
134 NVME_CC_CSS_NVM = 0 << 4,
135 NVME_CC_MPS_SHIFT = 7,
136 NVME_CC_ARB_RR = 0 << 11,
137 NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2
MW		 138 NVME_CC_ARB_VS = 7 << 11,
139 NVME_CC_SHN_NONE = 0 << 14,
140 NVME_CC_SHN_NORMAL = 1 << 14,
141 NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1 142 NVME_CC_SHN_MASK = 3 << 14,
69cd27e2
CH		 143 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
144 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba
MW		 145 NVME_CSTS_RDY = 1 << 0,
146 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 147 NVME_CSTS_NSSRO = 1 << 4,
b60503ba
MW		 148 NVME_CSTS_SHST_NORMAL = 0 << 2,
149 NVME_CSTS_SHST_OCCUR = 1 << 2,
150 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 151 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 152};
153
9d99a8dd
CH		 154struct nvme_id_power_state {
155 __le16 max_power; /* centiwatts */
156 __u8 rsvd2;
157 __u8 flags;
158 __le32 entry_lat; /* microseconds */
159 __le32 exit_lat; /* microseconds */
160 __u8 read_tput;
161 __u8 read_lat;
162 __u8 write_tput;
163 __u8 write_lat;
164 __le16 idle_power;
165 __u8 idle_scale;
166 __u8 rsvd19;
167 __le16 active_power;
168 __u8 active_work_scale;
169 __u8 rsvd23[9];
170};
171
172enum {
173 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
174 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
175};
176
177struct nvme_id_ctrl {
178 __le16 vid;
179 __le16 ssvid;
180 char sn[20];
181 char mn[40];
182 char fr[8];
183 __u8 rab;
184 __u8 ieee[3];
a446c084 185 __u8 cmic;
9d99a8dd 186 __u8 mdts;
08c69640
CH		 187 __le16 cntlid;
188 __le32 ver;
14e974a8
CH		 189 __le32 rtd3r;
190 __le32 rtd3e;
191 __le32 oaes;
eb793e2c
CH		 192 __le32 ctratt;
193 __u8 rsvd100[156];
9d99a8dd
CH		 194 __le16 oacs;
195 __u8 acl;
196 __u8 aerl;
197 __u8 frmw;
198 __u8 lpa;
199 __u8 elpe;
200 __u8 npss;
201 __u8 avscc;
202 __u8 apsta;
203 __le16 wctemp;
204 __le16 cctemp;
a446c084
CH		 205 __le16 mtfa;
206 __le32 hmpre;
207 __le32 hmmin;
208 __u8 tnvmcap[16];
209 __u8 unvmcap[16];
210 __le32 rpmbs;
211 __u8 rsvd316[4];
7b89eae2
SG		 212 __le16 kas;
213 __u8 rsvd322[190];
9d99a8dd
CH		 214 __u8 sqes;
215 __u8 cqes;
eb793e2c 216 __le16 maxcmd;
9d99a8dd
CH		 217 __le32 nn;
218 __le16 oncs;
219 __le16 fuses;
220 __u8 fna;
221 __u8 vwc;
222 __le16 awun;
223 __le16 awupf;
224 __u8 nvscc;
225 __u8 rsvd531;
226 __le16 acwu;
227 __u8 rsvd534[2];
228 __le32 sgls;
eb793e2c
CH		 229 __u8 rsvd540[228];
230 char subnqn[256];
231 __u8 rsvd1024[768];
232 __le32 ioccsz;
233 __le32 iorcsz;
234 __le16 icdoff;
235 __u8 ctrattr;
236 __u8 msdbd;
237 __u8 rsvd1804[244];
9d99a8dd
CH		 238 struct nvme_id_power_state psd[32];
239 __u8 vs[1024];
240};
241
242enum {
243 NVME_CTRL_ONCS_COMPARE = 1 << 0,
244 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
245 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 246 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
9d99a8dd 247 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 248 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f9f38e33 249 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7,
9d99a8dd
CH		 250};
251
252struct nvme_lbaf {
253 __le16 ms;
254 __u8 ds;
255 __u8 rp;
256};
257
258struct nvme_id_ns {
259 __le64 nsze;
260 __le64 ncap;
261 __le64 nuse;
262 __u8 nsfeat;
263 __u8 nlbaf;
264 __u8 flbas;
265 __u8 mc;
266 __u8 dpc;
267 __u8 dps;
268 __u8 nmic;
269 __u8 rescap;
270 __u8 fpi;
271 __u8 rsvd33;
272 __le16 nawun;
273 __le16 nawupf;
274 __le16 nacwu;
275 __le16 nabsn;
276 __le16 nabo;
277 __le16 nabspf;
278 __u16 rsvd46;
a446c084 279 __u8 nvmcap[16];
9d99a8dd
CH		 280 __u8 rsvd64[40];
281 __u8 nguid[16];
282 __u8 eui64[8];
283 struct nvme_lbaf lbaf[16];
284 __u8 rsvd192[192];
285 __u8 vs[3712];
286};
287
329dd768
CH		 288enum {
289 NVME_ID_CNS_NS = 0x00,
290 NVME_ID_CNS_CTRL = 0x01,
291 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
292 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
293 NVME_ID_CNS_NS_PRESENT = 0x11,
294 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
295 NVME_ID_CNS_CTRL_LIST = 0x13,
296};
297
9d99a8dd
CH		 298enum {
299 NVME_NS_FEAT_THIN = 1 << 0,
300 NVME_NS_FLBAS_LBA_MASK = 0xf,
301 NVME_NS_FLBAS_META_EXT = 0x10,
302 NVME_LBAF_RP_BEST = 0,
303 NVME_LBAF_RP_BETTER = 1,
304 NVME_LBAF_RP_GOOD = 2,
305 NVME_LBAF_RP_DEGRADED = 3,
306 NVME_NS_DPC_PI_LAST = 1 << 4,
307 NVME_NS_DPC_PI_FIRST = 1 << 3,
308 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
309 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
310 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
311 NVME_NS_DPS_PI_FIRST = 1 << 3,
312 NVME_NS_DPS_PI_MASK = 0x7,
313 NVME_NS_DPS_PI_TYPE1 = 1,
314 NVME_NS_DPS_PI_TYPE2 = 2,
315 NVME_NS_DPS_PI_TYPE3 = 3,
316};
317
318struct nvme_smart_log {
319 __u8 critical_warning;
320 __u8 temperature[2];
321 __u8 avail_spare;
322 __u8 spare_thresh;
323 __u8 percent_used;
324 __u8 rsvd6[26];
325 __u8 data_units_read[16];
326 __u8 data_units_written[16];
327 __u8 host_reads[16];
328 __u8 host_writes[16];
329 __u8 ctrl_busy_time[16];
330 __u8 power_cycles[16];
331 __u8 power_on_hours[16];
332 __u8 unsafe_shutdowns[16];
333 __u8 media_errors[16];
334 __u8 num_err_log_entries[16];
335 __le32 warning_temp_time;
336 __le32 critical_comp_time;
337 __le16 temp_sensor[8];
338 __u8 rsvd216[296];
339};
340
341enum {
342 NVME_SMART_CRIT_SPARE = 1 << 0,
343 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
344 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
345 NVME_SMART_CRIT_MEDIA = 1 << 3,
346 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
347};
348
349enum {
350 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
351};
352
353struct nvme_lba_range_type {
354 __u8 type;
355 __u8 attributes;
356 __u8 rsvd2[14];
357 __u64 slba;
358 __u64 nlb;
359 __u8 guid[16];
360 __u8 rsvd48[16];
361};
362
363enum {
364 NVME_LBART_TYPE_FS = 0x01,
365 NVME_LBART_TYPE_RAID = 0x02,
366 NVME_LBART_TYPE_CACHE = 0x03,
367 NVME_LBART_TYPE_SWAP = 0x04,
368
369 NVME_LBART_ATTRIB_TEMP = 1 << 0,
370 NVME_LBART_ATTRIB_HIDE = 1 << 1,
371};
372
373struct nvme_reservation_status {
374 __le32 gen;
375 __u8 rtype;
376 __u8 regctl[2];
377 __u8 resv5[2];
378 __u8 ptpls;
379 __u8 resv10[13];
380 struct {
381 __le16 cntlid;
382 __u8 rcsts;
383 __u8 resv3[5];
384 __le64 hostid;
385 __le64 rkey;
386 } regctl_ds[];
387};
388
79f370ea
CH		 389enum nvme_async_event_type {
390 NVME_AER_TYPE_ERROR = 0,
391 NVME_AER_TYPE_SMART = 1,
392 NVME_AER_TYPE_NOTICE = 2,
393};
394
9d99a8dd
CH		 395/* I/O commands */
396
397enum nvme_opcode {
398 nvme_cmd_flush = 0x00,
399 nvme_cmd_write = 0x01,
400 nvme_cmd_read = 0x02,
401 nvme_cmd_write_uncor = 0x04,
402 nvme_cmd_compare = 0x05,
403 nvme_cmd_write_zeroes = 0x08,
404 nvme_cmd_dsm = 0x09,
405 nvme_cmd_resv_register = 0x0d,
406 nvme_cmd_resv_report = 0x0e,
407 nvme_cmd_resv_acquire = 0x11,
408 nvme_cmd_resv_release = 0x15,
409};
410
eb793e2c
CH		 411/*
412 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
413 *
414 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
415 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
416 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
417 * request subtype
418 */
419enum {
420 NVME_SGL_FMT_ADDRESS = 0x00,
421 NVME_SGL_FMT_OFFSET = 0x01,
422 NVME_SGL_FMT_INVALIDATE = 0x0f,
423};
424
425/*
426 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
427 *
428 * For struct nvme_sgl_desc:
429 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
430 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
431 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
432 *
433 * For struct nvme_keyed_sgl_desc:
434 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
435 */
436enum {
437 NVME_SGL_FMT_DATA_DESC = 0x00,
438 NVME_SGL_FMT_SEG_DESC = 0x02,
439 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
440 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
441};
442
443struct nvme_sgl_desc {
444 __le64 addr;
445 __le32 length;
446 __u8 rsvd[3];
447 __u8 type;
448};
449
450struct nvme_keyed_sgl_desc {
451 __le64 addr;
452 __u8 length[3];
453 __u8 key[4];
454 __u8 type;
455};
456
457union nvme_data_ptr {
458 struct {
459 __le64 prp1;
460 __le64 prp2;
461 };
462 struct nvme_sgl_desc sgl;
463 struct nvme_keyed_sgl_desc ksgl;
464};
465
3972be23
JS		 466/*
467 * Lowest two bits of our flags field (FUSE field in the spec):
468 *
469 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
470 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
471 *
472 * Highest two bits in our flags field (PSDT field in the spec):
473 *
474 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
475 * If used, MPTR contains addr of single physical buffer (byte aligned).
476 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
477 * If used, MPTR contains an address of an SGL segment containing
478 * exactly 1 SGL descriptor (qword aligned).
479 */
480enum {
481 NVME_CMD_FUSE_FIRST = (1 << 0),
482 NVME_CMD_FUSE_SECOND = (1 << 1),
483
484 NVME_CMD_SGL_METABUF = (1 << 6),
485 NVME_CMD_SGL_METASEG = (1 << 7),
486 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
487};
488
9d99a8dd
CH		 489struct nvme_common_command {
490 __u8 opcode;
491 __u8 flags;
492 __u16 command_id;
493 __le32 nsid;
494 __le32 cdw2[2];
495 __le64 metadata;
eb793e2c 496 union nvme_data_ptr dptr;
9d99a8dd
CH		 497 __le32 cdw10[6];
498};
499
500struct nvme_rw_command {
501 __u8 opcode;
502 __u8 flags;
503 __u16 command_id;
504 __le32 nsid;
505 __u64 rsvd2;
506 __le64 metadata;
eb793e2c 507 union nvme_data_ptr dptr;
9d99a8dd
CH		 508 __le64 slba;
509 __le16 length;
510 __le16 control;
511 __le32 dsmgmt;
512 __le32 reftag;
513 __le16 apptag;
514 __le16 appmask;
515};
516
517enum {
518 NVME_RW_LR = 1 << 15,
519 NVME_RW_FUA = 1 << 14,
520 NVME_RW_DSM_FREQ_UNSPEC = 0,
521 NVME_RW_DSM_FREQ_TYPICAL = 1,
522 NVME_RW_DSM_FREQ_RARE = 2,
523 NVME_RW_DSM_FREQ_READS = 3,
524 NVME_RW_DSM_FREQ_WRITES = 4,
525 NVME_RW_DSM_FREQ_RW = 5,
526 NVME_RW_DSM_FREQ_ONCE = 6,
527 NVME_RW_DSM_FREQ_PREFETCH = 7,
528 NVME_RW_DSM_FREQ_TEMP = 8,
529 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
530 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
531 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
532 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
533 NVME_RW_DSM_SEQ_REQ = 1 << 6,
534 NVME_RW_DSM_COMPRESSED = 1 << 7,
535 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
536 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
537 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
538 NVME_RW_PRINFO_PRACT = 1 << 13,
539};
540
541struct nvme_dsm_cmd {
542 __u8 opcode;
543 __u8 flags;
544 __u16 command_id;
545 __le32 nsid;
546 __u64 rsvd2[2];
eb793e2c 547 union nvme_data_ptr dptr;
9d99a8dd
CH		 548 __le32 nr;
549 __le32 attributes;
550 __u32 rsvd12[4];
551};
552
553enum {
554 NVME_DSMGMT_IDR = 1 << 0,
555 NVME_DSMGMT_IDW = 1 << 1,
556 NVME_DSMGMT_AD = 1 << 2,
557};
558
b35ba01e
CH		 559#define NVME_DSM_MAX_RANGES 256
560
9d99a8dd
CH		 561struct nvme_dsm_range {
562 __le32 cattr;
563 __le32 nlb;
564 __le64 slba;
565};
566
3b7c33b2
CK		 567struct nvme_write_zeroes_cmd {
568 __u8 opcode;
569 __u8 flags;
570 __u16 command_id;
571 __le32 nsid;
572 __u64 rsvd2;
573 __le64 metadata;
574 union nvme_data_ptr dptr;
575 __le64 slba;
576 __le16 length;
577 __le16 control;
578 __le32 dsmgmt;
579 __le32 reftag;
580 __le16 apptag;
581 __le16 appmask;
582};
583
c5552fde
AL		 584/* Features */
585
586struct nvme_feat_auto_pst {
587 __le64 entries[32];
588};
589
39673e19
CH		 590enum {
591 NVME_HOST_MEM_ENABLE = (1 << 0),
592 NVME_HOST_MEM_RETURN = (1 << 1),
593};
594
9d99a8dd
CH		 595/* Admin commands */
596
597enum nvme_admin_opcode {
598 nvme_admin_delete_sq = 0x00,
599 nvme_admin_create_sq = 0x01,
600 nvme_admin_get_log_page = 0x02,
601 nvme_admin_delete_cq = 0x04,
602 nvme_admin_create_cq = 0x05,
603 nvme_admin_identify = 0x06,
604 nvme_admin_abort_cmd = 0x08,
605 nvme_admin_set_features = 0x09,
606 nvme_admin_get_features = 0x0a,
607 nvme_admin_async_event = 0x0c,
a446c084 608 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 609 nvme_admin_activate_fw = 0x10,
610 nvme_admin_download_fw = 0x11,
a446c084 611 nvme_admin_ns_attach = 0x15,
7b89eae2 612 nvme_admin_keep_alive = 0x18,
f9f38e33 613 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 614 nvme_admin_format_nvm = 0x80,
615 nvme_admin_security_send = 0x81,
616 nvme_admin_security_recv = 0x82,
617};
618
619enum {
620 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
621 NVME_CQ_IRQ_ENABLED = (1 << 1),
622 NVME_SQ_PRIO_URGENT = (0 << 1),
623 NVME_SQ_PRIO_HIGH = (1 << 1),
624 NVME_SQ_PRIO_MEDIUM = (2 << 1),
625 NVME_SQ_PRIO_LOW = (3 << 1),
626 NVME_FEAT_ARBITRATION = 0x01,
627 NVME_FEAT_POWER_MGMT = 0x02,
628 NVME_FEAT_LBA_RANGE = 0x03,
629 NVME_FEAT_TEMP_THRESH = 0x04,
630 NVME_FEAT_ERR_RECOVERY = 0x05,
631 NVME_FEAT_VOLATILE_WC = 0x06,
632 NVME_FEAT_NUM_QUEUES = 0x07,
633 NVME_FEAT_IRQ_COALESCE = 0x08,
634 NVME_FEAT_IRQ_CONFIG = 0x09,
635 NVME_FEAT_WRITE_ATOMIC = 0x0a,
636 NVME_FEAT_ASYNC_EVENT = 0x0b,
637 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 638 NVME_FEAT_HOST_MEM_BUF = 0x0d,
7b89eae2 639 NVME_FEAT_KATO = 0x0f,
9d99a8dd
CH		 640 NVME_FEAT_SW_PROGRESS = 0x80,
641 NVME_FEAT_HOST_ID = 0x81,
642 NVME_FEAT_RESV_MASK = 0x82,
643 NVME_FEAT_RESV_PERSIST = 0x83,
644 NVME_LOG_ERROR = 0x01,
645 NVME_LOG_SMART = 0x02,
646 NVME_LOG_FW_SLOT = 0x03,
eb793e2c 647 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 648 NVME_LOG_RESERVATION = 0x80,
649 NVME_FWACT_REPL = (0 << 3),
650 NVME_FWACT_REPL_ACTV = (1 << 3),
651 NVME_FWACT_ACTV = (2 << 3),
652};
653
654struct nvme_identify {
655 __u8 opcode;
656 __u8 flags;
657 __u16 command_id;
658 __le32 nsid;
659 __u64 rsvd2[2];
eb793e2c 660 union nvme_data_ptr dptr;
986994a2
PP		 661 __u8 cns;
662 __u8 rsvd3;
663 __le16 ctrlid;
9d99a8dd
CH		 664 __u32 rsvd11[5];
665};
666
667struct nvme_features {
668 __u8 opcode;
669 __u8 flags;
670 __u16 command_id;
671 __le32 nsid;
672 __u64 rsvd2[2];
eb793e2c 673 union nvme_data_ptr dptr;
9d99a8dd
CH		 674 __le32 fid;
675 __le32 dword11;
676 __u32 rsvd12[4];
677};
678
39673e19
CH		 679struct nvme_host_mem_buf_desc {
680 __le64 addr;
681 __le32 size;
682 __u32 rsvd;
683};
684
9d99a8dd
CH		 685struct nvme_create_cq {
686 __u8 opcode;
687 __u8 flags;
688 __u16 command_id;
689 __u32 rsvd1[5];
690 __le64 prp1;
691 __u64 rsvd8;
692 __le16 cqid;
693 __le16 qsize;
694 __le16 cq_flags;
695 __le16 irq_vector;
696 __u32 rsvd12[4];
697};
698
699struct nvme_create_sq {
700 __u8 opcode;
701 __u8 flags;
702 __u16 command_id;
703 __u32 rsvd1[5];
704 __le64 prp1;
705 __u64 rsvd8;
706 __le16 sqid;
707 __le16 qsize;
708 __le16 sq_flags;
709 __le16 cqid;
710 __u32 rsvd12[4];
711};
712
713struct nvme_delete_queue {
714 __u8 opcode;
715 __u8 flags;
716 __u16 command_id;
717 __u32 rsvd1[9];
718 __le16 qid;
719 __u16 rsvd10;
720 __u32 rsvd11[5];
721};
722
723struct nvme_abort_cmd {
724 __u8 opcode;
725 __u8 flags;
726 __u16 command_id;
727 __u32 rsvd1[9];
728 __le16 sqid;
729 __u16 cid;
730 __u32 rsvd11[5];
731};
732
733struct nvme_download_firmware {
734 __u8 opcode;
735 __u8 flags;
736 __u16 command_id;
737 __u32 rsvd1[5];
eb793e2c 738 union nvme_data_ptr dptr;
9d99a8dd
CH		 739 __le32 numd;
740 __le32 offset;
741 __u32 rsvd12[4];
742};
743
744struct nvme_format_cmd {
745 __u8 opcode;
746 __u8 flags;
747 __u16 command_id;
748 __le32 nsid;
749 __u64 rsvd2[4];
750 __le32 cdw10;
751 __u32 rsvd11[5];
752};
753
725b3588
AB		 754struct nvme_get_log_page_command {
755 __u8 opcode;
756 __u8 flags;
757 __u16 command_id;
758 __le32 nsid;
759 __u64 rsvd2[2];
eb793e2c 760 union nvme_data_ptr dptr;
725b3588
AB		 761 __u8 lid;
762 __u8 rsvd10;
763 __le16 numdl;
764 __le16 numdu;
765 __u16 rsvd11;
766 __le32 lpol;
767 __le32 lpou;
768 __u32 rsvd14[2];
769};
770
eb793e2c
CH		 771/*
772 * Fabrics subcommands.
773 */
774enum nvmf_fabrics_opcode {
775 nvme_fabrics_command = 0x7f,
776};
777
778enum nvmf_capsule_command {
779 nvme_fabrics_type_property_set = 0x00,
780 nvme_fabrics_type_connect = 0x01,
781 nvme_fabrics_type_property_get = 0x04,
782};
783
784struct nvmf_common_command {
785 __u8 opcode;
786 __u8 resv1;
787 __u16 command_id;
788 __u8 fctype;
789 __u8 resv2[35];
790 __u8 ts[24];
791};
792
793/*
794 * The legal cntlid range a NVMe Target will provide.
795 * Note that cntlid of value 0 is considered illegal in the fabrics world.
796 * Devices based on earlier specs did not have the subsystem concept;
797 * therefore, those devices had their cntlid value set to 0 as a result.
798 */
799#define NVME_CNTLID_MIN 1
800#define NVME_CNTLID_MAX 0xffef
801#define NVME_CNTLID_DYNAMIC 0xffff
802
803#define MAX_DISC_LOGS 255
804
805/* Discovery log page entry */
806struct nvmf_disc_rsp_page_entry {
807 __u8 trtype;
808 __u8 adrfam;
a446c084 809 __u8 subtype;
eb793e2c
CH		 810 __u8 treq;
811 __le16 portid;
812 __le16 cntlid;
813 __le16 asqsz;
814 __u8 resv8[22];
815 char trsvcid[NVMF_TRSVCID_SIZE];
816 __u8 resv64[192];
817 char subnqn[NVMF_NQN_FIELD_LEN];
818 char traddr[NVMF_TRADDR_SIZE];
819 union tsas {
820 char common[NVMF_TSAS_SIZE];
821 struct rdma {
822 __u8 qptype;
823 __u8 prtype;
824 __u8 cms;
825 __u8 resv3[5];
826 __u16 pkey;
827 __u8 resv10[246];
828 } rdma;
829 } tsas;
830};
831
832/* Discovery log page header */
833struct nvmf_disc_rsp_page_hdr {
834 __le64 genctr;
835 __le64 numrec;
836 __le16 recfmt;
837 __u8 resv14[1006];
838 struct nvmf_disc_rsp_page_entry entries[0];
839};
840
841struct nvmf_connect_command {
842 __u8 opcode;
843 __u8 resv1;
844 __u16 command_id;
845 __u8 fctype;
846 __u8 resv2[19];
847 union nvme_data_ptr dptr;
848 __le16 recfmt;
849 __le16 qid;
850 __le16 sqsize;
851 __u8 cattr;
852 __u8 resv3;
853 __le32 kato;
854 __u8 resv4[12];
855};
856
857struct nvmf_connect_data {
8e412263 858 uuid_t hostid;
eb793e2c
CH		 859 __le16 cntlid;
860 char resv4[238];
861 char subsysnqn[NVMF_NQN_FIELD_LEN];
862 char hostnqn[NVMF_NQN_FIELD_LEN];
863 char resv5[256];
864};
865
866struct nvmf_property_set_command {
867 __u8 opcode;
868 __u8 resv1;
869 __u16 command_id;
870 __u8 fctype;
871 __u8 resv2[35];
872 __u8 attrib;
873 __u8 resv3[3];
874 __le32 offset;
875 __le64 value;
876 __u8 resv4[8];
877};
878
879struct nvmf_property_get_command {
880 __u8 opcode;
881 __u8 resv1;
882 __u16 command_id;
883 __u8 fctype;
884 __u8 resv2[35];
885 __u8 attrib;
886 __u8 resv3[3];
887 __le32 offset;
888 __u8 resv4[16];
889};
890
f9f38e33
HK		 891struct nvme_dbbuf {
892 __u8 opcode;
893 __u8 flags;
894 __u16 command_id;
895 __u32 rsvd1[5];
896 __le64 prp1;
897 __le64 prp2;
898 __u32 rsvd12[6];
899};
900
9d99a8dd
CH		 901struct nvme_command {
902 union {
903 struct nvme_common_command common;
904 struct nvme_rw_command rw;
905 struct nvme_identify identify;
906 struct nvme_features features;
907 struct nvme_create_cq create_cq;
908 struct nvme_create_sq create_sq;
909 struct nvme_delete_queue delete_queue;
910 struct nvme_download_firmware dlfw;
911 struct nvme_format_cmd format;
912 struct nvme_dsm_cmd dsm;
3b7c33b2 913 struct nvme_write_zeroes_cmd write_zeroes;
9d99a8dd 914 struct nvme_abort_cmd abort;
725b3588 915 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 916 struct nvmf_common_command fabrics;
917 struct nvmf_connect_command connect;
918 struct nvmf_property_set_command prop_set;
919 struct nvmf_property_get_command prop_get;
f9f38e33 920 struct nvme_dbbuf dbbuf;
9d99a8dd
CH		 921 };
922};
923
7a5abb4b
CH		 924static inline bool nvme_is_write(struct nvme_command *cmd)
925{
eb793e2c
CH		 926 /*
927 * What a mess...
928 *
929 * Why can't we simply have a Fabrics In and Fabrics out command?
930 */
931 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
932 return cmd->fabrics.opcode & 1;
7a5abb4b
CH		 933 return cmd->common.opcode & 1;
934}
935
9d99a8dd 936enum {
eb793e2c
CH		 937 /*
938 * Generic Command Status:
939 */
9d99a8dd
CH		 940 NVME_SC_SUCCESS = 0x0,
941 NVME_SC_INVALID_OPCODE = 0x1,
942 NVME_SC_INVALID_FIELD = 0x2,
943 NVME_SC_CMDID_CONFLICT = 0x3,
944 NVME_SC_DATA_XFER_ERROR = 0x4,
945 NVME_SC_POWER_LOSS = 0x5,
946 NVME_SC_INTERNAL = 0x6,
947 NVME_SC_ABORT_REQ = 0x7,
948 NVME_SC_ABORT_QUEUE = 0x8,
949 NVME_SC_FUSED_FAIL = 0x9,
950 NVME_SC_FUSED_MISSING = 0xa,
951 NVME_SC_INVALID_NS = 0xb,
952 NVME_SC_CMD_SEQ_ERROR = 0xc,
953 NVME_SC_SGL_INVALID_LAST = 0xd,
954 NVME_SC_SGL_INVALID_COUNT = 0xe,
955 NVME_SC_SGL_INVALID_DATA = 0xf,
956 NVME_SC_SGL_INVALID_METADATA = 0x10,
957 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 958
959 NVME_SC_SGL_INVALID_OFFSET = 0x16,
960 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
961
9d99a8dd
CH		 962 NVME_SC_LBA_RANGE = 0x80,
963 NVME_SC_CAP_EXCEEDED = 0x81,
964 NVME_SC_NS_NOT_READY = 0x82,
965 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 966
967 /*
968 * Command Specific Status:
969 */
9d99a8dd
CH		 970 NVME_SC_CQ_INVALID = 0x100,
971 NVME_SC_QID_INVALID = 0x101,
972 NVME_SC_QUEUE_SIZE = 0x102,
973 NVME_SC_ABORT_LIMIT = 0x103,
974 NVME_SC_ABORT_MISSING = 0x104,
975 NVME_SC_ASYNC_LIMIT = 0x105,
976 NVME_SC_FIRMWARE_SLOT = 0x106,
977 NVME_SC_FIRMWARE_IMAGE = 0x107,
978 NVME_SC_INVALID_VECTOR = 0x108,
979 NVME_SC_INVALID_LOG_PAGE = 0x109,
980 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 981 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 982 NVME_SC_INVALID_QUEUE = 0x10c,
983 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
984 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
985 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 986 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
987 NVME_SC_FW_NEEDS_RESET = 0x111,
988 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
989 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
990 NVME_SC_OVERLAPPING_RANGE = 0x114,
991 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
992 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
993 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
994 NVME_SC_NS_IS_PRIVATE = 0x119,
995 NVME_SC_NS_NOT_ATTACHED = 0x11a,
996 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
997 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 998
999 /*
1000 * I/O Command Set Specific - NVM commands:
1001 */
9d99a8dd
CH		 1002 NVME_SC_BAD_ATTRIBUTES = 0x180,
1003 NVME_SC_INVALID_PI = 0x181,
1004 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1005 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1006
1007 /*
1008 * I/O Command Set Specific - Fabrics commands:
1009 */
1010 NVME_SC_CONNECT_FORMAT = 0x180,
1011 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1012 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1013 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1014 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1015
1016 NVME_SC_DISCOVERY_RESTART = 0x190,
1017 NVME_SC_AUTH_REQUIRED = 0x191,
1018
1019 /*
1020 * Media and Data Integrity Errors:
1021 */
9d99a8dd
CH		 1022 NVME_SC_WRITE_FAULT = 0x280,
1023 NVME_SC_READ_ERROR = 0x281,
1024 NVME_SC_GUARD_CHECK = 0x282,
1025 NVME_SC_APPTAG_CHECK = 0x283,
1026 NVME_SC_REFTAG_CHECK = 0x284,
1027 NVME_SC_COMPARE_FAILED = 0x285,
1028 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1029 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1030
9d99a8dd 1031 NVME_SC_DNR = 0x4000,
cba3bdfd
JS		 1032
1033
1034 /*
1035 * FC Transport-specific error status values for NVME commands
1036 *
1037 * Transport-specific status code values must be in the range 0xB0..0xBF
1038 */
1039
1040 /* Generic FC failure - catchall */
1041 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0,
1042
1043 /* I/O failure due to FC ABTS'd */
1044 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1,
9d99a8dd
CH		 1045};
1046
1047struct nvme_completion {
eb793e2c
CH		 1048 /*
1049 * Used by Admin and Fabrics commands to return data:
1050 */
d49187e9
CH		 1051 union nvme_result {
1052 __le16 u16;
1053 __le32 u32;
1054 __le64 u64;
1055 } result;
9d99a8dd
CH		 1056 __le16 sq_head; /* how much of this queue may be reclaimed */
1057 __le16 sq_id; /* submission queue that generated this entry */
1058 __u16 command_id; /* of the command which completed */
1059 __le16 status; /* did the command fail, and if so, why? */
1060};
1061
8ef2074d
GKB		 1062#define NVME_VS(major, minor, tertiary) \
1063 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1064
b60503ba 1065#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)