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nvme-rdma: move NVME_RDMA_IP_PORT from common file
[linux-2.6-block.git] / include / linux / nvme.h
CommitLineData
fadccd8f 1/* SPDX-License-Identifier: GPL-2.0 */
b60503ba
MW		 2/*
3 * Definitions for the NVM Express interface
8757ad65 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
685e6311 10#include <linux/bits.h>
2812dfe3 11#include <linux/types.h>
8e412263 12#include <linux/uuid.h>
eb793e2c
CH		 13
14/* NQN names in commands fields specified one size */
15#define NVMF_NQN_FIELD_LEN 256
16
17/* However the max length of a qualified name is another size */
18#define NVMF_NQN_SIZE 223
19
20#define NVMF_TRSVCID_SIZE 32
21#define NVMF_TRADDR_SIZE 256
22#define NVMF_TSAS_SIZE 256
23
24#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
62346eae
AD		 26#define NVME_NSID_ALL 0xffffffff
27
eb793e2c 28enum nvme_subsys_type {
785d584c
HR		 29 /* Referral to another discovery type target subsystem */
30 NVME_NQN_DISC = 1,
31
32 /* NVME type target subsystem */
33 NVME_NQN_NVME = 2,
34
35 /* Current discovery type target subsystem */
36 NVME_NQN_CURR = 3,
eb793e2c
CH		 37};
38
e15a8a97
HR		 39enum nvme_ctrl_type {
40 NVME_CTRL_IO = 1, /* I/O controller */
41 NVME_CTRL_DISC = 2, /* Discovery controller */
42 NVME_CTRL_ADMIN = 3, /* Administrative controller */
43};
44
86c2457a
MB		 45enum nvme_dctype {
46 NVME_DCTYPE_NOT_REPORTED = 0,
47 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
48 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
49};
50
eb793e2c
CH		 51/* Address Family codes for Discovery Log Page entry ADRFAM field */
52enum {
53 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
54 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
55 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
56 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
57 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
d02abd19
CK		 58 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
59 NVMF_ADDR_FAMILY_MAX,
eb793e2c
CH		 60};
61
62/* Transport Type codes for Discovery Log Page entry TRTYPE field */
63enum {
64 NVMF_TRTYPE_RDMA = 1, /* RDMA */
65 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
fc221d05 66 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
eb793e2c
CH		 67 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
68 NVMF_TRTYPE_MAX,
69};
70
71/* Transport Requirements codes for Discovery Log Page entry TREQ field */
72enum {
9b95d2fb
SG		 73 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
74 NVMF_TREQ_REQUIRED = 1, /* Required */
75 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 76#define NVME_TREQ_SECURE_CHANNEL_MASK \
77 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
9b95d2fb
SG		 78
79 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
eb793e2c
CH		 80};
81
82/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
83 * RDMA_QPTYPE field
84 */
85enum {
bf17aa36
RD		 86 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
87 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 88};
89
90/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
91 * RDMA_QPTYPE field
92 */
93enum {
bf17aa36
RD		 94 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
95 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
96 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
97 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
98 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 99};
100
101/* RDMA Connection Management Service Type codes for Discovery Log Page
102 * entry TSAS RDMA_CMS field
103 */
104enum {
bf17aa36 105 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 106};
107
646f45b2
HR		 108/* TSAS SECTYPE for TCP transport */
109enum {
110 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
111 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
112 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
113};
114
7aa1f427 115#define NVME_AQ_DEPTH 32
38dabe21
KB		 116#define NVME_NR_AEN_COMMANDS 1
117#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
118
119/*
120 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
121 * NVM-Express 1.2 specification, section 4.1.2.
122 */
123#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 124
7a67cbea
CH		 125enum {
126 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
127 NVME_REG_VS = 0x0008, /* Version */
128 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 129 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 130 NVME_REG_CC = 0x0014, /* Controller Configuration */
131 NVME_REG_CSTS = 0x001c, /* Controller Status */
132 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
133 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
134 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 135 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
48c9e85b 136 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea 137 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
48c9e85b
RR		 138 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
139 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
140 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
141 * Location
142 */
20d3bb92
KJ		 143 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
144 * Space Control
145 */
354201c5 146 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
48c9e85b
RR		 147 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
148 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
149 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
150 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
151 * Buffer Size
152 */
153 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
154 * Write Throughput
155 */
97f6ef64 156 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 157};
158
a0cadb85 159#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 160#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 161#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 162#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
71010c30 163#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
8fc23e03 164#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 165#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
20d3bb92 166#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
22605f96 167
8ffaadf7
JD		 168#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
169#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598 170
354201c5
CH		 171#define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
172#define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
173
88de4598
CH		 174enum {
175 NVME_CMBSZ_SQS = 1 << 0,
176 NVME_CMBSZ_CQS = 1 << 1,
177 NVME_CMBSZ_LISTS = 1 << 2,
178 NVME_CMBSZ_RDS = 1 << 3,
179 NVME_CMBSZ_WDS = 1 << 4,
180
181 NVME_CMBSZ_SZ_SHIFT = 12,
182 NVME_CMBSZ_SZ_MASK = 0xfffff,
183
184 NVME_CMBSZ_SZU_SHIFT = 8,
185 NVME_CMBSZ_SZU_MASK = 0xf,
186};
8ffaadf7 187
69cd27e2
CH		 188/*
189 * Submission and Completion Queue Entry Sizes for the NVM command set.
190 * (In bytes and specified as a power of two (2^n)).
191 */
c1e0cc7e 192#define NVME_ADM_SQES 6
69cd27e2
CH		 193#define NVME_NVM_IOSQES 6
194#define NVME_NVM_IOCQES 4
195
b60503ba
MW		 196enum {
197 NVME_CC_ENABLE = 1 << 0,
ad4e05b2
MG		 198 NVME_CC_EN_SHIFT = 0,
199 NVME_CC_CSS_SHIFT = 4,
b60503ba 200 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 201 NVME_CC_AMS_SHIFT = 11,
202 NVME_CC_SHN_SHIFT = 14,
203 NVME_CC_IOSQES_SHIFT = 16,
204 NVME_CC_IOCQES_SHIFT = 20,
71010c30
NC		 205 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
206 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
207 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
60b43f62
MG		 208 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
209 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
210 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 211 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
212 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
213 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
214 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
215 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
216 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
354201c5 217 NVME_CC_CRIME = 1 << 24,
e626f37e
CH		 218};
219
220enum {
b60503ba
MW		 221 NVME_CSTS_RDY = 1 << 0,
222 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 223 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 224 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 225 NVME_CSTS_SHST_NORMAL = 0 << 2,
226 NVME_CSTS_SHST_OCCUR = 1 << 2,
227 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 228 NVME_CSTS_SHST_MASK = 3 << 2,
e626f37e
CH		 229};
230
231enum {
20d3bb92
KJ		 232 NVME_CMBMSC_CRE = 1 << 0,
233 NVME_CMBMSC_CMSE = 1 << 1,
b60503ba
MW		 234};
235
e626f37e
CH		 236enum {
237 NVME_CAP_CSS_NVM = 1 << 0,
238 NVME_CAP_CSS_CSI = 1 << 6,
239};
240
354201c5 241enum {
23c9cd56
JG		 242 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
243 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
354201c5
CH		 244};
245
9d99a8dd
CH		 246struct nvme_id_power_state {
247 __le16 max_power; /* centiwatts */
248 __u8 rsvd2;
249 __u8 flags;
250 __le32 entry_lat; /* microseconds */
251 __le32 exit_lat; /* microseconds */
252 __u8 read_tput;
253 __u8 read_lat;
254 __u8 write_tput;
255 __u8 write_lat;
256 __le16 idle_power;
257 __u8 idle_scale;
258 __u8 rsvd19;
259 __le16 active_power;
260 __u8 active_work_scale;
261 __u8 rsvd23[9];
262};
263
264enum {
265 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
266 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
267};
268
12b21171
SG		 269enum nvme_ctrl_attr {
270 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 271 NVME_CTRL_ATTR_TBKAS = (1 << 6),
4020aad8 272 NVME_CTRL_ATTR_ELBAS = (1 << 15),
12b21171
SG		 273};
274
9d99a8dd
CH		 275struct nvme_id_ctrl {
276 __le16 vid;
277 __le16 ssvid;
278 char sn[20];
279 char mn[40];
280 char fr[8];
281 __u8 rab;
282 __u8 ieee[3];
a446c084 283 __u8 cmic;
9d99a8dd 284 __u8 mdts;
08c69640
CH		 285 __le16 cntlid;
286 __le32 ver;
14e974a8
CH		 287 __le32 rtd3r;
288 __le32 rtd3e;
289 __le32 oaes;
eb793e2c 290 __le32 ctratt;
e15a8a97
HR		 291 __u8 rsvd100[11];
292 __u8 cntrltype;
293 __u8 fguid[16];
49cd84b6
KB		 294 __le16 crdt1;
295 __le16 crdt2;
296 __le16 crdt3;
297 __u8 rsvd134[122];
9d99a8dd
CH		 298 __le16 oacs;
299 __u8 acl;
300 __u8 aerl;
301 __u8 frmw;
302 __u8 lpa;
303 __u8 elpe;
304 __u8 npss;
305 __u8 avscc;
306 __u8 apsta;
307 __le16 wctemp;
308 __le16 cctemp;
a446c084
CH		 309 __le16 mtfa;
310 __le32 hmpre;
311 __le32 hmmin;
312 __u8 tnvmcap[16];
313 __u8 unvmcap[16];
314 __le32 rpmbs;
435e8090
GJ		 315 __le16 edstt;
316 __u8 dsto;
317 __u8 fwug;
7b89eae2 318 __le16 kas;
435e8090
GJ		 319 __le16 hctma;
320 __le16 mntmt;
321 __le16 mxtmt;
322 __le32 sanicap;
044a9df1
CH		 323 __le32 hmminds;
324 __le16 hmmaxd;
1a376216
CH		 325 __u8 rsvd338[4];
326 __u8 anatt;
327 __u8 anacap;
328 __le32 anagrpmax;
329 __le32 nanagrpid;
330 __u8 rsvd352[160];
9d99a8dd
CH		 331 __u8 sqes;
332 __u8 cqes;
eb793e2c 333 __le16 maxcmd;
9d99a8dd
CH		 334 __le32 nn;
335 __le16 oncs;
336 __le16 fuses;
337 __u8 fna;
338 __u8 vwc;
339 __le16 awun;
340 __le16 awupf;
341 __u8 nvscc;
93045d59 342 __u8 nwpc;
9d99a8dd
CH		 343 __le16 acwu;
344 __u8 rsvd534[2];
345 __le32 sgls;
1a376216
CH		 346 __le32 mnan;
347 __u8 rsvd544[224];
eb793e2c
CH		 348 char subnqn[256];
349 __u8 rsvd1024[768];
350 __le32 ioccsz;
351 __le32 iorcsz;
352 __le16 icdoff;
353 __u8 ctrattr;
354 __u8 msdbd;
86c2457a
MB		 355 __u8 rsvd1804[2];
356 __u8 dctype;
357 __u8 rsvd1807[241];
9d99a8dd
CH		 358 struct nvme_id_power_state psd[32];
359 __u8 vs[1024];
360};
361
362enum {
d56ae18f 363 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
92decf11
KB		 364 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
365 NVME_CTRL_CMIC_ANA = 1 << 3,
9d99a8dd
CH		 366 NVME_CTRL_ONCS_COMPARE = 1 << 0,
367 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
368 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 369 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
c1fef73f 370 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
dbf86b39 371 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 372 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 373 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
5974ea7c 374 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
f5d11840 375 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 376 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 377 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
48c9e85b
RR		 378 NVME_CTRL_CTRATT_128_ID = 1 << 0,
379 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
380 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
381 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
382 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
383 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
384 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
385 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
9d99a8dd
CH		 386};
387
388struct nvme_lbaf {
389 __le16 ms;
390 __u8 ds;
391 __u8 rp;
392};
393
394struct nvme_id_ns {
395 __le64 nsze;
396 __le64 ncap;
397 __le64 nuse;
398 __u8 nsfeat;
399 __u8 nlbaf;
400 __u8 flbas;
401 __u8 mc;
402 __u8 dpc;
403 __u8 dps;
404 __u8 nmic;
405 __u8 rescap;
406 __u8 fpi;
6605bdd5 407 __u8 dlfeat;
9d99a8dd
CH		 408 __le16 nawun;
409 __le16 nawupf;
410 __le16 nacwu;
411 __le16 nabsn;
412 __le16 nabo;
413 __le16 nabspf;
6b8190d6 414 __le16 noiob;
a446c084 415 __u8 nvmcap[16];
6605bdd5
BVA		 416 __le16 npwg;
417 __le16 npwa;
418 __le16 npdg;
419 __le16 npda;
420 __le16 nows;
421 __u8 rsvd74[18];
1a376216 422 __le32 anagrpid;
93045d59
CK		 423 __u8 rsvd96[3];
424 __u8 nsattr;
6605bdd5
BVA		 425 __le16 nvmsetid;
426 __le16 endgid;
9d99a8dd
CH		 427 __u8 nguid[16];
428 __u8 eui64[8];
4020aad8 429 struct nvme_lbaf lbaf[64];
9d99a8dd
CH		 430 __u8 vs[3712];
431};
432
354201c5
CH		 433/* I/O Command Set Independent Identify Namespace Data Structure */
434struct nvme_id_ns_cs_indep {
435 __u8 nsfeat;
436 __u8 nmic;
437 __u8 rescap;
438 __u8 fpi;
439 __le32 anagrpid;
440 __u8 nsattr;
441 __u8 rsvd9;
442 __le16 nvmsetid;
443 __le16 endgid;
444 __u8 nstat;
445 __u8 rsvd15[4081];
446};
447
240e6ee2
KB		 448struct nvme_zns_lbafe {
449 __le64 zsze;
450 __u8 zdes;
451 __u8 rsvd9[7];
452};
453
454struct nvme_id_ns_zns {
455 __le16 zoc;
456 __le16 ozcs;
457 __le32 mar;
458 __le32 mor;
459 __le32 rrl;
460 __le32 frl;
461 __u8 rsvd20[2796];
4020aad8 462 struct nvme_zns_lbafe lbafe[64];
240e6ee2
KB		 463 __u8 vs[256];
464};
465
466struct nvme_id_ctrl_zns {
467 __u8 zasl;
468 __u8 rsvd1[4095];
469};
470
4020aad8
KB		 471struct nvme_id_ns_nvm {
472 __le64 lbstm;
473 __u8 pic;
474 __u8 rsvd9[3];
475 __le32 elbaf[64];
476 __u8 rsvd268[3828];
477};
478
479enum {
b938e660 480 NVME_ID_NS_NVM_STS_MASK = 0x7f,
4020aad8
KB		 481 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
482 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
483};
484
485static inline __u8 nvme_elbaf_sts(__u32 elbaf)
486{
487 return elbaf & NVME_ID_NS_NVM_STS_MASK;
488}
489
490static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
491{
492 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
493}
494
5befc7c2
KB		 495struct nvme_id_ctrl_nvm {
496 __u8 vsl;
497 __u8 wzsl;
498 __u8 wusl;
499 __u8 dmrl;
500 __le32 dmrsl;
501 __le64 dmsl;
502 __u8 rsvd16[4080];
503};
504
329dd768
CH		 505enum {
506 NVME_ID_CNS_NS = 0x00,
507 NVME_ID_CNS_CTRL = 0x01,
508 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 509 NVME_ID_CNS_NS_DESC_LIST = 0x03,
71010c30
NC		 510 NVME_ID_CNS_CS_NS = 0x05,
511 NVME_ID_CNS_CS_CTRL = 0x06,
354201c5 512 NVME_ID_CNS_NS_CS_INDEP = 0x08,
329dd768
CH		 513 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
514 NVME_ID_CNS_NS_PRESENT = 0x11,
515 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
516 NVME_ID_CNS_CTRL_LIST = 0x13,
48c9e85b
RR		 517 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
518 NVME_ID_CNS_NS_GRANULARITY = 0x16,
519 NVME_ID_CNS_UUID_LIST = 0x17,
329dd768
CH		 520};
521
71010c30
NC		 522enum {
523 NVME_CSI_NVM = 0,
240e6ee2 524 NVME_CSI_ZNS = 2,
71010c30
NC		 525};
526
f5d11840
JA		 527enum {
528 NVME_DIR_IDENTIFY = 0x00,
529 NVME_DIR_STREAMS = 0x01,
530 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
531 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
532 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
533 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
534 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
535 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
536 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
537 NVME_DIR_ENDIR = 0x01,
538};
539
9d99a8dd
CH		 540enum {
541 NVME_NS_FEAT_THIN = 1 << 0,
92decf11
KB		 542 NVME_NS_FEAT_ATOMICS = 1 << 1,
543 NVME_NS_FEAT_IO_OPT = 1 << 4,
544 NVME_NS_ATTR_RO = 1 << 0,
9d99a8dd 545 NVME_NS_FLBAS_LBA_MASK = 0xf,
4020aad8
KB		 546 NVME_NS_FLBAS_LBA_UMASK = 0x60,
547 NVME_NS_FLBAS_LBA_SHIFT = 1,
9d99a8dd 548 NVME_NS_FLBAS_META_EXT = 0x10,
92decf11 549 NVME_NS_NMIC_SHARED = 1 << 0,
9d99a8dd
CH		 550 NVME_LBAF_RP_BEST = 0,
551 NVME_LBAF_RP_BETTER = 1,
552 NVME_LBAF_RP_GOOD = 2,
553 NVME_LBAF_RP_DEGRADED = 3,
554 NVME_NS_DPC_PI_LAST = 1 << 4,
555 NVME_NS_DPC_PI_FIRST = 1 << 3,
556 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
557 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
558 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
559 NVME_NS_DPS_PI_FIRST = 1 << 3,
560 NVME_NS_DPS_PI_MASK = 0x7,
561 NVME_NS_DPS_PI_TYPE1 = 1,
562 NVME_NS_DPS_PI_TYPE2 = 2,
563 NVME_NS_DPS_PI_TYPE3 = 3,
564};
565
354201c5
CH		 566enum {
567 NVME_NSTAT_NRDY = 1 << 0,
568};
569
4020aad8
KB		 570enum {
571 NVME_NVM_NS_16B_GUARD = 0,
572 NVME_NVM_NS_32B_GUARD = 1,
573 NVME_NVM_NS_64B_GUARD = 2,
574};
575
576static inline __u8 nvme_lbaf_index(__u8 flbas)
577{
578 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
579 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
580}
581
39481fbd
IR		 582/* Identify Namespace Metadata Capabilities (MC): */
583enum {
584 NVME_MC_EXTENDED_LBA = (1 << 0),
585 NVME_MC_METADATA_PTR = (1 << 1),
586};
587
af8b86e9
JT		 588struct nvme_ns_id_desc {
589 __u8 nidt;
590 __u8 nidl;
591 __le16 reserved;
592};
593
594#define NVME_NIDT_EUI64_LEN 8
595#define NVME_NIDT_NGUID_LEN 16
596#define NVME_NIDT_UUID_LEN 16
71010c30 597#define NVME_NIDT_CSI_LEN 1
af8b86e9
JT		 598
599enum {
600 NVME_NIDT_EUI64 = 0x01,
601 NVME_NIDT_NGUID = 0x02,
602 NVME_NIDT_UUID = 0x03,
71010c30 603 NVME_NIDT_CSI = 0x04,
af8b86e9
JT		 604};
605
9d99a8dd
CH		 606struct nvme_smart_log {
607 __u8 critical_warning;
608 __u8 temperature[2];
609 __u8 avail_spare;
610 __u8 spare_thresh;
611 __u8 percent_used;
48c9e85b
RR		 612 __u8 endu_grp_crit_warn_sumry;
613 __u8 rsvd7[25];
9d99a8dd
CH		 614 __u8 data_units_read[16];
615 __u8 data_units_written[16];
616 __u8 host_reads[16];
617 __u8 host_writes[16];
618 __u8 ctrl_busy_time[16];
619 __u8 power_cycles[16];
620 __u8 power_on_hours[16];
621 __u8 unsafe_shutdowns[16];
622 __u8 media_errors[16];
623 __u8 num_err_log_entries[16];
624 __le32 warning_temp_time;
625 __le32 critical_comp_time;
626 __le16 temp_sensor[8];
48c9e85b
RR		 627 __le32 thm_temp1_trans_count;
628 __le32 thm_temp2_trans_count;
629 __le32 thm_temp1_total_time;
630 __le32 thm_temp2_total_time;
631 __u8 rsvd232[280];
9d99a8dd
CH		 632};
633
b6dccf7f
AD		 634struct nvme_fw_slot_info_log {
635 __u8 afi;
636 __u8 rsvd1[7];
637 __le64 frs[7];
638 __u8 rsvd64[448];
639};
640
84fef62d
KB		 641enum {
642 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
643 NVME_CMD_EFFECTS_LBCC = 1 << 1,
644 NVME_CMD_EFFECTS_NCC = 1 << 2,
645 NVME_CMD_EFFECTS_NIC = 1 << 3,
646 NVME_CMD_EFFECTS_CCC = 1 << 4,
685e6311 647 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
48c9e85b 648 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
6f99ac04 649 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
84fef62d
KB		 650};
651
652struct nvme_effects_log {
653 __le32 acs[256];
654 __le32 iocs[256];
655 __u8 resv[2048];
656};
657
1a376216
CH		 658enum nvme_ana_state {
659 NVME_ANA_OPTIMIZED = 0x01,
660 NVME_ANA_NONOPTIMIZED = 0x02,
661 NVME_ANA_INACCESSIBLE = 0x03,
662 NVME_ANA_PERSISTENT_LOSS = 0x04,
663 NVME_ANA_CHANGE = 0x0f,
664};
665
666struct nvme_ana_group_desc {
667 __le32 grpid;
668 __le32 nnsids;
669 __le64 chgcnt;
670 __u8 state;
8b92d0e3 671 __u8 rsvd17[15];
1a376216
CH		 672 __le32 nsids[];
673};
674
675/* flag for the log specific field of the ANA log */
676#define NVME_ANA_LOG_RGO (1 << 0)
677
678struct nvme_ana_rsp_hdr {
679 __le64 chgcnt;
680 __le16 ngrps;
681 __le16 rsvd10[3];
682};
683
240e6ee2
KB		 684struct nvme_zone_descriptor {
685 __u8 zt;
686 __u8 zs;
687 __u8 za;
688 __u8 rsvd3[5];
689 __le64 zcap;
690 __le64 zslba;
691 __le64 wp;
692 __u8 rsvd32[32];
693};
694
695enum {
696 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
697};
698
699struct nvme_zone_report {
700 __le64 nr_zones;
701 __u8 resv8[56];
702 struct nvme_zone_descriptor entries[];
703};
704
9d99a8dd
CH		 705enum {
706 NVME_SMART_CRIT_SPARE = 1 << 0,
707 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
708 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
709 NVME_SMART_CRIT_MEDIA = 1 << 3,
710 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
711};
712
713enum {
e3d7874d
KB		 714 NVME_AER_ERROR = 0,
715 NVME_AER_SMART = 1,
868c2392 716 NVME_AER_NOTICE = 2,
e3d7874d
KB		 717 NVME_AER_CSS = 6,
718 NVME_AER_VS = 7,
868c2392
CH		 719};
720
2c61c97f
MK		 721enum {
722 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
723};
724
868c2392
CH		 725enum {
726 NVME_AER_NOTICE_NS_CHANGED = 0x00,
727 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 728 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 729 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 730};
731
aafd3afe 732enum {
7114ddeb
JS		 733 NVME_AEN_BIT_NS_ATTR = 8,
734 NVME_AEN_BIT_FW_ACT = 9,
735 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 736 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 737};
738
739enum {
740 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
741 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
742 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 743 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 744};
745
9d99a8dd
CH		 746struct nvme_lba_range_type {
747 __u8 type;
748 __u8 attributes;
749 __u8 rsvd2[14];
8cf486e1
WS		 750 __le64 slba;
751 __le64 nlb;
9d99a8dd
CH		 752 __u8 guid[16];
753 __u8 rsvd48[16];
754};
755
756enum {
757 NVME_LBART_TYPE_FS = 0x01,
758 NVME_LBART_TYPE_RAID = 0x02,
759 NVME_LBART_TYPE_CACHE = 0x03,
760 NVME_LBART_TYPE_SWAP = 0x04,
761
762 NVME_LBART_ATTRIB_TEMP = 1 << 0,
763 NVME_LBART_ATTRIB_HIDE = 1 << 1,
764};
765
be1a7cd2
MC		 766enum nvme_pr_type {
767 NVME_PR_WRITE_EXCLUSIVE = 1,
768 NVME_PR_EXCLUSIVE_ACCESS = 2,
769 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
770 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
771 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
772 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
773};
774
5fd96a4e
MC		 775enum nvme_eds {
776 NVME_EXTENDED_DATA_STRUCT = 0x1,
777};
778
f2bf2e7e
MC		 779struct nvme_registered_ctrl {
780 __le16 cntlid;
781 __u8 rcsts;
782 __u8 rsvd3[5];
783 __le64 hostid;
784 __le64 rkey;
785};
786
9d99a8dd
CH		 787struct nvme_reservation_status {
788 __le32 gen;
789 __u8 rtype;
790 __u8 regctl[2];
791 __u8 resv5[2];
792 __u8 ptpls;
f2bf2e7e
MC		 793 __u8 resv10[14];
794 struct nvme_registered_ctrl regctl_ds[];
795};
796
797struct nvme_registered_ctrl_ext {
798 __le16 cntlid;
799 __u8 rcsts;
800 __u8 rsvd3[5];
801 __le64 rkey;
802 __u8 hostid[16];
803 __u8 rsvd32[32];
804};
805
806struct nvme_reservation_status_ext {
807 __le32 gen;
808 __u8 rtype;
809 __u8 regctl[2];
810 __u8 resv5[2];
811 __u8 ptpls;
812 __u8 resv10[14];
813 __u8 rsvd24[40];
814 struct nvme_registered_ctrl_ext regctl_eds[];
9d99a8dd
CH		 815};
816
817/* I/O commands */
818
819enum nvme_opcode {
820 nvme_cmd_flush = 0x00,
821 nvme_cmd_write = 0x01,
822 nvme_cmd_read = 0x02,
823 nvme_cmd_write_uncor = 0x04,
824 nvme_cmd_compare = 0x05,
825 nvme_cmd_write_zeroes = 0x08,
826 nvme_cmd_dsm = 0x09,
48c9e85b 827 nvme_cmd_verify = 0x0c,
9d99a8dd
CH		 828 nvme_cmd_resv_register = 0x0d,
829 nvme_cmd_resv_report = 0x0e,
830 nvme_cmd_resv_acquire = 0x11,
831 nvme_cmd_resv_release = 0x15,
240e6ee2
KB		 832 nvme_cmd_zone_mgmt_send = 0x79,
833 nvme_cmd_zone_mgmt_recv = 0x7a,
834 nvme_cmd_zone_append = 0x7d,
855b7717 835 nvme_cmd_vendor_start = 0x80,
9d99a8dd
CH		 836};
837
26f2990d
MI		 838#define nvme_opcode_name(opcode) { opcode, #opcode }
839#define show_nvm_opcode_name(val) \
840 __print_symbolic(val, \
841 nvme_opcode_name(nvme_cmd_flush), \
842 nvme_opcode_name(nvme_cmd_write), \
843 nvme_opcode_name(nvme_cmd_read), \
844 nvme_opcode_name(nvme_cmd_write_uncor), \
845 nvme_opcode_name(nvme_cmd_compare), \
846 nvme_opcode_name(nvme_cmd_write_zeroes), \
847 nvme_opcode_name(nvme_cmd_dsm), \
8e19b87c 848 nvme_opcode_name(nvme_cmd_verify), \
26f2990d
MI		 849 nvme_opcode_name(nvme_cmd_resv_register), \
850 nvme_opcode_name(nvme_cmd_resv_report), \
851 nvme_opcode_name(nvme_cmd_resv_acquire), \
4a407d5e
JT		 852 nvme_opcode_name(nvme_cmd_resv_release), \
853 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
854 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
855 nvme_opcode_name(nvme_cmd_zone_append))
856
26f2990d
MI		 857
858
eb793e2c
CH		 859/*
860 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
861 *
862 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
863 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 864 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 865 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
866 * request subtype
867 */
868enum {
869 NVME_SGL_FMT_ADDRESS = 0x00,
870 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 871 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 872 NVME_SGL_FMT_INVALIDATE = 0x0f,
873};
874
875/*
876 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
877 *
878 * For struct nvme_sgl_desc:
879 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
880 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
881 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
882 *
883 * For struct nvme_keyed_sgl_desc:
884 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 885 *
886 * Transport-specific SGL types:
887 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 888 */
889enum {
890 NVME_SGL_FMT_DATA_DESC = 0x00,
891 NVME_SGL_FMT_SEG_DESC = 0x02,
892 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
893 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 894 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 895};
896
897struct nvme_sgl_desc {
898 __le64 addr;
899 __le32 length;
900 __u8 rsvd[3];
901 __u8 type;
902};
903
904struct nvme_keyed_sgl_desc {
905 __le64 addr;
906 __u8 length[3];
907 __u8 key[4];
908 __u8 type;
909};
910
911union nvme_data_ptr {
912 struct {
913 __le64 prp1;
914 __le64 prp2;
915 };
916 struct nvme_sgl_desc sgl;
917 struct nvme_keyed_sgl_desc ksgl;
918};
919
3972be23
JS		 920/*
921 * Lowest two bits of our flags field (FUSE field in the spec):
922 *
923 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
924 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
925 *
926 * Highest two bits in our flags field (PSDT field in the spec):
927 *
928 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
929 * If used, MPTR contains addr of single physical buffer (byte aligned).
930 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
931 * If used, MPTR contains an address of an SGL segment containing
932 * exactly 1 SGL descriptor (qword aligned).
933 */
934enum {
935 NVME_CMD_FUSE_FIRST = (1 << 0),
936 NVME_CMD_FUSE_SECOND = (1 << 1),
937
938 NVME_CMD_SGL_METABUF = (1 << 6),
939 NVME_CMD_SGL_METASEG = (1 << 7),
940 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
941};
942
9d99a8dd
CH		 943struct nvme_common_command {
944 __u8 opcode;
945 __u8 flags;
946 __u16 command_id;
947 __le32 nsid;
948 __le32 cdw2[2];
949 __le64 metadata;
eb793e2c 950 union nvme_data_ptr dptr;
5c629dc9 951 struct_group(cdws,
b7c8f366
CK		 952 __le32 cdw10;
953 __le32 cdw11;
954 __le32 cdw12;
955 __le32 cdw13;
956 __le32 cdw14;
957 __le32 cdw15;
5c629dc9 958 );
9d99a8dd
CH		 959};
960
961struct nvme_rw_command {
962 __u8 opcode;
963 __u8 flags;
964 __u16 command_id;
965 __le32 nsid;
4020aad8
KB		 966 __le32 cdw2;
967 __le32 cdw3;
9d99a8dd 968 __le64 metadata;
eb793e2c 969 union nvme_data_ptr dptr;
9d99a8dd
CH		 970 __le64 slba;
971 __le16 length;
972 __le16 control;
973 __le32 dsmgmt;
974 __le32 reftag;
975 __le16 apptag;
976 __le16 appmask;
977};
978
979enum {
980 NVME_RW_LR = 1 << 15,
981 NVME_RW_FUA = 1 << 14,
240e6ee2 982 NVME_RW_APPEND_PIREMAP = 1 << 9,
9d99a8dd
CH		 983 NVME_RW_DSM_FREQ_UNSPEC = 0,
984 NVME_RW_DSM_FREQ_TYPICAL = 1,
985 NVME_RW_DSM_FREQ_RARE = 2,
986 NVME_RW_DSM_FREQ_READS = 3,
987 NVME_RW_DSM_FREQ_WRITES = 4,
988 NVME_RW_DSM_FREQ_RW = 5,
989 NVME_RW_DSM_FREQ_ONCE = 6,
990 NVME_RW_DSM_FREQ_PREFETCH = 7,
991 NVME_RW_DSM_FREQ_TEMP = 8,
992 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
993 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
994 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
995 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
996 NVME_RW_DSM_SEQ_REQ = 1 << 6,
997 NVME_RW_DSM_COMPRESSED = 1 << 7,
998 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
999 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1000 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1001 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 1002 NVME_RW_DTYPE_STREAMS = 1 << 4,
1b96f862 1003 NVME_WZ_DEAC = 1 << 9,
9d99a8dd
CH		 1004};
1005
1006struct nvme_dsm_cmd {
1007 __u8 opcode;
1008 __u8 flags;
1009 __u16 command_id;
1010 __le32 nsid;
1011 __u64 rsvd2[2];
eb793e2c 1012 union nvme_data_ptr dptr;
9d99a8dd
CH		 1013 __le32 nr;
1014 __le32 attributes;
1015 __u32 rsvd12[4];
1016};
1017
1018enum {
1019 NVME_DSMGMT_IDR = 1 << 0,
1020 NVME_DSMGMT_IDW = 1 << 1,
1021 NVME_DSMGMT_AD = 1 << 2,
1022};
1023
b35ba01e
CH		 1024#define NVME_DSM_MAX_RANGES 256
1025
9d99a8dd
CH		 1026struct nvme_dsm_range {
1027 __le32 cattr;
1028 __le32 nlb;
1029 __le64 slba;
1030};
1031
3b7c33b2
CK		 1032struct nvme_write_zeroes_cmd {
1033 __u8 opcode;
1034 __u8 flags;
1035 __u16 command_id;
1036 __le32 nsid;
1037 __u64 rsvd2;
1038 __le64 metadata;
1039 union nvme_data_ptr dptr;
1040 __le64 slba;
1041 __le16 length;
1042 __le16 control;
1043 __le32 dsmgmt;
1044 __le32 reftag;
1045 __le16 apptag;
1046 __le16 appmask;
1047};
1048
240e6ee2
KB		 1049enum nvme_zone_mgmt_action {
1050 NVME_ZONE_CLOSE = 0x1,
1051 NVME_ZONE_FINISH = 0x2,
1052 NVME_ZONE_OPEN = 0x3,
1053 NVME_ZONE_RESET = 0x4,
1054 NVME_ZONE_OFFLINE = 0x5,
1055 NVME_ZONE_SET_DESC_EXT = 0x10,
1056};
1057
1058struct nvme_zone_mgmt_send_cmd {
1059 __u8 opcode;
1060 __u8 flags;
1061 __u16 command_id;
1062 __le32 nsid;
1063 __le32 cdw2[2];
1064 __le64 metadata;
1065 union nvme_data_ptr dptr;
1066 __le64 slba;
1067 __le32 cdw12;
1068 __u8 zsa;
1069 __u8 select_all;
1070 __u8 rsvd13[2];
1071 __le32 cdw14[2];
1072};
1073
1074struct nvme_zone_mgmt_recv_cmd {
1075 __u8 opcode;
1076 __u8 flags;
1077 __u16 command_id;
1078 __le32 nsid;
1079 __le64 rsvd2[2];
1080 union nvme_data_ptr dptr;
1081 __le64 slba;
1082 __le32 numd;
1083 __u8 zra;
1084 __u8 zrasf;
1085 __u8 pr;
1086 __u8 rsvd13;
1087 __le32 cdw14[2];
1088};
1089
1090enum {
1091 NVME_ZRA_ZONE_REPORT = 0,
1092 NVME_ZRASF_ZONE_REPORT_ALL = 0,
aaf2e048
CK		 1093 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1094 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1095 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1096 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1097 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1098 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1099 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
240e6ee2
KB		 1100 NVME_REPORT_ZONE_PARTIAL = 1,
1101};
1102
c5552fde
AL		 1103/* Features */
1104
52deba0f
AM		 1105enum {
1106 NVME_TEMP_THRESH_MASK = 0xffff,
1107 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1108 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1109};
1110
c5552fde
AL		 1111struct nvme_feat_auto_pst {
1112 __le64 entries[32];
1113};
1114
39673e19
CH		 1115enum {
1116 NVME_HOST_MEM_ENABLE = (1 << 0),
1117 NVME_HOST_MEM_RETURN = (1 << 1),
1118};
1119
49cd84b6
KB		 1120struct nvme_feat_host_behavior {
1121 __u8 acre;
4020aad8
KB		 1122 __u8 etdas;
1123 __u8 lbafee;
1124 __u8 resv1[509];
49cd84b6
KB		 1125};
1126
1127enum {
1128 NVME_ENABLE_ACRE = 1,
4020aad8 1129 NVME_ENABLE_LBAFEE = 1,
49cd84b6
KB		 1130};
1131
9d99a8dd
CH		 1132/* Admin commands */
1133
1134enum nvme_admin_opcode {
1135 nvme_admin_delete_sq = 0x00,
1136 nvme_admin_create_sq = 0x01,
1137 nvme_admin_get_log_page = 0x02,
1138 nvme_admin_delete_cq = 0x04,
1139 nvme_admin_create_cq = 0x05,
1140 nvme_admin_identify = 0x06,
1141 nvme_admin_abort_cmd = 0x08,
1142 nvme_admin_set_features = 0x09,
1143 nvme_admin_get_features = 0x0a,
1144 nvme_admin_async_event = 0x0c,
a446c084 1145 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 1146 nvme_admin_activate_fw = 0x10,
1147 nvme_admin_download_fw = 0x11,
48c9e85b 1148 nvme_admin_dev_self_test = 0x14,
a446c084 1149 nvme_admin_ns_attach = 0x15,
7b89eae2 1150 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 1151 nvme_admin_directive_send = 0x19,
1152 nvme_admin_directive_recv = 0x1a,
48c9e85b
RR		 1153 nvme_admin_virtual_mgmt = 0x1c,
1154 nvme_admin_nvme_mi_send = 0x1d,
1155 nvme_admin_nvme_mi_recv = 0x1e,
f9f38e33 1156 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 1157 nvme_admin_format_nvm = 0x80,
1158 nvme_admin_security_send = 0x81,
1159 nvme_admin_security_recv = 0x82,
84fef62d 1160 nvme_admin_sanitize_nvm = 0x84,
c6389845 1161 nvme_admin_get_lba_status = 0x86,
c1fef73f 1162 nvme_admin_vendor_start = 0xC0,
9d99a8dd
CH		 1163};
1164
26f2990d
MI		 1165#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1166#define show_admin_opcode_name(val) \
1167 __print_symbolic(val, \
1168 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1169 nvme_admin_opcode_name(nvme_admin_create_sq), \
1170 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1171 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1172 nvme_admin_opcode_name(nvme_admin_create_cq), \
1173 nvme_admin_opcode_name(nvme_admin_identify), \
1174 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1175 nvme_admin_opcode_name(nvme_admin_set_features), \
1176 nvme_admin_opcode_name(nvme_admin_get_features), \
1177 nvme_admin_opcode_name(nvme_admin_async_event), \
1178 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1179 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1180 nvme_admin_opcode_name(nvme_admin_download_fw), \
8e19b87c 1181 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
26f2990d
MI		 1182 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1183 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1184 nvme_admin_opcode_name(nvme_admin_directive_send), \
1185 nvme_admin_opcode_name(nvme_admin_directive_recv), \
8e19b87c
MI		 1186 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1187 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1188 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
26f2990d
MI		 1189 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1190 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1191 nvme_admin_opcode_name(nvme_admin_security_send), \
1192 nvme_admin_opcode_name(nvme_admin_security_recv), \
a5ef7572
MI		 1193 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1194 nvme_admin_opcode_name(nvme_admin_get_lba_status))
26f2990d 1195
9d99a8dd
CH		 1196enum {
1197 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1198 NVME_CQ_IRQ_ENABLED = (1 << 1),
1199 NVME_SQ_PRIO_URGENT = (0 << 1),
1200 NVME_SQ_PRIO_HIGH = (1 << 1),
1201 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1202 NVME_SQ_PRIO_LOW = (3 << 1),
1203 NVME_FEAT_ARBITRATION = 0x01,
1204 NVME_FEAT_POWER_MGMT = 0x02,
1205 NVME_FEAT_LBA_RANGE = 0x03,
1206 NVME_FEAT_TEMP_THRESH = 0x04,
1207 NVME_FEAT_ERR_RECOVERY = 0x05,
1208 NVME_FEAT_VOLATILE_WC = 0x06,
1209 NVME_FEAT_NUM_QUEUES = 0x07,
1210 NVME_FEAT_IRQ_COALESCE = 0x08,
1211 NVME_FEAT_IRQ_CONFIG = 0x09,
1212 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1213 NVME_FEAT_ASYNC_EVENT = 0x0b,
1214 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 1215 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 1216 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 1217 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 1218 NVME_FEAT_HCTM = 0x10,
1219 NVME_FEAT_NOPSC = 0x11,
1220 NVME_FEAT_RRL = 0x12,
1221 NVME_FEAT_PLM_CONFIG = 0x13,
1222 NVME_FEAT_PLM_WINDOW = 0x14,
49cd84b6 1223 NVME_FEAT_HOST_BEHAVIOR = 0x16,
48c9e85b 1224 NVME_FEAT_SANITIZE = 0x17,
9d99a8dd
CH		 1225 NVME_FEAT_SW_PROGRESS = 0x80,
1226 NVME_FEAT_HOST_ID = 0x81,
1227 NVME_FEAT_RESV_MASK = 0x82,
1228 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 1229 NVME_FEAT_WRITE_PROTECT = 0x84,
c1fef73f
LG		 1230 NVME_FEAT_VENDOR_START = 0xC0,
1231 NVME_FEAT_VENDOR_END = 0xFF,
9d99a8dd
CH		 1232 NVME_LOG_ERROR = 0x01,
1233 NVME_LOG_SMART = 0x02,
1234 NVME_LOG_FW_SLOT = 0x03,
b3984e06 1235 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 1236 NVME_LOG_CMD_EFFECTS = 0x05,
48c9e85b
RR		 1237 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1238 NVME_LOG_TELEMETRY_HOST = 0x07,
1239 NVME_LOG_TELEMETRY_CTRL = 0x08,
1240 NVME_LOG_ENDURANCE_GROUP = 0x09,
1a376216 1241 NVME_LOG_ANA = 0x0c,
eb793e2c 1242 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 1243 NVME_LOG_RESERVATION = 0x80,
1244 NVME_FWACT_REPL = (0 << 3),
1245 NVME_FWACT_REPL_ACTV = (1 << 3),
1246 NVME_FWACT_ACTV = (2 << 3),
1247};
1248
93045d59
CK		 1249/* NVMe Namespace Write Protect State */
1250enum {
1251 NVME_NS_NO_WRITE_PROTECT = 0,
1252 NVME_NS_WRITE_PROTECT,
1253 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1254 NVME_NS_WRITE_PROTECT_PERMANENT,
1255};
1256
b3984e06
CH		 1257#define NVME_MAX_CHANGED_NAMESPACES 1024
1258
9d99a8dd
CH		 1259struct nvme_identify {
1260 __u8 opcode;
1261 __u8 flags;
1262 __u16 command_id;
1263 __le32 nsid;
1264 __u64 rsvd2[2];
eb793e2c 1265 union nvme_data_ptr dptr;
986994a2
PP		 1266 __u8 cns;
1267 __u8 rsvd3;
1268 __le16 ctrlid;
71010c30
NC		 1269 __u8 rsvd11[3];
1270 __u8 csi;
1271 __u32 rsvd12[4];
9d99a8dd
CH		 1272};
1273
0add5e8e
JT		 1274#define NVME_IDENTIFY_DATA_SIZE 4096
1275
9d99a8dd
CH		 1276struct nvme_features {
1277 __u8 opcode;
1278 __u8 flags;
1279 __u16 command_id;
1280 __le32 nsid;
1281 __u64 rsvd2[2];
eb793e2c 1282 union nvme_data_ptr dptr;
9d99a8dd
CH		 1283 __le32 fid;
1284 __le32 dword11;
b85cf734
AD		 1285 __le32 dword12;
1286 __le32 dword13;
1287 __le32 dword14;
1288 __le32 dword15;
9d99a8dd
CH		 1289};
1290
39673e19
CH		 1291struct nvme_host_mem_buf_desc {
1292 __le64 addr;
1293 __le32 size;
1294 __u32 rsvd;
1295};
1296
9d99a8dd
CH		 1297struct nvme_create_cq {
1298 __u8 opcode;
1299 __u8 flags;
1300 __u16 command_id;
1301 __u32 rsvd1[5];
1302 __le64 prp1;
1303 __u64 rsvd8;
1304 __le16 cqid;
1305 __le16 qsize;
1306 __le16 cq_flags;
1307 __le16 irq_vector;
1308 __u32 rsvd12[4];
1309};
1310
1311struct nvme_create_sq {
1312 __u8 opcode;
1313 __u8 flags;
1314 __u16 command_id;
1315 __u32 rsvd1[5];
1316 __le64 prp1;
1317 __u64 rsvd8;
1318 __le16 sqid;
1319 __le16 qsize;
1320 __le16 sq_flags;
1321 __le16 cqid;
1322 __u32 rsvd12[4];
1323};
1324
1325struct nvme_delete_queue {
1326 __u8 opcode;
1327 __u8 flags;
1328 __u16 command_id;
1329 __u32 rsvd1[9];
1330 __le16 qid;
1331 __u16 rsvd10;
1332 __u32 rsvd11[5];
1333};
1334
1335struct nvme_abort_cmd {
1336 __u8 opcode;
1337 __u8 flags;
1338 __u16 command_id;
1339 __u32 rsvd1[9];
1340 __le16 sqid;
1341 __u16 cid;
1342 __u32 rsvd11[5];
1343};
1344
1345struct nvme_download_firmware {
1346 __u8 opcode;
1347 __u8 flags;
1348 __u16 command_id;
1349 __u32 rsvd1[5];
eb793e2c 1350 union nvme_data_ptr dptr;
9d99a8dd
CH		 1351 __le32 numd;
1352 __le32 offset;
1353 __u32 rsvd12[4];
1354};
1355
1356struct nvme_format_cmd {
1357 __u8 opcode;
1358 __u8 flags;
1359 __u16 command_id;
1360 __le32 nsid;
1361 __u64 rsvd2[4];
1362 __le32 cdw10;
1363 __u32 rsvd11[5];
1364};
1365
725b3588
AB		 1366struct nvme_get_log_page_command {
1367 __u8 opcode;
1368 __u8 flags;
1369 __u16 command_id;
1370 __le32 nsid;
1371 __u64 rsvd2[2];
eb793e2c 1372 union nvme_data_ptr dptr;
725b3588 1373 __u8 lid;
9b89bc38 1374 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 1375 __le16 numdl;
1376 __le16 numdu;
1377 __u16 rsvd11;
d808b7f7
KB		 1378 union {
1379 struct {
1380 __le32 lpol;
1381 __le32 lpou;
1382 };
1383 __le64 lpo;
1384 };
be93e87e
KB		 1385 __u8 rsvd14[3];
1386 __u8 csi;
1387 __u32 rsvd15;
725b3588
AB		 1388};
1389
f5d11840
JA		 1390struct nvme_directive_cmd {
1391 __u8 opcode;
1392 __u8 flags;
1393 __u16 command_id;
1394 __le32 nsid;
1395 __u64 rsvd2[2];
1396 union nvme_data_ptr dptr;
1397 __le32 numd;
1398 __u8 doper;
1399 __u8 dtype;
1400 __le16 dspec;
1401 __u8 endir;
1402 __u8 tdtype;
1403 __u16 rsvd15;
1404
1405 __u32 rsvd16[3];
1406};
1407
eb793e2c
CH		 1408/*
1409 * Fabrics subcommands.
1410 */
1411enum nvmf_fabrics_opcode {
1412 nvme_fabrics_command = 0x7f,
1413};
1414
1415enum nvmf_capsule_command {
1416 nvme_fabrics_type_property_set = 0x00,
1417 nvme_fabrics_type_connect = 0x01,
1418 nvme_fabrics_type_property_get = 0x04,
88b140fe
HR		 1419 nvme_fabrics_type_auth_send = 0x05,
1420 nvme_fabrics_type_auth_receive = 0x06,
eb793e2c
CH		 1421};
1422
ad795e47
MI		 1423#define nvme_fabrics_type_name(type) { type, #type }
1424#define show_fabrics_type_name(type) \
1425 __print_symbolic(type, \
1426 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1427 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
88b140fe
HR		 1428 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1429 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1430 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
ad795e47
MI		 1431
1432/*
1433 * If not fabrics command, fctype will be ignored.
1434 */
1435#define show_opcode_name(qid, opcode, fctype) \
1436 ((opcode) == nvme_fabrics_command ? \
1437 show_fabrics_type_name(fctype) : \
1438 ((qid) ? \
1439 show_nvm_opcode_name(opcode) : \
1440 show_admin_opcode_name(opcode)))
1441
eb793e2c
CH		 1442struct nvmf_common_command {
1443 __u8 opcode;
1444 __u8 resv1;
1445 __u16 command_id;
1446 __u8 fctype;
1447 __u8 resv2[35];
1448 __u8 ts[24];
1449};
1450
1451/*
1452 * The legal cntlid range a NVMe Target will provide.
1453 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1454 * Devices based on earlier specs did not have the subsystem concept;
1455 * therefore, those devices had their cntlid value set to 0 as a result.
1456 */
1457#define NVME_CNTLID_MIN 1
1458#define NVME_CNTLID_MAX 0xffef
1459#define NVME_CNTLID_DYNAMIC 0xffff
1460
1461#define MAX_DISC_LOGS 255
1462
785d584c
HR		 1463/* Discovery log page entry flags (EFLAGS): */
1464enum {
1465 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1466 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1467};
1468
eb793e2c
CH		 1469/* Discovery log page entry */
1470struct nvmf_disc_rsp_page_entry {
1471 __u8 trtype;
1472 __u8 adrfam;
a446c084 1473 __u8 subtype;
eb793e2c
CH		 1474 __u8 treq;
1475 __le16 portid;
1476 __le16 cntlid;
1477 __le16 asqsz;
785d584c
HR		 1478 __le16 eflags;
1479 __u8 resv10[20];
eb793e2c
CH		 1480 char trsvcid[NVMF_TRSVCID_SIZE];
1481 __u8 resv64[192];
1482 char subnqn[NVMF_NQN_FIELD_LEN];
1483 char traddr[NVMF_TRADDR_SIZE];
1484 union tsas {
1485 char common[NVMF_TSAS_SIZE];
1486 struct rdma {
1487 __u8 qptype;
1488 __u8 prtype;
1489 __u8 cms;
1490 __u8 resv3[5];
1491 __u16 pkey;
1492 __u8 resv10[246];
1493 } rdma;
646f45b2
HR		 1494 struct tcp {
1495 __u8 sectype;
1496 } tcp;
eb793e2c
CH		 1497 } tsas;
1498};
1499
1500/* Discovery log page header */
1501struct nvmf_disc_rsp_page_hdr {
1502 __le64 genctr;
1503 __le64 numrec;
1504 __le16 recfmt;
1505 __u8 resv14[1006];
f1e71d75 1506 struct nvmf_disc_rsp_page_entry entries[];
eb793e2c
CH		 1507};
1508
e6a622fd
SG		 1509enum {
1510 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1511};
1512
eb793e2c
CH		 1513struct nvmf_connect_command {
1514 __u8 opcode;
1515 __u8 resv1;
1516 __u16 command_id;
1517 __u8 fctype;
1518 __u8 resv2[19];
1519 union nvme_data_ptr dptr;
1520 __le16 recfmt;
1521 __le16 qid;
1522 __le16 sqsize;
1523 __u8 cattr;
1524 __u8 resv3;
1525 __le32 kato;
1526 __u8 resv4[12];
1527};
1528
88b140fe 1529enum {
1c32a801
CH		 1530 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1531 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
88b140fe
HR		 1532};
1533
eb793e2c 1534struct nvmf_connect_data {
8e412263 1535 uuid_t hostid;
eb793e2c
CH		 1536 __le16 cntlid;
1537 char resv4[238];
1538 char subsysnqn[NVMF_NQN_FIELD_LEN];
1539 char hostnqn[NVMF_NQN_FIELD_LEN];
1540 char resv5[256];
1541};
1542
1543struct nvmf_property_set_command {
1544 __u8 opcode;
1545 __u8 resv1;
1546 __u16 command_id;
1547 __u8 fctype;
1548 __u8 resv2[35];
1549 __u8 attrib;
1550 __u8 resv3[3];
1551 __le32 offset;
1552 __le64 value;
1553 __u8 resv4[8];
1554};
1555
1556struct nvmf_property_get_command {
1557 __u8 opcode;
1558 __u8 resv1;
1559 __u16 command_id;
1560 __u8 fctype;
1561 __u8 resv2[35];
1562 __u8 attrib;
1563 __u8 resv3[3];
1564 __le32 offset;
1565 __u8 resv4[16];
1566};
1567
88b140fe
HR		 1568struct nvmf_auth_common_command {
1569 __u8 opcode;
1570 __u8 resv1;
1571 __u16 command_id;
1572 __u8 fctype;
1573 __u8 resv2[19];
1574 union nvme_data_ptr dptr;
1575 __u8 resv3;
1576 __u8 spsp0;
1577 __u8 spsp1;
1578 __u8 secp;
1579 __le32 al_tl;
1580 __u8 resv4[16];
1581};
1582
1583struct nvmf_auth_send_command {
1584 __u8 opcode;
1585 __u8 resv1;
1586 __u16 command_id;
1587 __u8 fctype;
1588 __u8 resv2[19];
1589 union nvme_data_ptr dptr;
1590 __u8 resv3;
1591 __u8 spsp0;
1592 __u8 spsp1;
1593 __u8 secp;
1594 __le32 tl;
1595 __u8 resv4[16];
1596};
1597
1598struct nvmf_auth_receive_command {
1599 __u8 opcode;
1600 __u8 resv1;
1601 __u16 command_id;
1602 __u8 fctype;
1603 __u8 resv2[19];
1604 union nvme_data_ptr dptr;
1605 __u8 resv3;
1606 __u8 spsp0;
1607 __u8 spsp1;
1608 __u8 secp;
1609 __le32 al;
1610 __u8 resv4[16];
1611};
1612
1613/* Value for secp */
1614enum {
1615 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1616};
1617
1618/* Defined value for auth_type */
1619enum {
1620 NVME_AUTH_COMMON_MESSAGES = 0x00,
1621 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1622};
1623
1624/* Defined messages for auth_id */
1625enum {
1626 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1627 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1628 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1629 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1630 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1631 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1632 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1633};
1634
1635struct nvmf_auth_dhchap_protocol_descriptor {
1636 __u8 authid;
1637 __u8 rsvd;
1638 __u8 halen;
1639 __u8 dhlen;
1640 __u8 idlist[60];
1641};
1642
1643enum {
1644 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1645};
1646
1647/* Defined hash functions for DH-HMAC-CHAP authentication */
1648enum {
1649 NVME_AUTH_HASH_SHA256 = 0x01,
1650 NVME_AUTH_HASH_SHA384 = 0x02,
1651 NVME_AUTH_HASH_SHA512 = 0x03,
1652 NVME_AUTH_HASH_INVALID = 0xff,
1653};
1654
1655/* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1656enum {
1657 NVME_AUTH_DHGROUP_NULL = 0x00,
1658 NVME_AUTH_DHGROUP_2048 = 0x01,
1659 NVME_AUTH_DHGROUP_3072 = 0x02,
1660 NVME_AUTH_DHGROUP_4096 = 0x03,
1661 NVME_AUTH_DHGROUP_6144 = 0x04,
1662 NVME_AUTH_DHGROUP_8192 = 0x05,
1663 NVME_AUTH_DHGROUP_INVALID = 0xff,
1664};
1665
1666union nvmf_auth_protocol {
1667 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1668};
1669
1670struct nvmf_auth_dhchap_negotiate_data {
1671 __u8 auth_type;
1672 __u8 auth_id;
1673 __le16 rsvd;
1674 __le16 t_id;
1675 __u8 sc_c;
1676 __u8 napd;
1677 union nvmf_auth_protocol auth_protocol[];
1678};
1679
1680struct nvmf_auth_dhchap_challenge_data {
1681 __u8 auth_type;
1682 __u8 auth_id;
1683 __u16 rsvd1;
1684 __le16 t_id;
1685 __u8 hl;
1686 __u8 rsvd2;
1687 __u8 hashid;
1688 __u8 dhgid;
1689 __le16 dhvlen;
1690 __le32 seqnum;
1691 /* 'hl' bytes of challenge value */
1692 __u8 cval[];
1693 /* followed by 'dhvlen' bytes of DH value */
1694};
1695
1696struct nvmf_auth_dhchap_reply_data {
1697 __u8 auth_type;
1698 __u8 auth_id;
1699 __le16 rsvd1;
1700 __le16 t_id;
1701 __u8 hl;
1702 __u8 rsvd2;
1703 __u8 cvalid;
1704 __u8 rsvd3;
1705 __le16 dhvlen;
1706 __le32 seqnum;
1707 /* 'hl' bytes of response data */
1708 __u8 rval[];
1709 /* followed by 'hl' bytes of Challenge value */
1710 /* followed by 'dhvlen' bytes of DH value */
1711};
1712
1713enum {
1714 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1715};
1716
1717struct nvmf_auth_dhchap_success1_data {
1718 __u8 auth_type;
1719 __u8 auth_id;
1720 __le16 rsvd1;
1721 __le16 t_id;
1722 __u8 hl;
1723 __u8 rsvd2;
1724 __u8 rvalid;
1725 __u8 rsvd3[7];
75276847 1726 /* 'hl' bytes of response value */
88b140fe
HR		 1727 __u8 rval[];
1728};
1729
1730struct nvmf_auth_dhchap_success2_data {
1731 __u8 auth_type;
1732 __u8 auth_id;
1733 __le16 rsvd1;
1734 __le16 t_id;
1735 __u8 rsvd2[10];
1736};
1737
1738struct nvmf_auth_dhchap_failure_data {
1739 __u8 auth_type;
1740 __u8 auth_id;
1741 __le16 rsvd1;
1742 __le16 t_id;
1743 __u8 rescode;
1744 __u8 rescode_exp;
1745};
1746
1747enum {
1748 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1749};
1750
1751enum {
1752 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1753 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1754 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1755 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1756 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1757 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1758 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1759};
1760
1761
f9f38e33
HK		 1762struct nvme_dbbuf {
1763 __u8 opcode;
1764 __u8 flags;
1765 __u16 command_id;
1766 __u32 rsvd1[5];
1767 __le64 prp1;
1768 __le64 prp2;
1769 __u32 rsvd12[6];
1770};
1771
f5d11840 1772struct streams_directive_params {
dc1a0afb
CH		 1773 __le16 msl;
1774 __le16 nssa;
1775 __le16 nsso;
f5d11840 1776 __u8 rsvd[10];
dc1a0afb
CH		 1777 __le32 sws;
1778 __le16 sgs;
1779 __le16 nsa;
1780 __le16 nso;
f5d11840
JA		 1781 __u8 rsvd2[6];
1782};
1783
9d99a8dd
CH		 1784struct nvme_command {
1785 union {
1786 struct nvme_common_command common;
1787 struct nvme_rw_command rw;
1788 struct nvme_identify identify;
1789 struct nvme_features features;
1790 struct nvme_create_cq create_cq;
1791 struct nvme_create_sq create_sq;
1792 struct nvme_delete_queue delete_queue;
1793 struct nvme_download_firmware dlfw;
1794 struct nvme_format_cmd format;
1795 struct nvme_dsm_cmd dsm;
3b7c33b2 1796 struct nvme_write_zeroes_cmd write_zeroes;
240e6ee2
KB		 1797 struct nvme_zone_mgmt_send_cmd zms;
1798 struct nvme_zone_mgmt_recv_cmd zmr;
9d99a8dd 1799 struct nvme_abort_cmd abort;
725b3588 1800 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1801 struct nvmf_common_command fabrics;
1802 struct nvmf_connect_command connect;
1803 struct nvmf_property_set_command prop_set;
1804 struct nvmf_property_get_command prop_get;
88b140fe
HR		 1805 struct nvmf_auth_common_command auth_common;
1806 struct nvmf_auth_send_command auth_send;
1807 struct nvmf_auth_receive_command auth_receive;
f9f38e33 1808 struct nvme_dbbuf dbbuf;
f5d11840 1809 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1810 };
1811};
1812
f9e9115d 1813static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
7a1f46e3
MI		 1814{
1815 return cmd->common.opcode == nvme_fabrics_command;
1816}
1817
b34de7ce
CK		 1818struct nvme_error_slot {
1819 __le64 error_count;
1820 __le16 sqid;
1821 __le16 cmdid;
1822 __le16 status_field;
1823 __le16 param_error_location;
1824 __le64 lba;
1825 __le32 nsid;
1826 __u8 vs;
1827 __u8 resv[3];
1828 __le64 cs;
1829 __u8 resv2[24];
1830};
1831
f9e9115d 1832static inline bool nvme_is_write(const struct nvme_command *cmd)
7a5abb4b 1833{
eb793e2c
CH		 1834 /*
1835 * What a mess...
1836 *
1837 * Why can't we simply have a Fabrics In and Fabrics out command?
1838 */
7a1f46e3 1839 if (unlikely(nvme_is_fabrics(cmd)))
2fd4167f 1840 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1841 return cmd->common.opcode & 1;
1842}
1843
9d99a8dd 1844enum {
eb793e2c
CH		 1845 /*
1846 * Generic Command Status:
1847 */
9d99a8dd
CH		 1848 NVME_SC_SUCCESS = 0x0,
1849 NVME_SC_INVALID_OPCODE = 0x1,
1850 NVME_SC_INVALID_FIELD = 0x2,
1851 NVME_SC_CMDID_CONFLICT = 0x3,
1852 NVME_SC_DATA_XFER_ERROR = 0x4,
1853 NVME_SC_POWER_LOSS = 0x5,
1854 NVME_SC_INTERNAL = 0x6,
1855 NVME_SC_ABORT_REQ = 0x7,
1856 NVME_SC_ABORT_QUEUE = 0x8,
1857 NVME_SC_FUSED_FAIL = 0x9,
1858 NVME_SC_FUSED_MISSING = 0xa,
1859 NVME_SC_INVALID_NS = 0xb,
1860 NVME_SC_CMD_SEQ_ERROR = 0xc,
1861 NVME_SC_SGL_INVALID_LAST = 0xd,
1862 NVME_SC_SGL_INVALID_COUNT = 0xe,
1863 NVME_SC_SGL_INVALID_DATA = 0xf,
1864 NVME_SC_SGL_INVALID_METADATA = 0x10,
1865 NVME_SC_SGL_INVALID_TYPE = 0x11,
3254899e
MG		 1866 NVME_SC_CMB_INVALID_USE = 0x12,
1867 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1868 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1869 NVME_SC_OP_DENIED = 0x15,
eb793e2c 1870 NVME_SC_SGL_INVALID_OFFSET = 0x16,
3254899e
MG		 1871 NVME_SC_RESERVED = 0x17,
1872 NVME_SC_HOST_ID_INCONSIST = 0x18,
1873 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1874 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1875 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
48c9e85b
RR		 1876 NVME_SC_SANITIZE_FAILED = 0x1C,
1877 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
3254899e
MG		 1878 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1879 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
93045d59 1880 NVME_SC_NS_WRITE_PROTECTED = 0x20,
48c9e85b 1881 NVME_SC_CMD_INTERRUPTED = 0x21,
3254899e 1882 NVME_SC_TRANSIENT_TR_ERR = 0x22,
354201c5 1883 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
ab5d0b38 1884 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
93045d59 1885
9d99a8dd
CH		 1886 NVME_SC_LBA_RANGE = 0x80,
1887 NVME_SC_CAP_EXCEEDED = 0x81,
1888 NVME_SC_NS_NOT_READY = 0x82,
1889 NVME_SC_RESERVATION_CONFLICT = 0x83,
3254899e 1890 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
eb793e2c
CH		 1891
1892 /*
1893 * Command Specific Status:
1894 */
9d99a8dd
CH		 1895 NVME_SC_CQ_INVALID = 0x100,
1896 NVME_SC_QID_INVALID = 0x101,
1897 NVME_SC_QUEUE_SIZE = 0x102,
1898 NVME_SC_ABORT_LIMIT = 0x103,
1899 NVME_SC_ABORT_MISSING = 0x104,
1900 NVME_SC_ASYNC_LIMIT = 0x105,
1901 NVME_SC_FIRMWARE_SLOT = 0x106,
1902 NVME_SC_FIRMWARE_IMAGE = 0x107,
1903 NVME_SC_INVALID_VECTOR = 0x108,
1904 NVME_SC_INVALID_LOG_PAGE = 0x109,
1905 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1906 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1907 NVME_SC_INVALID_QUEUE = 0x10c,
1908 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1909 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1910 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1911 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1912 NVME_SC_FW_NEEDS_RESET = 0x111,
1913 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
9581ae4f 1914 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
a446c084 1915 NVME_SC_OVERLAPPING_RANGE = 0x114,
9581ae4f 1916 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
a446c084
CH		 1917 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1918 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1919 NVME_SC_NS_IS_PRIVATE = 0x119,
1920 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1921 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1922 NVME_SC_CTRL_LIST_INVALID = 0x11c,
3254899e 1923 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
48c9e85b 1924 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
3254899e
MG		 1925 NVME_SC_CTRL_ID_INVALID = 0x11f,
1926 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1927 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1928 NVME_SC_RES_ID_INVALID = 0x122,
48c9e85b 1929 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
3254899e
MG		 1930 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1931 NVME_SC_ANA_ATTACH_FAILED = 0x125,
eb793e2c
CH		 1932
1933 /*
1934 * I/O Command Set Specific - NVM commands:
1935 */
9d99a8dd
CH		 1936 NVME_SC_BAD_ATTRIBUTES = 0x180,
1937 NVME_SC_INVALID_PI = 0x181,
1938 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1939 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1940
1941 /*
1942 * I/O Command Set Specific - Fabrics commands:
1943 */
1944 NVME_SC_CONNECT_FORMAT = 0x180,
1945 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1946 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1947 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1948 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1949
1950 NVME_SC_DISCOVERY_RESTART = 0x190,
1951 NVME_SC_AUTH_REQUIRED = 0x191,
1952
240e6ee2
KB		 1953 /*
1954 * I/O Command Set Specific - Zoned commands:
1955 */
1956 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1957 NVME_SC_ZONE_FULL = 0x1b9,
1958 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1959 NVME_SC_ZONE_OFFLINE = 0x1bb,
1960 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1961 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1962 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1963 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1964
eb793e2c
CH		 1965 /*
1966 * Media and Data Integrity Errors:
1967 */
9d99a8dd
CH		 1968 NVME_SC_WRITE_FAULT = 0x280,
1969 NVME_SC_READ_ERROR = 0x281,
1970 NVME_SC_GUARD_CHECK = 0x282,
1971 NVME_SC_APPTAG_CHECK = 0x283,
1972 NVME_SC_REFTAG_CHECK = 0x284,
1973 NVME_SC_COMPARE_FAILED = 0x285,
1974 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1975 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1976
1a376216
CH		 1977 /*
1978 * Path-related Errors:
1979 */
ca2d8992 1980 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1a376216
CH		 1981 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1982 NVME_SC_ANA_INACCESSIBLE = 0x302,
1983 NVME_SC_ANA_TRANSITION = 0x303,
ca2d8992 1984 NVME_SC_CTRL_PATH_ERROR = 0x360,
783f4a44 1985 NVME_SC_HOST_PATH_ERROR = 0x370,
2dc3947b 1986 NVME_SC_HOST_ABORTED_CMD = 0x371,
1a376216 1987
49cd84b6 1988 NVME_SC_CRD = 0x1800,
bd83fe6f 1989 NVME_SC_MORE = 0x2000,
9d99a8dd
CH		 1990 NVME_SC_DNR = 0x4000,
1991};
1992
1993struct nvme_completion {
eb793e2c
CH		 1994 /*
1995 * Used by Admin and Fabrics commands to return data:
1996 */
d49187e9
CH		 1997 union nvme_result {
1998 __le16 u16;
1999 __le32 u32;
2000 __le64 u64;
2001 } result;
9d99a8dd
CH		 2002 __le16 sq_head; /* how much of this queue may be reclaimed */
2003 __le16 sq_id; /* submission queue that generated this entry */
2004 __u16 command_id; /* of the command which completed */
2005 __le16 status; /* did the command fail, and if so, why? */
2006};
2007
8ef2074d
GKB		 2008#define NVME_VS(major, minor, tertiary) \
2009 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 2010
c61d788b
JT		 2011#define NVME_MAJOR(ver) ((ver) >> 16)
2012#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2013#define NVME_TERTIARY(ver) ((ver) & 0xff)
2014
b60503ba 2015#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)