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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-block.git] / include / linux / nvme.h
CommitLineData
fadccd8f 1/* SPDX-License-Identifier: GPL-2.0 */
b60503ba
MW		 2/*
3 * Definitions for the NVM Express interface
8757ad65 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
2812dfe3 10#include <linux/types.h>
8e412263 11#include <linux/uuid.h>
eb793e2c
CH		 12
13/* NQN names in commands fields specified one size */
14#define NVMF_NQN_FIELD_LEN 256
15
16/* However the max length of a qualified name is another size */
17#define NVMF_NQN_SIZE 223
18
19#define NVMF_TRSVCID_SIZE 32
20#define NVMF_TRADDR_SIZE 256
21#define NVMF_TSAS_SIZE 256
22
23#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
24
25#define NVME_RDMA_IP_PORT 4420
26
62346eae
AD		 27#define NVME_NSID_ALL 0xffffffff
28
eb793e2c
CH		 29enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
32};
33
34/* Address Family codes for Discovery Log Page entry ADRFAM field */
35enum {
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
d02abd19
CK		 41 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
42 NVMF_ADDR_FAMILY_MAX,
eb793e2c
CH		 43};
44
45/* Transport Type codes for Discovery Log Page entry TRTYPE field */
46enum {
47 NVMF_TRTYPE_RDMA = 1, /* RDMA */
48 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
fc221d05 49 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
eb793e2c
CH		 50 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
51 NVMF_TRTYPE_MAX,
52};
53
54/* Transport Requirements codes for Discovery Log Page entry TREQ field */
55enum {
9b95d2fb
SG		 56 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
57 NVMF_TREQ_REQUIRED = 1, /* Required */
58 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 59#define NVME_TREQ_SECURE_CHANNEL_MASK \
60 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
9b95d2fb
SG		 61
62 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
eb793e2c
CH		 63};
64
65/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
66 * RDMA_QPTYPE field
67 */
68enum {
bf17aa36
RD		 69 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
70 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 71};
72
73/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
74 * RDMA_QPTYPE field
75 */
76enum {
bf17aa36
RD		 77 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
78 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
79 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
80 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
81 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 82};
83
84/* RDMA Connection Management Service Type codes for Discovery Log Page
85 * entry TSAS RDMA_CMS field
86 */
87enum {
bf17aa36 88 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 89};
90
7aa1f427 91#define NVME_AQ_DEPTH 32
38dabe21
KB		 92#define NVME_NR_AEN_COMMANDS 1
93#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
94
95/*
96 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
97 * NVM-Express 1.2 specification, section 4.1.2.
98 */
99#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 100
7a67cbea
CH		 101enum {
102 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
103 NVME_REG_VS = 0x0008, /* Version */
104 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 105 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 106 NVME_REG_CC = 0x0014, /* Controller Configuration */
107 NVME_REG_CSTS = 0x001c, /* Controller Status */
108 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
109 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
110 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 111 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
48c9e85b 112 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea 113 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
48c9e85b
RR		 114 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
115 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
116 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
117 * Location
118 */
119 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
120 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
121 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
122 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
123 * Buffer Size
124 */
125 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
126 * Write Throughput
127 */
97f6ef64 128 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 129};
130
a0cadb85 131#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 132#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 133#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 134#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
71010c30 135#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
8fc23e03 136#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 137#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 138
8ffaadf7
JD		 139#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
140#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598
CH		 141
142enum {
143 NVME_CMBSZ_SQS = 1 << 0,
144 NVME_CMBSZ_CQS = 1 << 1,
145 NVME_CMBSZ_LISTS = 1 << 2,
146 NVME_CMBSZ_RDS = 1 << 3,
147 NVME_CMBSZ_WDS = 1 << 4,
148
149 NVME_CMBSZ_SZ_SHIFT = 12,
150 NVME_CMBSZ_SZ_MASK = 0xfffff,
151
152 NVME_CMBSZ_SZU_SHIFT = 8,
153 NVME_CMBSZ_SZU_MASK = 0xf,
154};
8ffaadf7 155
69cd27e2
CH		 156/*
157 * Submission and Completion Queue Entry Sizes for the NVM command set.
158 * (In bytes and specified as a power of two (2^n)).
159 */
c1e0cc7e 160#define NVME_ADM_SQES 6
69cd27e2
CH		 161#define NVME_NVM_IOSQES 6
162#define NVME_NVM_IOCQES 4
163
b60503ba
MW		 164enum {
165 NVME_CC_ENABLE = 1 << 0,
ad4e05b2
MG		 166 NVME_CC_EN_SHIFT = 0,
167 NVME_CC_CSS_SHIFT = 4,
b60503ba 168 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 169 NVME_CC_AMS_SHIFT = 11,
170 NVME_CC_SHN_SHIFT = 14,
171 NVME_CC_IOSQES_SHIFT = 16,
172 NVME_CC_IOCQES_SHIFT = 20,
71010c30
NC		 173 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
174 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
175 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
60b43f62
MG		 176 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
177 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
178 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 179 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
180 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
181 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
182 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
183 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
184 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
71010c30
NC		 185 NVME_CAP_CSS_NVM = 1 << 0,
186 NVME_CAP_CSS_CSI = 1 << 6,
b60503ba
MW		 187 NVME_CSTS_RDY = 1 << 0,
188 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 189 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 190 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 191 NVME_CSTS_SHST_NORMAL = 0 << 2,
192 NVME_CSTS_SHST_OCCUR = 1 << 2,
193 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 194 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 195};
196
9d99a8dd
CH		 197struct nvme_id_power_state {
198 __le16 max_power; /* centiwatts */
199 __u8 rsvd2;
200 __u8 flags;
201 __le32 entry_lat; /* microseconds */
202 __le32 exit_lat; /* microseconds */
203 __u8 read_tput;
204 __u8 read_lat;
205 __u8 write_tput;
206 __u8 write_lat;
207 __le16 idle_power;
208 __u8 idle_scale;
209 __u8 rsvd19;
210 __le16 active_power;
211 __u8 active_work_scale;
212 __u8 rsvd23[9];
213};
214
215enum {
216 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
217 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
218};
219
12b21171
SG		 220enum nvme_ctrl_attr {
221 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 222 NVME_CTRL_ATTR_TBKAS = (1 << 6),
12b21171
SG		 223};
224
9d99a8dd
CH		 225struct nvme_id_ctrl {
226 __le16 vid;
227 __le16 ssvid;
228 char sn[20];
229 char mn[40];
230 char fr[8];
231 __u8 rab;
232 __u8 ieee[3];
a446c084 233 __u8 cmic;
9d99a8dd 234 __u8 mdts;
08c69640
CH		 235 __le16 cntlid;
236 __le32 ver;
14e974a8
CH		 237 __le32 rtd3r;
238 __le32 rtd3e;
239 __le32 oaes;
eb793e2c 240 __le32 ctratt;
49cd84b6
KB		 241 __u8 rsvd100[28];
242 __le16 crdt1;
243 __le16 crdt2;
244 __le16 crdt3;
245 __u8 rsvd134[122];
9d99a8dd
CH		 246 __le16 oacs;
247 __u8 acl;
248 __u8 aerl;
249 __u8 frmw;
250 __u8 lpa;
251 __u8 elpe;
252 __u8 npss;
253 __u8 avscc;
254 __u8 apsta;
255 __le16 wctemp;
256 __le16 cctemp;
a446c084
CH		 257 __le16 mtfa;
258 __le32 hmpre;
259 __le32 hmmin;
260 __u8 tnvmcap[16];
261 __u8 unvmcap[16];
262 __le32 rpmbs;
435e8090
GJ		 263 __le16 edstt;
264 __u8 dsto;
265 __u8 fwug;
7b89eae2 266 __le16 kas;
435e8090
GJ		 267 __le16 hctma;
268 __le16 mntmt;
269 __le16 mxtmt;
270 __le32 sanicap;
044a9df1
CH		 271 __le32 hmminds;
272 __le16 hmmaxd;
1a376216
CH		 273 __u8 rsvd338[4];
274 __u8 anatt;
275 __u8 anacap;
276 __le32 anagrpmax;
277 __le32 nanagrpid;
278 __u8 rsvd352[160];
9d99a8dd
CH		 279 __u8 sqes;
280 __u8 cqes;
eb793e2c 281 __le16 maxcmd;
9d99a8dd
CH		 282 __le32 nn;
283 __le16 oncs;
284 __le16 fuses;
285 __u8 fna;
286 __u8 vwc;
287 __le16 awun;
288 __le16 awupf;
289 __u8 nvscc;
93045d59 290 __u8 nwpc;
9d99a8dd
CH		 291 __le16 acwu;
292 __u8 rsvd534[2];
293 __le32 sgls;
1a376216
CH		 294 __le32 mnan;
295 __u8 rsvd544[224];
eb793e2c
CH		 296 char subnqn[256];
297 __u8 rsvd1024[768];
298 __le32 ioccsz;
299 __le32 iorcsz;
300 __le16 icdoff;
301 __u8 ctrattr;
302 __u8 msdbd;
303 __u8 rsvd1804[244];
9d99a8dd
CH		 304 struct nvme_id_power_state psd[32];
305 __u8 vs[1024];
306};
307
308enum {
92decf11
KB		 309 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
310 NVME_CTRL_CMIC_ANA = 1 << 3,
9d99a8dd
CH		 311 NVME_CTRL_ONCS_COMPARE = 1 << 0,
312 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
313 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 314 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
c1fef73f 315 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
dbf86b39 316 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 317 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 318 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f5d11840 319 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 320 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 321 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
48c9e85b
RR		 322 NVME_CTRL_CTRATT_128_ID = 1 << 0,
323 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
324 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
325 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
326 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
327 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
328 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
329 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
9d99a8dd
CH		 330};
331
332struct nvme_lbaf {
333 __le16 ms;
334 __u8 ds;
335 __u8 rp;
336};
337
338struct nvme_id_ns {
339 __le64 nsze;
340 __le64 ncap;
341 __le64 nuse;
342 __u8 nsfeat;
343 __u8 nlbaf;
344 __u8 flbas;
345 __u8 mc;
346 __u8 dpc;
347 __u8 dps;
348 __u8 nmic;
349 __u8 rescap;
350 __u8 fpi;
6605bdd5 351 __u8 dlfeat;
9d99a8dd
CH		 352 __le16 nawun;
353 __le16 nawupf;
354 __le16 nacwu;
355 __le16 nabsn;
356 __le16 nabo;
357 __le16 nabspf;
6b8190d6 358 __le16 noiob;
a446c084 359 __u8 nvmcap[16];
6605bdd5
BVA		 360 __le16 npwg;
361 __le16 npwa;
362 __le16 npdg;
363 __le16 npda;
364 __le16 nows;
365 __u8 rsvd74[18];
1a376216 366 __le32 anagrpid;
93045d59
CK		 367 __u8 rsvd96[3];
368 __u8 nsattr;
6605bdd5
BVA		 369 __le16 nvmsetid;
370 __le16 endgid;
9d99a8dd
CH		 371 __u8 nguid[16];
372 __u8 eui64[8];
373 struct nvme_lbaf lbaf[16];
374 __u8 rsvd192[192];
375 __u8 vs[3712];
376};
377
240e6ee2
KB		 378struct nvme_zns_lbafe {
379 __le64 zsze;
380 __u8 zdes;
381 __u8 rsvd9[7];
382};
383
384struct nvme_id_ns_zns {
385 __le16 zoc;
386 __le16 ozcs;
387 __le32 mar;
388 __le32 mor;
389 __le32 rrl;
390 __le32 frl;
391 __u8 rsvd20[2796];
392 struct nvme_zns_lbafe lbafe[16];
393 __u8 rsvd3072[768];
394 __u8 vs[256];
395};
396
397struct nvme_id_ctrl_zns {
398 __u8 zasl;
399 __u8 rsvd1[4095];
400};
401
329dd768
CH		 402enum {
403 NVME_ID_CNS_NS = 0x00,
404 NVME_ID_CNS_CTRL = 0x01,
405 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 406 NVME_ID_CNS_NS_DESC_LIST = 0x03,
71010c30
NC		 407 NVME_ID_CNS_CS_NS = 0x05,
408 NVME_ID_CNS_CS_CTRL = 0x06,
329dd768
CH		 409 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
410 NVME_ID_CNS_NS_PRESENT = 0x11,
411 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
412 NVME_ID_CNS_CTRL_LIST = 0x13,
48c9e85b
RR		 413 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
414 NVME_ID_CNS_NS_GRANULARITY = 0x16,
415 NVME_ID_CNS_UUID_LIST = 0x17,
329dd768
CH		 416};
417
71010c30
NC		 418enum {
419 NVME_CSI_NVM = 0,
240e6ee2 420 NVME_CSI_ZNS = 2,
71010c30
NC		 421};
422
f5d11840
JA		 423enum {
424 NVME_DIR_IDENTIFY = 0x00,
425 NVME_DIR_STREAMS = 0x01,
426 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
427 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
428 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
429 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
430 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
431 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
432 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
433 NVME_DIR_ENDIR = 0x01,
434};
435
9d99a8dd
CH		 436enum {
437 NVME_NS_FEAT_THIN = 1 << 0,
92decf11
KB		 438 NVME_NS_FEAT_ATOMICS = 1 << 1,
439 NVME_NS_FEAT_IO_OPT = 1 << 4,
440 NVME_NS_ATTR_RO = 1 << 0,
9d99a8dd
CH		 441 NVME_NS_FLBAS_LBA_MASK = 0xf,
442 NVME_NS_FLBAS_META_EXT = 0x10,
92decf11 443 NVME_NS_NMIC_SHARED = 1 << 0,
9d99a8dd
CH		 444 NVME_LBAF_RP_BEST = 0,
445 NVME_LBAF_RP_BETTER = 1,
446 NVME_LBAF_RP_GOOD = 2,
447 NVME_LBAF_RP_DEGRADED = 3,
448 NVME_NS_DPC_PI_LAST = 1 << 4,
449 NVME_NS_DPC_PI_FIRST = 1 << 3,
450 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
451 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
452 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
453 NVME_NS_DPS_PI_FIRST = 1 << 3,
454 NVME_NS_DPS_PI_MASK = 0x7,
455 NVME_NS_DPS_PI_TYPE1 = 1,
456 NVME_NS_DPS_PI_TYPE2 = 2,
457 NVME_NS_DPS_PI_TYPE3 = 3,
458};
459
39481fbd
IR		 460/* Identify Namespace Metadata Capabilities (MC): */
461enum {
462 NVME_MC_EXTENDED_LBA = (1 << 0),
463 NVME_MC_METADATA_PTR = (1 << 1),
464};
465
af8b86e9
JT		 466struct nvme_ns_id_desc {
467 __u8 nidt;
468 __u8 nidl;
469 __le16 reserved;
470};
471
472#define NVME_NIDT_EUI64_LEN 8
473#define NVME_NIDT_NGUID_LEN 16
474#define NVME_NIDT_UUID_LEN 16
71010c30 475#define NVME_NIDT_CSI_LEN 1
af8b86e9
JT		 476
477enum {
478 NVME_NIDT_EUI64 = 0x01,
479 NVME_NIDT_NGUID = 0x02,
480 NVME_NIDT_UUID = 0x03,
71010c30 481 NVME_NIDT_CSI = 0x04,
af8b86e9
JT		 482};
483
9d99a8dd
CH		 484struct nvme_smart_log {
485 __u8 critical_warning;
486 __u8 temperature[2];
487 __u8 avail_spare;
488 __u8 spare_thresh;
489 __u8 percent_used;
48c9e85b
RR		 490 __u8 endu_grp_crit_warn_sumry;
491 __u8 rsvd7[25];
9d99a8dd
CH		 492 __u8 data_units_read[16];
493 __u8 data_units_written[16];
494 __u8 host_reads[16];
495 __u8 host_writes[16];
496 __u8 ctrl_busy_time[16];
497 __u8 power_cycles[16];
498 __u8 power_on_hours[16];
499 __u8 unsafe_shutdowns[16];
500 __u8 media_errors[16];
501 __u8 num_err_log_entries[16];
502 __le32 warning_temp_time;
503 __le32 critical_comp_time;
504 __le16 temp_sensor[8];
48c9e85b
RR		 505 __le32 thm_temp1_trans_count;
506 __le32 thm_temp2_trans_count;
507 __le32 thm_temp1_total_time;
508 __le32 thm_temp2_total_time;
509 __u8 rsvd232[280];
9d99a8dd
CH		 510};
511
b6dccf7f
AD		 512struct nvme_fw_slot_info_log {
513 __u8 afi;
514 __u8 rsvd1[7];
515 __le64 frs[7];
516 __u8 rsvd64[448];
517};
518
84fef62d
KB		 519enum {
520 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
521 NVME_CMD_EFFECTS_LBCC = 1 << 1,
522 NVME_CMD_EFFECTS_NCC = 1 << 2,
523 NVME_CMD_EFFECTS_NIC = 1 << 3,
524 NVME_CMD_EFFECTS_CCC = 1 << 4,
525 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
48c9e85b 526 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
84fef62d
KB		 527};
528
529struct nvme_effects_log {
530 __le32 acs[256];
531 __le32 iocs[256];
532 __u8 resv[2048];
533};
534
1a376216
CH		 535enum nvme_ana_state {
536 NVME_ANA_OPTIMIZED = 0x01,
537 NVME_ANA_NONOPTIMIZED = 0x02,
538 NVME_ANA_INACCESSIBLE = 0x03,
539 NVME_ANA_PERSISTENT_LOSS = 0x04,
540 NVME_ANA_CHANGE = 0x0f,
541};
542
543struct nvme_ana_group_desc {
544 __le32 grpid;
545 __le32 nnsids;
546 __le64 chgcnt;
547 __u8 state;
8b92d0e3 548 __u8 rsvd17[15];
1a376216
CH		 549 __le32 nsids[];
550};
551
552/* flag for the log specific field of the ANA log */
553#define NVME_ANA_LOG_RGO (1 << 0)
554
555struct nvme_ana_rsp_hdr {
556 __le64 chgcnt;
557 __le16 ngrps;
558 __le16 rsvd10[3];
559};
560
240e6ee2
KB		 561struct nvme_zone_descriptor {
562 __u8 zt;
563 __u8 zs;
564 __u8 za;
565 __u8 rsvd3[5];
566 __le64 zcap;
567 __le64 zslba;
568 __le64 wp;
569 __u8 rsvd32[32];
570};
571
572enum {
573 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
574};
575
576struct nvme_zone_report {
577 __le64 nr_zones;
578 __u8 resv8[56];
579 struct nvme_zone_descriptor entries[];
580};
581
9d99a8dd
CH		 582enum {
583 NVME_SMART_CRIT_SPARE = 1 << 0,
584 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
585 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
586 NVME_SMART_CRIT_MEDIA = 1 << 3,
587 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
588};
589
590enum {
e3d7874d
KB		 591 NVME_AER_ERROR = 0,
592 NVME_AER_SMART = 1,
868c2392 593 NVME_AER_NOTICE = 2,
e3d7874d
KB		 594 NVME_AER_CSS = 6,
595 NVME_AER_VS = 7,
868c2392
CH		 596};
597
598enum {
599 NVME_AER_NOTICE_NS_CHANGED = 0x00,
600 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 601 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 602 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 603};
604
aafd3afe 605enum {
7114ddeb
JS		 606 NVME_AEN_BIT_NS_ATTR = 8,
607 NVME_AEN_BIT_FW_ACT = 9,
608 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 609 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 610};
611
612enum {
613 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
614 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
615 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 616 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 617};
618
9d99a8dd
CH		 619struct nvme_lba_range_type {
620 __u8 type;
621 __u8 attributes;
622 __u8 rsvd2[14];
623 __u64 slba;
624 __u64 nlb;
625 __u8 guid[16];
626 __u8 rsvd48[16];
627};
628
629enum {
630 NVME_LBART_TYPE_FS = 0x01,
631 NVME_LBART_TYPE_RAID = 0x02,
632 NVME_LBART_TYPE_CACHE = 0x03,
633 NVME_LBART_TYPE_SWAP = 0x04,
634
635 NVME_LBART_ATTRIB_TEMP = 1 << 0,
636 NVME_LBART_ATTRIB_HIDE = 1 << 1,
637};
638
639struct nvme_reservation_status {
640 __le32 gen;
641 __u8 rtype;
642 __u8 regctl[2];
643 __u8 resv5[2];
644 __u8 ptpls;
645 __u8 resv10[13];
646 struct {
647 __le16 cntlid;
648 __u8 rcsts;
649 __u8 resv3[5];
650 __le64 hostid;
651 __le64 rkey;
652 } regctl_ds[];
653};
654
79f370ea
CH		 655enum nvme_async_event_type {
656 NVME_AER_TYPE_ERROR = 0,
657 NVME_AER_TYPE_SMART = 1,
658 NVME_AER_TYPE_NOTICE = 2,
659};
660
9d99a8dd
CH		 661/* I/O commands */
662
663enum nvme_opcode {
664 nvme_cmd_flush = 0x00,
665 nvme_cmd_write = 0x01,
666 nvme_cmd_read = 0x02,
667 nvme_cmd_write_uncor = 0x04,
668 nvme_cmd_compare = 0x05,
669 nvme_cmd_write_zeroes = 0x08,
670 nvme_cmd_dsm = 0x09,
48c9e85b 671 nvme_cmd_verify = 0x0c,
9d99a8dd
CH		 672 nvme_cmd_resv_register = 0x0d,
673 nvme_cmd_resv_report = 0x0e,
674 nvme_cmd_resv_acquire = 0x11,
675 nvme_cmd_resv_release = 0x15,
240e6ee2
KB		 676 nvme_cmd_zone_mgmt_send = 0x79,
677 nvme_cmd_zone_mgmt_recv = 0x7a,
678 nvme_cmd_zone_append = 0x7d,
9d99a8dd
CH		 679};
680
26f2990d
MI		 681#define nvme_opcode_name(opcode) { opcode, #opcode }
682#define show_nvm_opcode_name(val) \
683 __print_symbolic(val, \
684 nvme_opcode_name(nvme_cmd_flush), \
685 nvme_opcode_name(nvme_cmd_write), \
686 nvme_opcode_name(nvme_cmd_read), \
687 nvme_opcode_name(nvme_cmd_write_uncor), \
688 nvme_opcode_name(nvme_cmd_compare), \
689 nvme_opcode_name(nvme_cmd_write_zeroes), \
690 nvme_opcode_name(nvme_cmd_dsm), \
691 nvme_opcode_name(nvme_cmd_resv_register), \
692 nvme_opcode_name(nvme_cmd_resv_report), \
693 nvme_opcode_name(nvme_cmd_resv_acquire), \
694 nvme_opcode_name(nvme_cmd_resv_release))
695
696
eb793e2c
CH		 697/*
698 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
699 *
700 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
701 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 702 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 703 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
704 * request subtype
705 */
706enum {
707 NVME_SGL_FMT_ADDRESS = 0x00,
708 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 709 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 710 NVME_SGL_FMT_INVALIDATE = 0x0f,
711};
712
713/*
714 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
715 *
716 * For struct nvme_sgl_desc:
717 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
718 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
719 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
720 *
721 * For struct nvme_keyed_sgl_desc:
722 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 723 *
724 * Transport-specific SGL types:
725 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 726 */
727enum {
728 NVME_SGL_FMT_DATA_DESC = 0x00,
729 NVME_SGL_FMT_SEG_DESC = 0x02,
730 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
731 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 732 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 733};
734
735struct nvme_sgl_desc {
736 __le64 addr;
737 __le32 length;
738 __u8 rsvd[3];
739 __u8 type;
740};
741
742struct nvme_keyed_sgl_desc {
743 __le64 addr;
744 __u8 length[3];
745 __u8 key[4];
746 __u8 type;
747};
748
749union nvme_data_ptr {
750 struct {
751 __le64 prp1;
752 __le64 prp2;
753 };
754 struct nvme_sgl_desc sgl;
755 struct nvme_keyed_sgl_desc ksgl;
756};
757
3972be23
JS		 758/*
759 * Lowest two bits of our flags field (FUSE field in the spec):
760 *
761 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
762 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
763 *
764 * Highest two bits in our flags field (PSDT field in the spec):
765 *
766 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
767 * If used, MPTR contains addr of single physical buffer (byte aligned).
768 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
769 * If used, MPTR contains an address of an SGL segment containing
770 * exactly 1 SGL descriptor (qword aligned).
771 */
772enum {
773 NVME_CMD_FUSE_FIRST = (1 << 0),
774 NVME_CMD_FUSE_SECOND = (1 << 1),
775
776 NVME_CMD_SGL_METABUF = (1 << 6),
777 NVME_CMD_SGL_METASEG = (1 << 7),
778 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
779};
780
9d99a8dd
CH		 781struct nvme_common_command {
782 __u8 opcode;
783 __u8 flags;
784 __u16 command_id;
785 __le32 nsid;
786 __le32 cdw2[2];
787 __le64 metadata;
eb793e2c 788 union nvme_data_ptr dptr;
b7c8f366
CK		 789 __le32 cdw10;
790 __le32 cdw11;
791 __le32 cdw12;
792 __le32 cdw13;
793 __le32 cdw14;
794 __le32 cdw15;
9d99a8dd
CH		 795};
796
797struct nvme_rw_command {
798 __u8 opcode;
799 __u8 flags;
800 __u16 command_id;
801 __le32 nsid;
802 __u64 rsvd2;
803 __le64 metadata;
eb793e2c 804 union nvme_data_ptr dptr;
9d99a8dd
CH		 805 __le64 slba;
806 __le16 length;
807 __le16 control;
808 __le32 dsmgmt;
809 __le32 reftag;
810 __le16 apptag;
811 __le16 appmask;
812};
813
814enum {
815 NVME_RW_LR = 1 << 15,
816 NVME_RW_FUA = 1 << 14,
240e6ee2 817 NVME_RW_APPEND_PIREMAP = 1 << 9,
9d99a8dd
CH		 818 NVME_RW_DSM_FREQ_UNSPEC = 0,
819 NVME_RW_DSM_FREQ_TYPICAL = 1,
820 NVME_RW_DSM_FREQ_RARE = 2,
821 NVME_RW_DSM_FREQ_READS = 3,
822 NVME_RW_DSM_FREQ_WRITES = 4,
823 NVME_RW_DSM_FREQ_RW = 5,
824 NVME_RW_DSM_FREQ_ONCE = 6,
825 NVME_RW_DSM_FREQ_PREFETCH = 7,
826 NVME_RW_DSM_FREQ_TEMP = 8,
827 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
828 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
829 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
830 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
831 NVME_RW_DSM_SEQ_REQ = 1 << 6,
832 NVME_RW_DSM_COMPRESSED = 1 << 7,
833 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
834 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
835 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
836 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 837 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 838};
839
840struct nvme_dsm_cmd {
841 __u8 opcode;
842 __u8 flags;
843 __u16 command_id;
844 __le32 nsid;
845 __u64 rsvd2[2];
eb793e2c 846 union nvme_data_ptr dptr;
9d99a8dd
CH		 847 __le32 nr;
848 __le32 attributes;
849 __u32 rsvd12[4];
850};
851
852enum {
853 NVME_DSMGMT_IDR = 1 << 0,
854 NVME_DSMGMT_IDW = 1 << 1,
855 NVME_DSMGMT_AD = 1 << 2,
856};
857
b35ba01e
CH		 858#define NVME_DSM_MAX_RANGES 256
859
9d99a8dd
CH		 860struct nvme_dsm_range {
861 __le32 cattr;
862 __le32 nlb;
863 __le64 slba;
864};
865
3b7c33b2
CK		 866struct nvme_write_zeroes_cmd {
867 __u8 opcode;
868 __u8 flags;
869 __u16 command_id;
870 __le32 nsid;
871 __u64 rsvd2;
872 __le64 metadata;
873 union nvme_data_ptr dptr;
874 __le64 slba;
875 __le16 length;
876 __le16 control;
877 __le32 dsmgmt;
878 __le32 reftag;
879 __le16 apptag;
880 __le16 appmask;
881};
882
240e6ee2
KB		 883enum nvme_zone_mgmt_action {
884 NVME_ZONE_CLOSE = 0x1,
885 NVME_ZONE_FINISH = 0x2,
886 NVME_ZONE_OPEN = 0x3,
887 NVME_ZONE_RESET = 0x4,
888 NVME_ZONE_OFFLINE = 0x5,
889 NVME_ZONE_SET_DESC_EXT = 0x10,
890};
891
892struct nvme_zone_mgmt_send_cmd {
893 __u8 opcode;
894 __u8 flags;
895 __u16 command_id;
896 __le32 nsid;
897 __le32 cdw2[2];
898 __le64 metadata;
899 union nvme_data_ptr dptr;
900 __le64 slba;
901 __le32 cdw12;
902 __u8 zsa;
903 __u8 select_all;
904 __u8 rsvd13[2];
905 __le32 cdw14[2];
906};
907
908struct nvme_zone_mgmt_recv_cmd {
909 __u8 opcode;
910 __u8 flags;
911 __u16 command_id;
912 __le32 nsid;
913 __le64 rsvd2[2];
914 union nvme_data_ptr dptr;
915 __le64 slba;
916 __le32 numd;
917 __u8 zra;
918 __u8 zrasf;
919 __u8 pr;
920 __u8 rsvd13;
921 __le32 cdw14[2];
922};
923
924enum {
925 NVME_ZRA_ZONE_REPORT = 0,
926 NVME_ZRASF_ZONE_REPORT_ALL = 0,
927 NVME_REPORT_ZONE_PARTIAL = 1,
928};
929
c5552fde
AL		 930/* Features */
931
52deba0f
AM		 932enum {
933 NVME_TEMP_THRESH_MASK = 0xffff,
934 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
935 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
936};
937
c5552fde
AL		 938struct nvme_feat_auto_pst {
939 __le64 entries[32];
940};
941
39673e19
CH		 942enum {
943 NVME_HOST_MEM_ENABLE = (1 << 0),
944 NVME_HOST_MEM_RETURN = (1 << 1),
945};
946
49cd84b6
KB		 947struct nvme_feat_host_behavior {
948 __u8 acre;
949 __u8 resv1[511];
950};
951
952enum {
953 NVME_ENABLE_ACRE = 1,
954};
955
9d99a8dd
CH		 956/* Admin commands */
957
958enum nvme_admin_opcode {
959 nvme_admin_delete_sq = 0x00,
960 nvme_admin_create_sq = 0x01,
961 nvme_admin_get_log_page = 0x02,
962 nvme_admin_delete_cq = 0x04,
963 nvme_admin_create_cq = 0x05,
964 nvme_admin_identify = 0x06,
965 nvme_admin_abort_cmd = 0x08,
966 nvme_admin_set_features = 0x09,
967 nvme_admin_get_features = 0x0a,
968 nvme_admin_async_event = 0x0c,
a446c084 969 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 970 nvme_admin_activate_fw = 0x10,
971 nvme_admin_download_fw = 0x11,
48c9e85b 972 nvme_admin_dev_self_test = 0x14,
a446c084 973 nvme_admin_ns_attach = 0x15,
7b89eae2 974 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 975 nvme_admin_directive_send = 0x19,
976 nvme_admin_directive_recv = 0x1a,
48c9e85b
RR		 977 nvme_admin_virtual_mgmt = 0x1c,
978 nvme_admin_nvme_mi_send = 0x1d,
979 nvme_admin_nvme_mi_recv = 0x1e,
f9f38e33 980 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 981 nvme_admin_format_nvm = 0x80,
982 nvme_admin_security_send = 0x81,
983 nvme_admin_security_recv = 0x82,
84fef62d 984 nvme_admin_sanitize_nvm = 0x84,
c6389845 985 nvme_admin_get_lba_status = 0x86,
c1fef73f 986 nvme_admin_vendor_start = 0xC0,
9d99a8dd
CH		 987};
988
26f2990d
MI		 989#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
990#define show_admin_opcode_name(val) \
991 __print_symbolic(val, \
992 nvme_admin_opcode_name(nvme_admin_delete_sq), \
993 nvme_admin_opcode_name(nvme_admin_create_sq), \
994 nvme_admin_opcode_name(nvme_admin_get_log_page), \
995 nvme_admin_opcode_name(nvme_admin_delete_cq), \
996 nvme_admin_opcode_name(nvme_admin_create_cq), \
997 nvme_admin_opcode_name(nvme_admin_identify), \
998 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
999 nvme_admin_opcode_name(nvme_admin_set_features), \
1000 nvme_admin_opcode_name(nvme_admin_get_features), \
1001 nvme_admin_opcode_name(nvme_admin_async_event), \
1002 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1003 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1004 nvme_admin_opcode_name(nvme_admin_download_fw), \
1005 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1006 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1007 nvme_admin_opcode_name(nvme_admin_directive_send), \
1008 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1009 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1010 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1011 nvme_admin_opcode_name(nvme_admin_security_send), \
1012 nvme_admin_opcode_name(nvme_admin_security_recv), \
a5ef7572
MI		 1013 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1014 nvme_admin_opcode_name(nvme_admin_get_lba_status))
26f2990d 1015
9d99a8dd
CH		 1016enum {
1017 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1018 NVME_CQ_IRQ_ENABLED = (1 << 1),
1019 NVME_SQ_PRIO_URGENT = (0 << 1),
1020 NVME_SQ_PRIO_HIGH = (1 << 1),
1021 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1022 NVME_SQ_PRIO_LOW = (3 << 1),
1023 NVME_FEAT_ARBITRATION = 0x01,
1024 NVME_FEAT_POWER_MGMT = 0x02,
1025 NVME_FEAT_LBA_RANGE = 0x03,
1026 NVME_FEAT_TEMP_THRESH = 0x04,
1027 NVME_FEAT_ERR_RECOVERY = 0x05,
1028 NVME_FEAT_VOLATILE_WC = 0x06,
1029 NVME_FEAT_NUM_QUEUES = 0x07,
1030 NVME_FEAT_IRQ_COALESCE = 0x08,
1031 NVME_FEAT_IRQ_CONFIG = 0x09,
1032 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1033 NVME_FEAT_ASYNC_EVENT = 0x0b,
1034 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 1035 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 1036 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 1037 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 1038 NVME_FEAT_HCTM = 0x10,
1039 NVME_FEAT_NOPSC = 0x11,
1040 NVME_FEAT_RRL = 0x12,
1041 NVME_FEAT_PLM_CONFIG = 0x13,
1042 NVME_FEAT_PLM_WINDOW = 0x14,
49cd84b6 1043 NVME_FEAT_HOST_BEHAVIOR = 0x16,
48c9e85b 1044 NVME_FEAT_SANITIZE = 0x17,
9d99a8dd
CH		 1045 NVME_FEAT_SW_PROGRESS = 0x80,
1046 NVME_FEAT_HOST_ID = 0x81,
1047 NVME_FEAT_RESV_MASK = 0x82,
1048 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 1049 NVME_FEAT_WRITE_PROTECT = 0x84,
c1fef73f
LG		 1050 NVME_FEAT_VENDOR_START = 0xC0,
1051 NVME_FEAT_VENDOR_END = 0xFF,
9d99a8dd
CH		 1052 NVME_LOG_ERROR = 0x01,
1053 NVME_LOG_SMART = 0x02,
1054 NVME_LOG_FW_SLOT = 0x03,
b3984e06 1055 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 1056 NVME_LOG_CMD_EFFECTS = 0x05,
48c9e85b
RR		 1057 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1058 NVME_LOG_TELEMETRY_HOST = 0x07,
1059 NVME_LOG_TELEMETRY_CTRL = 0x08,
1060 NVME_LOG_ENDURANCE_GROUP = 0x09,
1a376216 1061 NVME_LOG_ANA = 0x0c,
eb793e2c 1062 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 1063 NVME_LOG_RESERVATION = 0x80,
1064 NVME_FWACT_REPL = (0 << 3),
1065 NVME_FWACT_REPL_ACTV = (1 << 3),
1066 NVME_FWACT_ACTV = (2 << 3),
1067};
1068
93045d59
CK		 1069/* NVMe Namespace Write Protect State */
1070enum {
1071 NVME_NS_NO_WRITE_PROTECT = 0,
1072 NVME_NS_WRITE_PROTECT,
1073 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1074 NVME_NS_WRITE_PROTECT_PERMANENT,
1075};
1076
b3984e06
CH		 1077#define NVME_MAX_CHANGED_NAMESPACES 1024
1078
9d99a8dd
CH		 1079struct nvme_identify {
1080 __u8 opcode;
1081 __u8 flags;
1082 __u16 command_id;
1083 __le32 nsid;
1084 __u64 rsvd2[2];
eb793e2c 1085 union nvme_data_ptr dptr;
986994a2
PP		 1086 __u8 cns;
1087 __u8 rsvd3;
1088 __le16 ctrlid;
71010c30
NC		 1089 __u8 rsvd11[3];
1090 __u8 csi;
1091 __u32 rsvd12[4];
9d99a8dd
CH		 1092};
1093
0add5e8e
JT		 1094#define NVME_IDENTIFY_DATA_SIZE 4096
1095
9d99a8dd
CH		 1096struct nvme_features {
1097 __u8 opcode;
1098 __u8 flags;
1099 __u16 command_id;
1100 __le32 nsid;
1101 __u64 rsvd2[2];
eb793e2c 1102 union nvme_data_ptr dptr;
9d99a8dd
CH		 1103 __le32 fid;
1104 __le32 dword11;
b85cf734
AD		 1105 __le32 dword12;
1106 __le32 dword13;
1107 __le32 dword14;
1108 __le32 dword15;
9d99a8dd
CH		 1109};
1110
39673e19
CH		 1111struct nvme_host_mem_buf_desc {
1112 __le64 addr;
1113 __le32 size;
1114 __u32 rsvd;
1115};
1116
9d99a8dd
CH		 1117struct nvme_create_cq {
1118 __u8 opcode;
1119 __u8 flags;
1120 __u16 command_id;
1121 __u32 rsvd1[5];
1122 __le64 prp1;
1123 __u64 rsvd8;
1124 __le16 cqid;
1125 __le16 qsize;
1126 __le16 cq_flags;
1127 __le16 irq_vector;
1128 __u32 rsvd12[4];
1129};
1130
1131struct nvme_create_sq {
1132 __u8 opcode;
1133 __u8 flags;
1134 __u16 command_id;
1135 __u32 rsvd1[5];
1136 __le64 prp1;
1137 __u64 rsvd8;
1138 __le16 sqid;
1139 __le16 qsize;
1140 __le16 sq_flags;
1141 __le16 cqid;
1142 __u32 rsvd12[4];
1143};
1144
1145struct nvme_delete_queue {
1146 __u8 opcode;
1147 __u8 flags;
1148 __u16 command_id;
1149 __u32 rsvd1[9];
1150 __le16 qid;
1151 __u16 rsvd10;
1152 __u32 rsvd11[5];
1153};
1154
1155struct nvme_abort_cmd {
1156 __u8 opcode;
1157 __u8 flags;
1158 __u16 command_id;
1159 __u32 rsvd1[9];
1160 __le16 sqid;
1161 __u16 cid;
1162 __u32 rsvd11[5];
1163};
1164
1165struct nvme_download_firmware {
1166 __u8 opcode;
1167 __u8 flags;
1168 __u16 command_id;
1169 __u32 rsvd1[5];
eb793e2c 1170 union nvme_data_ptr dptr;
9d99a8dd
CH		 1171 __le32 numd;
1172 __le32 offset;
1173 __u32 rsvd12[4];
1174};
1175
1176struct nvme_format_cmd {
1177 __u8 opcode;
1178 __u8 flags;
1179 __u16 command_id;
1180 __le32 nsid;
1181 __u64 rsvd2[4];
1182 __le32 cdw10;
1183 __u32 rsvd11[5];
1184};
1185
725b3588
AB		 1186struct nvme_get_log_page_command {
1187 __u8 opcode;
1188 __u8 flags;
1189 __u16 command_id;
1190 __le32 nsid;
1191 __u64 rsvd2[2];
eb793e2c 1192 union nvme_data_ptr dptr;
725b3588 1193 __u8 lid;
9b89bc38 1194 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 1195 __le16 numdl;
1196 __le16 numdu;
1197 __u16 rsvd11;
d808b7f7
KB		 1198 union {
1199 struct {
1200 __le32 lpol;
1201 __le32 lpou;
1202 };
1203 __le64 lpo;
1204 };
be93e87e
KB		 1205 __u8 rsvd14[3];
1206 __u8 csi;
1207 __u32 rsvd15;
725b3588
AB		 1208};
1209
f5d11840
JA		 1210struct nvme_directive_cmd {
1211 __u8 opcode;
1212 __u8 flags;
1213 __u16 command_id;
1214 __le32 nsid;
1215 __u64 rsvd2[2];
1216 union nvme_data_ptr dptr;
1217 __le32 numd;
1218 __u8 doper;
1219 __u8 dtype;
1220 __le16 dspec;
1221 __u8 endir;
1222 __u8 tdtype;
1223 __u16 rsvd15;
1224
1225 __u32 rsvd16[3];
1226};
1227
eb793e2c
CH		 1228/*
1229 * Fabrics subcommands.
1230 */
1231enum nvmf_fabrics_opcode {
1232 nvme_fabrics_command = 0x7f,
1233};
1234
1235enum nvmf_capsule_command {
1236 nvme_fabrics_type_property_set = 0x00,
1237 nvme_fabrics_type_connect = 0x01,
1238 nvme_fabrics_type_property_get = 0x04,
1239};
1240
ad795e47
MI		 1241#define nvme_fabrics_type_name(type) { type, #type }
1242#define show_fabrics_type_name(type) \
1243 __print_symbolic(type, \
1244 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1245 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1246 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1247
1248/*
1249 * If not fabrics command, fctype will be ignored.
1250 */
1251#define show_opcode_name(qid, opcode, fctype) \
1252 ((opcode) == nvme_fabrics_command ? \
1253 show_fabrics_type_name(fctype) : \
1254 ((qid) ? \
1255 show_nvm_opcode_name(opcode) : \
1256 show_admin_opcode_name(opcode)))
1257
eb793e2c
CH		 1258struct nvmf_common_command {
1259 __u8 opcode;
1260 __u8 resv1;
1261 __u16 command_id;
1262 __u8 fctype;
1263 __u8 resv2[35];
1264 __u8 ts[24];
1265};
1266
1267/*
1268 * The legal cntlid range a NVMe Target will provide.
1269 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1270 * Devices based on earlier specs did not have the subsystem concept;
1271 * therefore, those devices had their cntlid value set to 0 as a result.
1272 */
1273#define NVME_CNTLID_MIN 1
1274#define NVME_CNTLID_MAX 0xffef
1275#define NVME_CNTLID_DYNAMIC 0xffff
1276
1277#define MAX_DISC_LOGS 255
1278
1279/* Discovery log page entry */
1280struct nvmf_disc_rsp_page_entry {
1281 __u8 trtype;
1282 __u8 adrfam;
a446c084 1283 __u8 subtype;
eb793e2c
CH		 1284 __u8 treq;
1285 __le16 portid;
1286 __le16 cntlid;
1287 __le16 asqsz;
1288 __u8 resv8[22];
1289 char trsvcid[NVMF_TRSVCID_SIZE];
1290 __u8 resv64[192];
1291 char subnqn[NVMF_NQN_FIELD_LEN];
1292 char traddr[NVMF_TRADDR_SIZE];
1293 union tsas {
1294 char common[NVMF_TSAS_SIZE];
1295 struct rdma {
1296 __u8 qptype;
1297 __u8 prtype;
1298 __u8 cms;
1299 __u8 resv3[5];
1300 __u16 pkey;
1301 __u8 resv10[246];
1302 } rdma;
1303 } tsas;
1304};
1305
1306/* Discovery log page header */
1307struct nvmf_disc_rsp_page_hdr {
1308 __le64 genctr;
1309 __le64 numrec;
1310 __le16 recfmt;
1311 __u8 resv14[1006];
f1e71d75 1312 struct nvmf_disc_rsp_page_entry entries[];
eb793e2c
CH		 1313};
1314
e6a622fd
SG		 1315enum {
1316 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1317};
1318
eb793e2c
CH		 1319struct nvmf_connect_command {
1320 __u8 opcode;
1321 __u8 resv1;
1322 __u16 command_id;
1323 __u8 fctype;
1324 __u8 resv2[19];
1325 union nvme_data_ptr dptr;
1326 __le16 recfmt;
1327 __le16 qid;
1328 __le16 sqsize;
1329 __u8 cattr;
1330 __u8 resv3;
1331 __le32 kato;
1332 __u8 resv4[12];
1333};
1334
1335struct nvmf_connect_data {
8e412263 1336 uuid_t hostid;
eb793e2c
CH		 1337 __le16 cntlid;
1338 char resv4[238];
1339 char subsysnqn[NVMF_NQN_FIELD_LEN];
1340 char hostnqn[NVMF_NQN_FIELD_LEN];
1341 char resv5[256];
1342};
1343
1344struct nvmf_property_set_command {
1345 __u8 opcode;
1346 __u8 resv1;
1347 __u16 command_id;
1348 __u8 fctype;
1349 __u8 resv2[35];
1350 __u8 attrib;
1351 __u8 resv3[3];
1352 __le32 offset;
1353 __le64 value;
1354 __u8 resv4[8];
1355};
1356
1357struct nvmf_property_get_command {
1358 __u8 opcode;
1359 __u8 resv1;
1360 __u16 command_id;
1361 __u8 fctype;
1362 __u8 resv2[35];
1363 __u8 attrib;
1364 __u8 resv3[3];
1365 __le32 offset;
1366 __u8 resv4[16];
1367};
1368
f9f38e33
HK		 1369struct nvme_dbbuf {
1370 __u8 opcode;
1371 __u8 flags;
1372 __u16 command_id;
1373 __u32 rsvd1[5];
1374 __le64 prp1;
1375 __le64 prp2;
1376 __u32 rsvd12[6];
1377};
1378
f5d11840 1379struct streams_directive_params {
dc1a0afb
CH		 1380 __le16 msl;
1381 __le16 nssa;
1382 __le16 nsso;
f5d11840 1383 __u8 rsvd[10];
dc1a0afb
CH		 1384 __le32 sws;
1385 __le16 sgs;
1386 __le16 nsa;
1387 __le16 nso;
f5d11840
JA		 1388 __u8 rsvd2[6];
1389};
1390
9d99a8dd
CH		 1391struct nvme_command {
1392 union {
1393 struct nvme_common_command common;
1394 struct nvme_rw_command rw;
1395 struct nvme_identify identify;
1396 struct nvme_features features;
1397 struct nvme_create_cq create_cq;
1398 struct nvme_create_sq create_sq;
1399 struct nvme_delete_queue delete_queue;
1400 struct nvme_download_firmware dlfw;
1401 struct nvme_format_cmd format;
1402 struct nvme_dsm_cmd dsm;
3b7c33b2 1403 struct nvme_write_zeroes_cmd write_zeroes;
240e6ee2
KB		 1404 struct nvme_zone_mgmt_send_cmd zms;
1405 struct nvme_zone_mgmt_recv_cmd zmr;
9d99a8dd 1406 struct nvme_abort_cmd abort;
725b3588 1407 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1408 struct nvmf_common_command fabrics;
1409 struct nvmf_connect_command connect;
1410 struct nvmf_property_set_command prop_set;
1411 struct nvmf_property_get_command prop_get;
f9f38e33 1412 struct nvme_dbbuf dbbuf;
f5d11840 1413 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1414 };
1415};
1416
7a1f46e3
MI		 1417static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1418{
1419 return cmd->common.opcode == nvme_fabrics_command;
1420}
1421
b34de7ce
CK		 1422struct nvme_error_slot {
1423 __le64 error_count;
1424 __le16 sqid;
1425 __le16 cmdid;
1426 __le16 status_field;
1427 __le16 param_error_location;
1428 __le64 lba;
1429 __le32 nsid;
1430 __u8 vs;
1431 __u8 resv[3];
1432 __le64 cs;
1433 __u8 resv2[24];
1434};
1435
7a5abb4b
CH		 1436static inline bool nvme_is_write(struct nvme_command *cmd)
1437{
eb793e2c
CH		 1438 /*
1439 * What a mess...
1440 *
1441 * Why can't we simply have a Fabrics In and Fabrics out command?
1442 */
7a1f46e3 1443 if (unlikely(nvme_is_fabrics(cmd)))
2fd4167f 1444 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1445 return cmd->common.opcode & 1;
1446}
1447
9d99a8dd 1448enum {
eb793e2c
CH		 1449 /*
1450 * Generic Command Status:
1451 */
9d99a8dd
CH		 1452 NVME_SC_SUCCESS = 0x0,
1453 NVME_SC_INVALID_OPCODE = 0x1,
1454 NVME_SC_INVALID_FIELD = 0x2,
1455 NVME_SC_CMDID_CONFLICT = 0x3,
1456 NVME_SC_DATA_XFER_ERROR = 0x4,
1457 NVME_SC_POWER_LOSS = 0x5,
1458 NVME_SC_INTERNAL = 0x6,
1459 NVME_SC_ABORT_REQ = 0x7,
1460 NVME_SC_ABORT_QUEUE = 0x8,
1461 NVME_SC_FUSED_FAIL = 0x9,
1462 NVME_SC_FUSED_MISSING = 0xa,
1463 NVME_SC_INVALID_NS = 0xb,
1464 NVME_SC_CMD_SEQ_ERROR = 0xc,
1465 NVME_SC_SGL_INVALID_LAST = 0xd,
1466 NVME_SC_SGL_INVALID_COUNT = 0xe,
1467 NVME_SC_SGL_INVALID_DATA = 0xf,
1468 NVME_SC_SGL_INVALID_METADATA = 0x10,
1469 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 1470
1471 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1472 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1473
48c9e85b
RR		 1474 NVME_SC_SANITIZE_FAILED = 0x1C,
1475 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1476
93045d59 1477 NVME_SC_NS_WRITE_PROTECTED = 0x20,
48c9e85b 1478 NVME_SC_CMD_INTERRUPTED = 0x21,
93045d59 1479
9d99a8dd
CH		 1480 NVME_SC_LBA_RANGE = 0x80,
1481 NVME_SC_CAP_EXCEEDED = 0x81,
1482 NVME_SC_NS_NOT_READY = 0x82,
1483 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 1484
1485 /*
1486 * Command Specific Status:
1487 */
9d99a8dd
CH		 1488 NVME_SC_CQ_INVALID = 0x100,
1489 NVME_SC_QID_INVALID = 0x101,
1490 NVME_SC_QUEUE_SIZE = 0x102,
1491 NVME_SC_ABORT_LIMIT = 0x103,
1492 NVME_SC_ABORT_MISSING = 0x104,
1493 NVME_SC_ASYNC_LIMIT = 0x105,
1494 NVME_SC_FIRMWARE_SLOT = 0x106,
1495 NVME_SC_FIRMWARE_IMAGE = 0x107,
1496 NVME_SC_INVALID_VECTOR = 0x108,
1497 NVME_SC_INVALID_LOG_PAGE = 0x109,
1498 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1499 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1500 NVME_SC_INVALID_QUEUE = 0x10c,
1501 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1502 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1503 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1504 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1505 NVME_SC_FW_NEEDS_RESET = 0x111,
1506 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
9581ae4f 1507 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
a446c084 1508 NVME_SC_OVERLAPPING_RANGE = 0x114,
9581ae4f 1509 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
a446c084
CH		 1510 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1511 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1512 NVME_SC_NS_IS_PRIVATE = 0x119,
1513 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1514 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1515 NVME_SC_CTRL_LIST_INVALID = 0x11c,
48c9e85b
RR		 1516 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1517 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
eb793e2c
CH		 1518
1519 /*
1520 * I/O Command Set Specific - NVM commands:
1521 */
9d99a8dd
CH		 1522 NVME_SC_BAD_ATTRIBUTES = 0x180,
1523 NVME_SC_INVALID_PI = 0x181,
1524 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1525 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1526
1527 /*
1528 * I/O Command Set Specific - Fabrics commands:
1529 */
1530 NVME_SC_CONNECT_FORMAT = 0x180,
1531 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1532 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1533 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1534 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1535
1536 NVME_SC_DISCOVERY_RESTART = 0x190,
1537 NVME_SC_AUTH_REQUIRED = 0x191,
1538
240e6ee2
KB		 1539 /*
1540 * I/O Command Set Specific - Zoned commands:
1541 */
1542 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1543 NVME_SC_ZONE_FULL = 0x1b9,
1544 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1545 NVME_SC_ZONE_OFFLINE = 0x1bb,
1546 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1547 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1548 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1549 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1550
eb793e2c
CH		 1551 /*
1552 * Media and Data Integrity Errors:
1553 */
9d99a8dd
CH		 1554 NVME_SC_WRITE_FAULT = 0x280,
1555 NVME_SC_READ_ERROR = 0x281,
1556 NVME_SC_GUARD_CHECK = 0x282,
1557 NVME_SC_APPTAG_CHECK = 0x283,
1558 NVME_SC_REFTAG_CHECK = 0x284,
1559 NVME_SC_COMPARE_FAILED = 0x285,
1560 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1561 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1562
1a376216
CH		 1563 /*
1564 * Path-related Errors:
1565 */
1566 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1567 NVME_SC_ANA_INACCESSIBLE = 0x302,
1568 NVME_SC_ANA_TRANSITION = 0x303,
783f4a44 1569 NVME_SC_HOST_PATH_ERROR = 0x370,
2dc3947b 1570 NVME_SC_HOST_ABORTED_CMD = 0x371,
1a376216 1571
49cd84b6 1572 NVME_SC_CRD = 0x1800,
9d99a8dd
CH		 1573 NVME_SC_DNR = 0x4000,
1574};
1575
1576struct nvme_completion {
eb793e2c
CH		 1577 /*
1578 * Used by Admin and Fabrics commands to return data:
1579 */
d49187e9
CH		 1580 union nvme_result {
1581 __le16 u16;
1582 __le32 u32;
1583 __le64 u64;
1584 } result;
9d99a8dd
CH		 1585 __le16 sq_head; /* how much of this queue may be reclaimed */
1586 __le16 sq_id; /* submission queue that generated this entry */
1587 __u16 command_id; /* of the command which completed */
1588 __le16 status; /* did the command fail, and if so, why? */
1589};
1590
8ef2074d
GKB		 1591#define NVME_VS(major, minor, tertiary) \
1592 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1593
c61d788b
JT		 1594#define NVME_MAJOR(ver) ((ver) >> 16)
1595#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1596#define NVME_TERTIARY(ver) ((ver) & 0xff)
1597
b60503ba 1598#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)