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Merge tag 'block-6.0-2022-09-16' of git://git.kernel.dk/linux-block
[linux-2.6-block.git] / include / linux / nvme.h
CommitLineData
fadccd8f 1/* SPDX-License-Identifier: GPL-2.0 */
b60503ba
MW		 2/*
3 * Definitions for the NVM Express interface
8757ad65 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
2812dfe3 10#include <linux/types.h>
8e412263 11#include <linux/uuid.h>
eb793e2c
CH		 12
13/* NQN names in commands fields specified one size */
14#define NVMF_NQN_FIELD_LEN 256
15
16/* However the max length of a qualified name is another size */
17#define NVMF_NQN_SIZE 223
18
19#define NVMF_TRSVCID_SIZE 32
20#define NVMF_TRADDR_SIZE 256
21#define NVMF_TSAS_SIZE 256
88b140fe 22#define NVMF_AUTH_HASH_LEN 64
eb793e2c
CH		 23
24#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26#define NVME_RDMA_IP_PORT 4420
27
62346eae
AD		 28#define NVME_NSID_ALL 0xffffffff
29
eb793e2c 30enum nvme_subsys_type {
785d584c
HR		 31 /* Referral to another discovery type target subsystem */
32 NVME_NQN_DISC = 1,
33
34 /* NVME type target subsystem */
35 NVME_NQN_NVME = 2,
36
37 /* Current discovery type target subsystem */
38 NVME_NQN_CURR = 3,
eb793e2c
CH		 39};
40
e15a8a97
HR		 41enum nvme_ctrl_type {
42 NVME_CTRL_IO = 1, /* I/O controller */
43 NVME_CTRL_DISC = 2, /* Discovery controller */
44 NVME_CTRL_ADMIN = 3, /* Administrative controller */
45};
46
86c2457a
MB		 47enum nvme_dctype {
48 NVME_DCTYPE_NOT_REPORTED = 0,
49 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
50 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
51};
52
eb793e2c
CH		 53/* Address Family codes for Discovery Log Page entry ADRFAM field */
54enum {
55 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
56 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
57 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
58 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
59 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
d02abd19
CK		 60 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
61 NVMF_ADDR_FAMILY_MAX,
eb793e2c
CH		 62};
63
64/* Transport Type codes for Discovery Log Page entry TRTYPE field */
65enum {
66 NVMF_TRTYPE_RDMA = 1, /* RDMA */
67 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
fc221d05 68 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
eb793e2c
CH		 69 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
70 NVMF_TRTYPE_MAX,
71};
72
73/* Transport Requirements codes for Discovery Log Page entry TREQ field */
74enum {
9b95d2fb
SG		 75 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
76 NVMF_TREQ_REQUIRED = 1, /* Required */
77 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 78#define NVME_TREQ_SECURE_CHANNEL_MASK \
79 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
9b95d2fb
SG		 80
81 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
eb793e2c
CH		 82};
83
84/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
85 * RDMA_QPTYPE field
86 */
87enum {
bf17aa36
RD		 88 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
89 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 90};
91
92/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
93 * RDMA_QPTYPE field
94 */
95enum {
bf17aa36
RD		 96 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
97 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
98 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
99 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
100 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 101};
102
103/* RDMA Connection Management Service Type codes for Discovery Log Page
104 * entry TSAS RDMA_CMS field
105 */
106enum {
bf17aa36 107 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 108};
109
7aa1f427 110#define NVME_AQ_DEPTH 32
38dabe21
KB		 111#define NVME_NR_AEN_COMMANDS 1
112#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
113
114/*
115 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
116 * NVM-Express 1.2 specification, section 4.1.2.
117 */
118#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 119
7a67cbea
CH		 120enum {
121 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
122 NVME_REG_VS = 0x0008, /* Version */
123 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 124 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 125 NVME_REG_CC = 0x0014, /* Controller Configuration */
126 NVME_REG_CSTS = 0x001c, /* Controller Status */
127 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
128 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
129 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 130 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
48c9e85b 131 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea 132 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
48c9e85b
RR		 133 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
134 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
135 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
136 * Location
137 */
20d3bb92
KJ		 138 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
139 * Space Control
140 */
354201c5 141 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
48c9e85b
RR		 142 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
143 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
144 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
145 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
146 * Buffer Size
147 */
148 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
149 * Write Throughput
150 */
97f6ef64 151 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 152};
153
a0cadb85 154#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 155#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 156#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 157#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
71010c30 158#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
8fc23e03 159#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 160#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
20d3bb92 161#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
22605f96 162
8ffaadf7
JD		 163#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
164#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598 165
354201c5
CH		 166#define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
167#define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
168
88de4598
CH		 169enum {
170 NVME_CMBSZ_SQS = 1 << 0,
171 NVME_CMBSZ_CQS = 1 << 1,
172 NVME_CMBSZ_LISTS = 1 << 2,
173 NVME_CMBSZ_RDS = 1 << 3,
174 NVME_CMBSZ_WDS = 1 << 4,
175
176 NVME_CMBSZ_SZ_SHIFT = 12,
177 NVME_CMBSZ_SZ_MASK = 0xfffff,
178
179 NVME_CMBSZ_SZU_SHIFT = 8,
180 NVME_CMBSZ_SZU_MASK = 0xf,
181};
8ffaadf7 182
69cd27e2
CH		 183/*
184 * Submission and Completion Queue Entry Sizes for the NVM command set.
185 * (In bytes and specified as a power of two (2^n)).
186 */
c1e0cc7e 187#define NVME_ADM_SQES 6
69cd27e2
CH		 188#define NVME_NVM_IOSQES 6
189#define NVME_NVM_IOCQES 4
190
b60503ba
MW		 191enum {
192 NVME_CC_ENABLE = 1 << 0,
ad4e05b2
MG		 193 NVME_CC_EN_SHIFT = 0,
194 NVME_CC_CSS_SHIFT = 4,
b60503ba 195 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 196 NVME_CC_AMS_SHIFT = 11,
197 NVME_CC_SHN_SHIFT = 14,
198 NVME_CC_IOSQES_SHIFT = 16,
199 NVME_CC_IOCQES_SHIFT = 20,
71010c30
NC		 200 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
201 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
202 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
60b43f62
MG		 203 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
204 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
205 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 206 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
207 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
208 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
209 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
210 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
211 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
354201c5 212 NVME_CC_CRIME = 1 << 24,
e626f37e
CH		 213};
214
215enum {
b60503ba
MW		 216 NVME_CSTS_RDY = 1 << 0,
217 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 218 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 219 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 220 NVME_CSTS_SHST_NORMAL = 0 << 2,
221 NVME_CSTS_SHST_OCCUR = 1 << 2,
222 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 223 NVME_CSTS_SHST_MASK = 3 << 2,
e626f37e
CH		 224};
225
226enum {
20d3bb92
KJ		 227 NVME_CMBMSC_CRE = 1 << 0,
228 NVME_CMBMSC_CMSE = 1 << 1,
b60503ba
MW		 229};
230
e626f37e
CH		 231enum {
232 NVME_CAP_CSS_NVM = 1 << 0,
233 NVME_CAP_CSS_CSI = 1 << 6,
234};
235
354201c5 236enum {
23c9cd56
JG		 237 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
238 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
354201c5
CH		 239};
240
9d99a8dd
CH		 241struct nvme_id_power_state {
242 __le16 max_power; /* centiwatts */
243 __u8 rsvd2;
244 __u8 flags;
245 __le32 entry_lat; /* microseconds */
246 __le32 exit_lat; /* microseconds */
247 __u8 read_tput;
248 __u8 read_lat;
249 __u8 write_tput;
250 __u8 write_lat;
251 __le16 idle_power;
252 __u8 idle_scale;
253 __u8 rsvd19;
254 __le16 active_power;
255 __u8 active_work_scale;
256 __u8 rsvd23[9];
257};
258
259enum {
260 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
261 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
262};
263
12b21171
SG		 264enum nvme_ctrl_attr {
265 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 266 NVME_CTRL_ATTR_TBKAS = (1 << 6),
4020aad8 267 NVME_CTRL_ATTR_ELBAS = (1 << 15),
12b21171
SG		 268};
269
9d99a8dd
CH		 270struct nvme_id_ctrl {
271 __le16 vid;
272 __le16 ssvid;
273 char sn[20];
274 char mn[40];
275 char fr[8];
276 __u8 rab;
277 __u8 ieee[3];
a446c084 278 __u8 cmic;
9d99a8dd 279 __u8 mdts;
08c69640
CH		 280 __le16 cntlid;
281 __le32 ver;
14e974a8
CH		 282 __le32 rtd3r;
283 __le32 rtd3e;
284 __le32 oaes;
eb793e2c 285 __le32 ctratt;
e15a8a97
HR		 286 __u8 rsvd100[11];
287 __u8 cntrltype;
288 __u8 fguid[16];
49cd84b6
KB		 289 __le16 crdt1;
290 __le16 crdt2;
291 __le16 crdt3;
292 __u8 rsvd134[122];
9d99a8dd
CH		 293 __le16 oacs;
294 __u8 acl;
295 __u8 aerl;
296 __u8 frmw;
297 __u8 lpa;
298 __u8 elpe;
299 __u8 npss;
300 __u8 avscc;
301 __u8 apsta;
302 __le16 wctemp;
303 __le16 cctemp;
a446c084
CH		 304 __le16 mtfa;
305 __le32 hmpre;
306 __le32 hmmin;
307 __u8 tnvmcap[16];
308 __u8 unvmcap[16];
309 __le32 rpmbs;
435e8090
GJ		 310 __le16 edstt;
311 __u8 dsto;
312 __u8 fwug;
7b89eae2 313 __le16 kas;
435e8090
GJ		 314 __le16 hctma;
315 __le16 mntmt;
316 __le16 mxtmt;
317 __le32 sanicap;
044a9df1
CH		 318 __le32 hmminds;
319 __le16 hmmaxd;
1a376216
CH		 320 __u8 rsvd338[4];
321 __u8 anatt;
322 __u8 anacap;
323 __le32 anagrpmax;
324 __le32 nanagrpid;
325 __u8 rsvd352[160];
9d99a8dd
CH		 326 __u8 sqes;
327 __u8 cqes;
eb793e2c 328 __le16 maxcmd;
9d99a8dd
CH		 329 __le32 nn;
330 __le16 oncs;
331 __le16 fuses;
332 __u8 fna;
333 __u8 vwc;
334 __le16 awun;
335 __le16 awupf;
336 __u8 nvscc;
93045d59 337 __u8 nwpc;
9d99a8dd
CH		 338 __le16 acwu;
339 __u8 rsvd534[2];
340 __le32 sgls;
1a376216
CH		 341 __le32 mnan;
342 __u8 rsvd544[224];
eb793e2c
CH		 343 char subnqn[256];
344 __u8 rsvd1024[768];
345 __le32 ioccsz;
346 __le32 iorcsz;
347 __le16 icdoff;
348 __u8 ctrattr;
349 __u8 msdbd;
86c2457a
MB		 350 __u8 rsvd1804[2];
351 __u8 dctype;
352 __u8 rsvd1807[241];
9d99a8dd
CH		 353 struct nvme_id_power_state psd[32];
354 __u8 vs[1024];
355};
356
357enum {
d56ae18f 358 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
92decf11
KB		 359 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
360 NVME_CTRL_CMIC_ANA = 1 << 3,
9d99a8dd
CH		 361 NVME_CTRL_ONCS_COMPARE = 1 << 0,
362 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
363 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 364 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
c1fef73f 365 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
dbf86b39 366 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 367 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 368 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
5974ea7c 369 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
f5d11840 370 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 371 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 372 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
48c9e85b
RR		 373 NVME_CTRL_CTRATT_128_ID = 1 << 0,
374 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
375 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
376 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
377 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
378 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
379 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
380 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
9d99a8dd
CH		 381};
382
383struct nvme_lbaf {
384 __le16 ms;
385 __u8 ds;
386 __u8 rp;
387};
388
389struct nvme_id_ns {
390 __le64 nsze;
391 __le64 ncap;
392 __le64 nuse;
393 __u8 nsfeat;
394 __u8 nlbaf;
395 __u8 flbas;
396 __u8 mc;
397 __u8 dpc;
398 __u8 dps;
399 __u8 nmic;
400 __u8 rescap;
401 __u8 fpi;
6605bdd5 402 __u8 dlfeat;
9d99a8dd
CH		 403 __le16 nawun;
404 __le16 nawupf;
405 __le16 nacwu;
406 __le16 nabsn;
407 __le16 nabo;
408 __le16 nabspf;
6b8190d6 409 __le16 noiob;
a446c084 410 __u8 nvmcap[16];
6605bdd5
BVA		 411 __le16 npwg;
412 __le16 npwa;
413 __le16 npdg;
414 __le16 npda;
415 __le16 nows;
416 __u8 rsvd74[18];
1a376216 417 __le32 anagrpid;
93045d59
CK		 418 __u8 rsvd96[3];
419 __u8 nsattr;
6605bdd5
BVA		 420 __le16 nvmsetid;
421 __le16 endgid;
9d99a8dd
CH		 422 __u8 nguid[16];
423 __u8 eui64[8];
4020aad8 424 struct nvme_lbaf lbaf[64];
9d99a8dd
CH		 425 __u8 vs[3712];
426};
427
354201c5
CH		 428/* I/O Command Set Independent Identify Namespace Data Structure */
429struct nvme_id_ns_cs_indep {
430 __u8 nsfeat;
431 __u8 nmic;
432 __u8 rescap;
433 __u8 fpi;
434 __le32 anagrpid;
435 __u8 nsattr;
436 __u8 rsvd9;
437 __le16 nvmsetid;
438 __le16 endgid;
439 __u8 nstat;
440 __u8 rsvd15[4081];
441};
442
240e6ee2
KB		 443struct nvme_zns_lbafe {
444 __le64 zsze;
445 __u8 zdes;
446 __u8 rsvd9[7];
447};
448
449struct nvme_id_ns_zns {
450 __le16 zoc;
451 __le16 ozcs;
452 __le32 mar;
453 __le32 mor;
454 __le32 rrl;
455 __le32 frl;
456 __u8 rsvd20[2796];
4020aad8 457 struct nvme_zns_lbafe lbafe[64];
240e6ee2
KB		 458 __u8 vs[256];
459};
460
461struct nvme_id_ctrl_zns {
462 __u8 zasl;
463 __u8 rsvd1[4095];
464};
465
4020aad8
KB		 466struct nvme_id_ns_nvm {
467 __le64 lbstm;
468 __u8 pic;
469 __u8 rsvd9[3];
470 __le32 elbaf[64];
471 __u8 rsvd268[3828];
472};
473
474enum {
475 NVME_ID_NS_NVM_STS_MASK = 0x3f,
476 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
477 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
478};
479
480static inline __u8 nvme_elbaf_sts(__u32 elbaf)
481{
482 return elbaf & NVME_ID_NS_NVM_STS_MASK;
483}
484
485static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
486{
487 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
488}
489
5befc7c2
KB		 490struct nvme_id_ctrl_nvm {
491 __u8 vsl;
492 __u8 wzsl;
493 __u8 wusl;
494 __u8 dmrl;
495 __le32 dmrsl;
496 __le64 dmsl;
497 __u8 rsvd16[4080];
498};
499
329dd768
CH		 500enum {
501 NVME_ID_CNS_NS = 0x00,
502 NVME_ID_CNS_CTRL = 0x01,
503 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 504 NVME_ID_CNS_NS_DESC_LIST = 0x03,
71010c30
NC		 505 NVME_ID_CNS_CS_NS = 0x05,
506 NVME_ID_CNS_CS_CTRL = 0x06,
354201c5 507 NVME_ID_CNS_NS_CS_INDEP = 0x08,
329dd768
CH		 508 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
509 NVME_ID_CNS_NS_PRESENT = 0x11,
510 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
511 NVME_ID_CNS_CTRL_LIST = 0x13,
48c9e85b
RR		 512 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
513 NVME_ID_CNS_NS_GRANULARITY = 0x16,
514 NVME_ID_CNS_UUID_LIST = 0x17,
329dd768
CH		 515};
516
71010c30
NC		 517enum {
518 NVME_CSI_NVM = 0,
240e6ee2 519 NVME_CSI_ZNS = 2,
71010c30
NC		 520};
521
f5d11840
JA		 522enum {
523 NVME_DIR_IDENTIFY = 0x00,
524 NVME_DIR_STREAMS = 0x01,
525 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
526 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
527 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
528 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
529 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
530 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
531 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
532 NVME_DIR_ENDIR = 0x01,
533};
534
9d99a8dd
CH		 535enum {
536 NVME_NS_FEAT_THIN = 1 << 0,
92decf11
KB		 537 NVME_NS_FEAT_ATOMICS = 1 << 1,
538 NVME_NS_FEAT_IO_OPT = 1 << 4,
539 NVME_NS_ATTR_RO = 1 << 0,
9d99a8dd 540 NVME_NS_FLBAS_LBA_MASK = 0xf,
4020aad8
KB		 541 NVME_NS_FLBAS_LBA_UMASK = 0x60,
542 NVME_NS_FLBAS_LBA_SHIFT = 1,
9d99a8dd 543 NVME_NS_FLBAS_META_EXT = 0x10,
92decf11 544 NVME_NS_NMIC_SHARED = 1 << 0,
9d99a8dd
CH		 545 NVME_LBAF_RP_BEST = 0,
546 NVME_LBAF_RP_BETTER = 1,
547 NVME_LBAF_RP_GOOD = 2,
548 NVME_LBAF_RP_DEGRADED = 3,
549 NVME_NS_DPC_PI_LAST = 1 << 4,
550 NVME_NS_DPC_PI_FIRST = 1 << 3,
551 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
552 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
553 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
554 NVME_NS_DPS_PI_FIRST = 1 << 3,
555 NVME_NS_DPS_PI_MASK = 0x7,
556 NVME_NS_DPS_PI_TYPE1 = 1,
557 NVME_NS_DPS_PI_TYPE2 = 2,
558 NVME_NS_DPS_PI_TYPE3 = 3,
559};
560
354201c5
CH		 561enum {
562 NVME_NSTAT_NRDY = 1 << 0,
563};
564
4020aad8
KB		 565enum {
566 NVME_NVM_NS_16B_GUARD = 0,
567 NVME_NVM_NS_32B_GUARD = 1,
568 NVME_NVM_NS_64B_GUARD = 2,
569};
570
571static inline __u8 nvme_lbaf_index(__u8 flbas)
572{
573 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
574 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
575}
576
39481fbd
IR		 577/* Identify Namespace Metadata Capabilities (MC): */
578enum {
579 NVME_MC_EXTENDED_LBA = (1 << 0),
580 NVME_MC_METADATA_PTR = (1 << 1),
581};
582
af8b86e9
JT		 583struct nvme_ns_id_desc {
584 __u8 nidt;
585 __u8 nidl;
586 __le16 reserved;
587};
588
589#define NVME_NIDT_EUI64_LEN 8
590#define NVME_NIDT_NGUID_LEN 16
591#define NVME_NIDT_UUID_LEN 16
71010c30 592#define NVME_NIDT_CSI_LEN 1
af8b86e9
JT		 593
594enum {
595 NVME_NIDT_EUI64 = 0x01,
596 NVME_NIDT_NGUID = 0x02,
597 NVME_NIDT_UUID = 0x03,
71010c30 598 NVME_NIDT_CSI = 0x04,
af8b86e9
JT		 599};
600
9d99a8dd
CH		 601struct nvme_smart_log {
602 __u8 critical_warning;
603 __u8 temperature[2];
604 __u8 avail_spare;
605 __u8 spare_thresh;
606 __u8 percent_used;
48c9e85b
RR		 607 __u8 endu_grp_crit_warn_sumry;
608 __u8 rsvd7[25];
9d99a8dd
CH		 609 __u8 data_units_read[16];
610 __u8 data_units_written[16];
611 __u8 host_reads[16];
612 __u8 host_writes[16];
613 __u8 ctrl_busy_time[16];
614 __u8 power_cycles[16];
615 __u8 power_on_hours[16];
616 __u8 unsafe_shutdowns[16];
617 __u8 media_errors[16];
618 __u8 num_err_log_entries[16];
619 __le32 warning_temp_time;
620 __le32 critical_comp_time;
621 __le16 temp_sensor[8];
48c9e85b
RR		 622 __le32 thm_temp1_trans_count;
623 __le32 thm_temp2_trans_count;
624 __le32 thm_temp1_total_time;
625 __le32 thm_temp2_total_time;
626 __u8 rsvd232[280];
9d99a8dd
CH		 627};
628
b6dccf7f
AD		 629struct nvme_fw_slot_info_log {
630 __u8 afi;
631 __u8 rsvd1[7];
632 __le64 frs[7];
633 __u8 rsvd64[448];
634};
635
84fef62d
KB		 636enum {
637 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
638 NVME_CMD_EFFECTS_LBCC = 1 << 1,
639 NVME_CMD_EFFECTS_NCC = 1 << 2,
640 NVME_CMD_EFFECTS_NIC = 1 << 3,
641 NVME_CMD_EFFECTS_CCC = 1 << 4,
642 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
48c9e85b 643 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
84fef62d
KB		 644};
645
646struct nvme_effects_log {
647 __le32 acs[256];
648 __le32 iocs[256];
649 __u8 resv[2048];
650};
651
1a376216
CH		 652enum nvme_ana_state {
653 NVME_ANA_OPTIMIZED = 0x01,
654 NVME_ANA_NONOPTIMIZED = 0x02,
655 NVME_ANA_INACCESSIBLE = 0x03,
656 NVME_ANA_PERSISTENT_LOSS = 0x04,
657 NVME_ANA_CHANGE = 0x0f,
658};
659
660struct nvme_ana_group_desc {
661 __le32 grpid;
662 __le32 nnsids;
663 __le64 chgcnt;
664 __u8 state;
8b92d0e3 665 __u8 rsvd17[15];
1a376216
CH		 666 __le32 nsids[];
667};
668
669/* flag for the log specific field of the ANA log */
670#define NVME_ANA_LOG_RGO (1 << 0)
671
672struct nvme_ana_rsp_hdr {
673 __le64 chgcnt;
674 __le16 ngrps;
675 __le16 rsvd10[3];
676};
677
240e6ee2
KB		 678struct nvme_zone_descriptor {
679 __u8 zt;
680 __u8 zs;
681 __u8 za;
682 __u8 rsvd3[5];
683 __le64 zcap;
684 __le64 zslba;
685 __le64 wp;
686 __u8 rsvd32[32];
687};
688
689enum {
690 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
691};
692
693struct nvme_zone_report {
694 __le64 nr_zones;
695 __u8 resv8[56];
696 struct nvme_zone_descriptor entries[];
697};
698
9d99a8dd
CH		 699enum {
700 NVME_SMART_CRIT_SPARE = 1 << 0,
701 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
702 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
703 NVME_SMART_CRIT_MEDIA = 1 << 3,
704 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
705};
706
707enum {
e3d7874d
KB		 708 NVME_AER_ERROR = 0,
709 NVME_AER_SMART = 1,
868c2392 710 NVME_AER_NOTICE = 2,
e3d7874d
KB		 711 NVME_AER_CSS = 6,
712 NVME_AER_VS = 7,
868c2392
CH		 713};
714
2c61c97f
MK		 715enum {
716 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
717};
718
868c2392
CH		 719enum {
720 NVME_AER_NOTICE_NS_CHANGED = 0x00,
721 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 722 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 723 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 724};
725
aafd3afe 726enum {
7114ddeb
JS		 727 NVME_AEN_BIT_NS_ATTR = 8,
728 NVME_AEN_BIT_FW_ACT = 9,
729 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 730 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 731};
732
733enum {
734 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
735 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
736 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 737 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 738};
739
9d99a8dd
CH		 740struct nvme_lba_range_type {
741 __u8 type;
742 __u8 attributes;
743 __u8 rsvd2[14];
8cf486e1
WS		 744 __le64 slba;
745 __le64 nlb;
9d99a8dd
CH		 746 __u8 guid[16];
747 __u8 rsvd48[16];
748};
749
750enum {
751 NVME_LBART_TYPE_FS = 0x01,
752 NVME_LBART_TYPE_RAID = 0x02,
753 NVME_LBART_TYPE_CACHE = 0x03,
754 NVME_LBART_TYPE_SWAP = 0x04,
755
756 NVME_LBART_ATTRIB_TEMP = 1 << 0,
757 NVME_LBART_ATTRIB_HIDE = 1 << 1,
758};
759
760struct nvme_reservation_status {
761 __le32 gen;
762 __u8 rtype;
763 __u8 regctl[2];
764 __u8 resv5[2];
765 __u8 ptpls;
766 __u8 resv10[13];
767 struct {
768 __le16 cntlid;
769 __u8 rcsts;
770 __u8 resv3[5];
771 __le64 hostid;
772 __le64 rkey;
773 } regctl_ds[];
774};
775
79f370ea
CH		 776enum nvme_async_event_type {
777 NVME_AER_TYPE_ERROR = 0,
778 NVME_AER_TYPE_SMART = 1,
779 NVME_AER_TYPE_NOTICE = 2,
780};
781
9d99a8dd
CH		 782/* I/O commands */
783
784enum nvme_opcode {
785 nvme_cmd_flush = 0x00,
786 nvme_cmd_write = 0x01,
787 nvme_cmd_read = 0x02,
788 nvme_cmd_write_uncor = 0x04,
789 nvme_cmd_compare = 0x05,
790 nvme_cmd_write_zeroes = 0x08,
791 nvme_cmd_dsm = 0x09,
48c9e85b 792 nvme_cmd_verify = 0x0c,
9d99a8dd
CH		 793 nvme_cmd_resv_register = 0x0d,
794 nvme_cmd_resv_report = 0x0e,
795 nvme_cmd_resv_acquire = 0x11,
796 nvme_cmd_resv_release = 0x15,
240e6ee2
KB		 797 nvme_cmd_zone_mgmt_send = 0x79,
798 nvme_cmd_zone_mgmt_recv = 0x7a,
799 nvme_cmd_zone_append = 0x7d,
9d99a8dd
CH		 800};
801
26f2990d
MI		 802#define nvme_opcode_name(opcode) { opcode, #opcode }
803#define show_nvm_opcode_name(val) \
804 __print_symbolic(val, \
805 nvme_opcode_name(nvme_cmd_flush), \
806 nvme_opcode_name(nvme_cmd_write), \
807 nvme_opcode_name(nvme_cmd_read), \
808 nvme_opcode_name(nvme_cmd_write_uncor), \
809 nvme_opcode_name(nvme_cmd_compare), \
810 nvme_opcode_name(nvme_cmd_write_zeroes), \
811 nvme_opcode_name(nvme_cmd_dsm), \
812 nvme_opcode_name(nvme_cmd_resv_register), \
813 nvme_opcode_name(nvme_cmd_resv_report), \
814 nvme_opcode_name(nvme_cmd_resv_acquire), \
4a407d5e
JT		 815 nvme_opcode_name(nvme_cmd_resv_release), \
816 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
817 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
818 nvme_opcode_name(nvme_cmd_zone_append))
819
26f2990d
MI		 820
821
eb793e2c
CH		 822/*
823 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
824 *
825 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
826 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 827 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 828 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
829 * request subtype
830 */
831enum {
832 NVME_SGL_FMT_ADDRESS = 0x00,
833 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 834 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 835 NVME_SGL_FMT_INVALIDATE = 0x0f,
836};
837
838/*
839 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
840 *
841 * For struct nvme_sgl_desc:
842 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
843 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
844 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
845 *
846 * For struct nvme_keyed_sgl_desc:
847 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 848 *
849 * Transport-specific SGL types:
850 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 851 */
852enum {
853 NVME_SGL_FMT_DATA_DESC = 0x00,
854 NVME_SGL_FMT_SEG_DESC = 0x02,
855 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
856 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 857 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 858};
859
860struct nvme_sgl_desc {
861 __le64 addr;
862 __le32 length;
863 __u8 rsvd[3];
864 __u8 type;
865};
866
867struct nvme_keyed_sgl_desc {
868 __le64 addr;
869 __u8 length[3];
870 __u8 key[4];
871 __u8 type;
872};
873
874union nvme_data_ptr {
875 struct {
876 __le64 prp1;
877 __le64 prp2;
878 };
879 struct nvme_sgl_desc sgl;
880 struct nvme_keyed_sgl_desc ksgl;
881};
882
3972be23
JS		 883/*
884 * Lowest two bits of our flags field (FUSE field in the spec):
885 *
886 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
887 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
888 *
889 * Highest two bits in our flags field (PSDT field in the spec):
890 *
891 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
892 * If used, MPTR contains addr of single physical buffer (byte aligned).
893 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
894 * If used, MPTR contains an address of an SGL segment containing
895 * exactly 1 SGL descriptor (qword aligned).
896 */
897enum {
898 NVME_CMD_FUSE_FIRST = (1 << 0),
899 NVME_CMD_FUSE_SECOND = (1 << 1),
900
901 NVME_CMD_SGL_METABUF = (1 << 6),
902 NVME_CMD_SGL_METASEG = (1 << 7),
903 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
904};
905
9d99a8dd
CH		 906struct nvme_common_command {
907 __u8 opcode;
908 __u8 flags;
909 __u16 command_id;
910 __le32 nsid;
911 __le32 cdw2[2];
912 __le64 metadata;
eb793e2c 913 union nvme_data_ptr dptr;
5c629dc9 914 struct_group(cdws,
b7c8f366
CK		 915 __le32 cdw10;
916 __le32 cdw11;
917 __le32 cdw12;
918 __le32 cdw13;
919 __le32 cdw14;
920 __le32 cdw15;
5c629dc9 921 );
9d99a8dd
CH		 922};
923
924struct nvme_rw_command {
925 __u8 opcode;
926 __u8 flags;
927 __u16 command_id;
928 __le32 nsid;
4020aad8
KB		 929 __le32 cdw2;
930 __le32 cdw3;
9d99a8dd 931 __le64 metadata;
eb793e2c 932 union nvme_data_ptr dptr;
9d99a8dd
CH		 933 __le64 slba;
934 __le16 length;
935 __le16 control;
936 __le32 dsmgmt;
937 __le32 reftag;
938 __le16 apptag;
939 __le16 appmask;
940};
941
942enum {
943 NVME_RW_LR = 1 << 15,
944 NVME_RW_FUA = 1 << 14,
240e6ee2 945 NVME_RW_APPEND_PIREMAP = 1 << 9,
9d99a8dd
CH		 946 NVME_RW_DSM_FREQ_UNSPEC = 0,
947 NVME_RW_DSM_FREQ_TYPICAL = 1,
948 NVME_RW_DSM_FREQ_RARE = 2,
949 NVME_RW_DSM_FREQ_READS = 3,
950 NVME_RW_DSM_FREQ_WRITES = 4,
951 NVME_RW_DSM_FREQ_RW = 5,
952 NVME_RW_DSM_FREQ_ONCE = 6,
953 NVME_RW_DSM_FREQ_PREFETCH = 7,
954 NVME_RW_DSM_FREQ_TEMP = 8,
955 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
956 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
957 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
958 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
959 NVME_RW_DSM_SEQ_REQ = 1 << 6,
960 NVME_RW_DSM_COMPRESSED = 1 << 7,
961 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
962 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
963 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
964 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 965 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 966};
967
968struct nvme_dsm_cmd {
969 __u8 opcode;
970 __u8 flags;
971 __u16 command_id;
972 __le32 nsid;
973 __u64 rsvd2[2];
eb793e2c 974 union nvme_data_ptr dptr;
9d99a8dd
CH		 975 __le32 nr;
976 __le32 attributes;
977 __u32 rsvd12[4];
978};
979
980enum {
981 NVME_DSMGMT_IDR = 1 << 0,
982 NVME_DSMGMT_IDW = 1 << 1,
983 NVME_DSMGMT_AD = 1 << 2,
984};
985
b35ba01e
CH		 986#define NVME_DSM_MAX_RANGES 256
987
9d99a8dd
CH		 988struct nvme_dsm_range {
989 __le32 cattr;
990 __le32 nlb;
991 __le64 slba;
992};
993
3b7c33b2
CK		 994struct nvme_write_zeroes_cmd {
995 __u8 opcode;
996 __u8 flags;
997 __u16 command_id;
998 __le32 nsid;
999 __u64 rsvd2;
1000 __le64 metadata;
1001 union nvme_data_ptr dptr;
1002 __le64 slba;
1003 __le16 length;
1004 __le16 control;
1005 __le32 dsmgmt;
1006 __le32 reftag;
1007 __le16 apptag;
1008 __le16 appmask;
1009};
1010
240e6ee2
KB		 1011enum nvme_zone_mgmt_action {
1012 NVME_ZONE_CLOSE = 0x1,
1013 NVME_ZONE_FINISH = 0x2,
1014 NVME_ZONE_OPEN = 0x3,
1015 NVME_ZONE_RESET = 0x4,
1016 NVME_ZONE_OFFLINE = 0x5,
1017 NVME_ZONE_SET_DESC_EXT = 0x10,
1018};
1019
1020struct nvme_zone_mgmt_send_cmd {
1021 __u8 opcode;
1022 __u8 flags;
1023 __u16 command_id;
1024 __le32 nsid;
1025 __le32 cdw2[2];
1026 __le64 metadata;
1027 union nvme_data_ptr dptr;
1028 __le64 slba;
1029 __le32 cdw12;
1030 __u8 zsa;
1031 __u8 select_all;
1032 __u8 rsvd13[2];
1033 __le32 cdw14[2];
1034};
1035
1036struct nvme_zone_mgmt_recv_cmd {
1037 __u8 opcode;
1038 __u8 flags;
1039 __u16 command_id;
1040 __le32 nsid;
1041 __le64 rsvd2[2];
1042 union nvme_data_ptr dptr;
1043 __le64 slba;
1044 __le32 numd;
1045 __u8 zra;
1046 __u8 zrasf;
1047 __u8 pr;
1048 __u8 rsvd13;
1049 __le32 cdw14[2];
1050};
1051
1052enum {
1053 NVME_ZRA_ZONE_REPORT = 0,
1054 NVME_ZRASF_ZONE_REPORT_ALL = 0,
aaf2e048
CK		 1055 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1056 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1057 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1058 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1059 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1060 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1061 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
240e6ee2
KB		 1062 NVME_REPORT_ZONE_PARTIAL = 1,
1063};
1064
c5552fde
AL		 1065/* Features */
1066
52deba0f
AM		 1067enum {
1068 NVME_TEMP_THRESH_MASK = 0xffff,
1069 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1070 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1071};
1072
c5552fde
AL		 1073struct nvme_feat_auto_pst {
1074 __le64 entries[32];
1075};
1076
39673e19
CH		 1077enum {
1078 NVME_HOST_MEM_ENABLE = (1 << 0),
1079 NVME_HOST_MEM_RETURN = (1 << 1),
1080};
1081
49cd84b6
KB		 1082struct nvme_feat_host_behavior {
1083 __u8 acre;
4020aad8
KB		 1084 __u8 etdas;
1085 __u8 lbafee;
1086 __u8 resv1[509];
49cd84b6
KB		 1087};
1088
1089enum {
1090 NVME_ENABLE_ACRE = 1,
4020aad8 1091 NVME_ENABLE_LBAFEE = 1,
49cd84b6
KB		 1092};
1093
9d99a8dd
CH		 1094/* Admin commands */
1095
1096enum nvme_admin_opcode {
1097 nvme_admin_delete_sq = 0x00,
1098 nvme_admin_create_sq = 0x01,
1099 nvme_admin_get_log_page = 0x02,
1100 nvme_admin_delete_cq = 0x04,
1101 nvme_admin_create_cq = 0x05,
1102 nvme_admin_identify = 0x06,
1103 nvme_admin_abort_cmd = 0x08,
1104 nvme_admin_set_features = 0x09,
1105 nvme_admin_get_features = 0x0a,
1106 nvme_admin_async_event = 0x0c,
a446c084 1107 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 1108 nvme_admin_activate_fw = 0x10,
1109 nvme_admin_download_fw = 0x11,
48c9e85b 1110 nvme_admin_dev_self_test = 0x14,
a446c084 1111 nvme_admin_ns_attach = 0x15,
7b89eae2 1112 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 1113 nvme_admin_directive_send = 0x19,
1114 nvme_admin_directive_recv = 0x1a,
48c9e85b
RR		 1115 nvme_admin_virtual_mgmt = 0x1c,
1116 nvme_admin_nvme_mi_send = 0x1d,
1117 nvme_admin_nvme_mi_recv = 0x1e,
f9f38e33 1118 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 1119 nvme_admin_format_nvm = 0x80,
1120 nvme_admin_security_send = 0x81,
1121 nvme_admin_security_recv = 0x82,
84fef62d 1122 nvme_admin_sanitize_nvm = 0x84,
c6389845 1123 nvme_admin_get_lba_status = 0x86,
c1fef73f 1124 nvme_admin_vendor_start = 0xC0,
9d99a8dd
CH		 1125};
1126
26f2990d
MI		 1127#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1128#define show_admin_opcode_name(val) \
1129 __print_symbolic(val, \
1130 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1131 nvme_admin_opcode_name(nvme_admin_create_sq), \
1132 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1133 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1134 nvme_admin_opcode_name(nvme_admin_create_cq), \
1135 nvme_admin_opcode_name(nvme_admin_identify), \
1136 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1137 nvme_admin_opcode_name(nvme_admin_set_features), \
1138 nvme_admin_opcode_name(nvme_admin_get_features), \
1139 nvme_admin_opcode_name(nvme_admin_async_event), \
1140 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1141 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1142 nvme_admin_opcode_name(nvme_admin_download_fw), \
1143 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1144 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1145 nvme_admin_opcode_name(nvme_admin_directive_send), \
1146 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1147 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1148 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1149 nvme_admin_opcode_name(nvme_admin_security_send), \
1150 nvme_admin_opcode_name(nvme_admin_security_recv), \
a5ef7572
MI		 1151 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1152 nvme_admin_opcode_name(nvme_admin_get_lba_status))
26f2990d 1153
9d99a8dd
CH		 1154enum {
1155 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1156 NVME_CQ_IRQ_ENABLED = (1 << 1),
1157 NVME_SQ_PRIO_URGENT = (0 << 1),
1158 NVME_SQ_PRIO_HIGH = (1 << 1),
1159 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1160 NVME_SQ_PRIO_LOW = (3 << 1),
1161 NVME_FEAT_ARBITRATION = 0x01,
1162 NVME_FEAT_POWER_MGMT = 0x02,
1163 NVME_FEAT_LBA_RANGE = 0x03,
1164 NVME_FEAT_TEMP_THRESH = 0x04,
1165 NVME_FEAT_ERR_RECOVERY = 0x05,
1166 NVME_FEAT_VOLATILE_WC = 0x06,
1167 NVME_FEAT_NUM_QUEUES = 0x07,
1168 NVME_FEAT_IRQ_COALESCE = 0x08,
1169 NVME_FEAT_IRQ_CONFIG = 0x09,
1170 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1171 NVME_FEAT_ASYNC_EVENT = 0x0b,
1172 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 1173 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 1174 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 1175 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 1176 NVME_FEAT_HCTM = 0x10,
1177 NVME_FEAT_NOPSC = 0x11,
1178 NVME_FEAT_RRL = 0x12,
1179 NVME_FEAT_PLM_CONFIG = 0x13,
1180 NVME_FEAT_PLM_WINDOW = 0x14,
49cd84b6 1181 NVME_FEAT_HOST_BEHAVIOR = 0x16,
48c9e85b 1182 NVME_FEAT_SANITIZE = 0x17,
9d99a8dd
CH		 1183 NVME_FEAT_SW_PROGRESS = 0x80,
1184 NVME_FEAT_HOST_ID = 0x81,
1185 NVME_FEAT_RESV_MASK = 0x82,
1186 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 1187 NVME_FEAT_WRITE_PROTECT = 0x84,
c1fef73f
LG		 1188 NVME_FEAT_VENDOR_START = 0xC0,
1189 NVME_FEAT_VENDOR_END = 0xFF,
9d99a8dd
CH		 1190 NVME_LOG_ERROR = 0x01,
1191 NVME_LOG_SMART = 0x02,
1192 NVME_LOG_FW_SLOT = 0x03,
b3984e06 1193 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 1194 NVME_LOG_CMD_EFFECTS = 0x05,
48c9e85b
RR		 1195 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1196 NVME_LOG_TELEMETRY_HOST = 0x07,
1197 NVME_LOG_TELEMETRY_CTRL = 0x08,
1198 NVME_LOG_ENDURANCE_GROUP = 0x09,
1a376216 1199 NVME_LOG_ANA = 0x0c,
eb793e2c 1200 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 1201 NVME_LOG_RESERVATION = 0x80,
1202 NVME_FWACT_REPL = (0 << 3),
1203 NVME_FWACT_REPL_ACTV = (1 << 3),
1204 NVME_FWACT_ACTV = (2 << 3),
1205};
1206
93045d59
CK		 1207/* NVMe Namespace Write Protect State */
1208enum {
1209 NVME_NS_NO_WRITE_PROTECT = 0,
1210 NVME_NS_WRITE_PROTECT,
1211 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1212 NVME_NS_WRITE_PROTECT_PERMANENT,
1213};
1214
b3984e06
CH		 1215#define NVME_MAX_CHANGED_NAMESPACES 1024
1216
9d99a8dd
CH		 1217struct nvme_identify {
1218 __u8 opcode;
1219 __u8 flags;
1220 __u16 command_id;
1221 __le32 nsid;
1222 __u64 rsvd2[2];
eb793e2c 1223 union nvme_data_ptr dptr;
986994a2
PP		 1224 __u8 cns;
1225 __u8 rsvd3;
1226 __le16 ctrlid;
71010c30
NC		 1227 __u8 rsvd11[3];
1228 __u8 csi;
1229 __u32 rsvd12[4];
9d99a8dd
CH		 1230};
1231
0add5e8e
JT		 1232#define NVME_IDENTIFY_DATA_SIZE 4096
1233
9d99a8dd
CH		 1234struct nvme_features {
1235 __u8 opcode;
1236 __u8 flags;
1237 __u16 command_id;
1238 __le32 nsid;
1239 __u64 rsvd2[2];
eb793e2c 1240 union nvme_data_ptr dptr;
9d99a8dd
CH		 1241 __le32 fid;
1242 __le32 dword11;
b85cf734
AD		 1243 __le32 dword12;
1244 __le32 dword13;
1245 __le32 dword14;
1246 __le32 dword15;
9d99a8dd
CH		 1247};
1248
39673e19
CH		 1249struct nvme_host_mem_buf_desc {
1250 __le64 addr;
1251 __le32 size;
1252 __u32 rsvd;
1253};
1254
9d99a8dd
CH		 1255struct nvme_create_cq {
1256 __u8 opcode;
1257 __u8 flags;
1258 __u16 command_id;
1259 __u32 rsvd1[5];
1260 __le64 prp1;
1261 __u64 rsvd8;
1262 __le16 cqid;
1263 __le16 qsize;
1264 __le16 cq_flags;
1265 __le16 irq_vector;
1266 __u32 rsvd12[4];
1267};
1268
1269struct nvme_create_sq {
1270 __u8 opcode;
1271 __u8 flags;
1272 __u16 command_id;
1273 __u32 rsvd1[5];
1274 __le64 prp1;
1275 __u64 rsvd8;
1276 __le16 sqid;
1277 __le16 qsize;
1278 __le16 sq_flags;
1279 __le16 cqid;
1280 __u32 rsvd12[4];
1281};
1282
1283struct nvme_delete_queue {
1284 __u8 opcode;
1285 __u8 flags;
1286 __u16 command_id;
1287 __u32 rsvd1[9];
1288 __le16 qid;
1289 __u16 rsvd10;
1290 __u32 rsvd11[5];
1291};
1292
1293struct nvme_abort_cmd {
1294 __u8 opcode;
1295 __u8 flags;
1296 __u16 command_id;
1297 __u32 rsvd1[9];
1298 __le16 sqid;
1299 __u16 cid;
1300 __u32 rsvd11[5];
1301};
1302
1303struct nvme_download_firmware {
1304 __u8 opcode;
1305 __u8 flags;
1306 __u16 command_id;
1307 __u32 rsvd1[5];
eb793e2c 1308 union nvme_data_ptr dptr;
9d99a8dd
CH		 1309 __le32 numd;
1310 __le32 offset;
1311 __u32 rsvd12[4];
1312};
1313
1314struct nvme_format_cmd {
1315 __u8 opcode;
1316 __u8 flags;
1317 __u16 command_id;
1318 __le32 nsid;
1319 __u64 rsvd2[4];
1320 __le32 cdw10;
1321 __u32 rsvd11[5];
1322};
1323
725b3588
AB		 1324struct nvme_get_log_page_command {
1325 __u8 opcode;
1326 __u8 flags;
1327 __u16 command_id;
1328 __le32 nsid;
1329 __u64 rsvd2[2];
eb793e2c 1330 union nvme_data_ptr dptr;
725b3588 1331 __u8 lid;
9b89bc38 1332 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 1333 __le16 numdl;
1334 __le16 numdu;
1335 __u16 rsvd11;
d808b7f7
KB		 1336 union {
1337 struct {
1338 __le32 lpol;
1339 __le32 lpou;
1340 };
1341 __le64 lpo;
1342 };
be93e87e
KB		 1343 __u8 rsvd14[3];
1344 __u8 csi;
1345 __u32 rsvd15;
725b3588
AB		 1346};
1347
f5d11840
JA		 1348struct nvme_directive_cmd {
1349 __u8 opcode;
1350 __u8 flags;
1351 __u16 command_id;
1352 __le32 nsid;
1353 __u64 rsvd2[2];
1354 union nvme_data_ptr dptr;
1355 __le32 numd;
1356 __u8 doper;
1357 __u8 dtype;
1358 __le16 dspec;
1359 __u8 endir;
1360 __u8 tdtype;
1361 __u16 rsvd15;
1362
1363 __u32 rsvd16[3];
1364};
1365
eb793e2c
CH		 1366/*
1367 * Fabrics subcommands.
1368 */
1369enum nvmf_fabrics_opcode {
1370 nvme_fabrics_command = 0x7f,
1371};
1372
1373enum nvmf_capsule_command {
1374 nvme_fabrics_type_property_set = 0x00,
1375 nvme_fabrics_type_connect = 0x01,
1376 nvme_fabrics_type_property_get = 0x04,
88b140fe
HR		 1377 nvme_fabrics_type_auth_send = 0x05,
1378 nvme_fabrics_type_auth_receive = 0x06,
eb793e2c
CH		 1379};
1380
ad795e47
MI		 1381#define nvme_fabrics_type_name(type) { type, #type }
1382#define show_fabrics_type_name(type) \
1383 __print_symbolic(type, \
1384 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1385 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
88b140fe
HR		 1386 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1387 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1388 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
ad795e47
MI		 1389
1390/*
1391 * If not fabrics command, fctype will be ignored.
1392 */
1393#define show_opcode_name(qid, opcode, fctype) \
1394 ((opcode) == nvme_fabrics_command ? \
1395 show_fabrics_type_name(fctype) : \
1396 ((qid) ? \
1397 show_nvm_opcode_name(opcode) : \
1398 show_admin_opcode_name(opcode)))
1399
eb793e2c
CH		 1400struct nvmf_common_command {
1401 __u8 opcode;
1402 __u8 resv1;
1403 __u16 command_id;
1404 __u8 fctype;
1405 __u8 resv2[35];
1406 __u8 ts[24];
1407};
1408
1409/*
1410 * The legal cntlid range a NVMe Target will provide.
1411 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1412 * Devices based on earlier specs did not have the subsystem concept;
1413 * therefore, those devices had their cntlid value set to 0 as a result.
1414 */
1415#define NVME_CNTLID_MIN 1
1416#define NVME_CNTLID_MAX 0xffef
1417#define NVME_CNTLID_DYNAMIC 0xffff
1418
1419#define MAX_DISC_LOGS 255
1420
785d584c
HR		 1421/* Discovery log page entry flags (EFLAGS): */
1422enum {
1423 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1424 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1425};
1426
eb793e2c
CH		 1427/* Discovery log page entry */
1428struct nvmf_disc_rsp_page_entry {
1429 __u8 trtype;
1430 __u8 adrfam;
a446c084 1431 __u8 subtype;
eb793e2c
CH		 1432 __u8 treq;
1433 __le16 portid;
1434 __le16 cntlid;
1435 __le16 asqsz;
785d584c
HR		 1436 __le16 eflags;
1437 __u8 resv10[20];
eb793e2c
CH		 1438 char trsvcid[NVMF_TRSVCID_SIZE];
1439 __u8 resv64[192];
1440 char subnqn[NVMF_NQN_FIELD_LEN];
1441 char traddr[NVMF_TRADDR_SIZE];
1442 union tsas {
1443 char common[NVMF_TSAS_SIZE];
1444 struct rdma {
1445 __u8 qptype;
1446 __u8 prtype;
1447 __u8 cms;
1448 __u8 resv3[5];
1449 __u16 pkey;
1450 __u8 resv10[246];
1451 } rdma;
1452 } tsas;
1453};
1454
1455/* Discovery log page header */
1456struct nvmf_disc_rsp_page_hdr {
1457 __le64 genctr;
1458 __le64 numrec;
1459 __le16 recfmt;
1460 __u8 resv14[1006];
f1e71d75 1461 struct nvmf_disc_rsp_page_entry entries[];
eb793e2c
CH		 1462};
1463
e6a622fd
SG		 1464enum {
1465 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1466};
1467
eb793e2c
CH		 1468struct nvmf_connect_command {
1469 __u8 opcode;
1470 __u8 resv1;
1471 __u16 command_id;
1472 __u8 fctype;
1473 __u8 resv2[19];
1474 union nvme_data_ptr dptr;
1475 __le16 recfmt;
1476 __le16 qid;
1477 __le16 sqsize;
1478 __u8 cattr;
1479 __u8 resv3;
1480 __le32 kato;
1481 __u8 resv4[12];
1482};
1483
88b140fe
HR		 1484enum {
1485 NVME_CONNECT_AUTHREQ_ASCR = (1 << 2),
1486 NVME_CONNECT_AUTHREQ_ATR = (1 << 1),
1487};
1488
eb793e2c 1489struct nvmf_connect_data {
8e412263 1490 uuid_t hostid;
eb793e2c
CH		 1491 __le16 cntlid;
1492 char resv4[238];
1493 char subsysnqn[NVMF_NQN_FIELD_LEN];
1494 char hostnqn[NVMF_NQN_FIELD_LEN];
1495 char resv5[256];
1496};
1497
1498struct nvmf_property_set_command {
1499 __u8 opcode;
1500 __u8 resv1;
1501 __u16 command_id;
1502 __u8 fctype;
1503 __u8 resv2[35];
1504 __u8 attrib;
1505 __u8 resv3[3];
1506 __le32 offset;
1507 __le64 value;
1508 __u8 resv4[8];
1509};
1510
1511struct nvmf_property_get_command {
1512 __u8 opcode;
1513 __u8 resv1;
1514 __u16 command_id;
1515 __u8 fctype;
1516 __u8 resv2[35];
1517 __u8 attrib;
1518 __u8 resv3[3];
1519 __le32 offset;
1520 __u8 resv4[16];
1521};
1522
88b140fe
HR		 1523struct nvmf_auth_common_command {
1524 __u8 opcode;
1525 __u8 resv1;
1526 __u16 command_id;
1527 __u8 fctype;
1528 __u8 resv2[19];
1529 union nvme_data_ptr dptr;
1530 __u8 resv3;
1531 __u8 spsp0;
1532 __u8 spsp1;
1533 __u8 secp;
1534 __le32 al_tl;
1535 __u8 resv4[16];
1536};
1537
1538struct nvmf_auth_send_command {
1539 __u8 opcode;
1540 __u8 resv1;
1541 __u16 command_id;
1542 __u8 fctype;
1543 __u8 resv2[19];
1544 union nvme_data_ptr dptr;
1545 __u8 resv3;
1546 __u8 spsp0;
1547 __u8 spsp1;
1548 __u8 secp;
1549 __le32 tl;
1550 __u8 resv4[16];
1551};
1552
1553struct nvmf_auth_receive_command {
1554 __u8 opcode;
1555 __u8 resv1;
1556 __u16 command_id;
1557 __u8 fctype;
1558 __u8 resv2[19];
1559 union nvme_data_ptr dptr;
1560 __u8 resv3;
1561 __u8 spsp0;
1562 __u8 spsp1;
1563 __u8 secp;
1564 __le32 al;
1565 __u8 resv4[16];
1566};
1567
1568/* Value for secp */
1569enum {
1570 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1571};
1572
1573/* Defined value for auth_type */
1574enum {
1575 NVME_AUTH_COMMON_MESSAGES = 0x00,
1576 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1577};
1578
1579/* Defined messages for auth_id */
1580enum {
1581 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1582 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1583 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1584 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1585 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1586 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1587 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1588};
1589
1590struct nvmf_auth_dhchap_protocol_descriptor {
1591 __u8 authid;
1592 __u8 rsvd;
1593 __u8 halen;
1594 __u8 dhlen;
1595 __u8 idlist[60];
1596};
1597
1598enum {
1599 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1600};
1601
1602/* Defined hash functions for DH-HMAC-CHAP authentication */
1603enum {
1604 NVME_AUTH_HASH_SHA256 = 0x01,
1605 NVME_AUTH_HASH_SHA384 = 0x02,
1606 NVME_AUTH_HASH_SHA512 = 0x03,
1607 NVME_AUTH_HASH_INVALID = 0xff,
1608};
1609
1610/* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1611enum {
1612 NVME_AUTH_DHGROUP_NULL = 0x00,
1613 NVME_AUTH_DHGROUP_2048 = 0x01,
1614 NVME_AUTH_DHGROUP_3072 = 0x02,
1615 NVME_AUTH_DHGROUP_4096 = 0x03,
1616 NVME_AUTH_DHGROUP_6144 = 0x04,
1617 NVME_AUTH_DHGROUP_8192 = 0x05,
1618 NVME_AUTH_DHGROUP_INVALID = 0xff,
1619};
1620
1621union nvmf_auth_protocol {
1622 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1623};
1624
1625struct nvmf_auth_dhchap_negotiate_data {
1626 __u8 auth_type;
1627 __u8 auth_id;
1628 __le16 rsvd;
1629 __le16 t_id;
1630 __u8 sc_c;
1631 __u8 napd;
1632 union nvmf_auth_protocol auth_protocol[];
1633};
1634
1635struct nvmf_auth_dhchap_challenge_data {
1636 __u8 auth_type;
1637 __u8 auth_id;
1638 __u16 rsvd1;
1639 __le16 t_id;
1640 __u8 hl;
1641 __u8 rsvd2;
1642 __u8 hashid;
1643 __u8 dhgid;
1644 __le16 dhvlen;
1645 __le32 seqnum;
1646 /* 'hl' bytes of challenge value */
1647 __u8 cval[];
1648 /* followed by 'dhvlen' bytes of DH value */
1649};
1650
1651struct nvmf_auth_dhchap_reply_data {
1652 __u8 auth_type;
1653 __u8 auth_id;
1654 __le16 rsvd1;
1655 __le16 t_id;
1656 __u8 hl;
1657 __u8 rsvd2;
1658 __u8 cvalid;
1659 __u8 rsvd3;
1660 __le16 dhvlen;
1661 __le32 seqnum;
1662 /* 'hl' bytes of response data */
1663 __u8 rval[];
1664 /* followed by 'hl' bytes of Challenge value */
1665 /* followed by 'dhvlen' bytes of DH value */
1666};
1667
1668enum {
1669 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1670};
1671
1672struct nvmf_auth_dhchap_success1_data {
1673 __u8 auth_type;
1674 __u8 auth_id;
1675 __le16 rsvd1;
1676 __le16 t_id;
1677 __u8 hl;
1678 __u8 rsvd2;
1679 __u8 rvalid;
1680 __u8 rsvd3[7];
1681 /* 'hl' bytes of response value if 'rvalid' is set */
1682 __u8 rval[];
1683};
1684
1685struct nvmf_auth_dhchap_success2_data {
1686 __u8 auth_type;
1687 __u8 auth_id;
1688 __le16 rsvd1;
1689 __le16 t_id;
1690 __u8 rsvd2[10];
1691};
1692
1693struct nvmf_auth_dhchap_failure_data {
1694 __u8 auth_type;
1695 __u8 auth_id;
1696 __le16 rsvd1;
1697 __le16 t_id;
1698 __u8 rescode;
1699 __u8 rescode_exp;
1700};
1701
1702enum {
1703 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1704};
1705
1706enum {
1707 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1708 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1709 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1710 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1711 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1712 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1713 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1714};
1715
1716
f9f38e33
HK		 1717struct nvme_dbbuf {
1718 __u8 opcode;
1719 __u8 flags;
1720 __u16 command_id;
1721 __u32 rsvd1[5];
1722 __le64 prp1;
1723 __le64 prp2;
1724 __u32 rsvd12[6];
1725};
1726
f5d11840 1727struct streams_directive_params {
dc1a0afb
CH		 1728 __le16 msl;
1729 __le16 nssa;
1730 __le16 nsso;
f5d11840 1731 __u8 rsvd[10];
dc1a0afb
CH		 1732 __le32 sws;
1733 __le16 sgs;
1734 __le16 nsa;
1735 __le16 nso;
f5d11840
JA		 1736 __u8 rsvd2[6];
1737};
1738
9d99a8dd
CH		 1739struct nvme_command {
1740 union {
1741 struct nvme_common_command common;
1742 struct nvme_rw_command rw;
1743 struct nvme_identify identify;
1744 struct nvme_features features;
1745 struct nvme_create_cq create_cq;
1746 struct nvme_create_sq create_sq;
1747 struct nvme_delete_queue delete_queue;
1748 struct nvme_download_firmware dlfw;
1749 struct nvme_format_cmd format;
1750 struct nvme_dsm_cmd dsm;
3b7c33b2 1751 struct nvme_write_zeroes_cmd write_zeroes;
240e6ee2
KB		 1752 struct nvme_zone_mgmt_send_cmd zms;
1753 struct nvme_zone_mgmt_recv_cmd zmr;
9d99a8dd 1754 struct nvme_abort_cmd abort;
725b3588 1755 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1756 struct nvmf_common_command fabrics;
1757 struct nvmf_connect_command connect;
1758 struct nvmf_property_set_command prop_set;
1759 struct nvmf_property_get_command prop_get;
88b140fe
HR		 1760 struct nvmf_auth_common_command auth_common;
1761 struct nvmf_auth_send_command auth_send;
1762 struct nvmf_auth_receive_command auth_receive;
f9f38e33 1763 struct nvme_dbbuf dbbuf;
f5d11840 1764 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1765 };
1766};
1767
7a1f46e3
MI		 1768static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1769{
1770 return cmd->common.opcode == nvme_fabrics_command;
1771}
1772
b34de7ce
CK		 1773struct nvme_error_slot {
1774 __le64 error_count;
1775 __le16 sqid;
1776 __le16 cmdid;
1777 __le16 status_field;
1778 __le16 param_error_location;
1779 __le64 lba;
1780 __le32 nsid;
1781 __u8 vs;
1782 __u8 resv[3];
1783 __le64 cs;
1784 __u8 resv2[24];
1785};
1786
7a5abb4b
CH		 1787static inline bool nvme_is_write(struct nvme_command *cmd)
1788{
eb793e2c
CH		 1789 /*
1790 * What a mess...
1791 *
1792 * Why can't we simply have a Fabrics In and Fabrics out command?
1793 */
7a1f46e3 1794 if (unlikely(nvme_is_fabrics(cmd)))
2fd4167f 1795 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1796 return cmd->common.opcode & 1;
1797}
1798
9d99a8dd 1799enum {
eb793e2c
CH		 1800 /*
1801 * Generic Command Status:
1802 */
9d99a8dd
CH		 1803 NVME_SC_SUCCESS = 0x0,
1804 NVME_SC_INVALID_OPCODE = 0x1,
1805 NVME_SC_INVALID_FIELD = 0x2,
1806 NVME_SC_CMDID_CONFLICT = 0x3,
1807 NVME_SC_DATA_XFER_ERROR = 0x4,
1808 NVME_SC_POWER_LOSS = 0x5,
1809 NVME_SC_INTERNAL = 0x6,
1810 NVME_SC_ABORT_REQ = 0x7,
1811 NVME_SC_ABORT_QUEUE = 0x8,
1812 NVME_SC_FUSED_FAIL = 0x9,
1813 NVME_SC_FUSED_MISSING = 0xa,
1814 NVME_SC_INVALID_NS = 0xb,
1815 NVME_SC_CMD_SEQ_ERROR = 0xc,
1816 NVME_SC_SGL_INVALID_LAST = 0xd,
1817 NVME_SC_SGL_INVALID_COUNT = 0xe,
1818 NVME_SC_SGL_INVALID_DATA = 0xf,
1819 NVME_SC_SGL_INVALID_METADATA = 0x10,
1820 NVME_SC_SGL_INVALID_TYPE = 0x11,
3254899e
MG		 1821 NVME_SC_CMB_INVALID_USE = 0x12,
1822 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1823 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1824 NVME_SC_OP_DENIED = 0x15,
eb793e2c 1825 NVME_SC_SGL_INVALID_OFFSET = 0x16,
3254899e
MG		 1826 NVME_SC_RESERVED = 0x17,
1827 NVME_SC_HOST_ID_INCONSIST = 0x18,
1828 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1829 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1830 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
48c9e85b
RR		 1831 NVME_SC_SANITIZE_FAILED = 0x1C,
1832 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
3254899e
MG		 1833 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1834 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
93045d59 1835 NVME_SC_NS_WRITE_PROTECTED = 0x20,
48c9e85b 1836 NVME_SC_CMD_INTERRUPTED = 0x21,
3254899e 1837 NVME_SC_TRANSIENT_TR_ERR = 0x22,
354201c5 1838 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
ab5d0b38 1839 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
93045d59 1840
9d99a8dd
CH		 1841 NVME_SC_LBA_RANGE = 0x80,
1842 NVME_SC_CAP_EXCEEDED = 0x81,
1843 NVME_SC_NS_NOT_READY = 0x82,
1844 NVME_SC_RESERVATION_CONFLICT = 0x83,
3254899e 1845 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
eb793e2c
CH		 1846
1847 /*
1848 * Command Specific Status:
1849 */
9d99a8dd
CH		 1850 NVME_SC_CQ_INVALID = 0x100,
1851 NVME_SC_QID_INVALID = 0x101,
1852 NVME_SC_QUEUE_SIZE = 0x102,
1853 NVME_SC_ABORT_LIMIT = 0x103,
1854 NVME_SC_ABORT_MISSING = 0x104,
1855 NVME_SC_ASYNC_LIMIT = 0x105,
1856 NVME_SC_FIRMWARE_SLOT = 0x106,
1857 NVME_SC_FIRMWARE_IMAGE = 0x107,
1858 NVME_SC_INVALID_VECTOR = 0x108,
1859 NVME_SC_INVALID_LOG_PAGE = 0x109,
1860 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1861 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1862 NVME_SC_INVALID_QUEUE = 0x10c,
1863 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1864 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1865 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1866 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1867 NVME_SC_FW_NEEDS_RESET = 0x111,
1868 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
9581ae4f 1869 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
a446c084 1870 NVME_SC_OVERLAPPING_RANGE = 0x114,
9581ae4f 1871 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
a446c084
CH		 1872 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1873 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1874 NVME_SC_NS_IS_PRIVATE = 0x119,
1875 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1876 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1877 NVME_SC_CTRL_LIST_INVALID = 0x11c,
3254899e 1878 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
48c9e85b 1879 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
3254899e
MG		 1880 NVME_SC_CTRL_ID_INVALID = 0x11f,
1881 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1882 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1883 NVME_SC_RES_ID_INVALID = 0x122,
48c9e85b 1884 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
3254899e
MG		 1885 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1886 NVME_SC_ANA_ATTACH_FAILED = 0x125,
eb793e2c
CH		 1887
1888 /*
1889 * I/O Command Set Specific - NVM commands:
1890 */
9d99a8dd
CH		 1891 NVME_SC_BAD_ATTRIBUTES = 0x180,
1892 NVME_SC_INVALID_PI = 0x181,
1893 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1894 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1895
1896 /*
1897 * I/O Command Set Specific - Fabrics commands:
1898 */
1899 NVME_SC_CONNECT_FORMAT = 0x180,
1900 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1901 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1902 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1903 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1904
1905 NVME_SC_DISCOVERY_RESTART = 0x190,
1906 NVME_SC_AUTH_REQUIRED = 0x191,
1907
240e6ee2
KB		 1908 /*
1909 * I/O Command Set Specific - Zoned commands:
1910 */
1911 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1912 NVME_SC_ZONE_FULL = 0x1b9,
1913 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1914 NVME_SC_ZONE_OFFLINE = 0x1bb,
1915 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1916 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1917 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1918 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1919
eb793e2c
CH		 1920 /*
1921 * Media and Data Integrity Errors:
1922 */
9d99a8dd
CH		 1923 NVME_SC_WRITE_FAULT = 0x280,
1924 NVME_SC_READ_ERROR = 0x281,
1925 NVME_SC_GUARD_CHECK = 0x282,
1926 NVME_SC_APPTAG_CHECK = 0x283,
1927 NVME_SC_REFTAG_CHECK = 0x284,
1928 NVME_SC_COMPARE_FAILED = 0x285,
1929 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1930 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1931
1a376216
CH		 1932 /*
1933 * Path-related Errors:
1934 */
ca2d8992 1935 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1a376216
CH		 1936 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1937 NVME_SC_ANA_INACCESSIBLE = 0x302,
1938 NVME_SC_ANA_TRANSITION = 0x303,
ca2d8992 1939 NVME_SC_CTRL_PATH_ERROR = 0x360,
783f4a44 1940 NVME_SC_HOST_PATH_ERROR = 0x370,
2dc3947b 1941 NVME_SC_HOST_ABORTED_CMD = 0x371,
1a376216 1942
49cd84b6 1943 NVME_SC_CRD = 0x1800,
bd83fe6f 1944 NVME_SC_MORE = 0x2000,
9d99a8dd
CH		 1945 NVME_SC_DNR = 0x4000,
1946};
1947
1948struct nvme_completion {
eb793e2c
CH		 1949 /*
1950 * Used by Admin and Fabrics commands to return data:
1951 */
d49187e9
CH		 1952 union nvme_result {
1953 __le16 u16;
1954 __le32 u32;
1955 __le64 u64;
1956 } result;
9d99a8dd
CH		 1957 __le16 sq_head; /* how much of this queue may be reclaimed */
1958 __le16 sq_id; /* submission queue that generated this entry */
1959 __u16 command_id; /* of the command which completed */
1960 __le16 status; /* did the command fail, and if so, why? */
1961};
1962
8ef2074d
GKB		 1963#define NVME_VS(major, minor, tertiary) \
1964 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1965
c61d788b
JT		 1966#define NVME_MAJOR(ver) ((ver) >> 16)
1967#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1968#define NVME_TERTIARY(ver) ((ver) & 0xff)
1969
b60503ba 1970#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)