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sysctl: add and use base directory declarer and registration helper
[linux-block.git] / include / linux / nvme.h
CommitLineData
fadccd8f 1/* SPDX-License-Identifier: GPL-2.0 */
b60503ba
MW		 2/*
3 * Definitions for the NVM Express interface
8757ad65 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
2812dfe3 10#include <linux/types.h>
8e412263 11#include <linux/uuid.h>
eb793e2c
CH		 12
13/* NQN names in commands fields specified one size */
14#define NVMF_NQN_FIELD_LEN 256
15
16/* However the max length of a qualified name is another size */
17#define NVMF_NQN_SIZE 223
18
19#define NVMF_TRSVCID_SIZE 32
20#define NVMF_TRADDR_SIZE 256
21#define NVMF_TSAS_SIZE 256
22
23#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
24
25#define NVME_RDMA_IP_PORT 4420
26
62346eae
AD		 27#define NVME_NSID_ALL 0xffffffff
28
eb793e2c 29enum nvme_subsys_type {
785d584c
HR		 30 /* Referral to another discovery type target subsystem */
31 NVME_NQN_DISC = 1,
32
33 /* NVME type target subsystem */
34 NVME_NQN_NVME = 2,
35
36 /* Current discovery type target subsystem */
37 NVME_NQN_CURR = 3,
eb793e2c
CH		 38};
39
e15a8a97
HR		 40enum nvme_ctrl_type {
41 NVME_CTRL_IO = 1, /* I/O controller */
42 NVME_CTRL_DISC = 2, /* Discovery controller */
43 NVME_CTRL_ADMIN = 3, /* Administrative controller */
44};
45
eb793e2c
CH		 46/* Address Family codes for Discovery Log Page entry ADRFAM field */
47enum {
48 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
49 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
50 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
51 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
52 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
d02abd19
CK		 53 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
54 NVMF_ADDR_FAMILY_MAX,
eb793e2c
CH		 55};
56
57/* Transport Type codes for Discovery Log Page entry TRTYPE field */
58enum {
59 NVMF_TRTYPE_RDMA = 1, /* RDMA */
60 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
fc221d05 61 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
eb793e2c
CH		 62 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
63 NVMF_TRTYPE_MAX,
64};
65
66/* Transport Requirements codes for Discovery Log Page entry TREQ field */
67enum {
9b95d2fb
SG		 68 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
69 NVMF_TREQ_REQUIRED = 1, /* Required */
70 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 71#define NVME_TREQ_SECURE_CHANNEL_MASK \
72 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
9b95d2fb
SG		 73
74 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
eb793e2c
CH		 75};
76
77/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
78 * RDMA_QPTYPE field
79 */
80enum {
bf17aa36
RD		 81 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
82 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 83};
84
85/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88enum {
bf17aa36
RD		 89 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
90 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
91 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
92 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
93 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 94};
95
96/* RDMA Connection Management Service Type codes for Discovery Log Page
97 * entry TSAS RDMA_CMS field
98 */
99enum {
bf17aa36 100 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 101};
102
7aa1f427 103#define NVME_AQ_DEPTH 32
38dabe21
KB		 104#define NVME_NR_AEN_COMMANDS 1
105#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
106
107/*
108 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
109 * NVM-Express 1.2 specification, section 4.1.2.
110 */
111#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 112
7a67cbea
CH		 113enum {
114 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
115 NVME_REG_VS = 0x0008, /* Version */
116 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 117 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 118 NVME_REG_CC = 0x0014, /* Controller Configuration */
119 NVME_REG_CSTS = 0x001c, /* Controller Status */
120 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
121 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
122 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 123 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
48c9e85b 124 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
7a67cbea 125 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
48c9e85b
RR		 126 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
127 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
128 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
129 * Location
130 */
20d3bb92
KJ		 131 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
132 * Space Control
133 */
48c9e85b
RR		 134 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
135 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
136 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
137 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
138 * Buffer Size
139 */
140 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
141 * Write Throughput
142 */
97f6ef64 143 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 144};
145
a0cadb85 146#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 147#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 148#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 149#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
71010c30 150#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
8fc23e03 151#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 152#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
20d3bb92 153#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
22605f96 154
8ffaadf7
JD		 155#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
156#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598
CH		 157
158enum {
159 NVME_CMBSZ_SQS = 1 << 0,
160 NVME_CMBSZ_CQS = 1 << 1,
161 NVME_CMBSZ_LISTS = 1 << 2,
162 NVME_CMBSZ_RDS = 1 << 3,
163 NVME_CMBSZ_WDS = 1 << 4,
164
165 NVME_CMBSZ_SZ_SHIFT = 12,
166 NVME_CMBSZ_SZ_MASK = 0xfffff,
167
168 NVME_CMBSZ_SZU_SHIFT = 8,
169 NVME_CMBSZ_SZU_MASK = 0xf,
170};
8ffaadf7 171
69cd27e2
CH		 172/*
173 * Submission and Completion Queue Entry Sizes for the NVM command set.
174 * (In bytes and specified as a power of two (2^n)).
175 */
c1e0cc7e 176#define NVME_ADM_SQES 6
69cd27e2
CH		 177#define NVME_NVM_IOSQES 6
178#define NVME_NVM_IOCQES 4
179
b60503ba
MW		 180enum {
181 NVME_CC_ENABLE = 1 << 0,
ad4e05b2
MG		 182 NVME_CC_EN_SHIFT = 0,
183 NVME_CC_CSS_SHIFT = 4,
b60503ba 184 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 185 NVME_CC_AMS_SHIFT = 11,
186 NVME_CC_SHN_SHIFT = 14,
187 NVME_CC_IOSQES_SHIFT = 16,
188 NVME_CC_IOCQES_SHIFT = 20,
71010c30
NC		 189 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
190 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
191 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
60b43f62
MG		 192 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
193 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
194 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 195 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
196 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
197 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
198 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
199 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
200 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
71010c30
NC		 201 NVME_CAP_CSS_NVM = 1 << 0,
202 NVME_CAP_CSS_CSI = 1 << 6,
b60503ba
MW		 203 NVME_CSTS_RDY = 1 << 0,
204 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 205 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 206 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 207 NVME_CSTS_SHST_NORMAL = 0 << 2,
208 NVME_CSTS_SHST_OCCUR = 1 << 2,
209 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 210 NVME_CSTS_SHST_MASK = 3 << 2,
20d3bb92
KJ		 211 NVME_CMBMSC_CRE = 1 << 0,
212 NVME_CMBMSC_CMSE = 1 << 1,
b60503ba
MW		 213};
214
9d99a8dd
CH		 215struct nvme_id_power_state {
216 __le16 max_power; /* centiwatts */
217 __u8 rsvd2;
218 __u8 flags;
219 __le32 entry_lat; /* microseconds */
220 __le32 exit_lat; /* microseconds */
221 __u8 read_tput;
222 __u8 read_lat;
223 __u8 write_tput;
224 __u8 write_lat;
225 __le16 idle_power;
226 __u8 idle_scale;
227 __u8 rsvd19;
228 __le16 active_power;
229 __u8 active_work_scale;
230 __u8 rsvd23[9];
231};
232
233enum {
234 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
235 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
236};
237
12b21171
SG		 238enum nvme_ctrl_attr {
239 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 240 NVME_CTRL_ATTR_TBKAS = (1 << 6),
12b21171
SG		 241};
242
9d99a8dd
CH		 243struct nvme_id_ctrl {
244 __le16 vid;
245 __le16 ssvid;
246 char sn[20];
247 char mn[40];
248 char fr[8];
249 __u8 rab;
250 __u8 ieee[3];
a446c084 251 __u8 cmic;
9d99a8dd 252 __u8 mdts;
08c69640
CH		 253 __le16 cntlid;
254 __le32 ver;
14e974a8
CH		 255 __le32 rtd3r;
256 __le32 rtd3e;
257 __le32 oaes;
eb793e2c 258 __le32 ctratt;
e15a8a97
HR		 259 __u8 rsvd100[11];
260 __u8 cntrltype;
261 __u8 fguid[16];
49cd84b6
KB		 262 __le16 crdt1;
263 __le16 crdt2;
264 __le16 crdt3;
265 __u8 rsvd134[122];
9d99a8dd
CH		 266 __le16 oacs;
267 __u8 acl;
268 __u8 aerl;
269 __u8 frmw;
270 __u8 lpa;
271 __u8 elpe;
272 __u8 npss;
273 __u8 avscc;
274 __u8 apsta;
275 __le16 wctemp;
276 __le16 cctemp;
a446c084
CH		 277 __le16 mtfa;
278 __le32 hmpre;
279 __le32 hmmin;
280 __u8 tnvmcap[16];
281 __u8 unvmcap[16];
282 __le32 rpmbs;
435e8090
GJ		 283 __le16 edstt;
284 __u8 dsto;
285 __u8 fwug;
7b89eae2 286 __le16 kas;
435e8090
GJ		 287 __le16 hctma;
288 __le16 mntmt;
289 __le16 mxtmt;
290 __le32 sanicap;
044a9df1
CH		 291 __le32 hmminds;
292 __le16 hmmaxd;
1a376216
CH		 293 __u8 rsvd338[4];
294 __u8 anatt;
295 __u8 anacap;
296 __le32 anagrpmax;
297 __le32 nanagrpid;
298 __u8 rsvd352[160];
9d99a8dd
CH		 299 __u8 sqes;
300 __u8 cqes;
eb793e2c 301 __le16 maxcmd;
9d99a8dd
CH		 302 __le32 nn;
303 __le16 oncs;
304 __le16 fuses;
305 __u8 fna;
306 __u8 vwc;
307 __le16 awun;
308 __le16 awupf;
309 __u8 nvscc;
93045d59 310 __u8 nwpc;
9d99a8dd
CH		 311 __le16 acwu;
312 __u8 rsvd534[2];
313 __le32 sgls;
1a376216
CH		 314 __le32 mnan;
315 __u8 rsvd544[224];
eb793e2c
CH		 316 char subnqn[256];
317 __u8 rsvd1024[768];
318 __le32 ioccsz;
319 __le32 iorcsz;
320 __le16 icdoff;
321 __u8 ctrattr;
322 __u8 msdbd;
323 __u8 rsvd1804[244];
9d99a8dd
CH		 324 struct nvme_id_power_state psd[32];
325 __u8 vs[1024];
326};
327
328enum {
d56ae18f 329 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
92decf11
KB		 330 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
331 NVME_CTRL_CMIC_ANA = 1 << 3,
9d99a8dd
CH		 332 NVME_CTRL_ONCS_COMPARE = 1 << 0,
333 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
334 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 335 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
c1fef73f 336 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
dbf86b39 337 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 338 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 339 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f5d11840 340 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 341 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 342 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
48c9e85b
RR		 343 NVME_CTRL_CTRATT_128_ID = 1 << 0,
344 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
345 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
346 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
347 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
348 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
349 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
350 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
9d99a8dd
CH		 351};
352
353struct nvme_lbaf {
354 __le16 ms;
355 __u8 ds;
356 __u8 rp;
357};
358
359struct nvme_id_ns {
360 __le64 nsze;
361 __le64 ncap;
362 __le64 nuse;
363 __u8 nsfeat;
364 __u8 nlbaf;
365 __u8 flbas;
366 __u8 mc;
367 __u8 dpc;
368 __u8 dps;
369 __u8 nmic;
370 __u8 rescap;
371 __u8 fpi;
6605bdd5 372 __u8 dlfeat;
9d99a8dd
CH		 373 __le16 nawun;
374 __le16 nawupf;
375 __le16 nacwu;
376 __le16 nabsn;
377 __le16 nabo;
378 __le16 nabspf;
6b8190d6 379 __le16 noiob;
a446c084 380 __u8 nvmcap[16];
6605bdd5
BVA		 381 __le16 npwg;
382 __le16 npwa;
383 __le16 npdg;
384 __le16 npda;
385 __le16 nows;
386 __u8 rsvd74[18];
1a376216 387 __le32 anagrpid;
93045d59
CK		 388 __u8 rsvd96[3];
389 __u8 nsattr;
6605bdd5
BVA		 390 __le16 nvmsetid;
391 __le16 endgid;
9d99a8dd
CH		 392 __u8 nguid[16];
393 __u8 eui64[8];
394 struct nvme_lbaf lbaf[16];
395 __u8 rsvd192[192];
396 __u8 vs[3712];
397};
398
240e6ee2
KB		 399struct nvme_zns_lbafe {
400 __le64 zsze;
401 __u8 zdes;
402 __u8 rsvd9[7];
403};
404
405struct nvme_id_ns_zns {
406 __le16 zoc;
407 __le16 ozcs;
408 __le32 mar;
409 __le32 mor;
410 __le32 rrl;
411 __le32 frl;
412 __u8 rsvd20[2796];
413 struct nvme_zns_lbafe lbafe[16];
414 __u8 rsvd3072[768];
415 __u8 vs[256];
416};
417
418struct nvme_id_ctrl_zns {
419 __u8 zasl;
420 __u8 rsvd1[4095];
421};
422
5befc7c2
KB		 423struct nvme_id_ctrl_nvm {
424 __u8 vsl;
425 __u8 wzsl;
426 __u8 wusl;
427 __u8 dmrl;
428 __le32 dmrsl;
429 __le64 dmsl;
430 __u8 rsvd16[4080];
431};
432
329dd768
CH		 433enum {
434 NVME_ID_CNS_NS = 0x00,
435 NVME_ID_CNS_CTRL = 0x01,
436 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 437 NVME_ID_CNS_NS_DESC_LIST = 0x03,
71010c30
NC		 438 NVME_ID_CNS_CS_NS = 0x05,
439 NVME_ID_CNS_CS_CTRL = 0x06,
329dd768
CH		 440 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
441 NVME_ID_CNS_NS_PRESENT = 0x11,
442 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
443 NVME_ID_CNS_CTRL_LIST = 0x13,
48c9e85b
RR		 444 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
445 NVME_ID_CNS_NS_GRANULARITY = 0x16,
446 NVME_ID_CNS_UUID_LIST = 0x17,
329dd768
CH		 447};
448
71010c30
NC		 449enum {
450 NVME_CSI_NVM = 0,
240e6ee2 451 NVME_CSI_ZNS = 2,
71010c30
NC		 452};
453
f5d11840
JA		 454enum {
455 NVME_DIR_IDENTIFY = 0x00,
456 NVME_DIR_STREAMS = 0x01,
457 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
458 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
459 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
460 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
461 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
462 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
463 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
464 NVME_DIR_ENDIR = 0x01,
465};
466
9d99a8dd
CH		 467enum {
468 NVME_NS_FEAT_THIN = 1 << 0,
92decf11
KB		 469 NVME_NS_FEAT_ATOMICS = 1 << 1,
470 NVME_NS_FEAT_IO_OPT = 1 << 4,
471 NVME_NS_ATTR_RO = 1 << 0,
9d99a8dd
CH		 472 NVME_NS_FLBAS_LBA_MASK = 0xf,
473 NVME_NS_FLBAS_META_EXT = 0x10,
92decf11 474 NVME_NS_NMIC_SHARED = 1 << 0,
9d99a8dd
CH		 475 NVME_LBAF_RP_BEST = 0,
476 NVME_LBAF_RP_BETTER = 1,
477 NVME_LBAF_RP_GOOD = 2,
478 NVME_LBAF_RP_DEGRADED = 3,
479 NVME_NS_DPC_PI_LAST = 1 << 4,
480 NVME_NS_DPC_PI_FIRST = 1 << 3,
481 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
482 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
483 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
484 NVME_NS_DPS_PI_FIRST = 1 << 3,
485 NVME_NS_DPS_PI_MASK = 0x7,
486 NVME_NS_DPS_PI_TYPE1 = 1,
487 NVME_NS_DPS_PI_TYPE2 = 2,
488 NVME_NS_DPS_PI_TYPE3 = 3,
489};
490
39481fbd
IR		 491/* Identify Namespace Metadata Capabilities (MC): */
492enum {
493 NVME_MC_EXTENDED_LBA = (1 << 0),
494 NVME_MC_METADATA_PTR = (1 << 1),
495};
496
af8b86e9
JT		 497struct nvme_ns_id_desc {
498 __u8 nidt;
499 __u8 nidl;
500 __le16 reserved;
501};
502
503#define NVME_NIDT_EUI64_LEN 8
504#define NVME_NIDT_NGUID_LEN 16
505#define NVME_NIDT_UUID_LEN 16
71010c30 506#define NVME_NIDT_CSI_LEN 1
af8b86e9
JT		 507
508enum {
509 NVME_NIDT_EUI64 = 0x01,
510 NVME_NIDT_NGUID = 0x02,
511 NVME_NIDT_UUID = 0x03,
71010c30 512 NVME_NIDT_CSI = 0x04,
af8b86e9
JT		 513};
514
9d99a8dd
CH		 515struct nvme_smart_log {
516 __u8 critical_warning;
517 __u8 temperature[2];
518 __u8 avail_spare;
519 __u8 spare_thresh;
520 __u8 percent_used;
48c9e85b
RR		 521 __u8 endu_grp_crit_warn_sumry;
522 __u8 rsvd7[25];
9d99a8dd
CH		 523 __u8 data_units_read[16];
524 __u8 data_units_written[16];
525 __u8 host_reads[16];
526 __u8 host_writes[16];
527 __u8 ctrl_busy_time[16];
528 __u8 power_cycles[16];
529 __u8 power_on_hours[16];
530 __u8 unsafe_shutdowns[16];
531 __u8 media_errors[16];
532 __u8 num_err_log_entries[16];
533 __le32 warning_temp_time;
534 __le32 critical_comp_time;
535 __le16 temp_sensor[8];
48c9e85b
RR		 536 __le32 thm_temp1_trans_count;
537 __le32 thm_temp2_trans_count;
538 __le32 thm_temp1_total_time;
539 __le32 thm_temp2_total_time;
540 __u8 rsvd232[280];
9d99a8dd
CH		 541};
542
b6dccf7f
AD		 543struct nvme_fw_slot_info_log {
544 __u8 afi;
545 __u8 rsvd1[7];
546 __le64 frs[7];
547 __u8 rsvd64[448];
548};
549
84fef62d
KB		 550enum {
551 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
552 NVME_CMD_EFFECTS_LBCC = 1 << 1,
553 NVME_CMD_EFFECTS_NCC = 1 << 2,
554 NVME_CMD_EFFECTS_NIC = 1 << 3,
555 NVME_CMD_EFFECTS_CCC = 1 << 4,
556 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
48c9e85b 557 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
84fef62d
KB		 558};
559
560struct nvme_effects_log {
561 __le32 acs[256];
562 __le32 iocs[256];
563 __u8 resv[2048];
564};
565
1a376216
CH		 566enum nvme_ana_state {
567 NVME_ANA_OPTIMIZED = 0x01,
568 NVME_ANA_NONOPTIMIZED = 0x02,
569 NVME_ANA_INACCESSIBLE = 0x03,
570 NVME_ANA_PERSISTENT_LOSS = 0x04,
571 NVME_ANA_CHANGE = 0x0f,
572};
573
574struct nvme_ana_group_desc {
575 __le32 grpid;
576 __le32 nnsids;
577 __le64 chgcnt;
578 __u8 state;
8b92d0e3 579 __u8 rsvd17[15];
1a376216
CH		 580 __le32 nsids[];
581};
582
583/* flag for the log specific field of the ANA log */
584#define NVME_ANA_LOG_RGO (1 << 0)
585
586struct nvme_ana_rsp_hdr {
587 __le64 chgcnt;
588 __le16 ngrps;
589 __le16 rsvd10[3];
590};
591
240e6ee2
KB		 592struct nvme_zone_descriptor {
593 __u8 zt;
594 __u8 zs;
595 __u8 za;
596 __u8 rsvd3[5];
597 __le64 zcap;
598 __le64 zslba;
599 __le64 wp;
600 __u8 rsvd32[32];
601};
602
603enum {
604 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
605};
606
607struct nvme_zone_report {
608 __le64 nr_zones;
609 __u8 resv8[56];
610 struct nvme_zone_descriptor entries[];
611};
612
9d99a8dd
CH		 613enum {
614 NVME_SMART_CRIT_SPARE = 1 << 0,
615 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
616 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
617 NVME_SMART_CRIT_MEDIA = 1 << 3,
618 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
619};
620
621enum {
e3d7874d
KB		 622 NVME_AER_ERROR = 0,
623 NVME_AER_SMART = 1,
868c2392 624 NVME_AER_NOTICE = 2,
e3d7874d
KB		 625 NVME_AER_CSS = 6,
626 NVME_AER_VS = 7,
868c2392
CH		 627};
628
629enum {
630 NVME_AER_NOTICE_NS_CHANGED = 0x00,
631 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 632 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 633 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 634};
635
aafd3afe 636enum {
7114ddeb
JS		 637 NVME_AEN_BIT_NS_ATTR = 8,
638 NVME_AEN_BIT_FW_ACT = 9,
639 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 640 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 641};
642
643enum {
644 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
645 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
646 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 647 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 648};
649
9d99a8dd
CH		 650struct nvme_lba_range_type {
651 __u8 type;
652 __u8 attributes;
653 __u8 rsvd2[14];
8cf486e1
WS		 654 __le64 slba;
655 __le64 nlb;
9d99a8dd
CH		 656 __u8 guid[16];
657 __u8 rsvd48[16];
658};
659
660enum {
661 NVME_LBART_TYPE_FS = 0x01,
662 NVME_LBART_TYPE_RAID = 0x02,
663 NVME_LBART_TYPE_CACHE = 0x03,
664 NVME_LBART_TYPE_SWAP = 0x04,
665
666 NVME_LBART_ATTRIB_TEMP = 1 << 0,
667 NVME_LBART_ATTRIB_HIDE = 1 << 1,
668};
669
670struct nvme_reservation_status {
671 __le32 gen;
672 __u8 rtype;
673 __u8 regctl[2];
674 __u8 resv5[2];
675 __u8 ptpls;
676 __u8 resv10[13];
677 struct {
678 __le16 cntlid;
679 __u8 rcsts;
680 __u8 resv3[5];
681 __le64 hostid;
682 __le64 rkey;
683 } regctl_ds[];
684};
685
79f370ea
CH		 686enum nvme_async_event_type {
687 NVME_AER_TYPE_ERROR = 0,
688 NVME_AER_TYPE_SMART = 1,
689 NVME_AER_TYPE_NOTICE = 2,
690};
691
9d99a8dd
CH		 692/* I/O commands */
693
694enum nvme_opcode {
695 nvme_cmd_flush = 0x00,
696 nvme_cmd_write = 0x01,
697 nvme_cmd_read = 0x02,
698 nvme_cmd_write_uncor = 0x04,
699 nvme_cmd_compare = 0x05,
700 nvme_cmd_write_zeroes = 0x08,
701 nvme_cmd_dsm = 0x09,
48c9e85b 702 nvme_cmd_verify = 0x0c,
9d99a8dd
CH		 703 nvme_cmd_resv_register = 0x0d,
704 nvme_cmd_resv_report = 0x0e,
705 nvme_cmd_resv_acquire = 0x11,
706 nvme_cmd_resv_release = 0x15,
240e6ee2
KB		 707 nvme_cmd_zone_mgmt_send = 0x79,
708 nvme_cmd_zone_mgmt_recv = 0x7a,
709 nvme_cmd_zone_append = 0x7d,
9d99a8dd
CH		 710};
711
26f2990d
MI		 712#define nvme_opcode_name(opcode) { opcode, #opcode }
713#define show_nvm_opcode_name(val) \
714 __print_symbolic(val, \
715 nvme_opcode_name(nvme_cmd_flush), \
716 nvme_opcode_name(nvme_cmd_write), \
717 nvme_opcode_name(nvme_cmd_read), \
718 nvme_opcode_name(nvme_cmd_write_uncor), \
719 nvme_opcode_name(nvme_cmd_compare), \
720 nvme_opcode_name(nvme_cmd_write_zeroes), \
721 nvme_opcode_name(nvme_cmd_dsm), \
722 nvme_opcode_name(nvme_cmd_resv_register), \
723 nvme_opcode_name(nvme_cmd_resv_report), \
724 nvme_opcode_name(nvme_cmd_resv_acquire), \
4a407d5e
JT		 725 nvme_opcode_name(nvme_cmd_resv_release), \
726 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
727 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
728 nvme_opcode_name(nvme_cmd_zone_append))
729
26f2990d
MI		 730
731
eb793e2c
CH		 732/*
733 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
734 *
735 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
736 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 737 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 738 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
739 * request subtype
740 */
741enum {
742 NVME_SGL_FMT_ADDRESS = 0x00,
743 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 744 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 745 NVME_SGL_FMT_INVALIDATE = 0x0f,
746};
747
748/*
749 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
750 *
751 * For struct nvme_sgl_desc:
752 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
753 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
754 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
755 *
756 * For struct nvme_keyed_sgl_desc:
757 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 758 *
759 * Transport-specific SGL types:
760 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 761 */
762enum {
763 NVME_SGL_FMT_DATA_DESC = 0x00,
764 NVME_SGL_FMT_SEG_DESC = 0x02,
765 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
766 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 767 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 768};
769
770struct nvme_sgl_desc {
771 __le64 addr;
772 __le32 length;
773 __u8 rsvd[3];
774 __u8 type;
775};
776
777struct nvme_keyed_sgl_desc {
778 __le64 addr;
779 __u8 length[3];
780 __u8 key[4];
781 __u8 type;
782};
783
784union nvme_data_ptr {
785 struct {
786 __le64 prp1;
787 __le64 prp2;
788 };
789 struct nvme_sgl_desc sgl;
790 struct nvme_keyed_sgl_desc ksgl;
791};
792
3972be23
JS		 793/*
794 * Lowest two bits of our flags field (FUSE field in the spec):
795 *
796 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
797 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
798 *
799 * Highest two bits in our flags field (PSDT field in the spec):
800 *
801 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
802 * If used, MPTR contains addr of single physical buffer (byte aligned).
803 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
804 * If used, MPTR contains an address of an SGL segment containing
805 * exactly 1 SGL descriptor (qword aligned).
806 */
807enum {
808 NVME_CMD_FUSE_FIRST = (1 << 0),
809 NVME_CMD_FUSE_SECOND = (1 << 1),
810
811 NVME_CMD_SGL_METABUF = (1 << 6),
812 NVME_CMD_SGL_METASEG = (1 << 7),
813 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
814};
815
9d99a8dd
CH		 816struct nvme_common_command {
817 __u8 opcode;
818 __u8 flags;
819 __u16 command_id;
820 __le32 nsid;
821 __le32 cdw2[2];
822 __le64 metadata;
eb793e2c 823 union nvme_data_ptr dptr;
b7c8f366
CK		 824 __le32 cdw10;
825 __le32 cdw11;
826 __le32 cdw12;
827 __le32 cdw13;
828 __le32 cdw14;
829 __le32 cdw15;
9d99a8dd
CH		 830};
831
832struct nvme_rw_command {
833 __u8 opcode;
834 __u8 flags;
835 __u16 command_id;
836 __le32 nsid;
837 __u64 rsvd2;
838 __le64 metadata;
eb793e2c 839 union nvme_data_ptr dptr;
9d99a8dd
CH		 840 __le64 slba;
841 __le16 length;
842 __le16 control;
843 __le32 dsmgmt;
844 __le32 reftag;
845 __le16 apptag;
846 __le16 appmask;
847};
848
849enum {
850 NVME_RW_LR = 1 << 15,
851 NVME_RW_FUA = 1 << 14,
240e6ee2 852 NVME_RW_APPEND_PIREMAP = 1 << 9,
9d99a8dd
CH		 853 NVME_RW_DSM_FREQ_UNSPEC = 0,
854 NVME_RW_DSM_FREQ_TYPICAL = 1,
855 NVME_RW_DSM_FREQ_RARE = 2,
856 NVME_RW_DSM_FREQ_READS = 3,
857 NVME_RW_DSM_FREQ_WRITES = 4,
858 NVME_RW_DSM_FREQ_RW = 5,
859 NVME_RW_DSM_FREQ_ONCE = 6,
860 NVME_RW_DSM_FREQ_PREFETCH = 7,
861 NVME_RW_DSM_FREQ_TEMP = 8,
862 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
863 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
864 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
865 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
866 NVME_RW_DSM_SEQ_REQ = 1 << 6,
867 NVME_RW_DSM_COMPRESSED = 1 << 7,
868 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
869 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
870 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
871 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 872 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 873};
874
875struct nvme_dsm_cmd {
876 __u8 opcode;
877 __u8 flags;
878 __u16 command_id;
879 __le32 nsid;
880 __u64 rsvd2[2];
eb793e2c 881 union nvme_data_ptr dptr;
9d99a8dd
CH		 882 __le32 nr;
883 __le32 attributes;
884 __u32 rsvd12[4];
885};
886
887enum {
888 NVME_DSMGMT_IDR = 1 << 0,
889 NVME_DSMGMT_IDW = 1 << 1,
890 NVME_DSMGMT_AD = 1 << 2,
891};
892
b35ba01e
CH		 893#define NVME_DSM_MAX_RANGES 256
894
9d99a8dd
CH		 895struct nvme_dsm_range {
896 __le32 cattr;
897 __le32 nlb;
898 __le64 slba;
899};
900
3b7c33b2
CK		 901struct nvme_write_zeroes_cmd {
902 __u8 opcode;
903 __u8 flags;
904 __u16 command_id;
905 __le32 nsid;
906 __u64 rsvd2;
907 __le64 metadata;
908 union nvme_data_ptr dptr;
909 __le64 slba;
910 __le16 length;
911 __le16 control;
912 __le32 dsmgmt;
913 __le32 reftag;
914 __le16 apptag;
915 __le16 appmask;
916};
917
240e6ee2
KB		 918enum nvme_zone_mgmt_action {
919 NVME_ZONE_CLOSE = 0x1,
920 NVME_ZONE_FINISH = 0x2,
921 NVME_ZONE_OPEN = 0x3,
922 NVME_ZONE_RESET = 0x4,
923 NVME_ZONE_OFFLINE = 0x5,
924 NVME_ZONE_SET_DESC_EXT = 0x10,
925};
926
927struct nvme_zone_mgmt_send_cmd {
928 __u8 opcode;
929 __u8 flags;
930 __u16 command_id;
931 __le32 nsid;
932 __le32 cdw2[2];
933 __le64 metadata;
934 union nvme_data_ptr dptr;
935 __le64 slba;
936 __le32 cdw12;
937 __u8 zsa;
938 __u8 select_all;
939 __u8 rsvd13[2];
940 __le32 cdw14[2];
941};
942
943struct nvme_zone_mgmt_recv_cmd {
944 __u8 opcode;
945 __u8 flags;
946 __u16 command_id;
947 __le32 nsid;
948 __le64 rsvd2[2];
949 union nvme_data_ptr dptr;
950 __le64 slba;
951 __le32 numd;
952 __u8 zra;
953 __u8 zrasf;
954 __u8 pr;
955 __u8 rsvd13;
956 __le32 cdw14[2];
957};
958
959enum {
960 NVME_ZRA_ZONE_REPORT = 0,
961 NVME_ZRASF_ZONE_REPORT_ALL = 0,
aaf2e048
CK		 962 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
963 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
964 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
965 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
966 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
967 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
968 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
240e6ee2
KB		 969 NVME_REPORT_ZONE_PARTIAL = 1,
970};
971
c5552fde
AL		 972/* Features */
973
52deba0f
AM		 974enum {
975 NVME_TEMP_THRESH_MASK = 0xffff,
976 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
977 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
978};
979
c5552fde
AL		 980struct nvme_feat_auto_pst {
981 __le64 entries[32];
982};
983
39673e19
CH		 984enum {
985 NVME_HOST_MEM_ENABLE = (1 << 0),
986 NVME_HOST_MEM_RETURN = (1 << 1),
987};
988
49cd84b6
KB		 989struct nvme_feat_host_behavior {
990 __u8 acre;
991 __u8 resv1[511];
992};
993
994enum {
995 NVME_ENABLE_ACRE = 1,
996};
997
9d99a8dd
CH		 998/* Admin commands */
999
1000enum nvme_admin_opcode {
1001 nvme_admin_delete_sq = 0x00,
1002 nvme_admin_create_sq = 0x01,
1003 nvme_admin_get_log_page = 0x02,
1004 nvme_admin_delete_cq = 0x04,
1005 nvme_admin_create_cq = 0x05,
1006 nvme_admin_identify = 0x06,
1007 nvme_admin_abort_cmd = 0x08,
1008 nvme_admin_set_features = 0x09,
1009 nvme_admin_get_features = 0x0a,
1010 nvme_admin_async_event = 0x0c,
a446c084 1011 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 1012 nvme_admin_activate_fw = 0x10,
1013 nvme_admin_download_fw = 0x11,
48c9e85b 1014 nvme_admin_dev_self_test = 0x14,
a446c084 1015 nvme_admin_ns_attach = 0x15,
7b89eae2 1016 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 1017 nvme_admin_directive_send = 0x19,
1018 nvme_admin_directive_recv = 0x1a,
48c9e85b
RR		 1019 nvme_admin_virtual_mgmt = 0x1c,
1020 nvme_admin_nvme_mi_send = 0x1d,
1021 nvme_admin_nvme_mi_recv = 0x1e,
f9f38e33 1022 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 1023 nvme_admin_format_nvm = 0x80,
1024 nvme_admin_security_send = 0x81,
1025 nvme_admin_security_recv = 0x82,
84fef62d 1026 nvme_admin_sanitize_nvm = 0x84,
c6389845 1027 nvme_admin_get_lba_status = 0x86,
c1fef73f 1028 nvme_admin_vendor_start = 0xC0,
9d99a8dd
CH		 1029};
1030
26f2990d
MI		 1031#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1032#define show_admin_opcode_name(val) \
1033 __print_symbolic(val, \
1034 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1035 nvme_admin_opcode_name(nvme_admin_create_sq), \
1036 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1037 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1038 nvme_admin_opcode_name(nvme_admin_create_cq), \
1039 nvme_admin_opcode_name(nvme_admin_identify), \
1040 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1041 nvme_admin_opcode_name(nvme_admin_set_features), \
1042 nvme_admin_opcode_name(nvme_admin_get_features), \
1043 nvme_admin_opcode_name(nvme_admin_async_event), \
1044 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1045 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1046 nvme_admin_opcode_name(nvme_admin_download_fw), \
1047 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1048 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1049 nvme_admin_opcode_name(nvme_admin_directive_send), \
1050 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1051 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1052 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1053 nvme_admin_opcode_name(nvme_admin_security_send), \
1054 nvme_admin_opcode_name(nvme_admin_security_recv), \
a5ef7572
MI		 1055 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1056 nvme_admin_opcode_name(nvme_admin_get_lba_status))
26f2990d 1057
9d99a8dd
CH		 1058enum {
1059 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1060 NVME_CQ_IRQ_ENABLED = (1 << 1),
1061 NVME_SQ_PRIO_URGENT = (0 << 1),
1062 NVME_SQ_PRIO_HIGH = (1 << 1),
1063 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1064 NVME_SQ_PRIO_LOW = (3 << 1),
1065 NVME_FEAT_ARBITRATION = 0x01,
1066 NVME_FEAT_POWER_MGMT = 0x02,
1067 NVME_FEAT_LBA_RANGE = 0x03,
1068 NVME_FEAT_TEMP_THRESH = 0x04,
1069 NVME_FEAT_ERR_RECOVERY = 0x05,
1070 NVME_FEAT_VOLATILE_WC = 0x06,
1071 NVME_FEAT_NUM_QUEUES = 0x07,
1072 NVME_FEAT_IRQ_COALESCE = 0x08,
1073 NVME_FEAT_IRQ_CONFIG = 0x09,
1074 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1075 NVME_FEAT_ASYNC_EVENT = 0x0b,
1076 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 1077 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 1078 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 1079 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 1080 NVME_FEAT_HCTM = 0x10,
1081 NVME_FEAT_NOPSC = 0x11,
1082 NVME_FEAT_RRL = 0x12,
1083 NVME_FEAT_PLM_CONFIG = 0x13,
1084 NVME_FEAT_PLM_WINDOW = 0x14,
49cd84b6 1085 NVME_FEAT_HOST_BEHAVIOR = 0x16,
48c9e85b 1086 NVME_FEAT_SANITIZE = 0x17,
9d99a8dd
CH		 1087 NVME_FEAT_SW_PROGRESS = 0x80,
1088 NVME_FEAT_HOST_ID = 0x81,
1089 NVME_FEAT_RESV_MASK = 0x82,
1090 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 1091 NVME_FEAT_WRITE_PROTECT = 0x84,
c1fef73f
LG		 1092 NVME_FEAT_VENDOR_START = 0xC0,
1093 NVME_FEAT_VENDOR_END = 0xFF,
9d99a8dd
CH		 1094 NVME_LOG_ERROR = 0x01,
1095 NVME_LOG_SMART = 0x02,
1096 NVME_LOG_FW_SLOT = 0x03,
b3984e06 1097 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 1098 NVME_LOG_CMD_EFFECTS = 0x05,
48c9e85b
RR		 1099 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1100 NVME_LOG_TELEMETRY_HOST = 0x07,
1101 NVME_LOG_TELEMETRY_CTRL = 0x08,
1102 NVME_LOG_ENDURANCE_GROUP = 0x09,
1a376216 1103 NVME_LOG_ANA = 0x0c,
eb793e2c 1104 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 1105 NVME_LOG_RESERVATION = 0x80,
1106 NVME_FWACT_REPL = (0 << 3),
1107 NVME_FWACT_REPL_ACTV = (1 << 3),
1108 NVME_FWACT_ACTV = (2 << 3),
1109};
1110
93045d59
CK		 1111/* NVMe Namespace Write Protect State */
1112enum {
1113 NVME_NS_NO_WRITE_PROTECT = 0,
1114 NVME_NS_WRITE_PROTECT,
1115 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1116 NVME_NS_WRITE_PROTECT_PERMANENT,
1117};
1118
b3984e06
CH		 1119#define NVME_MAX_CHANGED_NAMESPACES 1024
1120
9d99a8dd
CH		 1121struct nvme_identify {
1122 __u8 opcode;
1123 __u8 flags;
1124 __u16 command_id;
1125 __le32 nsid;
1126 __u64 rsvd2[2];
eb793e2c 1127 union nvme_data_ptr dptr;
986994a2
PP		 1128 __u8 cns;
1129 __u8 rsvd3;
1130 __le16 ctrlid;
71010c30
NC		 1131 __u8 rsvd11[3];
1132 __u8 csi;
1133 __u32 rsvd12[4];
9d99a8dd
CH		 1134};
1135
0add5e8e
JT		 1136#define NVME_IDENTIFY_DATA_SIZE 4096
1137
9d99a8dd
CH		 1138struct nvme_features {
1139 __u8 opcode;
1140 __u8 flags;
1141 __u16 command_id;
1142 __le32 nsid;
1143 __u64 rsvd2[2];
eb793e2c 1144 union nvme_data_ptr dptr;
9d99a8dd
CH		 1145 __le32 fid;
1146 __le32 dword11;
b85cf734
AD		 1147 __le32 dword12;
1148 __le32 dword13;
1149 __le32 dword14;
1150 __le32 dword15;
9d99a8dd
CH		 1151};
1152
39673e19
CH		 1153struct nvme_host_mem_buf_desc {
1154 __le64 addr;
1155 __le32 size;
1156 __u32 rsvd;
1157};
1158
9d99a8dd
CH		 1159struct nvme_create_cq {
1160 __u8 opcode;
1161 __u8 flags;
1162 __u16 command_id;
1163 __u32 rsvd1[5];
1164 __le64 prp1;
1165 __u64 rsvd8;
1166 __le16 cqid;
1167 __le16 qsize;
1168 __le16 cq_flags;
1169 __le16 irq_vector;
1170 __u32 rsvd12[4];
1171};
1172
1173struct nvme_create_sq {
1174 __u8 opcode;
1175 __u8 flags;
1176 __u16 command_id;
1177 __u32 rsvd1[5];
1178 __le64 prp1;
1179 __u64 rsvd8;
1180 __le16 sqid;
1181 __le16 qsize;
1182 __le16 sq_flags;
1183 __le16 cqid;
1184 __u32 rsvd12[4];
1185};
1186
1187struct nvme_delete_queue {
1188 __u8 opcode;
1189 __u8 flags;
1190 __u16 command_id;
1191 __u32 rsvd1[9];
1192 __le16 qid;
1193 __u16 rsvd10;
1194 __u32 rsvd11[5];
1195};
1196
1197struct nvme_abort_cmd {
1198 __u8 opcode;
1199 __u8 flags;
1200 __u16 command_id;
1201 __u32 rsvd1[9];
1202 __le16 sqid;
1203 __u16 cid;
1204 __u32 rsvd11[5];
1205};
1206
1207struct nvme_download_firmware {
1208 __u8 opcode;
1209 __u8 flags;
1210 __u16 command_id;
1211 __u32 rsvd1[5];
eb793e2c 1212 union nvme_data_ptr dptr;
9d99a8dd
CH		 1213 __le32 numd;
1214 __le32 offset;
1215 __u32 rsvd12[4];
1216};
1217
1218struct nvme_format_cmd {
1219 __u8 opcode;
1220 __u8 flags;
1221 __u16 command_id;
1222 __le32 nsid;
1223 __u64 rsvd2[4];
1224 __le32 cdw10;
1225 __u32 rsvd11[5];
1226};
1227
725b3588
AB		 1228struct nvme_get_log_page_command {
1229 __u8 opcode;
1230 __u8 flags;
1231 __u16 command_id;
1232 __le32 nsid;
1233 __u64 rsvd2[2];
eb793e2c 1234 union nvme_data_ptr dptr;
725b3588 1235 __u8 lid;
9b89bc38 1236 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 1237 __le16 numdl;
1238 __le16 numdu;
1239 __u16 rsvd11;
d808b7f7
KB		 1240 union {
1241 struct {
1242 __le32 lpol;
1243 __le32 lpou;
1244 };
1245 __le64 lpo;
1246 };
be93e87e
KB		 1247 __u8 rsvd14[3];
1248 __u8 csi;
1249 __u32 rsvd15;
725b3588
AB		 1250};
1251
f5d11840
JA		 1252struct nvme_directive_cmd {
1253 __u8 opcode;
1254 __u8 flags;
1255 __u16 command_id;
1256 __le32 nsid;
1257 __u64 rsvd2[2];
1258 union nvme_data_ptr dptr;
1259 __le32 numd;
1260 __u8 doper;
1261 __u8 dtype;
1262 __le16 dspec;
1263 __u8 endir;
1264 __u8 tdtype;
1265 __u16 rsvd15;
1266
1267 __u32 rsvd16[3];
1268};
1269
eb793e2c
CH		 1270/*
1271 * Fabrics subcommands.
1272 */
1273enum nvmf_fabrics_opcode {
1274 nvme_fabrics_command = 0x7f,
1275};
1276
1277enum nvmf_capsule_command {
1278 nvme_fabrics_type_property_set = 0x00,
1279 nvme_fabrics_type_connect = 0x01,
1280 nvme_fabrics_type_property_get = 0x04,
1281};
1282
ad795e47
MI		 1283#define nvme_fabrics_type_name(type) { type, #type }
1284#define show_fabrics_type_name(type) \
1285 __print_symbolic(type, \
1286 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1287 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1288 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1289
1290/*
1291 * If not fabrics command, fctype will be ignored.
1292 */
1293#define show_opcode_name(qid, opcode, fctype) \
1294 ((opcode) == nvme_fabrics_command ? \
1295 show_fabrics_type_name(fctype) : \
1296 ((qid) ? \
1297 show_nvm_opcode_name(opcode) : \
1298 show_admin_opcode_name(opcode)))
1299
eb793e2c
CH		 1300struct nvmf_common_command {
1301 __u8 opcode;
1302 __u8 resv1;
1303 __u16 command_id;
1304 __u8 fctype;
1305 __u8 resv2[35];
1306 __u8 ts[24];
1307};
1308
1309/*
1310 * The legal cntlid range a NVMe Target will provide.
1311 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1312 * Devices based on earlier specs did not have the subsystem concept;
1313 * therefore, those devices had their cntlid value set to 0 as a result.
1314 */
1315#define NVME_CNTLID_MIN 1
1316#define NVME_CNTLID_MAX 0xffef
1317#define NVME_CNTLID_DYNAMIC 0xffff
1318
1319#define MAX_DISC_LOGS 255
1320
785d584c
HR		 1321/* Discovery log page entry flags (EFLAGS): */
1322enum {
1323 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1324 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1325};
1326
eb793e2c
CH		 1327/* Discovery log page entry */
1328struct nvmf_disc_rsp_page_entry {
1329 __u8 trtype;
1330 __u8 adrfam;
a446c084 1331 __u8 subtype;
eb793e2c
CH		 1332 __u8 treq;
1333 __le16 portid;
1334 __le16 cntlid;
1335 __le16 asqsz;
785d584c
HR		 1336 __le16 eflags;
1337 __u8 resv10[20];
eb793e2c
CH		 1338 char trsvcid[NVMF_TRSVCID_SIZE];
1339 __u8 resv64[192];
1340 char subnqn[NVMF_NQN_FIELD_LEN];
1341 char traddr[NVMF_TRADDR_SIZE];
1342 union tsas {
1343 char common[NVMF_TSAS_SIZE];
1344 struct rdma {
1345 __u8 qptype;
1346 __u8 prtype;
1347 __u8 cms;
1348 __u8 resv3[5];
1349 __u16 pkey;
1350 __u8 resv10[246];
1351 } rdma;
1352 } tsas;
1353};
1354
1355/* Discovery log page header */
1356struct nvmf_disc_rsp_page_hdr {
1357 __le64 genctr;
1358 __le64 numrec;
1359 __le16 recfmt;
1360 __u8 resv14[1006];
f1e71d75 1361 struct nvmf_disc_rsp_page_entry entries[];
eb793e2c
CH		 1362};
1363
e6a622fd
SG		 1364enum {
1365 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1366};
1367
eb793e2c
CH		 1368struct nvmf_connect_command {
1369 __u8 opcode;
1370 __u8 resv1;
1371 __u16 command_id;
1372 __u8 fctype;
1373 __u8 resv2[19];
1374 union nvme_data_ptr dptr;
1375 __le16 recfmt;
1376 __le16 qid;
1377 __le16 sqsize;
1378 __u8 cattr;
1379 __u8 resv3;
1380 __le32 kato;
1381 __u8 resv4[12];
1382};
1383
1384struct nvmf_connect_data {
8e412263 1385 uuid_t hostid;
eb793e2c
CH		 1386 __le16 cntlid;
1387 char resv4[238];
1388 char subsysnqn[NVMF_NQN_FIELD_LEN];
1389 char hostnqn[NVMF_NQN_FIELD_LEN];
1390 char resv5[256];
1391};
1392
1393struct nvmf_property_set_command {
1394 __u8 opcode;
1395 __u8 resv1;
1396 __u16 command_id;
1397 __u8 fctype;
1398 __u8 resv2[35];
1399 __u8 attrib;
1400 __u8 resv3[3];
1401 __le32 offset;
1402 __le64 value;
1403 __u8 resv4[8];
1404};
1405
1406struct nvmf_property_get_command {
1407 __u8 opcode;
1408 __u8 resv1;
1409 __u16 command_id;
1410 __u8 fctype;
1411 __u8 resv2[35];
1412 __u8 attrib;
1413 __u8 resv3[3];
1414 __le32 offset;
1415 __u8 resv4[16];
1416};
1417
f9f38e33
HK		 1418struct nvme_dbbuf {
1419 __u8 opcode;
1420 __u8 flags;
1421 __u16 command_id;
1422 __u32 rsvd1[5];
1423 __le64 prp1;
1424 __le64 prp2;
1425 __u32 rsvd12[6];
1426};
1427
f5d11840 1428struct streams_directive_params {
dc1a0afb
CH		 1429 __le16 msl;
1430 __le16 nssa;
1431 __le16 nsso;
f5d11840 1432 __u8 rsvd[10];
dc1a0afb
CH		 1433 __le32 sws;
1434 __le16 sgs;
1435 __le16 nsa;
1436 __le16 nso;
f5d11840
JA		 1437 __u8 rsvd2[6];
1438};
1439
9d99a8dd
CH		 1440struct nvme_command {
1441 union {
1442 struct nvme_common_command common;
1443 struct nvme_rw_command rw;
1444 struct nvme_identify identify;
1445 struct nvme_features features;
1446 struct nvme_create_cq create_cq;
1447 struct nvme_create_sq create_sq;
1448 struct nvme_delete_queue delete_queue;
1449 struct nvme_download_firmware dlfw;
1450 struct nvme_format_cmd format;
1451 struct nvme_dsm_cmd dsm;
3b7c33b2 1452 struct nvme_write_zeroes_cmd write_zeroes;
240e6ee2
KB		 1453 struct nvme_zone_mgmt_send_cmd zms;
1454 struct nvme_zone_mgmt_recv_cmd zmr;
9d99a8dd 1455 struct nvme_abort_cmd abort;
725b3588 1456 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1457 struct nvmf_common_command fabrics;
1458 struct nvmf_connect_command connect;
1459 struct nvmf_property_set_command prop_set;
1460 struct nvmf_property_get_command prop_get;
f9f38e33 1461 struct nvme_dbbuf dbbuf;
f5d11840 1462 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1463 };
1464};
1465
7a1f46e3
MI		 1466static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1467{
1468 return cmd->common.opcode == nvme_fabrics_command;
1469}
1470
b34de7ce
CK		 1471struct nvme_error_slot {
1472 __le64 error_count;
1473 __le16 sqid;
1474 __le16 cmdid;
1475 __le16 status_field;
1476 __le16 param_error_location;
1477 __le64 lba;
1478 __le32 nsid;
1479 __u8 vs;
1480 __u8 resv[3];
1481 __le64 cs;
1482 __u8 resv2[24];
1483};
1484
7a5abb4b
CH		 1485static inline bool nvme_is_write(struct nvme_command *cmd)
1486{
eb793e2c
CH		 1487 /*
1488 * What a mess...
1489 *
1490 * Why can't we simply have a Fabrics In and Fabrics out command?
1491 */
7a1f46e3 1492 if (unlikely(nvme_is_fabrics(cmd)))
2fd4167f 1493 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1494 return cmd->common.opcode & 1;
1495}
1496
9d99a8dd 1497enum {
eb793e2c
CH		 1498 /*
1499 * Generic Command Status:
1500 */
9d99a8dd
CH		 1501 NVME_SC_SUCCESS = 0x0,
1502 NVME_SC_INVALID_OPCODE = 0x1,
1503 NVME_SC_INVALID_FIELD = 0x2,
1504 NVME_SC_CMDID_CONFLICT = 0x3,
1505 NVME_SC_DATA_XFER_ERROR = 0x4,
1506 NVME_SC_POWER_LOSS = 0x5,
1507 NVME_SC_INTERNAL = 0x6,
1508 NVME_SC_ABORT_REQ = 0x7,
1509 NVME_SC_ABORT_QUEUE = 0x8,
1510 NVME_SC_FUSED_FAIL = 0x9,
1511 NVME_SC_FUSED_MISSING = 0xa,
1512 NVME_SC_INVALID_NS = 0xb,
1513 NVME_SC_CMD_SEQ_ERROR = 0xc,
1514 NVME_SC_SGL_INVALID_LAST = 0xd,
1515 NVME_SC_SGL_INVALID_COUNT = 0xe,
1516 NVME_SC_SGL_INVALID_DATA = 0xf,
1517 NVME_SC_SGL_INVALID_METADATA = 0x10,
1518 NVME_SC_SGL_INVALID_TYPE = 0x11,
3254899e
MG		 1519 NVME_SC_CMB_INVALID_USE = 0x12,
1520 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1521 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1522 NVME_SC_OP_DENIED = 0x15,
eb793e2c 1523 NVME_SC_SGL_INVALID_OFFSET = 0x16,
3254899e
MG		 1524 NVME_SC_RESERVED = 0x17,
1525 NVME_SC_HOST_ID_INCONSIST = 0x18,
1526 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1527 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1528 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
48c9e85b
RR		 1529 NVME_SC_SANITIZE_FAILED = 0x1C,
1530 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
3254899e
MG		 1531 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1532 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
93045d59 1533 NVME_SC_NS_WRITE_PROTECTED = 0x20,
48c9e85b 1534 NVME_SC_CMD_INTERRUPTED = 0x21,
3254899e 1535 NVME_SC_TRANSIENT_TR_ERR = 0x22,
ab5d0b38 1536 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
93045d59 1537
9d99a8dd
CH		 1538 NVME_SC_LBA_RANGE = 0x80,
1539 NVME_SC_CAP_EXCEEDED = 0x81,
1540 NVME_SC_NS_NOT_READY = 0x82,
1541 NVME_SC_RESERVATION_CONFLICT = 0x83,
3254899e 1542 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
eb793e2c
CH		 1543
1544 /*
1545 * Command Specific Status:
1546 */
9d99a8dd
CH		 1547 NVME_SC_CQ_INVALID = 0x100,
1548 NVME_SC_QID_INVALID = 0x101,
1549 NVME_SC_QUEUE_SIZE = 0x102,
1550 NVME_SC_ABORT_LIMIT = 0x103,
1551 NVME_SC_ABORT_MISSING = 0x104,
1552 NVME_SC_ASYNC_LIMIT = 0x105,
1553 NVME_SC_FIRMWARE_SLOT = 0x106,
1554 NVME_SC_FIRMWARE_IMAGE = 0x107,
1555 NVME_SC_INVALID_VECTOR = 0x108,
1556 NVME_SC_INVALID_LOG_PAGE = 0x109,
1557 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1558 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1559 NVME_SC_INVALID_QUEUE = 0x10c,
1560 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1561 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1562 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1563 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1564 NVME_SC_FW_NEEDS_RESET = 0x111,
1565 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
9581ae4f 1566 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
a446c084 1567 NVME_SC_OVERLAPPING_RANGE = 0x114,
9581ae4f 1568 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
a446c084
CH		 1569 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1570 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1571 NVME_SC_NS_IS_PRIVATE = 0x119,
1572 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1573 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1574 NVME_SC_CTRL_LIST_INVALID = 0x11c,
3254899e 1575 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
48c9e85b 1576 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
3254899e
MG		 1577 NVME_SC_CTRL_ID_INVALID = 0x11f,
1578 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1579 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1580 NVME_SC_RES_ID_INVALID = 0x122,
48c9e85b 1581 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
3254899e
MG		 1582 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1583 NVME_SC_ANA_ATTACH_FAILED = 0x125,
eb793e2c
CH		 1584
1585 /*
1586 * I/O Command Set Specific - NVM commands:
1587 */
9d99a8dd
CH		 1588 NVME_SC_BAD_ATTRIBUTES = 0x180,
1589 NVME_SC_INVALID_PI = 0x181,
1590 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1591 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1592
1593 /*
1594 * I/O Command Set Specific - Fabrics commands:
1595 */
1596 NVME_SC_CONNECT_FORMAT = 0x180,
1597 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1598 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1599 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1600 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1601
1602 NVME_SC_DISCOVERY_RESTART = 0x190,
1603 NVME_SC_AUTH_REQUIRED = 0x191,
1604
240e6ee2
KB		 1605 /*
1606 * I/O Command Set Specific - Zoned commands:
1607 */
1608 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1609 NVME_SC_ZONE_FULL = 0x1b9,
1610 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1611 NVME_SC_ZONE_OFFLINE = 0x1bb,
1612 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1613 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1614 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1615 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1616
eb793e2c
CH		 1617 /*
1618 * Media and Data Integrity Errors:
1619 */
9d99a8dd
CH		 1620 NVME_SC_WRITE_FAULT = 0x280,
1621 NVME_SC_READ_ERROR = 0x281,
1622 NVME_SC_GUARD_CHECK = 0x282,
1623 NVME_SC_APPTAG_CHECK = 0x283,
1624 NVME_SC_REFTAG_CHECK = 0x284,
1625 NVME_SC_COMPARE_FAILED = 0x285,
1626 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1627 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1628
1a376216
CH		 1629 /*
1630 * Path-related Errors:
1631 */
1632 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1633 NVME_SC_ANA_INACCESSIBLE = 0x302,
1634 NVME_SC_ANA_TRANSITION = 0x303,
783f4a44 1635 NVME_SC_HOST_PATH_ERROR = 0x370,
2dc3947b 1636 NVME_SC_HOST_ABORTED_CMD = 0x371,
1a376216 1637
49cd84b6 1638 NVME_SC_CRD = 0x1800,
9d99a8dd
CH		 1639 NVME_SC_DNR = 0x4000,
1640};
1641
1642struct nvme_completion {
eb793e2c
CH		 1643 /*
1644 * Used by Admin and Fabrics commands to return data:
1645 */
d49187e9
CH		 1646 union nvme_result {
1647 __le16 u16;
1648 __le32 u32;
1649 __le64 u64;
1650 } result;
9d99a8dd
CH		 1651 __le16 sq_head; /* how much of this queue may be reclaimed */
1652 __le16 sq_id; /* submission queue that generated this entry */
1653 __u16 command_id; /* of the command which completed */
1654 __le16 status; /* did the command fail, and if so, why? */
1655};
1656
8ef2074d
GKB		 1657#define NVME_VS(major, minor, tertiary) \
1658 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1659
c61d788b
JT		 1660#define NVME_MAJOR(ver) ((ver) >> 16)
1661#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1662#define NVME_TERTIARY(ver) ((ver) & 0xff)
1663
b60503ba 1664#endif /* _LINUX_NVME_H */
Linux 6.x block layer and io_uring tree(s)