Commit | Line | Data |
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e9f3a2bc | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
8eabdd1e HS |
2 | /* |
3 | * Copyright (C) 2014 Freescale Semiconductor, Inc. | |
8eabdd1e HS |
4 | */ |
5 | ||
f39d2fa0 HS |
6 | #ifndef __LINUX_MTD_SPI_NOR_H |
7 | #define __LINUX_MTD_SPI_NOR_H | |
8 | ||
801cf21b | 9 | #include <linux/bitops.h> |
db4745ed | 10 | #include <linux/mtd/cfi.h> |
2c81de77 | 11 | #include <linux/mtd/mtd.h> |
b35b9a10 | 12 | #include <linux/spi/spi-mem.h> |
db4745ed BN |
13 | |
14 | /* | |
15 | * Manufacturer IDs | |
16 | * | |
17 | * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. | |
18 | * Sometimes these are the same as CFI IDs, but sometimes they aren't. | |
19 | */ | |
20 | #define SNOR_MFR_ATMEL CFI_MFR_ATMEL | |
e5366a26 | 21 | #define SNOR_MFR_GIGADEVICE 0xc8 |
db4745ed | 22 | #define SNOR_MFR_INTEL CFI_MFR_INTEL |
0005aad0 YNG |
23 | #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ |
24 | #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ | |
83cba933 | 25 | #define SNOR_MFR_ISSI CFI_MFR_PMC |
db4745ed BN |
26 | #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX |
27 | #define SNOR_MFR_SPANSION CFI_MFR_AMD | |
28 | #define SNOR_MFR_SST CFI_MFR_SST | |
67b9bcd3 | 29 | #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ |
801cf21b | 30 | |
58b89a1f BN |
31 | /* |
32 | * Note on opcode nomenclature: some opcodes have a format like | |
33 | * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number | |
34 | * of I/O lines used for the opcode, address, and data (respectively). The | |
35 | * FUNCTION has an optional suffix of '4', to represent an opcode which | |
36 | * requires a 4-byte (32-bit) address. | |
37 | */ | |
38 | ||
f39d2fa0 | 39 | /* Flash opcodes. */ |
b02e7f3e BN |
40 | #define SPINOR_OP_WREN 0x06 /* Write enable */ |
41 | #define SPINOR_OP_RDSR 0x05 /* Read status register */ | |
42 | #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ | |
f384b352 CP |
43 | #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ |
44 | #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ | |
58b89a1f BN |
45 | #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ |
46 | #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ | |
902cc69a CP |
47 | #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ |
48 | #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ | |
49 | #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ | |
50 | #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ | |
fcd44b64 YNG |
51 | #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ |
52 | #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ | |
b02e7f3e | 53 | #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ |
902cc69a CP |
54 | #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ |
55 | #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ | |
fcd44b64 YNG |
56 | #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ |
57 | #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ | |
b02e7f3e BN |
58 | #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ |
59 | #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ | |
60 | #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ | |
61 | #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ | |
62 | #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ | |
63 | #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ | |
f384b352 | 64 | #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ |
b02e7f3e | 65 | #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ |
c14dedde | 66 | #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ |
20ccb993 | 67 | #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ |
f134fbbb N |
68 | #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ |
69 | #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ | |
f39d2fa0 HS |
70 | |
71 | /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ | |
902cc69a CP |
72 | #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ |
73 | #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ | |
74 | #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ | |
75 | #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ | |
76 | #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ | |
77 | #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ | |
fcd44b64 YNG |
78 | #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ |
79 | #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ | |
b02e7f3e | 80 | #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ |
902cc69a CP |
81 | #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ |
82 | #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ | |
fcd44b64 YNG |
83 | #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ |
84 | #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ | |
902cc69a CP |
85 | #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ |
86 | #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ | |
b02e7f3e | 87 | #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ |
f39d2fa0 | 88 | |
15f55331 CP |
89 | /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ |
90 | #define SPINOR_OP_READ_1_1_1_DTR 0x0d | |
91 | #define SPINOR_OP_READ_1_2_2_DTR 0xbd | |
92 | #define SPINOR_OP_READ_1_4_4_DTR 0xed | |
93 | ||
94 | #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e | |
95 | #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe | |
96 | #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee | |
97 | ||
f39d2fa0 | 98 | /* Used for SST flashes only. */ |
b02e7f3e BN |
99 | #define SPINOR_OP_BP 0x02 /* Byte program */ |
100 | #define SPINOR_OP_WRDI 0x04 /* Write disable */ | |
101 | #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ | |
f39d2fa0 | 102 | |
e99ca98f RR |
103 | /* Used for S3AN flashes only */ |
104 | #define SPINOR_OP_XSE 0x50 /* Sector erase */ | |
105 | #define SPINOR_OP_XPP 0x82 /* Page program */ | |
106 | #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ | |
107 | ||
108 | #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ | |
109 | #define XSR_RDY BIT(7) /* Ready */ | |
110 | ||
111 | ||
f39d2fa0 | 112 | /* Used for Macronix and Winbond flashes. */ |
b02e7f3e BN |
113 | #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ |
114 | #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ | |
f39d2fa0 HS |
115 | |
116 | /* Used for Spansion flashes only. */ | |
b02e7f3e | 117 | #define SPINOR_OP_BRWR 0x17 /* Bank register write */ |
c4b3eacc | 118 | #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ |
f39d2fa0 | 119 | |
548cd3ab BH |
120 | /* Used for Micron flashes only. */ |
121 | #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ | |
122 | #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ | |
123 | ||
f39d2fa0 | 124 | /* Status Register bits. */ |
a8a16454 BN |
125 | #define SR_WIP BIT(0) /* Write in progress */ |
126 | #define SR_WEL BIT(1) /* Write enable latch */ | |
f39d2fa0 | 127 | /* meaning of other SR_* bits may differ between vendors */ |
a8a16454 BN |
128 | #define SR_BP0 BIT(2) /* Block protect 0 */ |
129 | #define SR_BP1 BIT(3) /* Block protect 1 */ | |
130 | #define SR_BP2 BIT(4) /* Block protect 2 */ | |
52487e21 JL |
131 | #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ |
132 | #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ | |
a8a16454 | 133 | #define SR_SRWD BIT(7) /* SR write protect */ |
c4b3eacc AS |
134 | /* Spansion/Cypress specific status bits */ |
135 | #define SR_E_ERR BIT(5) | |
136 | #define SR_P_ERR BIT(6) | |
f39d2fa0 | 137 | |
658488ed | 138 | #define SR1_QUAD_EN_BIT6 BIT(6) |
f39d2fa0 | 139 | |
8c79fa6c JL |
140 | #define SR_BP_SHIFT 2 |
141 | ||
548cd3ab | 142 | /* Enhanced Volatile Configuration Register bits */ |
a8a16454 | 143 | #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ |
548cd3ab | 144 | |
c14dedde | 145 | /* Flag Status Register bits */ |
20ccb993 BH |
146 | #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ |
147 | #define FSR_E_ERR BIT(5) /* Erase operation status */ | |
148 | #define FSR_P_ERR BIT(4) /* Program operation status */ | |
149 | #define FSR_PT_ERR BIT(1) /* Protection error bit */ | |
c14dedde | 150 | |
f384b352 | 151 | /* Status Register 2 bits. */ |
bb2dc7f4 | 152 | #define SR2_QUAD_EN_BIT1 BIT(1) |
f384b352 CP |
153 | #define SR2_QUAD_EN_BIT7 BIT(7) |
154 | ||
cfc5604c CP |
155 | /* Supported SPI protocols */ |
156 | #define SNOR_PROTO_INST_MASK GENMASK(23, 16) | |
157 | #define SNOR_PROTO_INST_SHIFT 16 | |
158 | #define SNOR_PROTO_INST(_nbits) \ | |
159 | ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ | |
160 | SNOR_PROTO_INST_MASK) | |
161 | ||
162 | #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) | |
163 | #define SNOR_PROTO_ADDR_SHIFT 8 | |
164 | #define SNOR_PROTO_ADDR(_nbits) \ | |
165 | ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ | |
166 | SNOR_PROTO_ADDR_MASK) | |
167 | ||
168 | #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) | |
169 | #define SNOR_PROTO_DATA_SHIFT 0 | |
170 | #define SNOR_PROTO_DATA(_nbits) \ | |
171 | ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ | |
172 | SNOR_PROTO_DATA_MASK) | |
173 | ||
15f55331 CP |
174 | #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ |
175 | ||
cfc5604c CP |
176 | #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ |
177 | (SNOR_PROTO_INST(_inst_nbits) | \ | |
178 | SNOR_PROTO_ADDR(_addr_nbits) | \ | |
179 | SNOR_PROTO_DATA(_data_nbits)) | |
15f55331 CP |
180 | #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ |
181 | (SNOR_PROTO_IS_DTR | \ | |
182 | SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) | |
cfc5604c CP |
183 | |
184 | enum spi_nor_protocol { | |
185 | SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), | |
186 | SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), | |
187 | SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), | |
fe488a5e | 188 | SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), |
cfc5604c CP |
189 | SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), |
190 | SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), | |
fe488a5e | 191 | SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), |
cfc5604c CP |
192 | SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), |
193 | SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), | |
fe488a5e | 194 | SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), |
15f55331 CP |
195 | |
196 | SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), | |
197 | SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), | |
198 | SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), | |
fe488a5e | 199 | SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), |
6e602ef7 HS |
200 | }; |
201 | ||
15f55331 CP |
202 | static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) |
203 | { | |
204 | return !!(proto & SNOR_PROTO_IS_DTR); | |
205 | } | |
206 | ||
cfc5604c CP |
207 | static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) |
208 | { | |
209 | return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> | |
210 | SNOR_PROTO_INST_SHIFT; | |
211 | } | |
212 | ||
213 | static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) | |
214 | { | |
215 | return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> | |
216 | SNOR_PROTO_ADDR_SHIFT; | |
217 | } | |
218 | ||
219 | static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) | |
220 | { | |
221 | return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> | |
222 | SNOR_PROTO_DATA_SHIFT; | |
223 | } | |
224 | ||
225 | static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) | |
226 | { | |
227 | return spi_nor_get_protocol_data_nbits(proto); | |
228 | } | |
229 | ||
6af91949 BN |
230 | enum spi_nor_option_flags { |
231 | SNOR_F_USE_FSR = BIT(0), | |
3dd8012a | 232 | SNOR_F_HAS_SR_TB = BIT(1), |
e99ca98f | 233 | SNOR_F_NO_OP_CHIP_ERASE = BIT(2), |
36499596 BB |
234 | SNOR_F_READY_XSR_RDY = BIT(3), |
235 | SNOR_F_USE_CLSR = BIT(4), | |
236 | SNOR_F_BROKEN_RESET = BIT(5), | |
237 | SNOR_F_4B_OPCODES = BIT(6), | |
238 | SNOR_F_HAS_4BAIT = BIT(7), | |
239 | SNOR_F_HAS_LOCK = BIT(8), | |
39d1e334 TA |
240 | SNOR_F_HAS_16BIT_SR = BIT(9), |
241 | SNOR_F_NO_READ_CR = BIT(10), | |
adf1092f | 242 | SNOR_F_HAS_SR_TB_BIT6 = BIT(11), |
39d1e334 | 243 | |
6af91949 BN |
244 | }; |
245 | ||
5390a8df TA |
246 | /** |
247 | * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type | |
248 | * @size: the size of the sector/block erased by the erase type. | |
249 | * JEDEC JESD216B imposes erase sizes to be a power of 2. | |
250 | * @size_shift: @size is a power of 2, the shift is stored in | |
251 | * @size_shift. | |
252 | * @size_mask: the size mask based on @size_shift. | |
253 | * @opcode: the SPI command op code to erase the sector/block. | |
254 | * @idx: Erase Type index as sorted in the Basic Flash Parameter | |
255 | * Table. It will be used to synchronize the supported | |
256 | * Erase Types with the ones identified in the SFDP | |
257 | * optional tables. | |
258 | */ | |
259 | struct spi_nor_erase_type { | |
260 | u32 size; | |
261 | u32 size_shift; | |
262 | u32 size_mask; | |
263 | u8 opcode; | |
264 | u8 idx; | |
265 | }; | |
266 | ||
267 | /** | |
268 | * struct spi_nor_erase_command - Used for non-uniform erases | |
269 | * The structure is used to describe a list of erase commands to be executed | |
270 | * once we validate that the erase can be performed. The elements in the list | |
271 | * are run-length encoded. | |
272 | * @list: for inclusion into the list of erase commands. | |
273 | * @count: how many times the same erase command should be | |
274 | * consecutively used. | |
275 | * @size: the size of the sector/block erased by the command. | |
276 | * @opcode: the SPI command op code to erase the sector/block. | |
277 | */ | |
278 | struct spi_nor_erase_command { | |
279 | struct list_head list; | |
280 | u32 count; | |
281 | u32 size; | |
282 | u8 opcode; | |
283 | }; | |
284 | ||
285 | /** | |
286 | * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region | |
287 | * @offset: the offset in the data array of erase region start. | |
288 | * LSB bits are used as a bitmask encoding flags to | |
289 | * determine if this region is overlaid, if this region is | |
290 | * the last in the SPI NOR flash memory and to indicate | |
291 | * all the supported erase commands inside this region. | |
292 | * The erase types are sorted in ascending order with the | |
293 | * smallest Erase Type size being at BIT(0). | |
294 | * @size: the size of the region in bytes. | |
295 | */ | |
296 | struct spi_nor_erase_region { | |
297 | u64 offset; | |
298 | u64 size; | |
299 | }; | |
300 | ||
301 | #define SNOR_ERASE_TYPE_MAX 4 | |
302 | #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) | |
303 | ||
304 | #define SNOR_LAST_REGION BIT(4) | |
305 | #define SNOR_OVERLAID_REGION BIT(5) | |
306 | ||
307 | #define SNOR_ERASE_FLAGS_MAX 6 | |
308 | #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) | |
309 | ||
310 | /** | |
311 | * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map | |
312 | * @regions: array of erase regions. The regions are consecutive in | |
313 | * address space. Walking through the regions is done | |
314 | * incrementally. | |
315 | * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform | |
316 | * sector size (legacy implementation). | |
317 | * @erase_type: an array of erase types shared by all the regions. | |
318 | * The erase types are sorted in ascending order, with the | |
319 | * smallest Erase Type size being the first member in the | |
320 | * erase_type array. | |
321 | * @uniform_erase_type: bitmask encoding erase types that can erase the | |
322 | * entire memory. This member is completed at init by | |
323 | * uniform and non-uniform SPI NOR flash memories if they | |
324 | * support at least one erase type that can erase the | |
325 | * entire memory. | |
326 | */ | |
327 | struct spi_nor_erase_map { | |
328 | struct spi_nor_erase_region *regions; | |
329 | struct spi_nor_erase_region uniform_region; | |
330 | struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; | |
331 | u8 uniform_erase_type; | |
332 | }; | |
333 | ||
47599127 TA |
334 | /** |
335 | * struct spi_nor_hwcaps - Structure for describing the hardware capabilies | |
336 | * supported by the SPI controller (bus master). | |
337 | * @mask: the bitmask listing all the supported hw capabilies | |
338 | */ | |
339 | struct spi_nor_hwcaps { | |
340 | u32 mask; | |
341 | }; | |
342 | ||
343 | /* | |
344 | *(Fast) Read capabilities. | |
345 | * MUST be ordered by priority: the higher bit position, the higher priority. | |
346 | * As a matter of performances, it is relevant to use Octal SPI protocols first, | |
347 | * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly | |
348 | * (Slow) Read. | |
349 | */ | |
350 | #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) | |
351 | #define SNOR_HWCAPS_READ BIT(0) | |
352 | #define SNOR_HWCAPS_READ_FAST BIT(1) | |
353 | #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) | |
354 | ||
355 | #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) | |
356 | #define SNOR_HWCAPS_READ_1_1_2 BIT(3) | |
357 | #define SNOR_HWCAPS_READ_1_2_2 BIT(4) | |
358 | #define SNOR_HWCAPS_READ_2_2_2 BIT(5) | |
359 | #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) | |
360 | ||
361 | #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) | |
362 | #define SNOR_HWCAPS_READ_1_1_4 BIT(7) | |
363 | #define SNOR_HWCAPS_READ_1_4_4 BIT(8) | |
364 | #define SNOR_HWCAPS_READ_4_4_4 BIT(9) | |
365 | #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) | |
366 | ||
367 | #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11) | |
368 | #define SNOR_HWCAPS_READ_1_1_8 BIT(11) | |
369 | #define SNOR_HWCAPS_READ_1_8_8 BIT(12) | |
370 | #define SNOR_HWCAPS_READ_8_8_8 BIT(13) | |
371 | #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) | |
372 | ||
373 | /* | |
374 | * Page Program capabilities. | |
375 | * MUST be ordered by priority: the higher bit position, the higher priority. | |
376 | * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the | |
377 | * legacy SPI 1-1-1 protocol. | |
378 | * Note that Dual Page Programs are not supported because there is no existing | |
379 | * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory | |
380 | * implements such commands. | |
381 | */ | |
382 | #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) | |
383 | #define SNOR_HWCAPS_PP BIT(16) | |
384 | ||
385 | #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) | |
386 | #define SNOR_HWCAPS_PP_1_1_4 BIT(17) | |
387 | #define SNOR_HWCAPS_PP_1_4_4 BIT(18) | |
388 | #define SNOR_HWCAPS_PP_4_4_4 BIT(19) | |
389 | ||
390 | #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20) | |
391 | #define SNOR_HWCAPS_PP_1_1_8 BIT(20) | |
392 | #define SNOR_HWCAPS_PP_1_8_8 BIT(21) | |
393 | #define SNOR_HWCAPS_PP_8_8_8 BIT(22) | |
394 | ||
395 | #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \ | |
396 | SNOR_HWCAPS_READ_4_4_4 | \ | |
397 | SNOR_HWCAPS_READ_8_8_8 | \ | |
398 | SNOR_HWCAPS_PP_4_4_4 | \ | |
399 | SNOR_HWCAPS_PP_8_8_8) | |
400 | ||
401 | #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ | |
402 | SNOR_HWCAPS_READ_1_2_2_DTR | \ | |
403 | SNOR_HWCAPS_READ_1_4_4_DTR | \ | |
404 | SNOR_HWCAPS_READ_1_8_8_DTR) | |
405 | ||
406 | #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ | |
407 | SNOR_HWCAPS_PP_MASK) | |
408 | ||
409 | struct spi_nor_read_command { | |
410 | u8 num_mode_clocks; | |
411 | u8 num_wait_states; | |
412 | u8 opcode; | |
413 | enum spi_nor_protocol proto; | |
414 | }; | |
415 | ||
416 | struct spi_nor_pp_command { | |
417 | u8 opcode; | |
418 | enum spi_nor_protocol proto; | |
419 | }; | |
420 | ||
421 | enum spi_nor_read_command_index { | |
422 | SNOR_CMD_READ, | |
423 | SNOR_CMD_READ_FAST, | |
424 | SNOR_CMD_READ_1_1_1_DTR, | |
425 | ||
426 | /* Dual SPI */ | |
427 | SNOR_CMD_READ_1_1_2, | |
428 | SNOR_CMD_READ_1_2_2, | |
429 | SNOR_CMD_READ_2_2_2, | |
430 | SNOR_CMD_READ_1_2_2_DTR, | |
431 | ||
432 | /* Quad SPI */ | |
433 | SNOR_CMD_READ_1_1_4, | |
434 | SNOR_CMD_READ_1_4_4, | |
435 | SNOR_CMD_READ_4_4_4, | |
436 | SNOR_CMD_READ_1_4_4_DTR, | |
437 | ||
438 | /* Octal SPI */ | |
439 | SNOR_CMD_READ_1_1_8, | |
440 | SNOR_CMD_READ_1_8_8, | |
441 | SNOR_CMD_READ_8_8_8, | |
442 | SNOR_CMD_READ_1_8_8_DTR, | |
443 | ||
444 | SNOR_CMD_READ_MAX | |
445 | }; | |
446 | ||
447 | enum spi_nor_pp_command_index { | |
448 | SNOR_CMD_PP, | |
449 | ||
450 | /* Quad SPI */ | |
451 | SNOR_CMD_PP_1_1_4, | |
452 | SNOR_CMD_PP_1_4_4, | |
453 | SNOR_CMD_PP_4_4_4, | |
454 | ||
455 | /* Octal SPI */ | |
456 | SNOR_CMD_PP_1_1_8, | |
457 | SNOR_CMD_PP_1_8_8, | |
458 | SNOR_CMD_PP_8_8_8, | |
459 | ||
460 | SNOR_CMD_PP_MAX | |
461 | }; | |
462 | ||
463 | /* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */ | |
464 | struct spi_nor; | |
465 | ||
45397787 TA |
466 | /** |
467 | * struct spi_nor_controller_ops - SPI NOR controller driver specific | |
468 | * operations. | |
469 | * @prepare: [OPTIONAL] do some preparations for the | |
470 | * read/write/erase/lock/unlock operations. | |
471 | * @unprepare: [OPTIONAL] do some post work after the | |
472 | * read/write/erase/lock/unlock operations. | |
473 | * @read_reg: read out the register. | |
474 | * @write_reg: write data to the register. | |
475 | * @read: read data from the SPI NOR. | |
476 | * @write: write data to the SPI NOR. | |
477 | * @erase: erase a sector of the SPI NOR at the offset @offs; if | |
478 | * not provided by the driver, spi-nor will send the erase | |
479 | * opcode via write_reg(). | |
480 | */ | |
481 | struct spi_nor_controller_ops { | |
52bbd2dc MW |
482 | int (*prepare)(struct spi_nor *nor); |
483 | void (*unprepare)(struct spi_nor *nor); | |
45397787 TA |
484 | int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len); |
485 | int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf, | |
486 | size_t len); | |
487 | ||
488 | ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf); | |
489 | ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len, | |
490 | const u8 *buf); | |
491 | int (*erase)(struct spi_nor *nor, loff_t offs); | |
492 | }; | |
493 | ||
dff97245 BB |
494 | /** |
495 | * struct spi_nor_locking_ops - SPI NOR locking methods | |
496 | * @lock: lock a region of the SPI NOR. | |
497 | * @unlock: unlock a region of the SPI NOR. | |
498 | * @is_locked: check if a region of the SPI NOR is completely locked | |
499 | */ | |
500 | struct spi_nor_locking_ops { | |
501 | int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); | |
502 | int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); | |
503 | int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); | |
504 | }; | |
505 | ||
47599127 TA |
506 | /** |
507 | * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. | |
508 | * Includes legacy flash parameters and settings that can be overwritten | |
509 | * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 | |
510 | * Serial Flash Discoverable Parameters (SFDP) tables. | |
511 | * | |
512 | * @size: the flash memory density in bytes. | |
513 | * @page_size: the page size of the SPI NOR flash memory. | |
514 | * @hwcaps: describes the read and page program hardware | |
515 | * capabilities. | |
516 | * @reads: read capabilities ordered by priority: the higher index | |
517 | * in the array, the higher priority. | |
518 | * @page_programs: page program capabilities ordered by priority: the | |
519 | * higher index in the array, the higher priority. | |
c4687217 TA |
520 | * @erase_map: the erase map parsed from the SFDP Sector Map Parameter |
521 | * Table. | |
47599127 | 522 | * @quad_enable: enables SPI NOR quad mode. |
81924dae | 523 | * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. |
36499596 BB |
524 | * @convert_addr: converts an absolute address into something the flash |
525 | * will understand. Particularly useful when pagesize is | |
526 | * not a power-of-2. | |
2d7ff858 TA |
527 | * @setup: configures the SPI NOR memory. Useful for SPI NOR |
528 | * flashes that have peculiarities to the SPI NOR standard | |
529 | * e.g. different opcodes, specific address calculation, | |
530 | * page size, etc. | |
dff97245 | 531 | * @locking_ops: SPI NOR locking methods. |
47599127 TA |
532 | */ |
533 | struct spi_nor_flash_parameter { | |
534 | u64 size; | |
535 | u32 page_size; | |
536 | ||
537 | struct spi_nor_hwcaps hwcaps; | |
538 | struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; | |
539 | struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; | |
540 | ||
c4687217 TA |
541 | struct spi_nor_erase_map erase_map; |
542 | ||
47599127 | 543 | int (*quad_enable)(struct spi_nor *nor); |
81924dae | 544 | int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); |
36499596 | 545 | u32 (*convert_addr)(struct spi_nor *nor, u32 addr); |
2d7ff858 | 546 | int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); |
dff97245 BB |
547 | |
548 | const struct spi_nor_locking_ops *locking_ops; | |
47599127 TA |
549 | }; |
550 | ||
46dde01f KD |
551 | /** |
552 | * struct flash_info - Forward declaration of a structure used internally by | |
553 | * spi_nor_scan() | |
554 | */ | |
555 | struct flash_info; | |
556 | ||
9ec4bbcb BB |
557 | /** |
558 | * struct spi_nor_manufacturer - Forward declaration of a structure used | |
559 | * internally by the core and manufacturer drivers. | |
560 | */ | |
561 | struct spi_nor_manufacturer; | |
562 | ||
6e602ef7 HS |
563 | /** |
564 | * struct spi_nor - Structure for defining a the SPI NOR layer | |
565 | * @mtd: point to a mtd_info structure | |
566 | * @lock: the lock for the read/write/erase/lock/unlock operations | |
567 | * @dev: point to a spi device, or a spi nor controller device. | |
b35b9a10 | 568 | * @spimem: point to the spi mem device |
f173f26a VR |
569 | * @bouncebuf: bounce buffer used when the buffer passed by the MTD |
570 | * layer is not DMA-able | |
571 | * @bouncebuf_size: size of the bounce buffer | |
46dde01f | 572 | * @info: spi-nor part JDEC MFR id and other info |
9ec4bbcb | 573 | * @manufacturer: spi-nor manufacturer |
6e602ef7 HS |
574 | * @page_size: the page size of the SPI NOR |
575 | * @addr_width: number of address bytes | |
576 | * @erase_opcode: the opcode for erasing a sector | |
577 | * @read_opcode: the read opcode | |
578 | * @read_dummy: the dummy needed by the read operation | |
579 | * @program_opcode: the program opcode | |
6e602ef7 | 580 | * @sst_write_second: used by the SST write operation |
6af91949 | 581 | * @flags: flag options for the current SPI-NOR (SNOR_F_*) |
cfc5604c CP |
582 | * @read_proto: the SPI protocol for read operations |
583 | * @write_proto: the SPI protocol for write operations | |
584 | * @reg_proto the SPI protocol for read_reg/write_reg/erase operations | |
45397787 | 585 | * @controller_ops: SPI NOR controller driver specific operations. |
47599127 TA |
586 | * @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings. |
587 | * The structure includes legacy flash parameters and | |
588 | * settings that can be overwritten by the spi_nor_fixups | |
589 | * hooks, or dynamically when parsing the SFDP tables. | |
df5c2100 | 590 | * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes. |
6e602ef7 HS |
591 | * @priv: the private data |
592 | */ | |
593 | struct spi_nor { | |
19763671 | 594 | struct mtd_info mtd; |
6e602ef7 HS |
595 | struct mutex lock; |
596 | struct device *dev; | |
b35b9a10 | 597 | struct spi_mem *spimem; |
f173f26a VR |
598 | u8 *bouncebuf; |
599 | size_t bouncebuf_size; | |
46dde01f | 600 | const struct flash_info *info; |
9ec4bbcb | 601 | const struct spi_nor_manufacturer *manufacturer; |
6e602ef7 HS |
602 | u32 page_size; |
603 | u8 addr_width; | |
604 | u8 erase_opcode; | |
605 | u8 read_opcode; | |
606 | u8 read_dummy; | |
607 | u8 program_opcode; | |
cfc5604c CP |
608 | enum spi_nor_protocol read_proto; |
609 | enum spi_nor_protocol write_proto; | |
610 | enum spi_nor_protocol reg_proto; | |
6e602ef7 | 611 | bool sst_write_second; |
6af91949 | 612 | u32 flags; |
6e602ef7 | 613 | |
45397787 | 614 | const struct spi_nor_controller_ops *controller_ops; |
6e602ef7 | 615 | |
47599127 | 616 | struct spi_nor_flash_parameter params; |
8cc7f33a | 617 | |
df5c2100 SS |
618 | struct { |
619 | struct spi_mem_dirmap_desc *rdesc; | |
620 | struct spi_mem_dirmap_desc *wdesc; | |
621 | } dirmap; | |
622 | ||
6e602ef7 HS |
623 | void *priv; |
624 | }; | |
b199489d | 625 | |
5390a8df TA |
626 | static u64 __maybe_unused |
627 | spi_nor_region_is_last(const struct spi_nor_erase_region *region) | |
628 | { | |
629 | return region->offset & SNOR_LAST_REGION; | |
630 | } | |
631 | ||
632 | static u64 __maybe_unused | |
633 | spi_nor_region_end(const struct spi_nor_erase_region *region) | |
634 | { | |
635 | return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; | |
636 | } | |
637 | ||
b038e8e3 TA |
638 | static void __maybe_unused |
639 | spi_nor_region_mark_end(struct spi_nor_erase_region *region) | |
640 | { | |
641 | region->offset |= SNOR_LAST_REGION; | |
642 | } | |
643 | ||
644 | static void __maybe_unused | |
645 | spi_nor_region_mark_overlay(struct spi_nor_erase_region *region) | |
646 | { | |
647 | region->offset |= SNOR_OVERLAID_REGION; | |
648 | } | |
649 | ||
5390a8df TA |
650 | static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor) |
651 | { | |
c4687217 | 652 | return !!nor->params.erase_map.uniform_erase_type; |
5390a8df TA |
653 | } |
654 | ||
28b8b26b BN |
655 | static inline void spi_nor_set_flash_node(struct spi_nor *nor, |
656 | struct device_node *np) | |
657 | { | |
30069af7 | 658 | mtd_set_of_node(&nor->mtd, np); |
28b8b26b BN |
659 | } |
660 | ||
661 | static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) | |
662 | { | |
30069af7 | 663 | return mtd_get_of_node(&nor->mtd); |
28b8b26b BN |
664 | } |
665 | ||
b199489d HS |
666 | /** |
667 | * spi_nor_scan() - scan the SPI NOR | |
668 | * @nor: the spi_nor structure | |
70f3ce05 | 669 | * @name: the chip type name |
cfc5604c | 670 | * @hwcaps: the hardware capabilities supported by the controller driver |
b199489d HS |
671 | * |
672 | * The drivers can use this fuction to scan the SPI NOR. | |
673 | * In the scanning, it will try to get all the necessary information to | |
674 | * fill the mtd_info{} and the spi_nor{}. | |
675 | * | |
70f3ce05 | 676 | * The chip type name can be provided through the @name parameter. |
b199489d HS |
677 | * |
678 | * Return: 0 for success, others for failure. | |
679 | */ | |
cfc5604c CP |
680 | int spi_nor_scan(struct spi_nor *nor, const char *name, |
681 | const struct spi_nor_hwcaps *hwcaps); | |
b199489d | 682 | |
8dee1d97 HZ |
683 | /** |
684 | * spi_nor_restore_addr_mode() - restore the status of SPI NOR | |
685 | * @nor: the spi_nor structure | |
686 | */ | |
687 | void spi_nor_restore(struct spi_nor *nor); | |
688 | ||
f39d2fa0 | 689 | #endif |