[linux-2.6-block.git] / include / linux / mtd / onenand_regs.h

/*
 *  linux/include/linux/mtd/onenand_regs.h
 *
 *  OneNAND Register header file
 *
 *  Copyright (C) 2005-2007 Samsung Electronics
 *  Kyungmin Park <kyungmin.park@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ONENAND_REG_H
#define __ONENAND_REG_H

/* Memory Address Map Translation (Word order) */
#define ONENAND_MEMORY_MAP(x)		((x) << 1)

/*
 * External BufferRAM area
 */
#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)

/*
 * OneNAND Registers
 */
#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)

#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)

#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)

#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)

/*
 * Device ID Register F001h (R)
 */
#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
#define ONENAND_DEVICE_IS_DDP		(1 << 3)
#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
#define ONENAND_DEVICE_VCC_MASK		(0x3)

#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)

/*
 * Version ID Register F002h (R)
 */
#define ONENAND_VERSION_PROCESS_SHIFT	(8)

/*
 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
 */
#define ONENAND_DDP_SHIFT		(15)
#define ONENAND_DDP_CHIP0		(0)
#define ONENAND_DDP_CHIP1		(1 << ONENAND_DDP_SHIFT)

/*
 * Start Address 8 F107h (R/W)
 */
#define ONENAND_FPA_MASK		(0x3f)
#define ONENAND_FPA_SHIFT		(2)
#define ONENAND_FSA_MASK		(0x03)

/*
 * Start Buffer Register F200h (R/W)
 */
#define ONENAND_BSA_MASK		(0x03)
#define ONENAND_BSA_SHIFT		(8)
#define ONENAND_BSA_BOOTRAM		(0 << 2)
#define ONENAND_BSA_DATARAM0		(2 << 2)
#define ONENAND_BSA_DATARAM1		(3 << 2)
#define ONENAND_BSC_MASK		(0x03)

/*
 * Command Register F220h (R/W)
 */
#define ONENAND_CMD_READ		(0x00)
#define ONENAND_CMD_READOOB		(0x13)
#define ONENAND_CMD_PROG		(0x80)
#define ONENAND_CMD_PROGOOB		(0x1A)
#define ONENAND_CMD_2X_PROG		(0x7D)
#define ONENAND_CMD_2X_CACHE_PROG	(0x7F)
#define ONENAND_CMD_UNLOCK		(0x23)
#define ONENAND_CMD_LOCK		(0x2A)
#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
#define ONENAND_CMD_UNLOCK_ALL		(0x27)
#define ONENAND_CMD_ERASE		(0x94)
#define ONENAND_CMD_RESET		(0xF0)
#define ONENAND_CMD_OTP_ACCESS		(0x65)
#define ONENAND_CMD_READID		(0x90)

/* NOTE: Those are not *REAL* commands */
#define ONENAND_CMD_BUFFERRAM		(0x1978)

/*
 * System Configuration 1 Register F221h (R, R/W)
 */
#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
#define ONENAND_SYS_CFG1_RDY		(1 << 7)
#define ONENAND_SYS_CFG1_INT		(1 << 6)
#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)

/*
 * Controller Status Register F240h (R)
 */
#define ONENAND_CTRL_ONGO		(1 << 15)
#define ONENAND_CTRL_LOCK		(1 << 14)
#define ONENAND_CTRL_LOAD		(1 << 13)
#define ONENAND_CTRL_PROGRAM		(1 << 12)
#define ONENAND_CTRL_ERASE		(1 << 11)
#define ONENAND_CTRL_ERROR		(1 << 10)
#define ONENAND_CTRL_RSTB		(1 << 7)
#define ONENAND_CTRL_OTP_L		(1 << 6)
#define ONENAND_CTRL_OTP_BL		(1 << 5)

/*
 * Interrupt Status Register F241h (R)
 */
#define ONENAND_INT_MASTER		(1 << 15)
#define ONENAND_INT_READ		(1 << 7)
#define ONENAND_INT_WRITE		(1 << 6)
#define ONENAND_INT_ERASE		(1 << 5)
#define ONENAND_INT_RESET		(1 << 4)
#define ONENAND_INT_CLEAR		(0 << 0)

/*
 * NAND Flash Write Protection Status Register F24Eh (R)
 */
#define ONENAND_WP_US			(1 << 2)
#define ONENAND_WP_LS			(1 << 1)
#define ONENAND_WP_LTS			(1 << 0)

/*
 * ECC Status Reigser FF00h (R)
 */
#define ONENAND_ECC_1BIT		(1 << 0)
#define ONENAND_ECC_1BIT_ALL		(0x5555)
#define ONENAND_ECC_2BIT		(1 << 1)
#define ONENAND_ECC_2BIT_ALL		(0xAAAA)

/*
 * One-Time Programmable (OTP)
 */
#define ONENAND_OTP_LOCK_OFFSET		(14)

#endif	/* __ONENAND_REG_H */
Commit	Line	Data
cd5f6346 KP	1	/*
	2	* linux/include/linux/mtd/onenand_regs.h
	3	*
	4	* OneNAND Register header file
	5	*
75384b0d KP	6	* Copyright (C) 2005-2007 Samsung Electronics
75384b0d KP	7	* Kyungmin Park <kyungmin.park@samsung.com>
cd5f6346 KP	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#ifndef __ONENAND_REG_H
	15	#define __ONENAND_REG_H
	16
	17	/* Memory Address Map Translation (Word order) */
	18	#define ONENAND_MEMORY_MAP(x) ((x) << 1)
	19
	20	/*
	21	* External BufferRAM area
	22	*/
	23	#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
	24	#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
	25	#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
	26
	27	/*
	28	* OneNAND Registers
	29	*/
	30	#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
	31	#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
	32	#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
	33	#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
	34	#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
	35	#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
	36	#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
	37
	38	#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
	39	#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
	40	#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
	41	#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
	42	#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
	43	#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
	44	#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
	45	#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
	46
	47	#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
	48	#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
	49	#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
	50	#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
	51	#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
	52	#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
	53	#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
	54	#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
	55	#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
	56
	57	#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
	58	#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
	59	#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
	60	#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
	61	#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
	62	#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
	63	#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
	64	#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
	65	#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
	66
	67	/*
	68	* Device ID Register F001h (R)
	69	*/
	70	#define ONENAND_DEVICE_DENSITY_SHIFT (4)
	71	#define ONENAND_DEVICE_IS_DDP (1 << 3)
72	#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
73	#define ONENAND_DEVICE_VCC_MASK (0x3)
74
75	#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
28b79ff9	76	#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
ee9745fc KP	77	#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
ee9745fc KP	78	#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
cd5f6346 KP	79
	80	/*
	81	* Version ID Register F002h (R)
	82	*/
	83	#define ONENAND_VERSION_PROCESS_SHIFT (8)
	84
	85	/*
738d61f5	86	* Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
cd5f6346 KP	87	*/
cd5f6346 KP	88	#define ONENAND_DDP_SHIFT (15)
738d61f5 KP	89	#define ONENAND_DDP_CHIP0 (0)
738d61f5 KP	90	#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
cd5f6346 KP	91
	92	/*
	93	* Start Address 8 F107h (R/W)
	94	*/
	95	#define ONENAND_FPA_MASK (0x3f)
	96	#define ONENAND_FPA_SHIFT (2)
	97	#define ONENAND_FSA_MASK (0x03)
	98
	99	/*
	100	* Start Buffer Register F200h (R/W)
	101	*/
	102	#define ONENAND_BSA_MASK (0x03)
	103	#define ONENAND_BSA_SHIFT (8)
	104	#define ONENAND_BSA_BOOTRAM (0 << 2)
	105	#define ONENAND_BSA_DATARAM0 (2 << 2)
	106	#define ONENAND_BSA_DATARAM1 (3 << 2)
	107	#define ONENAND_BSC_MASK (0x03)
	108
	109	/*
	110	* Command Register F220h (R/W)
	111	*/
	112	#define ONENAND_CMD_READ (0x00)
	113	#define ONENAND_CMD_READOOB (0x13)
	114	#define ONENAND_CMD_PROG (0x80)
	115	#define ONENAND_CMD_PROGOOB (0x1A)
ee9745fc KP	116	#define ONENAND_CMD_2X_PROG (0x7D)
ee9745fc KP	117	#define ONENAND_CMD_2X_CACHE_PROG (0x7F)
cd5f6346 KP	118	#define ONENAND_CMD_UNLOCK (0x23)
	119	#define ONENAND_CMD_LOCK (0x2A)
	120	#define ONENAND_CMD_LOCK_TIGHT (0x2C)
28b79ff9	121	#define ONENAND_CMD_UNLOCK_ALL (0x27)
cd5f6346 KP	122	#define ONENAND_CMD_ERASE (0x94)
cd5f6346 KP	123	#define ONENAND_CMD_RESET (0xF0)
493c6460	124	#define ONENAND_CMD_OTP_ACCESS (0x65)
cd5f6346 KP	125	#define ONENAND_CMD_READID (0x90)
	126
	127	/* NOTE: Those are not REAL commands */
	128	#define ONENAND_CMD_BUFFERRAM (0x1978)
	129
	130	/*
	131	* System Configuration 1 Register F221h (R, R/W)
	132	*/
	133	#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
52b0eea7 KP	134	#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
	135	#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
	136	#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
	137	#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
	138	#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
	139	#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
	140	#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
	141	#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
	142	#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
	143	#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
	144	#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
	145	#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
	146	#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
	147	#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
	148	#define ONENAND_SYS_CFG1_BL_SHIFT (9)
cd5f6346 KP	149	#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
	150	#define ONENAND_SYS_CFG1_RDY (1 << 7)
	151	#define ONENAND_SYS_CFG1_INT (1 << 6)
	152	#define ONENAND_SYS_CFG1_IOBE (1 << 5)
	153	#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
	154
	155	/*
	156	* Controller Status Register F240h (R)
	157	*/
	158	#define ONENAND_CTRL_ONGO (1 << 15)
	159	#define ONENAND_CTRL_LOCK (1 << 14)
	160	#define ONENAND_CTRL_LOAD (1 << 13)
	161	#define ONENAND_CTRL_PROGRAM (1 << 12)
	162	#define ONENAND_CTRL_ERASE (1 << 11)
	163	#define ONENAND_CTRL_ERROR (1 << 10)
	164	#define ONENAND_CTRL_RSTB (1 << 7)
493c6460 KP	165	#define ONENAND_CTRL_OTP_L (1 << 6)
493c6460 KP	166	#define ONENAND_CTRL_OTP_BL (1 << 5)
cd5f6346 KP	167
	168	/*
	169	* Interrupt Status Register F241h (R)
	170	*/
	171	#define ONENAND_INT_MASTER (1 << 15)
	172	#define ONENAND_INT_READ (1 << 7)
	173	#define ONENAND_INT_WRITE (1 << 6)
	174	#define ONENAND_INT_ERASE (1 << 5)
	175	#define ONENAND_INT_RESET (1 << 4)
	176	#define ONENAND_INT_CLEAR (0 << 0)
	177
	178	/*
	179	* NAND Flash Write Protection Status Register F24Eh (R)
	180	*/
	181	#define ONENAND_WP_US (1 << 2)
	182	#define ONENAND_WP_LS (1 << 1)
	183	#define ONENAND_WP_LTS (1 << 0)
	184
	185	/*
	186	* ECC Status Reigser FF00h (R)
	187	*/
	188	#define ONENAND_ECC_1BIT (1 << 0)
f4f91ac3	189	#define ONENAND_ECC_1BIT_ALL (0x5555)
cd5f6346 KP	190	#define ONENAND_ECC_2BIT (1 << 1)
	191	#define ONENAND_ECC_2BIT_ALL (0xAAAA)
	192
493c6460 KP	193	/*
	194	* One-Time Programmable (OTP)
	195	*/
	196	#define ONENAND_OTP_LOCK_OFFSET (14)
	197
cd5f6346	198	#endif /* __ONENAND_REG_H */