Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3b7d1921 EB |
2 | #ifndef LINUX_MSI_H |
3 | #define LINUX_MSI_H | |
4 | ||
ef3350c5 TG |
5 | /* |
6 | * This header file contains MSI data structures and functions which are | |
7 | * only relevant for: | |
8 | * - Interrupt core code | |
9 | * - PCI/MSI core code | |
10 | * - MSI interrupt domain implementations | |
11 | * - IOMMU, low level VFIO, NTB and other justified exceptions | |
12 | * dealing with low level MSI details. | |
13 | * | |
14 | * Regular device drivers have no business with any of these functions and | |
15 | * especially storing MSI descriptor pointers in random code is considered | |
6b6941f6 TG |
16 | * abuse. |
17 | * | |
18 | * Device driver relevant functions are available in <linux/msi_api.h> | |
ef3350c5 TG |
19 | */ |
20 | ||
22db089a | 21 | #include <linux/irqdomain_defs.h> |
3ba1f050 | 22 | #include <linux/cpumask.h> |
6b6941f6 | 23 | #include <linux/msi_api.h> |
cd6cf065 | 24 | #include <linux/xarray.h> |
b5f687f9 | 25 | #include <linux/mutex.h> |
4aa9bc95 | 26 | #include <linux/list.h> |
ebca4396 | 27 | #include <linux/irq.h> |
2d958b02 TG |
28 | #include <linux/bits.h> |
29 | ||
8073c1ac TG |
30 | #include <asm/msi.h> |
31 | ||
32 | /* Dummy shadow structures if an architecture does not define them */ | |
33 | #ifndef arch_msi_msg_addr_lo | |
34 | typedef struct arch_msi_msg_addr_lo { | |
35 | u32 address_lo; | |
36 | } __attribute__ ((packed)) arch_msi_msg_addr_lo_t; | |
37 | #endif | |
38 | ||
39 | #ifndef arch_msi_msg_addr_hi | |
40 | typedef struct arch_msi_msg_addr_hi { | |
41 | u32 address_hi; | |
42 | } __attribute__ ((packed)) arch_msi_msg_addr_hi_t; | |
43 | #endif | |
44 | ||
45 | #ifndef arch_msi_msg_data | |
46 | typedef struct arch_msi_msg_data { | |
47 | u32 data; | |
48 | } __attribute__ ((packed)) arch_msi_msg_data_t; | |
49 | #endif | |
4aa9bc95 | 50 | |
8073c1ac TG |
51 | /** |
52 | * msi_msg - Representation of a MSI message | |
53 | * @address_lo: Low 32 bits of msi message address | |
54 | * @arch_addrlo: Architecture specific shadow of @address_lo | |
55 | * @address_hi: High 32 bits of msi message address | |
56 | * (only used when device supports it) | |
57 | * @arch_addrhi: Architecture specific shadow of @address_hi | |
58 | * @data: MSI message data (usually 16 bits) | |
59 | * @arch_data: Architecture specific shadow of @data | |
60 | */ | |
3b7d1921 | 61 | struct msi_msg { |
8073c1ac TG |
62 | union { |
63 | u32 address_lo; | |
64 | arch_msi_msg_addr_lo_t arch_addr_lo; | |
65 | }; | |
66 | union { | |
67 | u32 address_hi; | |
68 | arch_msi_msg_addr_hi_t arch_addr_hi; | |
69 | }; | |
70 | union { | |
71 | u32 data; | |
72 | arch_msi_msg_data_t arch_data; | |
73 | }; | |
3b7d1921 EB |
74 | }; |
75 | ||
38737d82 | 76 | extern int pci_msi_ignore_mask; |
c54c1879 | 77 | /* Helper functions */ |
39431acb | 78 | struct msi_desc; |
25a98bd4 | 79 | struct pci_dev; |
c09fcc4b | 80 | struct platform_msi_priv_data; |
bf5e758f | 81 | struct device_attribute; |
64258eaa | 82 | struct irq_domain; |
3d393b21 | 83 | struct irq_affinity_desc; |
bf6e054e | 84 | |
2366d06e | 85 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
2f44e29c | 86 | #ifdef CONFIG_GENERIC_MSI_IRQ |
2366d06e | 87 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); |
2f44e29c | 88 | #else |
13e7accb | 89 | static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) { } |
2f44e29c | 90 | #endif |
891d4a48 | 91 | |
c09fcc4b MZ |
92 | typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc, |
93 | struct msi_msg *msg); | |
94 | ||
e58f2259 TG |
95 | /** |
96 | * pci_msi_desc - PCI/MSI specific MSI descriptor data | |
97 | * | |
98 | * @msi_mask: [PCI MSI] MSI cached mask bits | |
99 | * @msix_ctrl: [PCI MSI-X] MSI-X cached per vector control bits | |
100 | * @is_msix: [PCI MSI/X] True if MSI-X | |
101 | * @multiple: [PCI MSI/X] log2 num of messages allocated | |
102 | * @multi_cap: [PCI MSI/X] log2 num of messages supported | |
103 | * @can_mask: [PCI MSI/X] Masking supported? | |
104 | * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit | |
e58f2259 TG |
105 | * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq |
106 | * @mask_pos: [PCI MSI] Mask register position | |
107 | * @mask_base: [PCI MSI-X] Mask register base address | |
108 | */ | |
109 | struct pci_msi_desc { | |
110 | union { | |
111 | u32 msi_mask; | |
112 | u32 msix_ctrl; | |
113 | }; | |
114 | struct { | |
115 | u8 is_msix : 1; | |
116 | u8 multiple : 3; | |
117 | u8 multi_cap : 3; | |
118 | u8 can_mask : 1; | |
119 | u8 is_64 : 1; | |
120 | u8 is_virtual : 1; | |
e58f2259 TG |
121 | unsigned default_irq; |
122 | } msi_attrib; | |
123 | union { | |
124 | u8 mask_pos; | |
125 | void __iomem *mask_base; | |
126 | }; | |
127 | }; | |
128 | ||
efd42049 TG |
129 | /** |
130 | * union msi_domain_cookie - Opaque MSI domain specific data | |
131 | * @value: u64 value store | |
132 | * @ptr: Pointer to domain specific data | |
133 | * @iobase: Domain specific IOmem pointer | |
134 | * | |
135 | * The content of this data is implementation defined and used by the MSI | |
136 | * domain to store domain specific information which is requried for | |
137 | * interrupt chip callbacks. | |
138 | */ | |
139 | union msi_domain_cookie { | |
140 | u64 value; | |
141 | void *ptr; | |
142 | void __iomem *iobase; | |
143 | }; | |
144 | ||
145 | /** | |
146 | * struct msi_desc_data - Generic MSI descriptor data | |
147 | * @dcookie: Cookie for MSI domain specific data which is required | |
148 | * for irq_chip callbacks | |
149 | * @icookie: Cookie for the MSI interrupt instance provided by | |
150 | * the usage site to the allocation function | |
151 | * | |
152 | * The content of this data is implementation defined, e.g. PCI/IMS | |
153 | * implementations define the meaning of the data. The MSI core ignores | |
154 | * this data completely. | |
155 | */ | |
156 | struct msi_desc_data { | |
157 | union msi_domain_cookie dcookie; | |
158 | union msi_instance_cookie icookie; | |
159 | }; | |
160 | ||
645474e2 TG |
161 | #define MSI_MAX_INDEX ((unsigned int)USHRT_MAX) |
162 | ||
fc88419c JL |
163 | /** |
164 | * struct msi_desc - Descriptor structure for MSI based interrupts | |
fc88419c JL |
165 | * @irq: The base interrupt number |
166 | * @nvec_used: The number of vectors used | |
167 | * @dev: Pointer to the device which uses this descriptor | |
168 | * @msg: The last set MSI message cached for reuse | |
0972fa57 | 169 | * @affinity: Optional pointer to a cpu affinity mask for this descriptor |
bf5e758f | 170 | * @sysfs_attr: Pointer to sysfs device attribute |
fc88419c | 171 | * |
d7cc609f LG |
172 | * @write_msi_msg: Callback that may be called when the MSI message |
173 | * address or data changes | |
174 | * @write_msi_msg_data: Data parameter for the callback. | |
175 | * | |
20c6d424 | 176 | * @msi_index: Index of the msi descriptor |
0f180958 | 177 | * @pci: PCI specific msi descriptor data |
efd42049 | 178 | * @data: Generic MSI descriptor data |
fc88419c | 179 | */ |
3b7d1921 | 180 | struct msi_desc { |
fc88419c | 181 | /* Shared device/bus type independent data */ |
fc88419c JL |
182 | unsigned int irq; |
183 | unsigned int nvec_used; | |
184 | struct device *dev; | |
185 | struct msi_msg msg; | |
bec04037 | 186 | struct irq_affinity_desc *affinity; |
aaebdf8d JG |
187 | #ifdef CONFIG_IRQ_MSI_IOMMU |
188 | const void *iommu_cookie; | |
189 | #endif | |
bf5e758f TG |
190 | #ifdef CONFIG_SYSFS |
191 | struct device_attribute *sysfs_attrs; | |
192 | #endif | |
3b7d1921 | 193 | |
d7cc609f LG |
194 | void (*write_msi_msg)(struct msi_desc *entry, void *data); |
195 | void *write_msi_msg_data; | |
196 | ||
20c6d424 | 197 | u16 msi_index; |
efd42049 TG |
198 | union { |
199 | struct pci_msi_desc pci; | |
200 | struct msi_desc_data data; | |
201 | }; | |
3b7d1921 EB |
202 | }; |
203 | ||
1046f71d TG |
204 | /* |
205 | * Filter values for the MSI descriptor iterators and accessor functions. | |
206 | */ | |
207 | enum msi_desc_filter { | |
208 | /* All descriptors */ | |
209 | MSI_DESC_ALL, | |
210 | /* Descriptors which have no interrupt associated */ | |
211 | MSI_DESC_NOTASSOCIATED, | |
212 | /* Descriptors which have an interrupt associated */ | |
213 | MSI_DESC_ASSOCIATED, | |
214 | }; | |
215 | ||
f1139f90 TG |
216 | |
217 | /** | |
218 | * struct msi_dev_domain - The internals of MSI domain info per device | |
219 | * @store: Xarray for storing MSI descriptor pointers | |
64258eaa | 220 | * @irqdomain: Pointer to a per device interrupt domain |
f1139f90 TG |
221 | */ |
222 | struct msi_dev_domain { | |
223 | struct xarray store; | |
64258eaa | 224 | struct irq_domain *domain; |
f1139f90 TG |
225 | }; |
226 | ||
013bd8e5 TG |
227 | /** |
228 | * msi_device_data - MSI per device data | |
229 | * @properties: MSI properties which are interesting to drivers | |
fc22e7db | 230 | * @platform_data: Platform-MSI specific data |
cd6cf065 | 231 | * @mutex: Mutex protecting the MSI descriptor store |
f1139f90 | 232 | * @__domains: Internal data for per device MSI domains |
cd6cf065 | 233 | * @__iter_idx: Index to search the next entry for iterators |
013bd8e5 TG |
234 | */ |
235 | struct msi_device_data { | |
236 | unsigned long properties; | |
fc22e7db | 237 | struct platform_msi_priv_data *platform_data; |
b5f687f9 | 238 | struct mutex mutex; |
f1139f90 | 239 | struct msi_dev_domain __domains[MSI_MAX_DEVICE_IRQDOMAINS]; |
cd6cf065 | 240 | unsigned long __iter_idx; |
013bd8e5 TG |
241 | }; |
242 | ||
243 | int msi_setup_device_data(struct device *dev); | |
244 | ||
b5f687f9 TG |
245 | void msi_lock_descs(struct device *dev); |
246 | void msi_unlock_descs(struct device *dev); | |
cf15f43a | 247 | |
94ff94cf TG |
248 | struct msi_desc *msi_domain_first_desc(struct device *dev, unsigned int domid, |
249 | enum msi_desc_filter filter); | |
1046f71d TG |
250 | |
251 | /** | |
94ff94cf TG |
252 | * msi_first_desc - Get the first MSI descriptor of the default irqdomain |
253 | * @dev: Device to operate on | |
254 | * @filter: Descriptor state filter | |
255 | * | |
256 | * Must be called with the MSI descriptor mutex held, i.e. msi_lock_descs() | |
257 | * must be invoked before the call. | |
258 | * | |
259 | * Return: Pointer to the first MSI descriptor matching the search | |
260 | * criteria, NULL if none found. | |
261 | */ | |
262 | static inline struct msi_desc *msi_first_desc(struct device *dev, | |
263 | enum msi_desc_filter filter) | |
264 | { | |
265 | return msi_domain_first_desc(dev, MSI_DEFAULT_DOMAIN, filter); | |
266 | } | |
267 | ||
268 | struct msi_desc *msi_next_desc(struct device *dev, unsigned int domid, | |
269 | enum msi_desc_filter filter); | |
270 | ||
271 | /** | |
272 | * msi_domain_for_each_desc - Iterate the MSI descriptors in a specific domain | |
273 | * | |
274 | * @desc: struct msi_desc pointer used as iterator | |
275 | * @dev: struct device pointer - device to iterate | |
276 | * @domid: The id of the interrupt domain which should be walked. | |
277 | * @filter: Filter for descriptor selection | |
278 | * | |
279 | * Notes: | |
280 | * - The loop must be protected with a msi_lock_descs()/msi_unlock_descs() | |
281 | * pair. | |
282 | * - It is safe to remove a retrieved MSI descriptor in the loop. | |
283 | */ | |
284 | #define msi_domain_for_each_desc(desc, dev, domid, filter) \ | |
285 | for ((desc) = msi_domain_first_desc((dev), (domid), (filter)); (desc); \ | |
286 | (desc) = msi_next_desc((dev), (domid), (filter))) | |
287 | ||
288 | /** | |
289 | * msi_for_each_desc - Iterate the MSI descriptors in the default irqdomain | |
1046f71d TG |
290 | * |
291 | * @desc: struct msi_desc pointer used as iterator | |
292 | * @dev: struct device pointer - device to iterate | |
293 | * @filter: Filter for descriptor selection | |
294 | * | |
295 | * Notes: | |
296 | * - The loop must be protected with a msi_lock_descs()/msi_unlock_descs() | |
297 | * pair. | |
298 | * - It is safe to remove a retrieved MSI descriptor in the loop. | |
299 | */ | |
94ff94cf TG |
300 | #define msi_for_each_desc(desc, dev, filter) \ |
301 | msi_domain_for_each_desc((desc), (dev), MSI_DEFAULT_DOMAIN, (filter)) | |
1046f71d | 302 | |
25a98bd4 | 303 | #define msi_desc_to_dev(desc) ((desc)->dev) |
d31eb342 | 304 | |
aaebdf8d JG |
305 | #ifdef CONFIG_IRQ_MSI_IOMMU |
306 | static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc) | |
307 | { | |
308 | return desc->iommu_cookie; | |
309 | } | |
310 | ||
311 | static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, | |
312 | const void *iommu_cookie) | |
313 | { | |
314 | desc->iommu_cookie = iommu_cookie; | |
315 | } | |
316 | #else | |
317 | static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc) | |
318 | { | |
319 | return NULL; | |
320 | } | |
321 | ||
322 | static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, | |
323 | const void *iommu_cookie) | |
324 | { | |
325 | } | |
326 | #endif | |
327 | ||
fc8ab388 TG |
328 | int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, |
329 | struct msi_desc *init_desc); | |
330 | /** | |
331 | * msi_insert_msi_desc - Allocate and initialize a MSI descriptor in the | |
332 | * default irqdomain and insert it at @init_desc->msi_index | |
333 | * @dev: Pointer to the device for which the descriptor is allocated | |
334 | * @init_desc: Pointer to an MSI descriptor to initialize the new descriptor | |
335 | * | |
336 | * Return: 0 on success or an appropriate failure code. | |
337 | */ | |
338 | static inline int msi_insert_msi_desc(struct device *dev, struct msi_desc *init_desc) | |
339 | { | |
340 | return msi_domain_insert_msi_desc(dev, MSI_DEFAULT_DOMAIN, init_desc); | |
341 | } | |
342 | ||
377712c5 TG |
343 | void msi_domain_free_msi_descs_range(struct device *dev, unsigned int domid, |
344 | unsigned int first, unsigned int last); | |
645474e2 TG |
345 | |
346 | /** | |
377712c5 TG |
347 | * msi_free_msi_descs_range - Free a range of MSI descriptors of a device |
348 | * in the default irqdomain | |
349 | * | |
350 | * @dev: Device for which to free the descriptors | |
351 | * @first: Index to start freeing from (inclusive) | |
352 | * @last: Last index to be freed (inclusive) | |
353 | */ | |
354 | static inline void msi_free_msi_descs_range(struct device *dev, unsigned int first, | |
355 | unsigned int last) | |
356 | { | |
357 | msi_domain_free_msi_descs_range(dev, MSI_DEFAULT_DOMAIN, first, last); | |
358 | } | |
359 | ||
360 | /** | |
361 | * msi_free_msi_descs - Free all MSI descriptors of a device in the default irqdomain | |
645474e2 TG |
362 | * @dev: Device to free the descriptors |
363 | */ | |
364 | static inline void msi_free_msi_descs(struct device *dev) | |
365 | { | |
2f2940d1 | 366 | msi_free_msi_descs_range(dev, 0, MSI_MAX_INDEX); |
645474e2 | 367 | } |
60290525 | 368 | |
3b7d1921 | 369 | /* |
077ee78e TG |
370 | * The arch hooks to setup up msi irqs. Default functions are implemented |
371 | * as weak symbols so that they /can/ be overriden by architecture specific | |
b227be0d | 372 | * code if needed. These hooks can only be enabled by the architecture. |
077ee78e TG |
373 | * |
374 | * If CONFIG_PCI_MSI_ARCH_FALLBACKS is not selected they are replaced by | |
375 | * stubs with warnings. | |
3b7d1921 | 376 | */ |
077ee78e | 377 | #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS |
f7feaca7 | 378 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); |
3b7d1921 | 379 | void arch_teardown_msi_irq(unsigned int irq); |
2366d06e BH |
380 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); |
381 | void arch_teardown_msi_irqs(struct pci_dev *dev); | |
bf5e758f TG |
382 | #ifdef CONFIG_SYSFS |
383 | int msi_device_populate_sysfs(struct device *dev); | |
384 | void msi_device_destroy_sysfs(struct device *dev); | |
385 | #else /* CONFIG_SYSFS */ | |
386 | static inline int msi_device_populate_sysfs(struct device *dev) { return 0; } | |
387 | static inline void msi_device_destroy_sysfs(struct device *dev) { } | |
388 | #endif /* !CONFIG_SYSFS */ | |
24cff375 | 389 | #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */ |
077ee78e TG |
390 | |
391 | /* | |
ae72f315 TG |
392 | * The restore hook is still available even for fully irq domain based |
393 | * setups. Courtesy to XEN/X86. | |
077ee78e | 394 | */ |
ae72f315 | 395 | bool arch_restore_msi_irqs(struct pci_dev *dev); |
3b7d1921 | 396 | |
13e7accb | 397 | #ifdef CONFIG_GENERIC_MSI_IRQ |
d9109698 | 398 | |
aeeb5965 | 399 | #include <linux/irqhandler.h> |
d9109698 | 400 | |
f3cf8bb0 | 401 | struct irq_domain; |
552c494a | 402 | struct irq_domain_ops; |
f3cf8bb0 JL |
403 | struct irq_chip; |
404 | struct device_node; | |
be5436c8 | 405 | struct fwnode_handle; |
f3cf8bb0 JL |
406 | struct msi_domain_info; |
407 | ||
408 | /** | |
409 | * struct msi_domain_ops - MSI interrupt domain callbacks | |
410 | * @get_hwirq: Retrieve the resulting hw irq number | |
411 | * @msi_init: Domain specific init function for MSI interrupts | |
412 | * @msi_free: Domain specific function to free a MSI interrupts | |
d9109698 | 413 | * @msi_prepare: Prepare the allocation of the interrupts in the domain |
8f986fd7 TG |
414 | * @prepare_desc: Optional function to prepare the allocated MSI descriptor |
415 | * in the domain | |
d9109698 | 416 | * @set_desc: Set the msi descriptor for an interrupt |
43e9e705 TG |
417 | * @domain_alloc_irqs: Optional function to override the default allocation |
418 | * function. | |
419 | * @domain_free_irqs: Optional function to override the default free | |
420 | * function. | |
f6d3486a TG |
421 | * @msi_post_free: Optional function which is invoked after freeing |
422 | * all interrupts. | |
d9109698 | 423 | * |
1dd2c6a0 TG |
424 | * @get_hwirq, @msi_init and @msi_free are callbacks used by the underlying |
425 | * irqdomain. | |
d9109698 | 426 | * |
8f986fd7 | 427 | * @msi_check, @msi_prepare, @prepare_desc and @set_desc are callbacks used by the |
f2480e7d | 428 | * msi_domain_alloc/free_irqs*() variants. |
43e9e705 TG |
429 | * |
430 | * @domain_alloc_irqs, @domain_free_irqs can be used to override the | |
431 | * default allocation/free functions (__msi_domain_alloc/free_irqs). This | |
432 | * is initially for a wrapper around XENs seperate MSI universe which can't | |
433 | * be wrapped into the regular irq domains concepts by mere mortals. This | |
434 | * allows to universally use msi_domain_alloc/free_irqs without having to | |
435 | * special case XEN all over the place. | |
f3cf8bb0 JL |
436 | */ |
437 | struct msi_domain_ops { | |
aeeb5965 JL |
438 | irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info, |
439 | msi_alloc_info_t *arg); | |
f3cf8bb0 JL |
440 | int (*msi_init)(struct irq_domain *domain, |
441 | struct msi_domain_info *info, | |
442 | unsigned int virq, irq_hw_number_t hwirq, | |
aeeb5965 | 443 | msi_alloc_info_t *arg); |
f3cf8bb0 JL |
444 | void (*msi_free)(struct irq_domain *domain, |
445 | struct msi_domain_info *info, | |
446 | unsigned int virq); | |
d9109698 JL |
447 | int (*msi_prepare)(struct irq_domain *domain, |
448 | struct device *dev, int nvec, | |
449 | msi_alloc_info_t *arg); | |
8f986fd7 TG |
450 | void (*prepare_desc)(struct irq_domain *domain, msi_alloc_info_t *arg, |
451 | struct msi_desc *desc); | |
d9109698 JL |
452 | void (*set_desc)(msi_alloc_info_t *arg, |
453 | struct msi_desc *desc); | |
43e9e705 TG |
454 | int (*domain_alloc_irqs)(struct irq_domain *domain, |
455 | struct device *dev, int nvec); | |
456 | void (*domain_free_irqs)(struct irq_domain *domain, | |
457 | struct device *dev); | |
f6d3486a TG |
458 | void (*msi_post_free)(struct irq_domain *domain, |
459 | struct device *dev); | |
f3cf8bb0 JL |
460 | }; |
461 | ||
462 | /** | |
463 | * struct msi_domain_info - MSI interrupt domain data | |
aeeb5965 | 464 | * @flags: Flags to decribe features and capabilities |
22db089a | 465 | * @bus_token: The domain bus token |
61bf992f TG |
466 | * @hwsize: The hardware table size or the software index limit. |
467 | * If 0 then the size is considered unlimited and | |
468 | * gets initialized to the maximum software index limit | |
469 | * by the domain creation code. | |
aeeb5965 JL |
470 | * @ops: The callback data structure |
471 | * @chip: Optional: associated interrupt chip | |
472 | * @chip_data: Optional: associated interrupt chip data | |
473 | * @handler: Optional: associated interrupt flow handler | |
474 | * @handler_data: Optional: associated interrupt flow handler data | |
475 | * @handler_name: Optional: associated interrupt flow handler name | |
476 | * @data: Optional: domain specific data | |
f3cf8bb0 JL |
477 | */ |
478 | struct msi_domain_info { | |
22db089a AD |
479 | u32 flags; |
480 | enum irq_domain_bus_token bus_token; | |
61bf992f | 481 | unsigned int hwsize; |
22db089a AD |
482 | struct msi_domain_ops *ops; |
483 | struct irq_chip *chip; | |
484 | void *chip_data; | |
485 | irq_flow_handler_t handler; | |
486 | void *handler_data; | |
487 | const char *handler_name; | |
488 | void *data; | |
f3cf8bb0 JL |
489 | }; |
490 | ||
ebca4396 TG |
491 | /** |
492 | * struct msi_domain_template - Template for MSI device domains | |
493 | * @name: Storage for the resulting name. Filled in by the core. | |
494 | * @chip: Interrupt chip for this domain | |
495 | * @ops: MSI domain ops | |
496 | * @info: MSI domain info data | |
497 | */ | |
498 | struct msi_domain_template { | |
499 | char name[48]; | |
500 | struct irq_chip chip; | |
501 | struct msi_domain_ops ops; | |
502 | struct msi_domain_info info; | |
503 | }; | |
504 | ||
2d958b02 TG |
505 | /* |
506 | * Flags for msi_domain_info | |
507 | * | |
508 | * Bit 0-15: Generic MSI functionality which is not subject to restriction | |
509 | * by parent domains | |
510 | * | |
511 | * Bit 16-31: Functionality which depends on the underlying parent domain and | |
512 | * can be masked out by msi_parent_ops::init_dev_msi_info() when | |
513 | * a device MSI domain is initialized. | |
514 | */ | |
aeeb5965 JL |
515 | enum { |
516 | /* | |
517 | * Init non implemented ops callbacks with default MSI domain | |
518 | * callbacks. | |
519 | */ | |
520 | MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0), | |
521 | /* | |
522 | * Init non implemented chip callbacks with default MSI chip | |
523 | * callbacks. | |
524 | */ | |
525 | MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), | |
f3b0946d | 526 | /* Needs early activate, required for PCI */ |
2d958b02 | 527 | MSI_FLAG_ACTIVATE_EARLY = (1 << 2), |
22d0b12f TG |
528 | /* |
529 | * Must reactivate when irq is started even when | |
530 | * MSI_FLAG_ACTIVATE_EARLY has been set. | |
531 | */ | |
2d958b02 | 532 | MSI_FLAG_MUST_REACTIVATE = (1 << 3), |
013bd8e5 | 533 | /* Populate sysfs on alloc() and destroy it on free() */ |
2d958b02 | 534 | MSI_FLAG_DEV_SYSFS = (1 << 4), |
645474e2 | 535 | /* Allocate simple MSI descriptors */ |
2d958b02 | 536 | MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = (1 << 5), |
645474e2 | 537 | /* Free MSI descriptors */ |
2d958b02 | 538 | MSI_FLAG_FREE_MSI_DESCS = (1 << 6), |
3dad5f9a TG |
539 | /* |
540 | * Quirk to handle MSI implementations which do not provide | |
541 | * masking. Currently known to affect x86, but has to be partially | |
542 | * handled in the core MSI code. | |
543 | */ | |
2d958b02 TG |
544 | MSI_FLAG_NOMASK_QUIRK = (1 << 7), |
545 | ||
546 | /* Mask for the generic functionality */ | |
547 | MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), | |
548 | ||
549 | /* Mask for the domain specific functionality */ | |
550 | MSI_DOMAIN_FLAGS_MASK = GENMASK(31, 16), | |
551 | ||
552 | /* Support multiple PCI MSI interrupts */ | |
553 | MSI_FLAG_MULTI_PCI_MSI = (1 << 16), | |
554 | /* Support PCI MSIX interrupts */ | |
555 | MSI_FLAG_PCI_MSIX = (1 << 17), | |
556 | /* Is level-triggered capable, using two messages */ | |
557 | MSI_FLAG_LEVEL_CAPABLE = (1 << 18), | |
558 | /* MSI-X entries must be contiguous */ | |
559 | MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19), | |
b834e3c0 TG |
560 | /* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */ |
561 | MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20), | |
e23d4192 TG |
562 | /* Support for PCI/IMS */ |
563 | MSI_FLAG_PCI_IMS = (1 << 21), | |
aeeb5965 JL |
564 | }; |
565 | ||
b78780d9 TG |
566 | /** |
567 | * struct msi_parent_ops - MSI parent domain callbacks and configuration info | |
568 | * | |
569 | * @supported_flags: Required: The supported MSI flags of the parent domain | |
570 | * @prefix: Optional: Prefix for the domain and chip name | |
571 | * @init_dev_msi_info: Required: Callback for MSI parent domains to setup parent | |
572 | * domain specific domain flags, domain ops and interrupt chip | |
573 | * callbacks when a per device domain is created. | |
574 | */ | |
575 | struct msi_parent_ops { | |
576 | u32 supported_flags; | |
577 | const char *prefix; | |
578 | bool (*init_dev_msi_info)(struct device *dev, struct irq_domain *domain, | |
579 | struct irq_domain *msi_parent_domain, | |
580 | struct msi_domain_info *msi_child_info); | |
581 | }; | |
582 | ||
583 | bool msi_parent_init_dev_msi_info(struct device *dev, struct irq_domain *domain, | |
584 | struct irq_domain *msi_parent_domain, | |
585 | struct msi_domain_info *msi_child_info); | |
586 | ||
f3cf8bb0 JL |
587 | int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, |
588 | bool force); | |
589 | ||
be5436c8 | 590 | struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode, |
f3cf8bb0 JL |
591 | struct msi_domain_info *info, |
592 | struct irq_domain *parent); | |
4cd5f440 | 593 | |
27a6dea3 TG |
594 | bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, |
595 | const struct msi_domain_template *template, | |
596 | unsigned int hwsize, void *domain_data, | |
597 | void *chip_data); | |
598 | void msi_remove_device_irq_domain(struct device *dev, unsigned int domid); | |
599 | ||
26e91b75 TG |
600 | bool msi_match_device_irq_domain(struct device *dev, unsigned int domid, |
601 | enum irq_domain_bus_token bus_token); | |
602 | ||
f2480e7d TG |
603 | int msi_domain_alloc_irqs_range_locked(struct device *dev, unsigned int domid, |
604 | unsigned int first, unsigned int last); | |
605 | int msi_domain_alloc_irqs_range(struct device *dev, unsigned int domid, | |
606 | unsigned int first, unsigned int last); | |
607 | int msi_domain_alloc_irqs_all_locked(struct device *dev, unsigned int domid, int nirqs); | |
608 | ||
3d393b21 TG |
609 | struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, unsigned int index, |
610 | const struct irq_affinity_desc *affdesc, | |
611 | union msi_instance_cookie *cookie); | |
f2480e7d | 612 | |
4cd5f440 TG |
613 | void msi_domain_free_irqs_range_locked(struct device *dev, unsigned int domid, |
614 | unsigned int first, unsigned int last); | |
615 | void msi_domain_free_irqs_range(struct device *dev, unsigned int domid, | |
616 | unsigned int first, unsigned int last); | |
4cd5f440 TG |
617 | void msi_domain_free_irqs_all_locked(struct device *dev, unsigned int domid); |
618 | void msi_domain_free_irqs_all(struct device *dev, unsigned int domid); | |
619 | ||
f3cf8bb0 JL |
620 | struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); |
621 | ||
be5436c8 | 622 | struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, |
c09fcc4b MZ |
623 | struct msi_domain_info *info, |
624 | struct irq_domain *parent); | |
625 | int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, | |
626 | irq_write_msi_msg_t write_msi_msg); | |
627 | void platform_msi_domain_free_irqs(struct device *dev); | |
b2eba39b MZ |
628 | |
629 | /* When an MSI domain is used as an intermediate domain */ | |
630 | int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, | |
631 | int nvec, msi_alloc_info_t *args); | |
2145ac93 MZ |
632 | int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev, |
633 | int virq, int nvec, msi_alloc_info_t *args); | |
552c494a | 634 | struct irq_domain * |
1f83515b MZ |
635 | __platform_msi_create_device_domain(struct device *dev, |
636 | unsigned int nvec, | |
637 | bool is_tree, | |
638 | irq_write_msi_msg_t write_msi_msg, | |
639 | const struct irq_domain_ops *ops, | |
640 | void *host_data); | |
641 | ||
642 | #define platform_msi_create_device_domain(dev, nvec, write, ops, data) \ | |
643 | __platform_msi_create_device_domain(dev, nvec, false, write, ops, data) | |
644 | #define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \ | |
645 | __platform_msi_create_device_domain(dev, nvec, true, write, ops, data) | |
646 | ||
9835cec6 TG |
647 | int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int virq, |
648 | unsigned int nr_irqs); | |
649 | void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, | |
650 | unsigned int nvec); | |
552c494a | 651 | void *platform_msi_get_host_data(struct irq_domain *domain); |
13e7accb | 652 | #endif /* CONFIG_GENERIC_MSI_IRQ */ |
f3cf8bb0 | 653 | |
a474d3fb TG |
654 | /* PCI specific interfaces */ |
655 | #ifdef CONFIG_PCI_MSI | |
656 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc); | |
657 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg); | |
658 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); | |
659 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); | |
660 | void pci_msi_mask_irq(struct irq_data *data); | |
661 | void pci_msi_unmask_irq(struct irq_data *data); | |
be5436c8 | 662 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
663 | struct msi_domain_info *info, |
664 | struct irq_domain *parent); | |
b6eec9b7 | 665 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev); |
54fa97ee | 666 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); |
a474d3fb | 667 | #else /* CONFIG_PCI_MSI */ |
54fa97ee MZ |
668 | static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) |
669 | { | |
670 | return NULL; | |
671 | } | |
a474d3fb TG |
672 | static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) { } |
673 | #endif /* !CONFIG_PCI_MSI */ | |
3878eaef | 674 | |
3b7d1921 | 675 | #endif /* LINUX_MSI_H */ |