[linux-2.6-block.git] / include / linux / msi.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef LINUX_MSI_H
#define LINUX_MSI_H

#include <linux/kobject.h>
#include <linux/list.h>

struct msi_msg {
	u32	address_lo;	/* low 32 bits of msi message address */
	u32	address_hi;	/* high 32 bits of msi message address */
	u32	data;		/* 16 bits of msi message data */
};

extern int pci_msi_ignore_mask;
/* Helper functions */
struct irq_data;
struct msi_desc;
struct pci_dev;
struct platform_msi_priv_data;
void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
#ifdef CONFIG_GENERIC_MSI_IRQ
void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
#else
static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
{
}
#endif

typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
				    struct msi_msg *msg);

/**
 * platform_msi_desc - Platform device specific msi descriptor data
 * @msi_priv_data:	Pointer to platform private data
 * @msi_index:		The index of the MSI descriptor for multi MSI
 */
struct platform_msi_desc {
	struct platform_msi_priv_data	*msi_priv_data;
	u16				msi_index;
};

/**
 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
 * @msi_index:		The index of the MSI descriptor
 */
struct fsl_mc_msi_desc {
	u16				msi_index;
};

/**
 * ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
 * @dev_index: TISCI device index
 */
struct ti_sci_inta_msi_desc {
	u16	dev_index;
};

/**
 * struct msi_desc - Descriptor structure for MSI based interrupts
 * @list:	List head for management
 * @irq:	The base interrupt number
 * @nvec_used:	The number of vectors used
 * @dev:	Pointer to the device which uses this descriptor
 * @msg:	The last set MSI message cached for reuse
 * @affinity:	Optional pointer to a cpu affinity mask for this descriptor
 *
 * @write_msi_msg:	Callback that may be called when the MSI message
 *			address or data changes
 * @write_msi_msg_data:	Data parameter for the callback.
 *
 * @masked:	[PCI MSI/X] Mask bits
 * @is_msix:	[PCI MSI/X] True if MSI-X
 * @multiple:	[PCI MSI/X] log2 num of messages allocated
 * @multi_cap:	[PCI MSI/X] log2 num of messages supported
 * @maskbit:	[PCI MSI/X] Mask-Pending bit supported?
 * @is_64:	[PCI MSI/X] Address size: 0=32bit 1=64bit
 * @entry_nr:	[PCI MSI/X] Entry which is described by this descriptor
 * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
 * @mask_pos:	[PCI MSI]   Mask register position
 * @mask_base:	[PCI MSI-X] Mask register base address
 * @platform:	[platform]  Platform device specific msi descriptor data
 * @fsl_mc:	[fsl-mc]    FSL MC device specific msi descriptor data
 * @inta:	[INTA]	    TISCI based INTA specific msi descriptor data
 */
struct msi_desc {
	/* Shared device/bus type independent data */
	struct list_head		list;
	unsigned int			irq;
	unsigned int			nvec_used;
	struct device			*dev;
	struct msi_msg			msg;
	struct irq_affinity_desc	*affinity;
#ifdef CONFIG_IRQ_MSI_IOMMU
	const void			*iommu_cookie;
#endif

	void (*write_msi_msg)(struct msi_desc *entry, void *data);
	void *write_msi_msg_data;

	union {
		/* PCI MSI/X specific data */
		struct {
			u32 masked;
			struct {
				u8	is_msix		: 1;
				u8	multiple	: 3;
				u8	multi_cap	: 3;
				u8	maskbit		: 1;
				u8	is_64		: 1;
				u8	is_virtual	: 1;
				u16	entry_nr;
				unsigned default_irq;
			} msi_attrib;
			union {
				u8	mask_pos;
				void __iomem *mask_base;
			};
		};

		/*
		 * Non PCI variants add their data structure here. New
		 * entries need to use a named structure. We want
		 * proper name spaces for this. The PCI part is
		 * anonymous for now as it would require an immediate
		 * tree wide cleanup.
		 */
		struct platform_msi_desc platform;
		struct fsl_mc_msi_desc fsl_mc;
		struct ti_sci_inta_msi_desc inta;
	};
};

/* Helpers to hide struct msi_desc implementation details */
#define msi_desc_to_dev(desc)		((desc)->dev)
#define dev_to_msi_list(dev)		(&(dev)->msi_list)
#define first_msi_entry(dev)		\
	list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
#define for_each_msi_entry(desc, dev)	\
	list_for_each_entry((desc), dev_to_msi_list((dev)), list)
#define for_each_msi_entry_safe(desc, tmp, dev)	\
	list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)

#ifdef CONFIG_IRQ_MSI_IOMMU
static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
{
	return desc->iommu_cookie;
}

static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
					     const void *iommu_cookie)
{
	desc->iommu_cookie = iommu_cookie;
}
#else
static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
{
	return NULL;
}

static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
					     const void *iommu_cookie)
{
}
#endif

#ifdef CONFIG_PCI_MSI
#define first_pci_msi_entry(pdev)	first_msi_entry(&(pdev)->dev)
#define for_each_pci_msi_entry(desc, pdev)	\
	for_each_msi_entry((desc), &(pdev)->dev)

struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc);
void *msi_desc_to_pci_sysdata(struct msi_desc *desc);
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
#else /* CONFIG_PCI_MSI */
static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
{
	return NULL;
}
static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
{
}
#endif /* CONFIG_PCI_MSI */

struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
				 const struct irq_affinity_desc *affinity);
void free_msi_entry(struct msi_desc *entry);
void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);

u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
void pci_msi_mask_irq(struct irq_data *data);
void pci_msi_unmask_irq(struct irq_data *data);

/*
 * The arch hooks to setup up msi irqs. Those functions are
 * implemented as weak symbols so that they /can/ be overriden by
 * architecture specific code if needed.
 */
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
void arch_teardown_msi_irq(unsigned int irq);
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
void arch_teardown_msi_irqs(struct pci_dev *dev);
void arch_restore_msi_irqs(struct pci_dev *dev);

void default_teardown_msi_irqs(struct pci_dev *dev);
void default_restore_msi_irqs(struct pci_dev *dev);

struct msi_controller {
	struct module *owner;
	struct device *dev;
	struct device_node *of_node;
	struct list_head list;

	int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev,
			 struct msi_desc *desc);
	int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev,
			  int nvec, int type);
	void (*teardown_irq)(struct msi_controller *chip, unsigned int irq);
};

#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN

#include <linux/irqhandler.h>
#include <asm/msi.h>

struct irq_domain;
struct irq_domain_ops;
struct irq_chip;
struct device_node;
struct fwnode_handle;
struct msi_domain_info;

/**
 * struct msi_domain_ops - MSI interrupt domain callbacks
 * @get_hwirq:		Retrieve the resulting hw irq number
 * @msi_init:		Domain specific init function for MSI interrupts
 * @msi_free:		Domain specific function to free a MSI interrupts
 * @msi_check:		Callback for verification of the domain/info/dev data
 * @msi_prepare:	Prepare the allocation of the interrupts in the domain
 * @msi_finish:		Optional callback to finalize the allocation
 * @set_desc:		Set the msi descriptor for an interrupt
 * @handle_error:	Optional error handler if the allocation fails
 *
 * @get_hwirq, @msi_init and @msi_free are callbacks used by
 * msi_create_irq_domain() and related interfaces
 *
 * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
 * are callbacks used by msi_domain_alloc_irqs() and related
 * interfaces which are based on msi_desc.
 */
struct msi_domain_ops {
	irq_hw_number_t	(*get_hwirq)(struct msi_domain_info *info,
				     msi_alloc_info_t *arg);
	int		(*msi_init)(struct irq_domain *domain,
				    struct msi_domain_info *info,
				    unsigned int virq, irq_hw_number_t hwirq,
				    msi_alloc_info_t *arg);
	void		(*msi_free)(struct irq_domain *domain,
				    struct msi_domain_info *info,
				    unsigned int virq);
	int		(*msi_check)(struct irq_domain *domain,
				     struct msi_domain_info *info,
				     struct device *dev);
	int		(*msi_prepare)(struct irq_domain *domain,
				       struct device *dev, int nvec,
				       msi_alloc_info_t *arg);
	void		(*msi_finish)(msi_alloc_info_t *arg, int retval);
	void		(*set_desc)(msi_alloc_info_t *arg,
				    struct msi_desc *desc);
	int		(*handle_error)(struct irq_domain *domain,
					struct msi_desc *desc, int error);
};

/**
 * struct msi_domain_info - MSI interrupt domain data
 * @flags:		Flags to decribe features and capabilities
 * @ops:		The callback data structure
 * @chip:		Optional: associated interrupt chip
 * @chip_data:		Optional: associated interrupt chip data
 * @handler:		Optional: associated interrupt flow handler
 * @handler_data:	Optional: associated interrupt flow handler data
 * @handler_name:	Optional: associated interrupt flow handler name
 * @data:		Optional: domain specific data
 */
struct msi_domain_info {
	u32			flags;
	struct msi_domain_ops	*ops;
	struct irq_chip		*chip;
	void			*chip_data;
	irq_flow_handler_t	handler;
	void			*handler_data;
	const char		*handler_name;
	void			*data;
};

/* Flags for msi_domain_info */
enum {
	/*
	 * Init non implemented ops callbacks with default MSI domain
	 * callbacks.
	 */
	MSI_FLAG_USE_DEF_DOM_OPS	= (1 << 0),
	/*
	 * Init non implemented chip callbacks with default MSI chip
	 * callbacks.
	 */
	MSI_FLAG_USE_DEF_CHIP_OPS	= (1 << 1),
	/* Support multiple PCI MSI interrupts */
	MSI_FLAG_MULTI_PCI_MSI		= (1 << 2),
	/* Support PCI MSIX interrupts */
	MSI_FLAG_PCI_MSIX		= (1 << 3),
	/* Needs early activate, required for PCI */
	MSI_FLAG_ACTIVATE_EARLY		= (1 << 4),
	/*
	 * Must reactivate when irq is started even when
	 * MSI_FLAG_ACTIVATE_EARLY has been set.
	 */
	MSI_FLAG_MUST_REACTIVATE	= (1 << 5),
	/* Is level-triggered capable, using two messages */
	MSI_FLAG_LEVEL_CAPABLE		= (1 << 6),
};

int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
			    bool force);

struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
					 struct msi_domain_info *info,
					 struct irq_domain *parent);
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
			  int nvec);
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain);

struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
						  struct msi_domain_info *info,
						  struct irq_domain *parent);
int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
				   irq_write_msi_msg_t write_msi_msg);
void platform_msi_domain_free_irqs(struct device *dev);

/* When an MSI domain is used as an intermediate domain */
int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
			    int nvec, msi_alloc_info_t *args);
int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
			     int virq, int nvec, msi_alloc_info_t *args);
struct irq_domain *
__platform_msi_create_device_domain(struct device *dev,
				    unsigned int nvec,
				    bool is_tree,
				    irq_write_msi_msg_t write_msi_msg,
				    const struct irq_domain_ops *ops,
				    void *host_data);

#define platform_msi_create_device_domain(dev, nvec, write, ops, data)	\
	__platform_msi_create_device_domain(dev, nvec, false, write, ops, data)
#define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \
	__platform_msi_create_device_domain(dev, nvec, true, write, ops, data)

int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
			      unsigned int nr_irqs);
void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
			      unsigned int nvec);
void *platform_msi_get_host_data(struct irq_domain *domain);
#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */

#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg);
struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
					     struct msi_domain_info *info,
					     struct irq_domain *parent);
irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
					  struct msi_desc *desc);
int pci_msi_domain_check_cap(struct irq_domain *domain,
			     struct msi_domain_info *info, struct device *dev);
u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
#else
static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
{
	return NULL;
}
#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */

#endif /* LINUX_MSI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
3b7d1921 EB	2	#ifndef LINUX_MSI_H
	3	#define LINUX_MSI_H
	4
b50cac55	5	#include <linux/kobject.h>
4aa9bc95 ME	6	#include <linux/list.h>
4aa9bc95 ME	7
3b7d1921 EB	8	struct msi_msg {
	9	u32 address_lo; /* low 32 bits of msi message address */
	10	u32 address_hi; /* high 32 bits of msi message address */
	11	u32 data; /* 16 bits of msi message data */
	12	};
	13
38737d82	14	extern int pci_msi_ignore_mask;
c54c1879	15	/* Helper functions */
1c9db525	16	struct irq_data;
39431acb	17	struct msi_desc;
25a98bd4	18	struct pci_dev;
c09fcc4b	19	struct platform_msi_priv_data;
2366d06e	20	void __get_cached_msi_msg(struct msi_desc entry, struct msi_msg msg);
2f44e29c	21	#ifdef CONFIG_GENERIC_MSI_IRQ
2366d06e	22	void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
2f44e29c AB	23	#else
	24	static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
	25	{
	26	}
	27	#endif
891d4a48	28
c09fcc4b MZ	29	typedef void (irq_write_msi_msg_t)(struct msi_desc desc,
	30	struct msi_msg *msg);
	31
	32	/**
	33	* platform_msi_desc - Platform device specific msi descriptor data
	34	* @msi_priv_data: Pointer to platform private data
	35	* @msi_index: The index of the MSI descriptor for multi MSI
	36	*/
	37	struct platform_msi_desc {
	38	struct platform_msi_priv_data *msi_priv_data;
	39	u16 msi_index;
	40	};
	41
550308e4 GR	42	/**
	43	* fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
	44	* @msi_index: The index of the MSI descriptor
	45	*/
	46	struct fsl_mc_msi_desc {
	47	u16 msi_index;
	48	};
	49
49b32315 LV	50	/**
	51	* ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
	52	* @dev_index: TISCI device index
	53	*/
	54	struct ti_sci_inta_msi_desc {
	55	u16 dev_index;
	56	};
	57
fc88419c JL	58	/**
	59	* struct msi_desc - Descriptor structure for MSI based interrupts
	60	* @list: List head for management
	61	* @irq: The base interrupt number
	62	* @nvec_used: The number of vectors used
	63	* @dev: Pointer to the device which uses this descriptor
	64	* @msg: The last set MSI message cached for reuse
0972fa57	65	* @affinity: Optional pointer to a cpu affinity mask for this descriptor
fc88419c	66	*
d7cc609f LG	67	* @write_msi_msg: Callback that may be called when the MSI message
	68	* address or data changes
	69	* @write_msi_msg_data: Data parameter for the callback.
	70	*
fc88419c JL	71	* @masked: [PCI MSI/X] Mask bits
	72	* @is_msix: [PCI MSI/X] True if MSI-X
	73	* @multiple: [PCI MSI/X] log2 num of messages allocated
	74	* @multi_cap: [PCI MSI/X] log2 num of messages supported
	75	* @maskbit: [PCI MSI/X] Mask-Pending bit supported?
	76	* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
	77	* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
	78	* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
	79	* @mask_pos: [PCI MSI] Mask register position
	80	* @mask_base: [PCI MSI-X] Mask register base address
c09fcc4b	81	* @platform: [platform] Platform device specific msi descriptor data
87840fb5	82	* @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
49b32315	83	* @inta: [INTA] TISCI based INTA specific msi descriptor data
fc88419c	84	*/
3b7d1921	85	struct msi_desc {
fc88419c JL	86	/* Shared device/bus type independent data */
	87	struct list_head list;
	88	unsigned int irq;
	89	unsigned int nvec_used;
	90	struct device *dev;
	91	struct msi_msg msg;
bec04037	92	struct irq_affinity_desc *affinity;
aaebdf8d JG	93	#ifdef CONFIG_IRQ_MSI_IOMMU
	94	const void *iommu_cookie;
	95	#endif
3b7d1921	96
d7cc609f LG	97	void (write_msi_msg)(struct msi_desc entry, void *data);
	98	void *write_msi_msg_data;
	99
264d9caa	100	union {
fc88419c JL	101	/* PCI MSI/X specific data */
	102	struct {
	103	u32 masked;
	104	struct {
ddd065e4 LG	105	u8 is_msix : 1;
	106	u8 multiple : 3;
	107	u8 multi_cap : 3;
	108	u8 maskbit : 1;
	109	u8 is_64 : 1;
d7cc609f	110	u8 is_virtual : 1;
ddd065e4	111	u16 entry_nr;
fc88419c JL	112	unsigned default_irq;
	113	} msi_attrib;
	114	union {
	115	u8 mask_pos;
	116	void __iomem *mask_base;
	117	};
	118	};
3b7d1921	119
fc88419c JL	120	/*
	121	* Non PCI variants add their data structure here. New
	122	* entries need to use a named structure. We want
	123	* proper name spaces for this. The PCI part is
	124	* anonymous for now as it would require an immediate
	125	* tree wide cleanup.
	126	*/
c09fcc4b	127	struct platform_msi_desc platform;
550308e4	128	struct fsl_mc_msi_desc fsl_mc;
49b32315	129	struct ti_sci_inta_msi_desc inta;
fc88419c	130	};
3b7d1921 EB	131	};
3b7d1921 EB	132
d31eb342	133	/* Helpers to hide struct msi_desc implementation details */
25a98bd4	134	#define msi_desc_to_dev(desc) ((desc)->dev)
4a7cc831	135	#define dev_to_msi_list(dev) (&(dev)->msi_list)
d31eb342 JL	136	#define first_msi_entry(dev) \
	137	list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
	138	#define for_each_msi_entry(desc, dev) \
	139	list_for_each_entry((desc), dev_to_msi_list((dev)), list)
81b1e6e6 MR	140	#define for_each_msi_entry_safe(desc, tmp, dev) \
81b1e6e6 MR	141	list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)
d31eb342	142
aaebdf8d JG	143	#ifdef CONFIG_IRQ_MSI_IOMMU
	144	static inline const void msi_desc_get_iommu_cookie(struct msi_desc desc)
	145	{
	146	return desc->iommu_cookie;
	147	}
	148
	149	static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
	150	const void *iommu_cookie)
	151	{
	152	desc->iommu_cookie = iommu_cookie;
	153	}
	154	#else
	155	static inline const void msi_desc_get_iommu_cookie(struct msi_desc desc)
	156	{
	157	return NULL;
	158	}
	159
	160	static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
	161	const void *iommu_cookie)
	162	{
	163	}
	164	#endif
	165
d31eb342 JL	166	#ifdef CONFIG_PCI_MSI
	167	#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
	168	#define for_each_pci_msi_entry(desc, pdev) \
	169	for_each_msi_entry((desc), &(pdev)->dev)
	170
25a98bd4	171	struct pci_dev msi_desc_to_pci_dev(struct msi_desc desc);
c179c9b9	172	void msi_desc_to_pci_sysdata(struct msi_desc desc);
2f44e29c	173	void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
c179c9b9 JL	174	#else /* CONFIG_PCI_MSI */
	175	static inline void msi_desc_to_pci_sysdata(struct msi_desc desc)
	176	{
	177	return NULL;
	178	}
2f44e29c AB	179	static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
	180	{
	181	}
d31eb342 JL	182	#endif /* CONFIG_PCI_MSI */
d31eb342 JL	183
28f4b041	184	struct msi_desc alloc_msi_entry(struct device dev, int nvec,
bec04037	185	const struct irq_affinity_desc *affinity);
aa48b6f7	186	void free_msi_entry(struct msi_desc *entry);
891d4a48	187	void __pci_read_msi_msg(struct msi_desc entry, struct msi_msg msg);
83a18912	188	void __pci_write_msi_msg(struct msi_desc entry, struct msi_msg msg);
83a18912	189
23ed8d57 TG	190	u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
	191	u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
	192	void pci_msi_mask_irq(struct irq_data *data);
	193	void pci_msi_unmask_irq(struct irq_data *data);
	194
3b7d1921	195	/*
4287d824 TP	196	* The arch hooks to setup up msi irqs. Those functions are
	197	* implemented as weak symbols so that they /can/ be overriden by
	198	* architecture specific code if needed.
3b7d1921	199	*/
f7feaca7	200	int arch_setup_msi_irq(struct pci_dev dev, struct msi_desc desc);
3b7d1921	201	void arch_teardown_msi_irq(unsigned int irq);
2366d06e BH	202	int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
2366d06e BH	203	void arch_teardown_msi_irqs(struct pci_dev *dev);
ac8344c4	204	void arch_restore_msi_irqs(struct pci_dev *dev);
4287d824 TP	205
4287d824 TP	206	void default_teardown_msi_irqs(struct pci_dev *dev);
ac8344c4	207	void default_restore_msi_irqs(struct pci_dev *dev);
3b7d1921	208
c2791b80	209	struct msi_controller {
0cbdcfcf TR	210	struct module *owner;
0cbdcfcf TR	211	struct device *dev;
0d5a6db3 TP	212	struct device_node *of_node;
0d5a6db3 TP	213	struct list_head list;
0cbdcfcf	214
c2791b80	215	int (setup_irq)(struct msi_controller chip, struct pci_dev *dev,
0cbdcfcf	216	struct msi_desc *desc);
339e5b44 LS	217	int (setup_irqs)(struct msi_controller chip, struct pci_dev *dev,
339e5b44 LS	218	int nvec, int type);
c2791b80	219	void (teardown_irq)(struct msi_controller chip, unsigned int irq);
0cbdcfcf TR	220	};
0cbdcfcf TR	221
f3cf8bb0	222	#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
d9109698	223
aeeb5965	224	#include <linux/irqhandler.h>
d9109698 JL	225	#include <asm/msi.h>
d9109698 JL	226
f3cf8bb0	227	struct irq_domain;
552c494a	228	struct irq_domain_ops;
f3cf8bb0 JL	229	struct irq_chip;
f3cf8bb0 JL	230	struct device_node;
be5436c8	231	struct fwnode_handle;
f3cf8bb0 JL	232	struct msi_domain_info;
	233
	234	/**
	235	* struct msi_domain_ops - MSI interrupt domain callbacks
	236	* @get_hwirq: Retrieve the resulting hw irq number
	237	* @msi_init: Domain specific init function for MSI interrupts
	238	* @msi_free: Domain specific function to free a MSI interrupts
d9109698 JL	239	* @msi_check: Callback for verification of the domain/info/dev data
d9109698 JL	240	* @msi_prepare: Prepare the allocation of the interrupts in the domain
1d1e8cdc	241	* @msi_finish: Optional callback to finalize the allocation
d9109698 JL	242	* @set_desc: Set the msi descriptor for an interrupt
	243	* @handle_error: Optional error handler if the allocation fails
	244	*
	245	* @get_hwirq, @msi_init and @msi_free are callbacks used by
	246	* msi_create_irq_domain() and related interfaces
	247	*
	248	* @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
1d1e8cdc	249	* are callbacks used by msi_domain_alloc_irqs() and related
d9109698	250	* interfaces which are based on msi_desc.
f3cf8bb0 JL	251	*/
f3cf8bb0 JL	252	struct msi_domain_ops {
aeeb5965 JL	253	irq_hw_number_t (get_hwirq)(struct msi_domain_info info,
aeeb5965 JL	254	msi_alloc_info_t *arg);
f3cf8bb0 JL	255	int (msi_init)(struct irq_domain domain,
	256	struct msi_domain_info *info,
	257	unsigned int virq, irq_hw_number_t hwirq,
aeeb5965	258	msi_alloc_info_t *arg);
f3cf8bb0 JL	259	void (msi_free)(struct irq_domain domain,
	260	struct msi_domain_info *info,
	261	unsigned int virq);
d9109698 JL	262	int (msi_check)(struct irq_domain domain,
	263	struct msi_domain_info *info,
	264	struct device *dev);
	265	int (msi_prepare)(struct irq_domain domain,
	266	struct device *dev, int nvec,
	267	msi_alloc_info_t *arg);
	268	void (msi_finish)(msi_alloc_info_t arg, int retval);
	269	void (set_desc)(msi_alloc_info_t arg,
	270	struct msi_desc *desc);
	271	int (handle_error)(struct irq_domain domain,
	272	struct msi_desc *desc, int error);
f3cf8bb0 JL	273	};
	274
	275	/**
	276	* struct msi_domain_info - MSI interrupt domain data
aeeb5965 JL	277	* @flags: Flags to decribe features and capabilities
	278	* @ops: The callback data structure
	279	* @chip: Optional: associated interrupt chip
	280	* @chip_data: Optional: associated interrupt chip data
	281	* @handler: Optional: associated interrupt flow handler
	282	* @handler_data: Optional: associated interrupt flow handler data
	283	* @handler_name: Optional: associated interrupt flow handler name
	284	* @data: Optional: domain specific data
f3cf8bb0 JL	285	*/
f3cf8bb0 JL	286	struct msi_domain_info {
aeeb5965	287	u32 flags;
f3cf8bb0 JL	288	struct msi_domain_ops *ops;
f3cf8bb0 JL	289	struct irq_chip *chip;
aeeb5965 JL	290	void *chip_data;
	291	irq_flow_handler_t handler;
	292	void *handler_data;
	293	const char *handler_name;
f3cf8bb0 JL	294	void *data;
	295	};
	296
aeeb5965 JL	297	/* Flags for msi_domain_info */
	298	enum {
	299	/*
	300	* Init non implemented ops callbacks with default MSI domain
	301	* callbacks.
	302	*/
	303	MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0),
	304	/*
	305	* Init non implemented chip callbacks with default MSI chip
	306	* callbacks.
	307	*/
	308	MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1),
aeeb5965	309	/* Support multiple PCI MSI interrupts */
b6140914	310	MSI_FLAG_MULTI_PCI_MSI = (1 << 2),
aeeb5965	311	/* Support PCI MSIX interrupts */
b6140914	312	MSI_FLAG_PCI_MSIX = (1 << 3),
f3b0946d MZ	313	/* Needs early activate, required for PCI */
f3b0946d MZ	314	MSI_FLAG_ACTIVATE_EARLY = (1 << 4),
22d0b12f TG	315	/*
	316	* Must reactivate when irq is started even when
	317	* MSI_FLAG_ACTIVATE_EARLY has been set.
	318	*/
	319	MSI_FLAG_MUST_REACTIVATE = (1 << 5),
0be8153c MZ	320	/* Is level-triggered capable, using two messages */
0be8153c MZ	321	MSI_FLAG_LEVEL_CAPABLE = (1 << 6),
aeeb5965 JL	322	};
aeeb5965 JL	323
f3cf8bb0 JL	324	int msi_domain_set_affinity(struct irq_data data, const struct cpumask mask,
	325	bool force);
	326
be5436c8	327	struct irq_domain msi_create_irq_domain(struct fwnode_handle fwnode,
f3cf8bb0 JL	328	struct msi_domain_info *info,
f3cf8bb0 JL	329	struct irq_domain *parent);
d9109698 JL	330	int msi_domain_alloc_irqs(struct irq_domain domain, struct device dev,
	331	int nvec);
	332	void msi_domain_free_irqs(struct irq_domain domain, struct device dev);
f3cf8bb0 JL	333	struct msi_domain_info msi_get_domain_info(struct irq_domain domain);
f3cf8bb0 JL	334
be5436c8	335	struct irq_domain platform_msi_create_irq_domain(struct fwnode_handle fwnode,
c09fcc4b MZ	336	struct msi_domain_info *info,
	337	struct irq_domain *parent);
	338	int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
	339	irq_write_msi_msg_t write_msi_msg);
	340	void platform_msi_domain_free_irqs(struct device *dev);
b2eba39b MZ	341
	342	/* When an MSI domain is used as an intermediate domain */
	343	int msi_domain_prepare_irqs(struct irq_domain domain, struct device dev,
	344	int nvec, msi_alloc_info_t *args);
2145ac93 MZ	345	int msi_domain_populate_irqs(struct irq_domain domain, struct device dev,
2145ac93 MZ	346	int virq, int nvec, msi_alloc_info_t *args);
552c494a	347	struct irq_domain *
1f83515b MZ	348	__platform_msi_create_device_domain(struct device *dev,
	349	unsigned int nvec,
	350	bool is_tree,
	351	irq_write_msi_msg_t write_msi_msg,
	352	const struct irq_domain_ops *ops,
	353	void *host_data);
	354
	355	#define platform_msi_create_device_domain(dev, nvec, write, ops, data) \
	356	__platform_msi_create_device_domain(dev, nvec, false, write, ops, data)
	357	#define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \
	358	__platform_msi_create_device_domain(dev, nvec, true, write, ops, data)
	359
552c494a MZ	360	int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
	361	unsigned int nr_irqs);
	362	void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
	363	unsigned int nvec);
	364	void platform_msi_get_host_data(struct irq_domain domain);
f3cf8bb0 JL	365	#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
f3cf8bb0 JL	366
3878eaef JL	367	#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
3878eaef JL	368	void pci_msi_domain_write_msg(struct irq_data irq_data, struct msi_msg msg);
be5436c8	369	struct irq_domain pci_msi_create_irq_domain(struct fwnode_handle fwnode,
3878eaef JL	370	struct msi_domain_info *info,
3878eaef JL	371	struct irq_domain *parent);
3878eaef JL	372	irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
	373	struct msi_desc *desc);
	374	int pci_msi_domain_check_cap(struct irq_domain *domain,
	375	struct msi_domain_info info, struct device dev);
b6eec9b7	376	u32 pci_msi_domain_get_msi_rid(struct irq_domain domain, struct pci_dev pdev);
54fa97ee MZ	377	struct irq_domain pci_msi_get_device_domain(struct pci_dev pdev);
	378	#else
	379	static inline struct irq_domain pci_msi_get_device_domain(struct pci_dev pdev)
	380	{
	381	return NULL;
	382	}
3878eaef JL	383	#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
3878eaef JL	384
3b7d1921	385	#endif /* LINUX_MSI_H */