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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
100e9186 RD |
14 | #ifndef LINUX_MMC_DW_MMC_H |
15 | #define LINUX_MMC_DW_MMC_H | |
f95f3850 | 16 | |
f9c2a0dc | 17 | #include <linux/scatterlist.h> |
90c2143a | 18 | #include <linux/mmc/core.h> |
3fc7eaef | 19 | #include <linux/dmaengine.h> |
d6786fef | 20 | #include <linux/reset.h> |
f9c2a0dc | 21 | |
f95f3850 WN |
22 | #define MAX_MCI_SLOTS 2 |
23 | ||
24 | enum dw_mci_state { | |
25 | STATE_IDLE = 0, | |
26 | STATE_SENDING_CMD, | |
27 | STATE_SENDING_DATA, | |
28 | STATE_DATA_BUSY, | |
29 | STATE_SENDING_STOP, | |
30 | STATE_DATA_ERROR, | |
01730558 DA |
31 | STATE_SENDING_CMD11, |
32 | STATE_WAITING_CMD11_DONE, | |
f95f3850 WN |
33 | }; |
34 | ||
35 | enum { | |
36 | EVENT_CMD_COMPLETE = 0, | |
37 | EVENT_XFER_COMPLETE, | |
38 | EVENT_DATA_COMPLETE, | |
39 | EVENT_DATA_ERROR, | |
f95f3850 WN |
40 | }; |
41 | ||
42 | struct mmc_data; | |
43 | ||
3fc7eaef SL |
44 | enum { |
45 | TRANS_MODE_PIO = 0, | |
46 | TRANS_MODE_IDMAC, | |
47 | TRANS_MODE_EDMAC | |
48 | }; | |
49 | ||
50 | struct dw_mci_dma_slave { | |
51 | struct dma_chan *ch; | |
52 | enum dma_transfer_direction direction; | |
53 | }; | |
54 | ||
f95f3850 WN |
55 | /** |
56 | * struct dw_mci - MMC controller state shared between all slots | |
57 | * @lock: Spinlock protecting the queue and associated data. | |
49b17858 | 58 | * @irq_lock: Spinlock protecting the INTMASK setting. |
f95f3850 | 59 | * @regs: Pointer to MMIO registers. |
76184ac1 | 60 | * @fifo_reg: Pointer to MMIO registers for data FIFO |
f95f3850 | 61 | * @sg: Scatterlist entry currently being processed by PIO code, if any. |
f9c2a0dc | 62 | * @sg_miter: PIO mapping scatterlist iterator. |
f95f3850 WN |
63 | * @cur_slot: The slot which is currently using the controller. |
64 | * @mrq: The request currently being processed on @cur_slot, | |
65 | * or NULL if the controller is idle. | |
66 | * @cmd: The command currently being sent to the card, or NULL. | |
67 | * @data: The data currently being transferred, or NULL if no data | |
68 | * transfer is in progress. | |
49b17858 SL |
69 | * @stop_abort: The command currently prepared for stoping transfer. |
70 | * @prev_blksz: The former transfer blksz record. | |
71 | * @timing: Record of current ios timing. | |
f95f3850 | 72 | * @use_dma: Whether DMA channel is initialized or not. |
03e8cb53 | 73 | * @using_dma: Whether DMA is in use for the current transfer. |
69d99fdc | 74 | * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. |
f95f3850 WN |
75 | * @sg_dma: Bus address of DMA buffer. |
76 | * @sg_cpu: Virtual address of DMA buffer. | |
77 | * @dma_ops: Pointer to platform-specific DMA callbacks. | |
78 | * @cmd_status: Snapshot of SR taken upon completion of the current | |
49b17858 | 79 | * @ring_size: Buffer size for idma descriptors. |
f95f3850 | 80 | * command. Only valid when EVENT_CMD_COMPLETE is pending. |
49b17858 SL |
81 | * @dms: structure of slave-dma private data. |
82 | * @phy_regs: physical address of controller's register map | |
f95f3850 WN |
83 | * @data_status: Snapshot of SR taken upon completion of the current |
84 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
85 | * EVENT_DATA_ERROR is pending. | |
86 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
87 | * to be sent. | |
88 | * @dir_status: Direction of current transfer. | |
89 | * @tasklet: Tasklet running the request state machine. | |
f95f3850 WN |
90 | * @pending_events: Bitmask of events flagged by the interrupt handler |
91 | * to be processed by the tasklet. | |
92 | * @completed_events: Bitmask of events which the state machine has | |
93 | * processed. | |
94 | * @state: Tasklet state. | |
95 | * @queue: List of slots waiting for access to the controller. | |
96 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus | |
97 | * rate and timeout calculations. | |
98 | * @current_speed: Configured rate of the controller. | |
99 | * @num_slots: Number of slots available. | |
49b17858 | 100 | * @fifoth_val: The value of FIFOTH register. |
4e0a5adf | 101 | * @verid: Denote Version ID. |
62ca8034 | 102 | * @dev: Device associated with the MMC controller. |
f95f3850 | 103 | * @pdata: Platform data associated with the MMC controller. |
800d78bf TA |
104 | * @drv_data: Driver specific data for identified variant of the controller |
105 | * @priv: Implementation defined private data. | |
f90a0612 TA |
106 | * @biu_clk: Pointer to bus interface unit clock instance. |
107 | * @ciu_clk: Pointer to card interface unit clock instance. | |
f95f3850 | 108 | * @slot: Slots sharing this MMC controller. |
b86d8253 | 109 | * @fifo_depth: depth of FIFO. |
f95f3850 | 110 | * @data_shift: log2 of FIFO item size. |
34b664a2 JH |
111 | * @part_buf_start: Start index in part_buf. |
112 | * @part_buf_count: Bytes of partial data in part_buf. | |
113 | * @part_buf: Simple buffer for partial fifo reads/writes. | |
f95f3850 WN |
114 | * @push_data: Pointer to FIFO push function. |
115 | * @pull_data: Pointer to FIFO pull function. | |
49b17858 | 116 | * @vqmmc_enabled: Status of vqmmc, should be true or false. |
62ca8034 SH |
117 | * @irq_flags: The flags to be passed to request_irq. |
118 | * @irq: The irq value to be passed to request_irq. | |
76756234 | 119 | * @sdio_id0: Number of slot0 in the SDIO interrupt registers. |
49b17858 | 120 | * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. |
57e10486 | 121 | * @dto_timer: Timer for broken data transfer over scheme. |
f95f3850 WN |
122 | * |
123 | * Locking | |
124 | * ======= | |
125 | * | |
126 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
127 | * @cur_slot, @mrq and @state. These must always be updated | |
128 | * at the same time while holding @lock. | |
129 | * | |
f8c58c11 DA |
130 | * @irq_lock is an irq-safe spinlock protecting the INTMASK register |
131 | * to allow the interrupt handler to modify it directly. Held for only long | |
132 | * enough to read-modify-write INTMASK and no other locks are grabbed when | |
133 | * holding this one. | |
134 | * | |
f95f3850 WN |
135 | * The @mrq field of struct dw_mci_slot is also protected by @lock, |
136 | * and must always be written at the same time as the slot is added to | |
137 | * @queue. | |
138 | * | |
139 | * @pending_events and @completed_events are accessed using atomic bit | |
140 | * operations, so they don't need any locking. | |
141 | * | |
142 | * None of the fields touched by the interrupt handler need any | |
143 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
144 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
145 | * interrupts must be disabled and @data_status updated with a | |
146 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
25985edc | 147 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
f95f3850 WN |
148 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
149 | * bytes_xfered field of @data must be written. This is ensured by | |
150 | * using barriers. | |
151 | */ | |
152 | struct dw_mci { | |
153 | spinlock_t lock; | |
f8c58c11 | 154 | spinlock_t irq_lock; |
f95f3850 | 155 | void __iomem *regs; |
76184ac1 | 156 | void __iomem *fifo_reg; |
f95f3850 WN |
157 | |
158 | struct scatterlist *sg; | |
f9c2a0dc | 159 | struct sg_mapping_iter sg_miter; |
f95f3850 WN |
160 | |
161 | struct dw_mci_slot *cur_slot; | |
162 | struct mmc_request *mrq; | |
163 | struct mmc_command *cmd; | |
164 | struct mmc_data *data; | |
90c2143a | 165 | struct mmc_command stop_abort; |
52426899 | 166 | unsigned int prev_blksz; |
f1d2736c | 167 | unsigned char timing; |
f95f3850 WN |
168 | |
169 | /* DMA interface members*/ | |
170 | int use_dma; | |
03e8cb53 | 171 | int using_dma; |
69d99fdc | 172 | int dma_64bit_address; |
f95f3850 WN |
173 | |
174 | dma_addr_t sg_dma; | |
175 | void *sg_cpu; | |
8e2b36ea | 176 | const struct dw_mci_dma_ops *dma_ops; |
3fc7eaef | 177 | /* For idmac */ |
f95f3850 | 178 | unsigned int ring_size; |
3fc7eaef SL |
179 | |
180 | /* For edmac */ | |
181 | struct dw_mci_dma_slave *dms; | |
182 | /* Registers's physical base address */ | |
260b3164 | 183 | resource_size_t phy_regs; |
3fc7eaef | 184 | |
f95f3850 WN |
185 | u32 cmd_status; |
186 | u32 data_status; | |
187 | u32 stop_cmdr; | |
188 | u32 dir_status; | |
189 | struct tasklet_struct tasklet; | |
f95f3850 WN |
190 | unsigned long pending_events; |
191 | unsigned long completed_events; | |
192 | enum dw_mci_state state; | |
193 | struct list_head queue; | |
194 | ||
195 | u32 bus_hz; | |
196 | u32 current_speed; | |
197 | u32 num_slots; | |
e61cf118 | 198 | u32 fifoth_val; |
4e0a5adf | 199 | u16 verid; |
4a90920c | 200 | struct device *dev; |
f95f3850 | 201 | struct dw_mci_board *pdata; |
8e2b36ea | 202 | const struct dw_mci_drv_data *drv_data; |
800d78bf | 203 | void *priv; |
f90a0612 TA |
204 | struct clk *biu_clk; |
205 | struct clk *ciu_clk; | |
f95f3850 WN |
206 | struct dw_mci_slot *slot[MAX_MCI_SLOTS]; |
207 | ||
208 | /* FIFO push and pull */ | |
b86d8253 | 209 | int fifo_depth; |
f95f3850 | 210 | int data_shift; |
34b664a2 JH |
211 | u8 part_buf_start; |
212 | u8 part_buf_count; | |
213 | union { | |
214 | u16 part_buf16; | |
215 | u32 part_buf32; | |
216 | u64 part_buf; | |
217 | }; | |
f95f3850 WN |
218 | void (*push_data)(struct dw_mci *host, void *buf, int cnt); |
219 | void (*pull_data)(struct dw_mci *host, void *buf, int cnt); | |
220 | ||
51da2240 | 221 | bool vqmmc_enabled; |
62ca8034 | 222 | unsigned long irq_flags; /* IRQ flags */ |
d676188e | 223 | int irq; |
76756234 AK |
224 | |
225 | int sdio_id0; | |
5c935165 DA |
226 | |
227 | struct timer_list cmd11_timer; | |
57e10486 | 228 | struct timer_list dto_timer; |
f95f3850 WN |
229 | }; |
230 | ||
231 | /* DMA ops for Internal/External DMAC interface */ | |
232 | struct dw_mci_dma_ops { | |
233 | /* DMA Ops */ | |
234 | int (*init)(struct dw_mci *host); | |
3fc7eaef SL |
235 | int (*start)(struct dw_mci *host, unsigned int sg_len); |
236 | void (*complete)(void *host); | |
f95f3850 WN |
237 | void (*stop)(struct dw_mci *host); |
238 | void (*cleanup)(struct dw_mci *host); | |
239 | void (*exit)(struct dw_mci *host); | |
240 | }; | |
241 | ||
f95f3850 WN |
242 | struct dma_pdata; |
243 | ||
f95f3850 WN |
244 | /* Board platform data */ |
245 | struct dw_mci_board { | |
246 | u32 num_slots; | |
247 | ||
c3665006 | 248 | unsigned int bus_hz; /* Clock speed at the cclk_in pad */ |
f95f3850 | 249 | |
5f1a4dd0 LJ |
250 | u32 caps; /* Capabilities */ |
251 | u32 caps2; /* More capabilities */ | |
ab269128 | 252 | u32 pm_caps; /* PM capabilities */ |
b86d8253 JH |
253 | /* |
254 | * Override fifo depth. If 0, autodetect it from the FIFOTH register, | |
255 | * but note that this may not be reliable after a bootloader has used | |
256 | * it. | |
257 | */ | |
258 | unsigned int fifo_depth; | |
fc3d7720 | 259 | |
f95f3850 WN |
260 | /* delay in mS before detecting cards after interrupt */ |
261 | u32 detect_delay_ms; | |
262 | ||
d6786fef | 263 | struct reset_control *rstc; |
f95f3850 WN |
264 | struct dw_mci_dma_ops *dma_ops; |
265 | struct dma_pdata *data; | |
f95f3850 WN |
266 | }; |
267 | ||
100e9186 | 268 | #endif /* LINUX_MMC_DW_MMC_H */ |