[linux-2.6-block.git] / include / linux / mlx5 / qp.h

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_QP_H
#define MLX5_QP_H

#include <linux/mlx5/device.h>
#include <linux/mlx5/driver.h>

#define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_to_be32(0x100)
/* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
#define MLX5_SIG_WQE_SIZE	(MLX5_SEND_WQE_BB * 8)
#define MLX5_DIF_SIZE		8
#define MLX5_STRIDE_BLOCK_OP	0x400
#define MLX5_CPY_GRD_MASK	0xc0
#define MLX5_CPY_APP_MASK	0x30
#define MLX5_CPY_REF_MASK	0x0f
#define MLX5_BSF_INC_REFTAG	(1 << 6)
#define MLX5_BSF_INL_VALID	(1 << 15)
#define MLX5_BSF_REFRESH_DIF	(1 << 14)
#define MLX5_BSF_REPEAT_BLOCK	(1 << 7)
#define MLX5_BSF_APPTAG_ESCAPE	0x1
#define MLX5_BSF_APPREF_ESCAPE	0x2

enum mlx5_qp_optpar {
	MLX5_QP_OPTPAR_ALT_ADDR_PATH		= 1 << 0,
	MLX5_QP_OPTPAR_RRE			= 1 << 1,
	MLX5_QP_OPTPAR_RAE			= 1 << 2,
	MLX5_QP_OPTPAR_RWE			= 1 << 3,
	MLX5_QP_OPTPAR_PKEY_INDEX		= 1 << 4,
	MLX5_QP_OPTPAR_Q_KEY			= 1 << 5,
	MLX5_QP_OPTPAR_RNR_TIMEOUT		= 1 << 6,
	MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH	= 1 << 7,
	MLX5_QP_OPTPAR_SRA_MAX			= 1 << 8,
	MLX5_QP_OPTPAR_RRA_MAX			= 1 << 9,
	MLX5_QP_OPTPAR_PM_STATE			= 1 << 10,
	MLX5_QP_OPTPAR_RETRY_COUNT		= 1 << 12,
	MLX5_QP_OPTPAR_RNR_RETRY		= 1 << 13,
	MLX5_QP_OPTPAR_ACK_TIMEOUT		= 1 << 14,
	MLX5_QP_OPTPAR_LAG_TX_AFF		= 1 << 15,
	MLX5_QP_OPTPAR_PRI_PORT			= 1 << 16,
	MLX5_QP_OPTPAR_SRQN			= 1 << 18,
	MLX5_QP_OPTPAR_CQN_RCV			= 1 << 19,
	MLX5_QP_OPTPAR_DC_HS			= 1 << 20,
	MLX5_QP_OPTPAR_DC_KEY			= 1 << 21,
	MLX5_QP_OPTPAR_COUNTER_SET_ID		= 1 << 25,
};

enum mlx5_qp_state {
	MLX5_QP_STATE_RST			= 0,
	MLX5_QP_STATE_INIT			= 1,
	MLX5_QP_STATE_RTR			= 2,
	MLX5_QP_STATE_RTS			= 3,
	MLX5_QP_STATE_SQER			= 4,
	MLX5_QP_STATE_SQD			= 5,
	MLX5_QP_STATE_ERR			= 6,
	MLX5_QP_STATE_SQ_DRAINING		= 7,
	MLX5_QP_STATE_SUSPENDED			= 9,
	MLX5_QP_NUM_STATE,
	MLX5_QP_STATE,
	MLX5_QP_STATE_BAD,
};

enum {
	MLX5_SQ_STATE_NA	= MLX5_SQC_STATE_ERR + 1,
	MLX5_SQ_NUM_STATE	= MLX5_SQ_STATE_NA + 1,
	MLX5_RQ_STATE_NA	= MLX5_RQC_STATE_ERR + 1,
	MLX5_RQ_NUM_STATE	= MLX5_RQ_STATE_NA + 1,
};

enum {
	MLX5_QP_ST_RC				= 0x0,
	MLX5_QP_ST_UC				= 0x1,
	MLX5_QP_ST_UD				= 0x2,
	MLX5_QP_ST_XRC				= 0x3,
	MLX5_QP_ST_MLX				= 0x4,
	MLX5_QP_ST_DCI				= 0x5,
	MLX5_QP_ST_DCT				= 0x6,
	MLX5_QP_ST_QP0				= 0x7,
	MLX5_QP_ST_QP1				= 0x8,
	MLX5_QP_ST_RAW_ETHERTYPE		= 0x9,
	MLX5_QP_ST_RAW_IPV6			= 0xa,
	MLX5_QP_ST_SNIFFER			= 0xb,
	MLX5_QP_ST_SYNC_UMR			= 0xe,
	MLX5_QP_ST_PTP_1588			= 0xd,
	MLX5_QP_ST_REG_UMR			= 0xc,
	MLX5_QP_ST_MAX
};

enum {
	MLX5_QP_PM_MIGRATED			= 0x3,
	MLX5_QP_PM_ARMED			= 0x0,
	MLX5_QP_PM_REARM			= 0x1
};

enum {
	MLX5_NON_ZERO_RQ	= 0x0,
	MLX5_SRQ_RQ		= 0x1,
	MLX5_CRQ_RQ		= 0x2,
	MLX5_ZERO_LEN_RQ	= 0x3
};

/* TODO REM */
enum {
	/* params1 */
	MLX5_QP_BIT_SRE				= 1 << 15,
	MLX5_QP_BIT_SWE				= 1 << 14,
	MLX5_QP_BIT_SAE				= 1 << 13,
	/* params2 */
	MLX5_QP_BIT_RRE				= 1 << 15,
	MLX5_QP_BIT_RWE				= 1 << 14,
	MLX5_QP_BIT_RAE				= 1 << 13,
	MLX5_QP_BIT_RIC				= 1 <<	4,
	MLX5_QP_BIT_CC_SLAVE_RECV		= 1 <<  2,
	MLX5_QP_BIT_CC_SLAVE_SEND		= 1 <<  1,
	MLX5_QP_BIT_CC_MASTER			= 1 <<  0
};

enum {
	MLX5_WQE_CTRL_CQ_UPDATE		= 2 << 2,
	MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE	= 3 << 2,
	MLX5_WQE_CTRL_SOLICITED		= 1 << 1,
	MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5,
};

enum {
	MLX5_SEND_WQE_DS	= 16,
	MLX5_SEND_WQE_BB	= 64,
};

#define MLX5_SEND_WQEBB_NUM_DS	(MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)

enum {
	MLX5_SEND_WQE_MAX_WQEBBS	= 16,
};

#define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQE_BB)

enum {
	MLX5_WQE_FMR_PERM_LOCAL_READ	= 1 << 27,
	MLX5_WQE_FMR_PERM_LOCAL_WRITE	= 1 << 28,
	MLX5_WQE_FMR_PERM_REMOTE_READ	= 1 << 29,
	MLX5_WQE_FMR_PERM_REMOTE_WRITE	= 1 << 30,
	MLX5_WQE_FMR_PERM_ATOMIC	= 1 << 31
};

enum {
	MLX5_FENCE_MODE_NONE			= 0 << 5,
	MLX5_FENCE_MODE_INITIATOR_SMALL		= 1 << 5,
	MLX5_FENCE_MODE_FENCE			= 2 << 5,
	MLX5_FENCE_MODE_STRONG_ORDERING		= 3 << 5,
	MLX5_FENCE_MODE_SMALL_AND_FENCE		= 4 << 5,
};

enum {
	MLX5_RCV_DBR	= 0,
	MLX5_SND_DBR	= 1,
};

enum {
	MLX5_FLAGS_INLINE	= 1<<7,
	MLX5_FLAGS_CHECK_FREE   = 1<<5,
};

struct mlx5_wqe_fmr_seg {
	__be32			flags;
	__be32			mem_key;
	__be64			buf_list;
	__be64			start_addr;
	__be64			reg_len;
	__be32			offset;
	__be32			page_size;
	u32			reserved[2];
};

struct mlx5_wqe_ctrl_seg {
	__be32			opmod_idx_opcode;
	__be32			qpn_ds;

	struct_group(trailer,

	u8			signature;
	u8			rsvd[2];
	u8			fm_ce_se;
	union {
		__be32		general_id;
		__be32		imm;
		__be32		umr_mkey;
		__be32		tis_tir_num;
	};

	); /* end of trailer group */
};

#define MLX5_WQE_CTRL_DS_MASK 0x3f
#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
#define MLX5_WQE_CTRL_QPN_SHIFT 8
#define MLX5_WQE_DS_UNITS 16
#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8

enum {
	MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
	MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
	MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
	MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
};

enum {
	MLX5_ETH_WQE_SVLAN              = 1 << 0,
	MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
	MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
	MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
	MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
	MLX5_ETH_WQE_INSERT_TRAILER     = 1 << 30,
	MLX5_ETH_WQE_INSERT_VLAN        = 1 << 15,
};

enum {
	MLX5_ETH_WQE_SWP_INNER_L3_IPV6  = 1 << 0,
	MLX5_ETH_WQE_SWP_INNER_L4_UDP   = 1 << 1,
	MLX5_ETH_WQE_SWP_OUTER_L3_IPV6  = 1 << 4,
	MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
};

enum {
	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
};

struct mlx5_wqe_eth_seg {
	u8              swp_outer_l4_offset;
	u8              swp_outer_l3_offset;
	u8              swp_inner_l4_offset;
	u8              swp_inner_l3_offset;
	u8              cs_flags;
	u8              swp_flags;
	__be16          mss;
	__be32          flow_table_metadata;
	union {
		struct {
			__be16 sz;
			union {
				u8     start[2];
				DECLARE_FLEX_ARRAY(u8, data);
			};
		} inline_hdr;
		struct {
			__be16 type;
			__be16 vlan_tci;
		} insert;
		__be32 trailer;
	};
};

struct mlx5_wqe_xrc_seg {
	__be32			xrc_srqn;
	u8			rsvd[12];
};

struct mlx5_wqe_masked_atomic_seg {
	__be64			swap_add;
	__be64			compare;
	__be64			swap_add_mask;
	__be64			compare_mask;
};

struct mlx5_base_av {
	union {
		struct {
			__be32	qkey;
			__be32	reserved;
		} qkey;
		__be64	dc_key;
	} key;
	__be32	dqp_dct;
	u8	stat_rate_sl;
	u8	fl_mlid;
	union {
		__be16	rlid;
		__be16  udp_sport;
	};
};

struct mlx5_av {
	union {
		struct {
			__be32	qkey;
			__be32	reserved;
		} qkey;
		__be64	dc_key;
	} key;
	__be32	dqp_dct;
	u8	stat_rate_sl;
	u8	fl_mlid;
	union {
		__be16	rlid;
		__be16  udp_sport;
	};
	u8	reserved0[4];
	u8	rmac[6];
	u8	tclass;
	u8	hop_limit;
	__be32	grh_gid_fl;
	u8	rgid[16];
};

struct mlx5_ib_ah {
	struct ib_ah		ibah;
	struct mlx5_av		av;
	u8			xmit_port;
};

static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
{
	return container_of(ibah, struct mlx5_ib_ah, ibah);
}

struct mlx5_wqe_datagram_seg {
	struct mlx5_av	av;
};

struct mlx5_wqe_raddr_seg {
	__be64			raddr;
	__be32			rkey;
	u32			reserved;
};

struct mlx5_wqe_atomic_seg {
	__be64			swap_add;
	__be64			compare;
};

struct mlx5_wqe_data_seg {
	__be32			byte_count;
	__be32			lkey;
	__be64			addr;
};

struct mlx5_wqe_umr_ctrl_seg {
	u8		flags;
	u8		rsvd0[3];
	__be16		xlt_octowords;
	union {
		__be16	xlt_offset;
		__be16	bsf_octowords;
	};
	__be64		mkey_mask;
	__be32		xlt_offset_47_16;
	u8		rsvd1[28];
};

struct mlx5_seg_set_psv {
	__be32		psv_num;
	__be16		syndrome;
	__be16		status;
	__be32		transient_sig;
	__be32		ref_tag;
};

struct mlx5_seg_get_psv {
	u8		rsvd[19];
	u8		num_psv;
	__be32		l_key;
	__be64		va;
	__be32		psv_index[4];
};

struct mlx5_seg_check_psv {
	u8		rsvd0[2];
	__be16		err_coalescing_op;
	u8		rsvd1[2];
	__be16		xport_err_op;
	u8		rsvd2[2];
	__be16		xport_err_mask;
	u8		rsvd3[7];
	u8		num_psv;
	__be32		l_key;
	__be64		va;
	__be32		psv_index[4];
};

struct mlx5_rwqe_sig {
	u8	rsvd0[4];
	u8	signature;
	u8	rsvd1[11];
};

struct mlx5_wqe_signature_seg {
	u8	rsvd0[4];
	u8	signature;
	u8	rsvd1[11];
};

#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff

struct mlx5_wqe_inline_seg {
	__be32	byte_count;
	__be32	data[];
};

enum mlx5_sig_type {
	MLX5_DIF_CRC = 0x1,
	MLX5_DIF_IPCS = 0x2,
};

struct mlx5_bsf_inl {
	__be16		vld_refresh;
	__be16		dif_apptag;
	__be32		dif_reftag;
	u8		sig_type;
	u8		rp_inv_seed;
	u8		rsvd[3];
	u8		dif_inc_ref_guard_check;
	__be16		dif_app_bitmask_check;
};

struct mlx5_bsf {
	struct mlx5_bsf_basic {
		u8		bsf_size_sbs;
		u8		check_byte_mask;
		union {
			u8	copy_byte_mask;
			u8	bs_selector;
			u8	rsvd_wflags;
		} wire;
		union {
			u8	bs_selector;
			u8	rsvd_mflags;
		} mem;
		__be32		raw_data_size;
		__be32		w_bfs_psv;
		__be32		m_bfs_psv;
	} basic;
	struct mlx5_bsf_ext {
		__be32		t_init_gen_pro_size;
		__be32		rsvd_epi_size;
		__be32		w_tfs_psv;
		__be32		m_tfs_psv;
	} ext;
	struct mlx5_bsf_inl	w_inl;
	struct mlx5_bsf_inl	m_inl;
};

struct mlx5_mtt {
	__be64		ptag;
};

struct mlx5_klm {
	__be32		bcount;
	__be32		key;
	__be64		va;
};

struct mlx5_ksm {
	__be32		reserved;
	__be32		key;
	__be64		va;
};

struct mlx5_stride_block_entry {
	__be16		stride;
	__be16		bcount;
	__be32		key;
	__be64		va;
};

struct mlx5_stride_block_ctrl_seg {
	__be32		bcount_per_cycle;
	__be32		op;
	__be32		repeat_count;
	u16		rsvd;
	__be16		num_entries;
};

struct mlx5_wqe_flow_update_ctrl_seg {
	__be32		flow_idx_update;
	__be32		dest_handle;
	u8		reserved0[40];
};

struct mlx5_wqe_header_modify_argument_update_seg {
	u8		argument_list[64];
};

struct mlx5_core_qp {
	struct mlx5_core_rsc_common	common; /* must be first */
	void (*event)		(struct mlx5_core_qp *, int);
	int			qpn;
	struct mlx5_rsc_debug	*dbg;
	int			pid;
	u16			uid;
};

struct mlx5_core_dct {
	struct mlx5_core_qp	mqp;
	struct completion	drained;
};

int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);

static inline const char *mlx5_qp_type_str(int type)
{
	switch (type) {
	case MLX5_QP_ST_RC: return "RC";
	case MLX5_QP_ST_UC: return "C";
	case MLX5_QP_ST_UD: return "UD";
	case MLX5_QP_ST_XRC: return "XRC";
	case MLX5_QP_ST_MLX: return "MLX";
	case MLX5_QP_ST_QP0: return "QP0";
	case MLX5_QP_ST_QP1: return "QP1";
	case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
	case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
	case MLX5_QP_ST_SNIFFER: return "SNIFFER";
	case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
	case MLX5_QP_ST_PTP_1588: return "PTP_1588";
	case MLX5_QP_ST_REG_UMR: return "REG_UMR";
	default: return "Invalid transport type";
	}
}

static inline const char *mlx5_qp_state_str(int state)
{
	switch (state) {
	case MLX5_QP_STATE_RST:
	return "RST";
	case MLX5_QP_STATE_INIT:
	return "INIT";
	case MLX5_QP_STATE_RTR:
	return "RTR";
	case MLX5_QP_STATE_RTS:
	return "RTS";
	case MLX5_QP_STATE_SQER:
	return "SQER";
	case MLX5_QP_STATE_SQD:
	return "SQD";
	case MLX5_QP_STATE_ERR:
	return "ERR";
	case MLX5_QP_STATE_SQ_DRAINING:
	return "SQ_DRAINING";
	case MLX5_QP_STATE_SUSPENDED:
	return "SUSPENDED";
	default: return "Invalid QP state";
	}
}

static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
{
	u8 supported_ts_cap = mlx5_get_roce_state(dev) ?
			      MLX5_CAP_ROCE(dev, qp_ts_format) :
			      MLX5_CAP_GEN(dev, sq_ts_format);

	return supported_ts_cap ? MLX5_TIMESTAMP_FORMAT_DEFAULT :
	       MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
}

#endif /* MLX5_QP_H */
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX5_QP_H
	34	#define MLX5_QP_H
	35
	36	#include <linux/mlx5/device.h>
	37	#include <linux/mlx5/driver.h>
	38
a419bfb7	39	#define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_to_be32(0x100)
38ca87c6 MG	40	/* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
38ca87c6 MG	41	#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
e6631814 SG	42	#define MLX5_DIF_SIZE 8
e6631814 SG	43	#define MLX5_STRIDE_BLOCK_OP 0x400
fd22f78c SG	44	#define MLX5_CPY_GRD_MASK 0xc0
	45	#define MLX5_CPY_APP_MASK 0x30
	46	#define MLX5_CPY_REF_MASK 0x0f
142537f4 SG	47	#define MLX5_BSF_INC_REFTAG (1 << 6)
	48	#define MLX5_BSF_INL_VALID (1 << 15)
	49	#define MLX5_BSF_REFRESH_DIF (1 << 14)
	50	#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
	51	#define MLX5_BSF_APPTAG_ESCAPE 0x1
	52	#define MLX5_BSF_APPREF_ESCAPE 0x2
e126ba97 EC	53
	54	enum mlx5_qp_optpar {
	55	MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
	56	MLX5_QP_OPTPAR_RRE = 1 << 1,
	57	MLX5_QP_OPTPAR_RAE = 1 << 2,
	58	MLX5_QP_OPTPAR_RWE = 1 << 3,
	59	MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
	60	MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
	61	MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
	62	MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
	63	MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
	64	MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
	65	MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
	66	MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
	67	MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
	68	MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
cfc1a89e	69	MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
e126ba97 EC	70	MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
	71	MLX5_QP_OPTPAR_SRQN = 1 << 18,
	72	MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
	73	MLX5_QP_OPTPAR_DC_HS = 1 << 20,
	74	MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
d14133dd	75	MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
e126ba97 EC	76	};
	77
	78	enum mlx5_qp_state {
	79	MLX5_QP_STATE_RST = 0,
	80	MLX5_QP_STATE_INIT = 1,
	81	MLX5_QP_STATE_RTR = 2,
	82	MLX5_QP_STATE_RTS = 3,
	83	MLX5_QP_STATE_SQER = 4,
	84	MLX5_QP_STATE_SQD = 5,
	85	MLX5_QP_STATE_ERR = 6,
	86	MLX5_QP_STATE_SQ_DRAINING = 7,
	87	MLX5_QP_STATE_SUSPENDED = 9,
6d2f89df	88	MLX5_QP_NUM_STATE,
	89	MLX5_QP_STATE,
	90	MLX5_QP_STATE_BAD,
	91	};
	92
	93	enum {
	94	MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
	95	MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
	96	MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
	97	MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
e126ba97 EC	98	};
	99
	100	enum {
	101	MLX5_QP_ST_RC = 0x0,
	102	MLX5_QP_ST_UC = 0x1,
	103	MLX5_QP_ST_UD = 0x2,
	104	MLX5_QP_ST_XRC = 0x3,
	105	MLX5_QP_ST_MLX = 0x4,
	106	MLX5_QP_ST_DCI = 0x5,
	107	MLX5_QP_ST_DCT = 0x6,
	108	MLX5_QP_ST_QP0 = 0x7,
	109	MLX5_QP_ST_QP1 = 0x8,
	110	MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
	111	MLX5_QP_ST_RAW_IPV6 = 0xa,
	112	MLX5_QP_ST_SNIFFER = 0xb,
	113	MLX5_QP_ST_SYNC_UMR = 0xe,
	114	MLX5_QP_ST_PTP_1588 = 0xd,
	115	MLX5_QP_ST_REG_UMR = 0xc,
	116	MLX5_QP_ST_MAX
	117	};
	118
	119	enum {
	120	MLX5_QP_PM_MIGRATED = 0x3,
	121	MLX5_QP_PM_ARMED = 0x0,
	122	MLX5_QP_PM_REARM = 0x1
	123	};
	124
	125	enum {
09a7d9ec SM	126	MLX5_NON_ZERO_RQ = 0x0,
	127	MLX5_SRQ_RQ = 0x1,
	128	MLX5_CRQ_RQ = 0x2,
	129	MLX5_ZERO_LEN_RQ = 0x3
e126ba97 EC	130	};
e126ba97 EC	131
09a7d9ec	132	/* TODO REM */
e126ba97 EC	133	enum {
	134	/* params1 */
	135	MLX5_QP_BIT_SRE = 1 << 15,
	136	MLX5_QP_BIT_SWE = 1 << 14,
	137	MLX5_QP_BIT_SAE = 1 << 13,
	138	/* params2 */
	139	MLX5_QP_BIT_RRE = 1 << 15,
	140	MLX5_QP_BIT_RWE = 1 << 14,
	141	MLX5_QP_BIT_RAE = 1 << 13,
	142	MLX5_QP_BIT_RIC = 1 << 4,
051f2630 LR	143	MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
	144	MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
	145	MLX5_QP_BIT_CC_MASTER = 1 << 0
e126ba97 EC	146	};
	147
	148	enum {
	149	MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
e281682b	150	MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
e126ba97	151	MLX5_WQE_CTRL_SOLICITED = 1 << 1,
00b9f0da	152	MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5,
e126ba97 EC	153	};
	154
	155	enum {
e281682b	156	MLX5_SEND_WQE_DS = 16,
e126ba97 EC	157	MLX5_SEND_WQE_BB = 64,
	158	};
	159
e281682b SM	160	#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
	161
	162	enum {
	163	MLX5_SEND_WQE_MAX_WQEBBS = 16,
	164	};
	165
e5a3cc83 MM	166	#define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQE_BB)
e5a3cc83 MM	167
e126ba97 EC	168	enum {
	169	MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
	170	MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
	171	MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
	172	MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
	173	MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
	174	};
	175
	176	enum {
	177	MLX5_FENCE_MODE_NONE = 0 << 5,
	178	MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
c9b25495	179	MLX5_FENCE_MODE_FENCE = 2 << 5,
e126ba97 EC	180	MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
	181	MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
	182	};
	183
e126ba97 EC	184	enum {
	185	MLX5_RCV_DBR = 0,
	186	MLX5_SND_DBR = 1,
	187	};
	188
e6631814 SG	189	enum {
	190	MLX5_FLAGS_INLINE = 1<<7,
	191	MLX5_FLAGS_CHECK_FREE = 1<<5,
	192	};
	193
e126ba97 EC	194	struct mlx5_wqe_fmr_seg {
	195	__be32 flags;
	196	__be32 mem_key;
	197	__be64 buf_list;
	198	__be64 start_addr;
	199	__be64 reg_len;
	200	__be32 offset;
	201	__be32 page_size;
	202	u32 reserved[2];
	203	};
	204
	205	struct mlx5_wqe_ctrl_seg {
	206	__be32 opmod_idx_opcode;
	207	__be32 qpn_ds;
2af7e566 SM	208
	209	struct_group(trailer,
	210
e126ba97 EC	211	u8 signature;
	212	u8 rsvd[2];
	213	u8 fm_ce_se;
0718edf5 TT	214	union {
	215	__be32 general_id;
	216	__be32 imm;
	217	__be32 umr_mkey;
2d1b69ed	218	__be32 tis_tir_num;
0718edf5	219	};
2af7e566 SM	220
2af7e566 SM	221	); /* end of trailer group */
e126ba97 EC	222	};
e126ba97 EC	223
c1395a2a	224	#define MLX5_WQE_CTRL_DS_MASK 0x3f
7bdf65d4 HE	225	#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
7bdf65d4 HE	226	#define MLX5_WQE_CTRL_QPN_SHIFT 8
c1395a2a	227	#define MLX5_WQE_DS_UNITS 16
7bdf65d4 HE	228	#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
	229	#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
	230	#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
c1395a2a	231
e281682b SM	232	enum {
	233	MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
	234	MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
	235	MLX5_ETH_WQE_L3_CSUM = 1 << 6,
	236	MLX5_ETH_WQE_L4_CSUM = 1 << 7,
	237	};
	238
2b31f7ae	239	enum {
4382c7b9	240	MLX5_ETH_WQE_SVLAN = 1 << 0,
2dc8b524 RS	241	MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
	242	MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
	243	MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
	244	MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
	245	MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
2b31f7ae SM	246	MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
	247	};
	248
547eede0 IT	249	enum {
	250	MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
	251	MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
	252	MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
	253	MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
	254	};
	255
9b9d454d HN	256	enum {
9b9d454d HN	257	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
e467b283	258	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
9b9d454d HN	259	};
9b9d454d HN	260
e281682b	261	struct mlx5_wqe_eth_seg {
547eede0 IT	262	u8 swp_outer_l4_offset;
	263	u8 swp_outer_l3_offset;
	264	u8 swp_inner_l4_offset;
	265	u8 swp_inner_l3_offset;
e281682b	266	u8 cs_flags;
547eede0	267	u8 swp_flags;
e281682b	268	__be16 mss;
9b9d454d	269	__be32 flow_table_metadata;
2b31f7ae SM	270	union {
	271	struct {
	272	__be16 sz;
4d5e86a5 LR	273	union {
	274	u8 start[2];
	275	DECLARE_FLEX_ARRAY(u8, data);
	276	};
2b31f7ae SM	277	} inline_hdr;
	278	struct {
	279	__be16 type;
	280	__be16 vlan_tci;
	281	} insert;
2dc8b524	282	__be32 trailer;
2b31f7ae	283	};
e281682b SM	284	};
e281682b SM	285
e126ba97 EC	286	struct mlx5_wqe_xrc_seg {
	287	__be32 xrc_srqn;
	288	u8 rsvd[12];
	289	};
	290
	291	struct mlx5_wqe_masked_atomic_seg {
	292	__be64 swap_add;
	293	__be64 compare;
	294	__be64 swap_add_mask;
	295	__be64 compare_mask;
	296	};
	297
17d2f88f AK	298	struct mlx5_base_av {
	299	union {
	300	struct {
	301	__be32 qkey;
	302	__be32 reserved;
	303	} qkey;
	304	__be64 dc_key;
	305	} key;
	306	__be32 dqp_dct;
	307	u8 stat_rate_sl;
	308	u8 fl_mlid;
	309	union {
	310	__be16 rlid;
	311	__be16 udp_sport;
	312	};
	313	};
	314
e126ba97 EC	315	struct mlx5_av {
	316	union {
	317	struct {
	318	__be32 qkey;
	319	__be32 reserved;
	320	} qkey;
	321	__be64 dc_key;
	322	} key;
	323	__be32 dqp_dct;
	324	u8 stat_rate_sl;
	325	u8 fl_mlid;
2811ba51 AS	326	union {
	327	__be16 rlid;
	328	__be16 udp_sport;
	329	};
	330	u8 reserved0[4];
	331	u8 rmac[6];
e126ba97 EC	332	u8 tclass;
	333	u8 hop_limit;
	334	__be32 grh_gid_fl;
	335	u8 rgid[16];
	336	};
	337
25854544 SM	338	struct mlx5_ib_ah {
	339	struct ib_ah ibah;
	340	struct mlx5_av av;
cfc1a89e	341	u8 xmit_port;
25854544 SM	342	};
	343
	344	static inline struct mlx5_ib_ah to_mah(struct ib_ah ibah)
	345	{
	346	return container_of(ibah, struct mlx5_ib_ah, ibah);
	347	}
	348
e126ba97 EC	349	struct mlx5_wqe_datagram_seg {
	350	struct mlx5_av av;
	351	};
	352
	353	struct mlx5_wqe_raddr_seg {
	354	__be64 raddr;
	355	__be32 rkey;
	356	u32 reserved;
	357	};
	358
	359	struct mlx5_wqe_atomic_seg {
	360	__be64 swap_add;
	361	__be64 compare;
	362	};
	363
	364	struct mlx5_wqe_data_seg {
	365	__be32 byte_count;
	366	__be32 lkey;
	367	__be64 addr;
	368	};
	369
	370	struct mlx5_wqe_umr_ctrl_seg {
	371	u8 flags;
	372	u8 rsvd0[3];
31616255 AK	373	__be16 xlt_octowords;
	374	union {
	375	__be16 xlt_offset;
	376	__be16 bsf_octowords;
	377	};
e126ba97	378	__be64 mkey_mask;
31616255 AK	379	__be32 xlt_offset_47_16;
31616255 AK	380	u8 rsvd1[28];
e126ba97 EC	381	};
	382
	383	struct mlx5_seg_set_psv {
	384	__be32 psv_num;
	385	__be16 syndrome;
	386	__be16 status;
	387	__be32 transient_sig;
	388	__be32 ref_tag;
	389	};
	390
	391	struct mlx5_seg_get_psv {
	392	u8 rsvd[19];
	393	u8 num_psv;
	394	__be32 l_key;
	395	__be64 va;
	396	__be32 psv_index[4];
	397	};
	398
	399	struct mlx5_seg_check_psv {
	400	u8 rsvd0[2];
	401	__be16 err_coalescing_op;
	402	u8 rsvd1[2];
	403	__be16 xport_err_op;
	404	u8 rsvd2[2];
	405	__be16 xport_err_mask;
	406	u8 rsvd3[7];
	407	u8 num_psv;
	408	__be32 l_key;
	409	__be64 va;
	410	__be32 psv_index[4];
	411	};
	412
	413	struct mlx5_rwqe_sig {
	414	u8 rsvd0[4];
	415	u8 signature;
	416	u8 rsvd1[11];
	417	};
	418
	419	struct mlx5_wqe_signature_seg {
	420	u8 rsvd0[4];
	421	u8 signature;
	422	u8 rsvd1[11];
	423	};
	424
7bdf65d4 HE	425	#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
7bdf65d4 HE	426
e126ba97 EC	427	struct mlx5_wqe_inline_seg {
e126ba97 EC	428	__be32 byte_count;
b6ca09cb	429	__be32 data[];
e126ba97 EC	430	};
e126ba97 EC	431
142537f4 SG	432	enum mlx5_sig_type {
	433	MLX5_DIF_CRC = 0x1,
	434	MLX5_DIF_IPCS = 0x2,
	435	};
	436
	437	struct mlx5_bsf_inl {
	438	__be16 vld_refresh;
	439	__be16 dif_apptag;
	440	__be32 dif_reftag;
	441	u8 sig_type;
	442	u8 rp_inv_seed;
	443	u8 rsvd[3];
	444	u8 dif_inc_ref_guard_check;
	445	__be16 dif_app_bitmask_check;
	446	};
	447
e6631814 SG	448	struct mlx5_bsf {
	449	struct mlx5_bsf_basic {
	450	u8 bsf_size_sbs;
	451	u8 check_byte_mask;
	452	union {
	453	u8 copy_byte_mask;
	454	u8 bs_selector;
	455	u8 rsvd_wflags;
	456	} wire;
	457	union {
	458	u8 bs_selector;
	459	u8 rsvd_mflags;
	460	} mem;
	461	__be32 raw_data_size;
	462	__be32 w_bfs_psv;
	463	__be32 m_bfs_psv;
	464	} basic;
	465	struct mlx5_bsf_ext {
	466	__be32 t_init_gen_pro_size;
	467	__be32 rsvd_epi_size;
	468	__be32 w_tfs_psv;
	469	__be32 m_tfs_psv;
	470	} ext;
142537f4 SG	471	struct mlx5_bsf_inl w_inl;
142537f4 SG	472	struct mlx5_bsf_inl m_inl;
e6631814 SG	473	};
e6631814 SG	474
31616255 AK	475	struct mlx5_mtt {
	476	__be64 ptag;
	477	};
	478
e6631814 SG	479	struct mlx5_klm {
	480	__be32 bcount;
	481	__be32 key;
	482	__be64 va;
	483	};
	484
6470d2e7 MM	485	struct mlx5_ksm {
	486	__be32 reserved;
	487	__be32 key;
	488	__be64 va;
	489	};
	490
e6631814 SG	491	struct mlx5_stride_block_entry {
	492	__be16 stride;
	493	__be16 bcount;
	494	__be32 key;
	495	__be64 va;
	496	};
	497
	498	struct mlx5_stride_block_ctrl_seg {
	499	__be32 bcount_per_cycle;
	500	__be32 op;
	501	__be32 repeat_count;
	502	u16 rsvd;
	503	__be16 num_entries;
	504	};
	505
977c4a3e YK	506	struct mlx5_wqe_flow_update_ctrl_seg {
	507	__be32 flow_idx_update;
	508	__be32 dest_handle;
	509	u8 reserved0[40];
	510	};
	511
	512	struct mlx5_wqe_header_modify_argument_update_seg {
	513	u8 argument_list[64];
	514	};
	515
e126ba97	516	struct mlx5_core_qp {
5903325a	517	struct mlx5_core_rsc_common common; /* must be first */
e126ba97 EC	518	void (event) (struct mlx5_core_qp , int);
e126ba97 EC	519	int qpn;
e126ba97 EC	520	struct mlx5_rsc_debug *dbg;
e126ba97 EC	521	int pid;
4ac63ec7	522	u16 uid;
e126ba97 EC	523	};
e126ba97 EC	524
57cda166 MS	525	struct mlx5_core_dct {
	526	struct mlx5_core_qp mqp;
	527	struct completion drained;
	528	};
	529
e126ba97 EC	530	int mlx5_debug_qp_add(struct mlx5_core_dev dev, struct mlx5_core_qp qp);
e126ba97 EC	531	void mlx5_debug_qp_remove(struct mlx5_core_dev dev, struct mlx5_core_qp qp);
27e95603	532
db81a5c3 EC	533	static inline const char *mlx5_qp_type_str(int type)
	534	{
	535	switch (type) {
	536	case MLX5_QP_ST_RC: return "RC";
	537	case MLX5_QP_ST_UC: return "C";
	538	case MLX5_QP_ST_UD: return "UD";
	539	case MLX5_QP_ST_XRC: return "XRC";
	540	case MLX5_QP_ST_MLX: return "MLX";
	541	case MLX5_QP_ST_QP0: return "QP0";
	542	case MLX5_QP_ST_QP1: return "QP1";
	543	case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
	544	case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
	545	case MLX5_QP_ST_SNIFFER: return "SNIFFER";
	546	case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
	547	case MLX5_QP_ST_PTP_1588: return "PTP_1588";
	548	case MLX5_QP_ST_REG_UMR: return "REG_UMR";
	549	default: return "Invalid transport type";
	550	}
	551	}
	552
	553	static inline const char *mlx5_qp_state_str(int state)
	554	{
	555	switch (state) {
	556	case MLX5_QP_STATE_RST:
	557	return "RST";
	558	case MLX5_QP_STATE_INIT:
	559	return "INIT";
	560	case MLX5_QP_STATE_RTR:
	561	return "RTR";
	562	case MLX5_QP_STATE_RTS:
	563	return "RTS";
	564	case MLX5_QP_STATE_SQER:
	565	return "SQER";
	566	case MLX5_QP_STATE_SQD:
	567	return "SQD";
	568	case MLX5_QP_STATE_ERR:
	569	return "ERR";
	570	case MLX5_QP_STATE_SQ_DRAINING:
	571	return "SQ_DRAINING";
	572	case MLX5_QP_STATE_SUSPENDED:
	573	return "SUSPENDED";
	574	default: return "Invalid QP state";
	575	}
	576	}
	577
4806f1e2 MG	578	static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
4806f1e2 MG	579	{
0c5275bf OHT	580	u8 supported_ts_cap = mlx5_get_roce_state(dev) ?
	581	MLX5_CAP_ROCE(dev, qp_ts_format) :
	582	MLX5_CAP_GEN(dev, sq_ts_format);
	583
	584	return supported_ts_cap ? MLX5_TIMESTAMP_FORMAT_DEFAULT :
	585	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
4806f1e2 MG	586	}
4806f1e2 MG	587
e126ba97	588	#endif /* MLX5_QP_H */