[linux-block.git] / include / linux / mlx5 / port.h

/*
 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_PORT_H__
#define __MLX5_PORT_H__

#include <linux/mlx5/driver.h>

enum mlx5_beacon_duration {
	MLX5_BEACON_DURATION_OFF = 0x0,
	MLX5_BEACON_DURATION_INF = 0xffff,
};

enum mlx5_module_id {
	MLX5_MODULE_ID_SFP              = 0x3,
	MLX5_MODULE_ID_QSFP             = 0xC,
	MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
	MLX5_MODULE_ID_QSFP28           = 0x11,
	MLX5_MODULE_ID_DSFP		= 0x1B,
};

enum mlx5_an_status {
	MLX5_AN_UNAVAILABLE = 0,
	MLX5_AN_COMPLETE    = 1,
	MLX5_AN_FAILED      = 2,
	MLX5_AN_LINK_UP     = 3,
	MLX5_AN_LINK_DOWN   = 4,
};

#define MLX5_I2C_ADDR_LOW		0x50
#define MLX5_I2C_ADDR_HIGH		0x51
#define MLX5_EEPROM_PAGE_LENGTH		256
#define MLX5_EEPROM_HIGH_PAGE_LENGTH	128

struct mlx5_module_eeprom_query_params {
	u16 size;
	u16 offset;
	u16 i2c_address;
	u32 page;
	u32 bank;
	u32 module_number;
};

enum mlx5e_link_mode {
	MLX5E_1000BASE_CX_SGMII	 = 0,
	MLX5E_1000BASE_KX	 = 1,
	MLX5E_10GBASE_CX4	 = 2,
	MLX5E_10GBASE_KX4	 = 3,
	MLX5E_10GBASE_KR	 = 4,
	MLX5E_20GBASE_KR2	 = 5,
	MLX5E_40GBASE_CR4	 = 6,
	MLX5E_40GBASE_KR4	 = 7,
	MLX5E_56GBASE_R4	 = 8,
	MLX5E_10GBASE_CR	 = 12,
	MLX5E_10GBASE_SR	 = 13,
	MLX5E_10GBASE_ER	 = 14,
	MLX5E_40GBASE_SR4	 = 15,
	MLX5E_40GBASE_LR4	 = 16,
	MLX5E_50GBASE_SR2	 = 18,
	MLX5E_100GBASE_CR4	 = 20,
	MLX5E_100GBASE_SR4	 = 21,
	MLX5E_100GBASE_KR4	 = 22,
	MLX5E_100GBASE_LR4	 = 23,
	MLX5E_100BASE_TX	 = 24,
	MLX5E_1000BASE_T	 = 25,
	MLX5E_10GBASE_T		 = 26,
	MLX5E_25GBASE_CR	 = 27,
	MLX5E_25GBASE_KR	 = 28,
	MLX5E_25GBASE_SR	 = 29,
	MLX5E_50GBASE_CR2	 = 30,
	MLX5E_50GBASE_KR2	 = 31,
	MLX5E_LINK_MODES_NUMBER,
};

enum mlx5e_ext_link_mode {
	MLX5E_SGMII_100M			= 0,
	MLX5E_1000BASE_X_SGMII			= 1,
	MLX5E_5GBASE_R				= 3,
	MLX5E_10GBASE_XFI_XAUI_1		= 4,
	MLX5E_40GBASE_XLAUI_4_XLPPI_4		= 5,
	MLX5E_25GAUI_1_25GBASE_CR_KR		= 6,
	MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	= 7,
	MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR	= 8,
	MLX5E_CAUI_4_100GBASE_CR4_KR4		= 9,
	MLX5E_100GAUI_2_100GBASE_CR2_KR2	= 10,
	MLX5E_100GAUI_1_100GBASE_CR_KR		= 11,
	MLX5E_200GAUI_4_200GBASE_CR4_KR4	= 12,
	MLX5E_200GAUI_2_200GBASE_CR2_KR2	= 13,
	MLX5E_400GAUI_8				= 15,
	MLX5E_400GAUI_4_400GBASE_CR4_KR4	= 16,
	MLX5E_EXT_LINK_MODES_NUMBER,
};

enum mlx5e_connector_type {
	MLX5E_PORT_UNKNOWN	= 0,
	MLX5E_PORT_NONE			= 1,
	MLX5E_PORT_TP			= 2,
	MLX5E_PORT_AUI			= 3,
	MLX5E_PORT_BNC			= 4,
	MLX5E_PORT_MII			= 5,
	MLX5E_PORT_FIBRE		= 6,
	MLX5E_PORT_DA			= 7,
	MLX5E_PORT_OTHER		= 8,
	MLX5E_CONNECTOR_TYPE_NUMBER,
};

enum mlx5_ptys_width {
	MLX5_PTYS_WIDTH_1X	= 1 << 0,
	MLX5_PTYS_WIDTH_2X	= 1 << 1,
	MLX5_PTYS_WIDTH_4X	= 1 << 2,
	MLX5_PTYS_WIDTH_8X	= 1 << 3,
	MLX5_PTYS_WIDTH_12X	= 1 << 4,
};

struct mlx5_port_eth_proto {
	u32 cap;
	u32 admin;
	u32 oper;
};

#define MLX5E_PROT_MASK(link_mode) (1U << link_mode)
#define MLX5_GET_ETH_PROTO(reg, out, ext, field)	\
	(ext ? MLX5_GET(reg, out, ext_##field) :	\
	MLX5_GET(reg, out, field))

int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
			 int ptys_size, int proto_mask, u8 local_port);

int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
			    u16 *proto_oper, u8 local_port);
void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
			       enum mlx5_port_status status);
int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
				 enum mlx5_port_status *status);
int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);

int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
			      u8 port);

int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
			      u8 *vl_hw_cap, u8 local_port);

int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
int mlx5_query_port_pause(struct mlx5_core_dev *dev,
			  u32 *rx_pause, u32 *tx_pause);

int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
			u8 *pfc_en_rx);

int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
				  u16 stall_critical_watermark,
				  u16 stall_minor_watermark);
int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
				    u16 *stall_critical_watermark, u16 *stall_minor_watermark);

int mlx5_max_tc(struct mlx5_core_dev *mdev);

int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
			    u8 prio, u8 *tc);
int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
			     u8 tc, u8 *tc_group);
int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
				u8 tc, u8 *bw_pct);
int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				    u8 *max_bw_value,
				    u8 *max_bw_unit);
int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				   u8 *max_bw_value,
				   u8 *max_bw_unit);
int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);

int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
			 bool *enabled);
int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
			     u16 offset, u16 size, u8 *data);
int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
				     struct mlx5_module_eeprom_query_params *params, u8 *data);

int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);

int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);

int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
			      struct mlx5_port_eth_proto *eproto);
bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev);
u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper,
			 bool force_legacy);
u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed,
			      bool force_legacy);
int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);

#endif /* __MLX5_PORT_H__ */
Commit	Line	Data
ada68c31 AS	1	/*
	2	* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_PORT_H__
	34	#define __MLX5_PORT_H__
	35
	36	#include <linux/mlx5/driver.h>
	37
da54d24e GP	38	enum mlx5_beacon_duration {
	39	MLX5_BEACON_DURATION_OFF = 0x0,
	40	MLX5_BEACON_DURATION_INF = 0xffff,
	41	};
	42
bb64143e GP	43	enum mlx5_module_id {
	44	MLX5_MODULE_ID_SFP = 0x3,
	45	MLX5_MODULE_ID_QSFP = 0xC,
	46	MLX5_MODULE_ID_QSFP_PLUS = 0xD,
	47	MLX5_MODULE_ID_QSFP28 = 0x11,
4c88fa41	48	MLX5_MODULE_ID_DSFP = 0x1B,
bb64143e GP	49	};
bb64143e GP	50
52244d96 GP	51	enum mlx5_an_status {
	52	MLX5_AN_UNAVAILABLE = 0,
	53	MLX5_AN_COMPLETE = 1,
	54	MLX5_AN_FAILED = 2,
	55	MLX5_AN_LINK_UP = 3,
	56	MLX5_AN_LINK_DOWN = 4,
	57	};
	58
bb64143e GP	59	#define MLX5_I2C_ADDR_LOW 0x50
	60	#define MLX5_I2C_ADDR_HIGH 0x51
	61	#define MLX5_EEPROM_PAGE_LENGTH 256
a708fb7b	62	#define MLX5_EEPROM_HIGH_PAGE_LENGTH 128
bb64143e	63
e19b0a34 VT	64	struct mlx5_module_eeprom_query_params {
	65	u16 size;
	66	u16 offset;
	67	u16 i2c_address;
	68	u32 page;
	69	u32 bank;
	70	u32 module_number;
	71	};
	72
8cca30a7 NO	73	enum mlx5e_link_mode {
	74	MLX5E_1000BASE_CX_SGMII = 0,
	75	MLX5E_1000BASE_KX = 1,
	76	MLX5E_10GBASE_CX4 = 2,
	77	MLX5E_10GBASE_KX4 = 3,
	78	MLX5E_10GBASE_KR = 4,
	79	MLX5E_20GBASE_KR2 = 5,
	80	MLX5E_40GBASE_CR4 = 6,
	81	MLX5E_40GBASE_KR4 = 7,
	82	MLX5E_56GBASE_R4 = 8,
	83	MLX5E_10GBASE_CR = 12,
	84	MLX5E_10GBASE_SR = 13,
	85	MLX5E_10GBASE_ER = 14,
	86	MLX5E_40GBASE_SR4 = 15,
	87	MLX5E_40GBASE_LR4 = 16,
	88	MLX5E_50GBASE_SR2 = 18,
	89	MLX5E_100GBASE_CR4 = 20,
	90	MLX5E_100GBASE_SR4 = 21,
	91	MLX5E_100GBASE_KR4 = 22,
	92	MLX5E_100GBASE_LR4 = 23,
	93	MLX5E_100BASE_TX = 24,
	94	MLX5E_1000BASE_T = 25,
	95	MLX5E_10GBASE_T = 26,
	96	MLX5E_25GBASE_CR = 27,
	97	MLX5E_25GBASE_KR = 28,
	98	MLX5E_25GBASE_SR = 29,
	99	MLX5E_50GBASE_CR2 = 30,
	100	MLX5E_50GBASE_KR2 = 31,
	101	MLX5E_LINK_MODES_NUMBER,
	102	};
	103
a08b4ed1 AL	104	enum mlx5e_ext_link_mode {
	105	MLX5E_SGMII_100M = 0,
	106	MLX5E_1000BASE_X_SGMII = 1,
	107	MLX5E_5GBASE_R = 3,
	108	MLX5E_10GBASE_XFI_XAUI_1 = 4,
	109	MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
	110	MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
	111	MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
	112	MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
	113	MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
	114	MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
12fdafb8	115	MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
a08b4ed1	116	MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
12fdafb8	117	MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
a08b4ed1	118	MLX5E_400GAUI_8 = 15,
12fdafb8	119	MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
a08b4ed1 AL	120	MLX5E_EXT_LINK_MODES_NUMBER,
	121	};
	122
5b4793f8 EBE	123	enum mlx5e_connector_type {
	124	MLX5E_PORT_UNKNOWN = 0,
	125	MLX5E_PORT_NONE = 1,
	126	MLX5E_PORT_TP = 2,
	127	MLX5E_PORT_AUI = 3,
	128	MLX5E_PORT_BNC = 4,
	129	MLX5E_PORT_MII = 5,
	130	MLX5E_PORT_FIBRE = 6,
	131	MLX5E_PORT_DA = 7,
	132	MLX5E_PORT_OTHER = 8,
	133	MLX5E_CONNECTOR_TYPE_NUMBER,
	134	};
	135
e27014bd AL	136	enum mlx5_ptys_width {
	137	MLX5_PTYS_WIDTH_1X = 1 << 0,
	138	MLX5_PTYS_WIDTH_2X = 1 << 1,
	139	MLX5_PTYS_WIDTH_4X = 1 << 2,
	140	MLX5_PTYS_WIDTH_8X = 1 << 3,
	141	MLX5_PTYS_WIDTH_12X = 1 << 4,
	142	};
	143
028522e2 GP	144	struct mlx5_port_eth_proto {
	145	u32 cap;
	146	u32 admin;
	147	u32 oper;
	148	};
	149
0276bd3a	150	#define MLX5E_PROT_MASK(link_mode) (1U << link_mode)
a08b4ed1 AL	151	#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
	152	(ext ? MLX5_GET(reg, out, ext_##field) : \
	153	MLX5_GET(reg, out, field))
8cca30a7	154
ada68c31 AS	155	int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
	156	int mlx5_query_port_ptys(struct mlx5_core_dev dev, u32 ptys,
	157	int ptys_size, int proto_mask, u8 local_port);
639bf441 AL	158
	159	int mlx5_query_ib_port_oper(struct mlx5_core_dev dev, u16 link_width_oper,
	160	u16 *proto_oper, u8 local_port);
667daeda	161	void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
ada68c31 AS	162	int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
	163	enum mlx5_port_status status);
	164	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
	165	enum mlx5_port_status *status);
da54d24e	166	int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
ada68c31	167
046339ea SM	168	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
	169	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, u16 max_mtu, u8 port);
	170	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, u16 oper_mtu,
ada68c31 AS	171	u8 port);
	172
	173	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
	174	u8 *vl_hw_cap, u8 local_port);
	175
	176	int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
	177	int mlx5_query_port_pause(struct mlx5_core_dev *dev,
	178	u32 rx_pause, u32 tx_pause);
	179
ad909eb0 AS	180	int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
	181	int mlx5_query_port_pfc(struct mlx5_core_dev dev, u8 pfc_en_tx,
	182	u8 *pfc_en_rx);
	183
2afa609f IK	184	int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
	185	u16 stall_critical_watermark,
	186	u16 stall_minor_watermark);
	187	int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
	188	u16 stall_critical_watermark, u16 stall_minor_watermark);
	189
4f3961ee SM	190	int mlx5_max_tc(struct mlx5_core_dev *mdev);
	191
	192	int mlx5_set_port_prio_tc(struct mlx5_core_dev mdev, u8 prio_tc);
3a6a931d HN	193	int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
3a6a931d HN	194	u8 prio, u8 *tc);
4f3961ee	195	int mlx5_set_port_tc_group(struct mlx5_core_dev mdev, u8 tc_group);
be0f161e HN	196	int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
be0f161e HN	197	u8 tc, u8 *tc_group);
4f3961ee	198	int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev mdev, u8 tc_bw);
3a6a931d HN	199	int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
3a6a931d HN	200	u8 tc, u8 *bw_pct);
d8880795 TT	201	int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	202	u8 *max_bw_value,
	203	u8 *max_bw_unit);
	204	int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	205	u8 *max_bw_value,
	206	u8 *max_bw_unit);
928cfe87 TT	207	int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
928cfe87 TT	208	int mlx5_query_port_wol(struct mlx5_core_dev mdev, u8 wol_mode);
4f3961ee	209
97417f61 EB	210	int mlx5_query_ports_check(struct mlx5_core_dev mdev, u32 out, int outlen);
97417f61 EB	211	int mlx5_set_ports_check(struct mlx5_core_dev mdev, u32 in, int inlen);
94cb1ebb EBE	212	int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
	213	void mlx5_query_port_fcs(struct mlx5_core_dev mdev, bool supported,
	214	bool *enabled);
bb64143e GP	215	int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
bb64143e GP	216	u16 offset, u16 size, u8 *data);
e109d2b2 VT	217	int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
e109d2b2 VT	218	struct mlx5_module_eeprom_query_params params, u8 data);
94cb1ebb	219
341c5ee2 HN	220	int mlx5_query_port_dcbx_param(struct mlx5_core_dev mdev, u32 out);
341c5ee2 HN	221	int mlx5_set_port_dcbx_param(struct mlx5_core_dev mdev, u32 in);
415a64aa HN	222
	223	int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
	224	int mlx5_query_trust_state(struct mlx5_core_dev mdev, u8 trust_state);
	225	int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
	226	int mlx5_query_dscp2prio(struct mlx5_core_dev mdev, u8 dscp2prio);
028522e2 GP	227
	228	int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
	229	struct mlx5_port_eth_proto *eproto);
	230	bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev);
	231	u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper,
	232	bool force_legacy);
	233	u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed,
	234	bool force_legacy);
	235	int mlx5_port_max_linkspeed(struct mlx5_core_dev mdev, u32 speed);
	236
ada68c31	237	#endif /* __MLX5_PORT_H__ */