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e29341fb IT |
1 | /* |
2 | * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | #ifndef MLX5_IFC_FPGA_H | |
33 | #define MLX5_IFC_FPGA_H | |
34 | ||
35 | struct mlx5_ifc_fpga_shell_caps_bits { | |
36 | u8 max_num_qps[0x10]; | |
37 | u8 reserved_at_10[0x8]; | |
38 | u8 total_rcv_credits[0x8]; | |
39 | ||
40 | u8 reserved_at_20[0xe]; | |
41 | u8 qp_type[0x2]; | |
42 | u8 reserved_at_30[0x5]; | |
43 | u8 rae[0x1]; | |
44 | u8 rwe[0x1]; | |
45 | u8 rre[0x1]; | |
46 | u8 reserved_at_38[0x4]; | |
47 | u8 dc[0x1]; | |
48 | u8 ud[0x1]; | |
49 | u8 uc[0x1]; | |
50 | u8 rc[0x1]; | |
51 | ||
52 | u8 reserved_at_40[0x1a]; | |
53 | u8 log_ddr_size[0x6]; | |
54 | ||
55 | u8 max_fpga_qp_msg_size[0x20]; | |
56 | ||
57 | u8 reserved_at_80[0x180]; | |
58 | }; | |
59 | ||
60 | struct mlx5_ifc_fpga_cap_bits { | |
61 | u8 fpga_id[0x8]; | |
62 | u8 fpga_device[0x18]; | |
63 | ||
64 | u8 register_file_ver[0x20]; | |
65 | ||
66 | u8 fpga_ctrl_modify[0x1]; | |
67 | u8 reserved_at_41[0x5]; | |
68 | u8 access_reg_query_mode[0x2]; | |
69 | u8 reserved_at_48[0x6]; | |
70 | u8 access_reg_modify_mode[0x2]; | |
71 | u8 reserved_at_50[0x10]; | |
72 | ||
73 | u8 reserved_at_60[0x20]; | |
74 | ||
75 | u8 image_version[0x20]; | |
76 | ||
77 | u8 image_date[0x20]; | |
78 | ||
79 | u8 image_time[0x20]; | |
80 | ||
81 | u8 shell_version[0x20]; | |
82 | ||
83 | u8 reserved_at_100[0x80]; | |
84 | ||
85 | struct mlx5_ifc_fpga_shell_caps_bits shell_caps; | |
86 | ||
87 | u8 reserved_at_380[0x8]; | |
88 | u8 ieee_vendor_id[0x18]; | |
89 | ||
90 | u8 sandbox_product_version[0x10]; | |
91 | u8 sandbox_product_id[0x10]; | |
92 | ||
93 | u8 sandbox_basic_caps[0x20]; | |
94 | ||
95 | u8 reserved_at_3e0[0x10]; | |
96 | u8 sandbox_extended_caps_len[0x10]; | |
97 | ||
98 | u8 sandbox_extended_caps_addr[0x40]; | |
99 | ||
100 | u8 fpga_ddr_start_addr[0x40]; | |
101 | ||
102 | u8 fpga_cr_space_start_addr[0x40]; | |
103 | ||
104 | u8 fpga_ddr_size[0x20]; | |
105 | ||
106 | u8 fpga_cr_space_size[0x20]; | |
107 | ||
108 | u8 reserved_at_500[0x300]; | |
109 | }; | |
110 | ||
111 | struct mlx5_ifc_fpga_ctrl_bits { | |
112 | u8 reserved_at_0[0x8]; | |
113 | u8 operation[0x8]; | |
114 | u8 reserved_at_10[0x8]; | |
115 | u8 status[0x8]; | |
116 | ||
117 | u8 reserved_at_20[0x8]; | |
118 | u8 flash_select_admin[0x8]; | |
119 | u8 reserved_at_30[0x8]; | |
120 | u8 flash_select_oper[0x8]; | |
121 | ||
122 | u8 reserved_at_40[0x40]; | |
123 | }; | |
124 | ||
125 | enum { | |
126 | MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, | |
127 | MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, | |
128 | MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, | |
129 | MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, | |
130 | MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, | |
131 | MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, | |
132 | MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, | |
133 | }; | |
134 | ||
135 | struct mlx5_ifc_fpga_error_event_bits { | |
136 | u8 reserved_at_0[0x40]; | |
137 | ||
138 | u8 reserved_at_40[0x18]; | |
139 | u8 syndrome[0x8]; | |
140 | ||
141 | u8 reserved_at_60[0x80]; | |
142 | }; | |
143 | ||
6062118d IT |
144 | enum mlx5_ifc_fpga_qp_state { |
145 | MLX5_FPGA_QPC_STATE_INIT = 0x0, | |
146 | MLX5_FPGA_QPC_STATE_ACTIVE = 0x1, | |
147 | MLX5_FPGA_QPC_STATE_ERROR = 0x2, | |
148 | }; | |
149 | ||
150 | enum mlx5_ifc_fpga_qp_type { | |
151 | MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0, | |
152 | MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1, | |
153 | }; | |
154 | ||
155 | enum mlx5_ifc_fpga_qp_service_type { | |
156 | MLX5_FPGA_QPC_ST_RC = 0x0, | |
157 | }; | |
158 | ||
159 | struct mlx5_ifc_fpga_qpc_bits { | |
160 | u8 state[0x4]; | |
161 | u8 reserved_at_4[0x1b]; | |
162 | u8 qp_type[0x1]; | |
163 | ||
164 | u8 reserved_at_20[0x4]; | |
165 | u8 st[0x4]; | |
166 | u8 reserved_at_28[0x10]; | |
167 | u8 traffic_class[0x8]; | |
168 | ||
169 | u8 ether_type[0x10]; | |
170 | u8 prio[0x3]; | |
171 | u8 dei[0x1]; | |
172 | u8 vid[0xc]; | |
173 | ||
174 | u8 reserved_at_60[0x20]; | |
175 | ||
176 | u8 reserved_at_80[0x8]; | |
177 | u8 next_rcv_psn[0x18]; | |
178 | ||
179 | u8 reserved_at_a0[0x8]; | |
180 | u8 next_send_psn[0x18]; | |
181 | ||
182 | u8 reserved_at_c0[0x10]; | |
183 | u8 pkey[0x10]; | |
184 | ||
185 | u8 reserved_at_e0[0x8]; | |
186 | u8 remote_qpn[0x18]; | |
187 | ||
188 | u8 reserved_at_100[0x15]; | |
189 | u8 rnr_retry[0x3]; | |
190 | u8 reserved_at_118[0x5]; | |
191 | u8 retry_count[0x3]; | |
192 | ||
193 | u8 reserved_at_120[0x20]; | |
194 | ||
195 | u8 reserved_at_140[0x10]; | |
196 | u8 remote_mac_47_32[0x10]; | |
197 | ||
198 | u8 remote_mac_31_0[0x20]; | |
199 | ||
200 | u8 remote_ip[16][0x8]; | |
201 | ||
202 | u8 reserved_at_200[0x40]; | |
203 | ||
204 | u8 reserved_at_240[0x10]; | |
205 | u8 fpga_mac_47_32[0x10]; | |
206 | ||
207 | u8 fpga_mac_31_0[0x20]; | |
208 | ||
209 | u8 fpga_ip[16][0x8]; | |
210 | }; | |
211 | ||
212 | struct mlx5_ifc_fpga_create_qp_in_bits { | |
213 | u8 opcode[0x10]; | |
214 | u8 reserved_at_10[0x10]; | |
215 | ||
216 | u8 reserved_at_20[0x10]; | |
217 | u8 op_mod[0x10]; | |
218 | ||
219 | u8 reserved_at_40[0x40]; | |
220 | ||
221 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
222 | }; | |
223 | ||
224 | struct mlx5_ifc_fpga_create_qp_out_bits { | |
225 | u8 status[0x8]; | |
226 | u8 reserved_at_8[0x18]; | |
227 | ||
228 | u8 syndrome[0x20]; | |
229 | ||
230 | u8 reserved_at_40[0x8]; | |
231 | u8 fpga_qpn[0x18]; | |
232 | ||
233 | u8 reserved_at_60[0x20]; | |
234 | ||
235 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
236 | }; | |
237 | ||
238 | struct mlx5_ifc_fpga_modify_qp_in_bits { | |
239 | u8 opcode[0x10]; | |
240 | u8 reserved_at_10[0x10]; | |
241 | ||
242 | u8 reserved_at_20[0x10]; | |
243 | u8 op_mod[0x10]; | |
244 | ||
245 | u8 reserved_at_40[0x8]; | |
246 | u8 fpga_qpn[0x18]; | |
247 | ||
248 | u8 field_select[0x20]; | |
249 | ||
250 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
251 | }; | |
252 | ||
253 | struct mlx5_ifc_fpga_modify_qp_out_bits { | |
254 | u8 status[0x8]; | |
255 | u8 reserved_at_8[0x18]; | |
256 | ||
257 | u8 syndrome[0x20]; | |
258 | ||
259 | u8 reserved_at_40[0x40]; | |
260 | }; | |
261 | ||
262 | struct mlx5_ifc_fpga_query_qp_in_bits { | |
263 | u8 opcode[0x10]; | |
264 | u8 reserved_at_10[0x10]; | |
265 | ||
266 | u8 reserved_at_20[0x10]; | |
267 | u8 op_mod[0x10]; | |
268 | ||
269 | u8 reserved_at_40[0x8]; | |
270 | u8 fpga_qpn[0x18]; | |
271 | ||
272 | u8 reserved_at_60[0x20]; | |
273 | }; | |
274 | ||
275 | struct mlx5_ifc_fpga_query_qp_out_bits { | |
276 | u8 status[0x8]; | |
277 | u8 reserved_at_8[0x18]; | |
278 | ||
279 | u8 syndrome[0x20]; | |
280 | ||
281 | u8 reserved_at_40[0x40]; | |
282 | ||
283 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
284 | }; | |
285 | ||
286 | struct mlx5_ifc_fpga_query_qp_counters_in_bits { | |
287 | u8 opcode[0x10]; | |
288 | u8 reserved_at_10[0x10]; | |
289 | ||
290 | u8 reserved_at_20[0x10]; | |
291 | u8 op_mod[0x10]; | |
292 | ||
293 | u8 clear[0x1]; | |
294 | u8 reserved_at_41[0x7]; | |
295 | u8 fpga_qpn[0x18]; | |
296 | ||
297 | u8 reserved_at_60[0x20]; | |
298 | }; | |
299 | ||
300 | struct mlx5_ifc_fpga_query_qp_counters_out_bits { | |
301 | u8 status[0x8]; | |
302 | u8 reserved_at_8[0x18]; | |
303 | ||
304 | u8 syndrome[0x20]; | |
305 | ||
306 | u8 reserved_at_40[0x40]; | |
307 | ||
308 | u8 rx_ack_packets[0x40]; | |
309 | ||
310 | u8 rx_send_packets[0x40]; | |
311 | ||
312 | u8 tx_ack_packets[0x40]; | |
313 | ||
314 | u8 tx_send_packets[0x40]; | |
315 | ||
316 | u8 rx_total_drop[0x40]; | |
317 | ||
318 | u8 reserved_at_1c0[0x1c0]; | |
319 | }; | |
320 | ||
321 | struct mlx5_ifc_fpga_destroy_qp_in_bits { | |
322 | u8 opcode[0x10]; | |
323 | u8 reserved_at_10[0x10]; | |
324 | ||
325 | u8 reserved_at_20[0x10]; | |
326 | u8 op_mod[0x10]; | |
327 | ||
328 | u8 reserved_at_40[0x8]; | |
329 | u8 fpga_qpn[0x18]; | |
330 | ||
331 | u8 reserved_at_60[0x20]; | |
332 | }; | |
333 | ||
334 | struct mlx5_ifc_fpga_destroy_qp_out_bits { | |
335 | u8 status[0x8]; | |
336 | u8 reserved_at_8[0x18]; | |
337 | ||
338 | u8 syndrome[0x20]; | |
339 | ||
340 | u8 reserved_at_40[0x40]; | |
341 | }; | |
342 | ||
e29341fb | 343 | #endif /* MLX5_IFC_FPGA_H */ |