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e29341fb IT |
1 | /* |
2 | * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | #ifndef MLX5_IFC_FPGA_H | |
33 | #define MLX5_IFC_FPGA_H | |
34 | ||
1ae17322 IL |
35 | struct mlx5_ifc_ipv4_layout_bits { |
36 | u8 reserved_at_0[0x60]; | |
37 | ||
38 | u8 ipv4[0x20]; | |
39 | }; | |
40 | ||
41 | struct mlx5_ifc_ipv6_layout_bits { | |
42 | u8 ipv6[16][0x8]; | |
43 | }; | |
44 | ||
45 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { | |
46 | struct mlx5_ifc_ipv6_layout_bits ipv6_layout; | |
47 | struct mlx5_ifc_ipv4_layout_bits ipv4_layout; | |
48 | u8 reserved_at_0[0x80]; | |
49 | }; | |
50 | ||
bebb23e6 IT |
51 | enum { |
52 | MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9, | |
53 | }; | |
54 | ||
55 | enum { | |
56 | MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2, | |
1ae17322 | 57 | MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3, |
bebb23e6 IT |
58 | }; |
59 | ||
e29341fb IT |
60 | struct mlx5_ifc_fpga_shell_caps_bits { |
61 | u8 max_num_qps[0x10]; | |
62 | u8 reserved_at_10[0x8]; | |
63 | u8 total_rcv_credits[0x8]; | |
64 | ||
65 | u8 reserved_at_20[0xe]; | |
66 | u8 qp_type[0x2]; | |
67 | u8 reserved_at_30[0x5]; | |
68 | u8 rae[0x1]; | |
69 | u8 rwe[0x1]; | |
70 | u8 rre[0x1]; | |
71 | u8 reserved_at_38[0x4]; | |
72 | u8 dc[0x1]; | |
73 | u8 ud[0x1]; | |
74 | u8 uc[0x1]; | |
75 | u8 rc[0x1]; | |
76 | ||
77 | u8 reserved_at_40[0x1a]; | |
78 | u8 log_ddr_size[0x6]; | |
79 | ||
80 | u8 max_fpga_qp_msg_size[0x20]; | |
81 | ||
82 | u8 reserved_at_80[0x180]; | |
83 | }; | |
84 | ||
85 | struct mlx5_ifc_fpga_cap_bits { | |
86 | u8 fpga_id[0x8]; | |
87 | u8 fpga_device[0x18]; | |
88 | ||
89 | u8 register_file_ver[0x20]; | |
90 | ||
91 | u8 fpga_ctrl_modify[0x1]; | |
92 | u8 reserved_at_41[0x5]; | |
93 | u8 access_reg_query_mode[0x2]; | |
94 | u8 reserved_at_48[0x6]; | |
95 | u8 access_reg_modify_mode[0x2]; | |
96 | u8 reserved_at_50[0x10]; | |
97 | ||
98 | u8 reserved_at_60[0x20]; | |
99 | ||
100 | u8 image_version[0x20]; | |
101 | ||
102 | u8 image_date[0x20]; | |
103 | ||
104 | u8 image_time[0x20]; | |
105 | ||
106 | u8 shell_version[0x20]; | |
107 | ||
108 | u8 reserved_at_100[0x80]; | |
109 | ||
110 | struct mlx5_ifc_fpga_shell_caps_bits shell_caps; | |
111 | ||
112 | u8 reserved_at_380[0x8]; | |
113 | u8 ieee_vendor_id[0x18]; | |
114 | ||
115 | u8 sandbox_product_version[0x10]; | |
116 | u8 sandbox_product_id[0x10]; | |
117 | ||
118 | u8 sandbox_basic_caps[0x20]; | |
119 | ||
120 | u8 reserved_at_3e0[0x10]; | |
121 | u8 sandbox_extended_caps_len[0x10]; | |
122 | ||
123 | u8 sandbox_extended_caps_addr[0x40]; | |
124 | ||
125 | u8 fpga_ddr_start_addr[0x40]; | |
126 | ||
127 | u8 fpga_cr_space_start_addr[0x40]; | |
128 | ||
129 | u8 fpga_ddr_size[0x20]; | |
130 | ||
131 | u8 fpga_cr_space_size[0x20]; | |
132 | ||
133 | u8 reserved_at_500[0x300]; | |
134 | }; | |
135 | ||
c43051d7 IT |
136 | enum { |
137 | MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1, | |
138 | MLX5_FPGA_CTRL_OPERATION_RESET = 0x2, | |
139 | MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3, | |
140 | MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4, | |
141 | MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5, | |
142 | MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6, | |
143 | }; | |
144 | ||
e29341fb IT |
145 | struct mlx5_ifc_fpga_ctrl_bits { |
146 | u8 reserved_at_0[0x8]; | |
147 | u8 operation[0x8]; | |
148 | u8 reserved_at_10[0x8]; | |
149 | u8 status[0x8]; | |
150 | ||
151 | u8 reserved_at_20[0x8]; | |
152 | u8 flash_select_admin[0x8]; | |
153 | u8 reserved_at_30[0x8]; | |
154 | u8 flash_select_oper[0x8]; | |
155 | ||
156 | u8 reserved_at_40[0x40]; | |
157 | }; | |
158 | ||
159 | enum { | |
160 | MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, | |
161 | MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, | |
162 | MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, | |
163 | MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, | |
164 | MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, | |
165 | MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, | |
166 | MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, | |
167 | }; | |
168 | ||
169 | struct mlx5_ifc_fpga_error_event_bits { | |
170 | u8 reserved_at_0[0x40]; | |
171 | ||
172 | u8 reserved_at_40[0x18]; | |
173 | u8 syndrome[0x8]; | |
174 | ||
175 | u8 reserved_at_60[0x80]; | |
176 | }; | |
177 | ||
a9956d35 IT |
178 | #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64 |
179 | ||
180 | struct mlx5_ifc_fpga_access_reg_bits { | |
181 | u8 reserved_at_0[0x20]; | |
182 | ||
183 | u8 reserved_at_20[0x10]; | |
184 | u8 size[0x10]; | |
185 | ||
186 | u8 address[0x40]; | |
187 | ||
188 | u8 data[0][0x8]; | |
189 | }; | |
190 | ||
6062118d IT |
191 | enum mlx5_ifc_fpga_qp_state { |
192 | MLX5_FPGA_QPC_STATE_INIT = 0x0, | |
193 | MLX5_FPGA_QPC_STATE_ACTIVE = 0x1, | |
194 | MLX5_FPGA_QPC_STATE_ERROR = 0x2, | |
195 | }; | |
196 | ||
197 | enum mlx5_ifc_fpga_qp_type { | |
198 | MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0, | |
199 | MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1, | |
200 | }; | |
201 | ||
202 | enum mlx5_ifc_fpga_qp_service_type { | |
203 | MLX5_FPGA_QPC_ST_RC = 0x0, | |
204 | }; | |
205 | ||
206 | struct mlx5_ifc_fpga_qpc_bits { | |
207 | u8 state[0x4]; | |
208 | u8 reserved_at_4[0x1b]; | |
209 | u8 qp_type[0x1]; | |
210 | ||
211 | u8 reserved_at_20[0x4]; | |
212 | u8 st[0x4]; | |
213 | u8 reserved_at_28[0x10]; | |
214 | u8 traffic_class[0x8]; | |
215 | ||
216 | u8 ether_type[0x10]; | |
217 | u8 prio[0x3]; | |
218 | u8 dei[0x1]; | |
219 | u8 vid[0xc]; | |
220 | ||
221 | u8 reserved_at_60[0x20]; | |
222 | ||
223 | u8 reserved_at_80[0x8]; | |
224 | u8 next_rcv_psn[0x18]; | |
225 | ||
226 | u8 reserved_at_a0[0x8]; | |
227 | u8 next_send_psn[0x18]; | |
228 | ||
229 | u8 reserved_at_c0[0x10]; | |
230 | u8 pkey[0x10]; | |
231 | ||
232 | u8 reserved_at_e0[0x8]; | |
233 | u8 remote_qpn[0x18]; | |
234 | ||
235 | u8 reserved_at_100[0x15]; | |
236 | u8 rnr_retry[0x3]; | |
237 | u8 reserved_at_118[0x5]; | |
238 | u8 retry_count[0x3]; | |
239 | ||
240 | u8 reserved_at_120[0x20]; | |
241 | ||
242 | u8 reserved_at_140[0x10]; | |
243 | u8 remote_mac_47_32[0x10]; | |
244 | ||
245 | u8 remote_mac_31_0[0x20]; | |
246 | ||
247 | u8 remote_ip[16][0x8]; | |
248 | ||
249 | u8 reserved_at_200[0x40]; | |
250 | ||
251 | u8 reserved_at_240[0x10]; | |
252 | u8 fpga_mac_47_32[0x10]; | |
253 | ||
254 | u8 fpga_mac_31_0[0x20]; | |
255 | ||
256 | u8 fpga_ip[16][0x8]; | |
257 | }; | |
258 | ||
259 | struct mlx5_ifc_fpga_create_qp_in_bits { | |
260 | u8 opcode[0x10]; | |
261 | u8 reserved_at_10[0x10]; | |
262 | ||
263 | u8 reserved_at_20[0x10]; | |
264 | u8 op_mod[0x10]; | |
265 | ||
266 | u8 reserved_at_40[0x40]; | |
267 | ||
268 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
269 | }; | |
270 | ||
271 | struct mlx5_ifc_fpga_create_qp_out_bits { | |
272 | u8 status[0x8]; | |
273 | u8 reserved_at_8[0x18]; | |
274 | ||
275 | u8 syndrome[0x20]; | |
276 | ||
277 | u8 reserved_at_40[0x8]; | |
278 | u8 fpga_qpn[0x18]; | |
279 | ||
280 | u8 reserved_at_60[0x20]; | |
281 | ||
282 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
283 | }; | |
284 | ||
285 | struct mlx5_ifc_fpga_modify_qp_in_bits { | |
286 | u8 opcode[0x10]; | |
287 | u8 reserved_at_10[0x10]; | |
288 | ||
289 | u8 reserved_at_20[0x10]; | |
290 | u8 op_mod[0x10]; | |
291 | ||
292 | u8 reserved_at_40[0x8]; | |
293 | u8 fpga_qpn[0x18]; | |
294 | ||
295 | u8 field_select[0x20]; | |
296 | ||
297 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
298 | }; | |
299 | ||
300 | struct mlx5_ifc_fpga_modify_qp_out_bits { | |
301 | u8 status[0x8]; | |
302 | u8 reserved_at_8[0x18]; | |
303 | ||
304 | u8 syndrome[0x20]; | |
305 | ||
306 | u8 reserved_at_40[0x40]; | |
307 | }; | |
308 | ||
309 | struct mlx5_ifc_fpga_query_qp_in_bits { | |
310 | u8 opcode[0x10]; | |
311 | u8 reserved_at_10[0x10]; | |
312 | ||
313 | u8 reserved_at_20[0x10]; | |
314 | u8 op_mod[0x10]; | |
315 | ||
316 | u8 reserved_at_40[0x8]; | |
317 | u8 fpga_qpn[0x18]; | |
318 | ||
319 | u8 reserved_at_60[0x20]; | |
320 | }; | |
321 | ||
322 | struct mlx5_ifc_fpga_query_qp_out_bits { | |
323 | u8 status[0x8]; | |
324 | u8 reserved_at_8[0x18]; | |
325 | ||
326 | u8 syndrome[0x20]; | |
327 | ||
328 | u8 reserved_at_40[0x40]; | |
329 | ||
330 | struct mlx5_ifc_fpga_qpc_bits fpga_qpc; | |
331 | }; | |
332 | ||
333 | struct mlx5_ifc_fpga_query_qp_counters_in_bits { | |
334 | u8 opcode[0x10]; | |
335 | u8 reserved_at_10[0x10]; | |
336 | ||
337 | u8 reserved_at_20[0x10]; | |
338 | u8 op_mod[0x10]; | |
339 | ||
340 | u8 clear[0x1]; | |
341 | u8 reserved_at_41[0x7]; | |
342 | u8 fpga_qpn[0x18]; | |
343 | ||
344 | u8 reserved_at_60[0x20]; | |
345 | }; | |
346 | ||
347 | struct mlx5_ifc_fpga_query_qp_counters_out_bits { | |
348 | u8 status[0x8]; | |
349 | u8 reserved_at_8[0x18]; | |
350 | ||
351 | u8 syndrome[0x20]; | |
352 | ||
353 | u8 reserved_at_40[0x40]; | |
354 | ||
355 | u8 rx_ack_packets[0x40]; | |
356 | ||
357 | u8 rx_send_packets[0x40]; | |
358 | ||
359 | u8 tx_ack_packets[0x40]; | |
360 | ||
361 | u8 tx_send_packets[0x40]; | |
362 | ||
363 | u8 rx_total_drop[0x40]; | |
364 | ||
365 | u8 reserved_at_1c0[0x1c0]; | |
366 | }; | |
367 | ||
368 | struct mlx5_ifc_fpga_destroy_qp_in_bits { | |
369 | u8 opcode[0x10]; | |
370 | u8 reserved_at_10[0x10]; | |
371 | ||
372 | u8 reserved_at_20[0x10]; | |
373 | u8 op_mod[0x10]; | |
374 | ||
375 | u8 reserved_at_40[0x8]; | |
376 | u8 fpga_qpn[0x18]; | |
377 | ||
378 | u8 reserved_at_60[0x20]; | |
379 | }; | |
380 | ||
381 | struct mlx5_ifc_fpga_destroy_qp_out_bits { | |
382 | u8 status[0x8]; | |
383 | u8 reserved_at_8[0x18]; | |
384 | ||
385 | u8 syndrome[0x20]; | |
386 | ||
387 | u8 reserved_at_40[0x40]; | |
388 | }; | |
389 | ||
1ae17322 IL |
390 | struct mlx5_ifc_tls_extended_cap_bits { |
391 | u8 aes_gcm_128[0x1]; | |
392 | u8 aes_gcm_256[0x1]; | |
393 | u8 reserved_at_2[0x1e]; | |
394 | u8 reserved_at_20[0x20]; | |
395 | u8 context_capacity_total[0x20]; | |
396 | u8 context_capacity_rx[0x20]; | |
397 | u8 context_capacity_tx[0x20]; | |
398 | u8 reserved_at_a0[0x10]; | |
399 | u8 tls_counter_size[0x10]; | |
400 | u8 tls_counters_addr_low[0x20]; | |
401 | u8 tls_counters_addr_high[0x20]; | |
402 | u8 rx[0x1]; | |
403 | u8 tx[0x1]; | |
404 | u8 tls_v12[0x1]; | |
405 | u8 tls_v13[0x1]; | |
406 | u8 lro[0x1]; | |
407 | u8 ipv6[0x1]; | |
408 | u8 reserved_at_106[0x1a]; | |
409 | }; | |
410 | ||
bebb23e6 IT |
411 | struct mlx5_ifc_ipsec_extended_cap_bits { |
412 | u8 encapsulation[0x20]; | |
413 | ||
65802f48 AY |
414 | u8 reserved_0[0x12]; |
415 | u8 v2_command[0x1]; | |
416 | u8 udp_encap[0x1]; | |
788a8210 | 417 | u8 rx_no_trailer[0x1]; |
bebb23e6 IT |
418 | u8 ipv4_fragment[0x1]; |
419 | u8 ipv6[0x1]; | |
420 | u8 esn[0x1]; | |
421 | u8 lso[0x1]; | |
422 | u8 transport_and_tunnel_mode[0x1]; | |
423 | u8 tunnel_mode[0x1]; | |
424 | u8 transport_mode[0x1]; | |
425 | u8 ah_esp[0x1]; | |
426 | u8 esp[0x1]; | |
427 | u8 ah[0x1]; | |
428 | u8 ipv4_options[0x1]; | |
429 | ||
430 | u8 auth_alg[0x20]; | |
431 | ||
432 | u8 enc_alg[0x20]; | |
433 | ||
434 | u8 sa_cap[0x20]; | |
435 | ||
436 | u8 reserved_1[0x10]; | |
437 | u8 number_of_ipsec_counters[0x10]; | |
438 | ||
439 | u8 ipsec_counters_addr_low[0x20]; | |
440 | u8 ipsec_counters_addr_high[0x20]; | |
441 | }; | |
442 | ||
443 | struct mlx5_ifc_ipsec_counters_bits { | |
444 | u8 dec_in_packets[0x40]; | |
445 | ||
446 | u8 dec_out_packets[0x40]; | |
447 | ||
448 | u8 dec_bypass_packets[0x40]; | |
449 | ||
450 | u8 enc_in_packets[0x40]; | |
451 | ||
452 | u8 enc_out_packets[0x40]; | |
453 | ||
454 | u8 enc_bypass_packets[0x40]; | |
455 | ||
456 | u8 drop_dec_packets[0x40]; | |
457 | ||
458 | u8 failed_auth_dec_packets[0x40]; | |
459 | ||
460 | u8 drop_enc_packets[0x40]; | |
461 | ||
462 | u8 success_add_sa[0x40]; | |
463 | ||
464 | u8 fail_add_sa[0x40]; | |
465 | ||
466 | u8 success_delete_sa[0x40]; | |
467 | ||
468 | u8 fail_delete_sa[0x40]; | |
469 | ||
470 | u8 dropped_cmd[0x40]; | |
471 | }; | |
472 | ||
1f0cf89b IT |
473 | enum { |
474 | MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1, | |
475 | MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2, | |
476 | }; | |
477 | ||
478 | struct mlx5_ifc_fpga_qp_error_event_bits { | |
479 | u8 reserved_at_0[0x40]; | |
480 | ||
481 | u8 reserved_at_40[0x18]; | |
482 | u8 syndrome[0x8]; | |
483 | ||
484 | u8 reserved_at_60[0x60]; | |
485 | ||
486 | u8 reserved_at_c0[0x8]; | |
487 | u8 fpga_qpn[0x18]; | |
488 | }; | |
581fddde YK |
489 | enum mlx5_ifc_fpga_ipsec_response_syndrome { |
490 | MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0, | |
491 | MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1, | |
492 | MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE = 2, | |
493 | MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3, | |
494 | }; | |
495 | ||
496 | struct mlx5_ifc_fpga_ipsec_cmd_resp { | |
497 | __be32 syndrome; | |
498 | union { | |
499 | __be32 sw_sa_handle; | |
500 | __be32 flags; | |
501 | }; | |
502 | u8 reserved[24]; | |
503 | } __packed; | |
504 | ||
d6c4f029 AY |
505 | enum mlx5_ifc_fpga_ipsec_cmd_opcode { |
506 | MLX5_FPGA_IPSEC_CMD_OP_ADD_SA = 0, | |
507 | MLX5_FPGA_IPSEC_CMD_OP_DEL_SA = 1, | |
508 | MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 = 2, | |
509 | MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 = 3, | |
510 | MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2 = 4, | |
511 | MLX5_FPGA_IPSEC_CMD_OP_SET_CAP = 5, | |
512 | }; | |
513 | ||
788a8210 YK |
514 | enum mlx5_ifc_fpga_ipsec_cap { |
515 | MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0), | |
516 | }; | |
517 | ||
518 | struct mlx5_ifc_fpga_ipsec_cmd_cap { | |
519 | __be32 cmd; | |
520 | __be32 flags; | |
521 | u8 reserved[24]; | |
522 | } __packed; | |
523 | ||
d6c4f029 | 524 | enum mlx5_ifc_fpga_ipsec_sa_flags { |
cb010083 AY |
525 | MLX5_FPGA_IPSEC_SA_ESN_EN = BIT(0), |
526 | MLX5_FPGA_IPSEC_SA_ESN_OVERLAP = BIT(1), | |
d6c4f029 AY |
527 | MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2), |
528 | MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3), | |
529 | MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4), | |
530 | MLX5_FPGA_IPSEC_SA_SA_VALID = BIT(5), | |
531 | MLX5_FPGA_IPSEC_SA_IP_ESP = BIT(6), | |
532 | MLX5_FPGA_IPSEC_SA_IP_AH = BIT(7), | |
533 | }; | |
534 | ||
535 | enum mlx5_ifc_fpga_ipsec_sa_enc_mode { | |
536 | MLX5_FPGA_IPSEC_SA_ENC_MODE_NONE = 0, | |
537 | MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128 = 1, | |
538 | MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128 = 3, | |
539 | }; | |
540 | ||
541 | struct mlx5_ifc_fpga_ipsec_sa_v1 { | |
542 | __be32 cmd; | |
543 | u8 key_enc[32]; | |
544 | u8 key_auth[32]; | |
545 | __be32 sip[4]; | |
546 | __be32 dip[4]; | |
547 | union { | |
548 | struct { | |
549 | __be32 reserved; | |
550 | u8 salt_iv[8]; | |
551 | __be32 salt; | |
552 | } __packed gcm; | |
553 | struct { | |
554 | u8 salt[16]; | |
555 | } __packed cbc; | |
556 | }; | |
557 | __be32 spi; | |
558 | __be32 sw_sa_handle; | |
559 | __be16 tfclen; | |
560 | u8 enc_mode; | |
561 | u8 reserved1[2]; | |
562 | u8 flags; | |
563 | u8 reserved2[2]; | |
564 | }; | |
565 | ||
566 | struct mlx5_ifc_fpga_ipsec_sa { | |
567 | struct mlx5_ifc_fpga_ipsec_sa_v1 ipsec_sa_v1; | |
568 | __be16 udp_sp; | |
569 | __be16 udp_dp; | |
570 | u8 reserved1[4]; | |
571 | __be32 esn; | |
572 | __be16 vid; /* only 12 bits, rest is reserved */ | |
573 | __be16 reserved2; | |
574 | } __packed; | |
575 | ||
1ae17322 IL |
576 | enum fpga_tls_cmds { |
577 | CMD_SETUP_STREAM = 0x1001, | |
578 | CMD_TEARDOWN_STREAM = 0x1002, | |
579 | }; | |
580 | ||
581 | #define MLX5_TLS_1_2 (0) | |
582 | ||
583 | #define MLX5_TLS_ALG_AES_GCM_128 (0) | |
584 | #define MLX5_TLS_ALG_AES_GCM_256 (1) | |
585 | ||
586 | struct mlx5_ifc_tls_cmd_bits { | |
587 | u8 command_type[0x20]; | |
588 | u8 ipv6[0x1]; | |
589 | u8 direction_sx[0x1]; | |
590 | u8 tls_version[0x2]; | |
591 | u8 reserved[0x1c]; | |
592 | u8 swid[0x20]; | |
593 | u8 src_port[0x10]; | |
594 | u8 dst_port[0x10]; | |
595 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; | |
596 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; | |
597 | u8 tls_rcd_sn[0x40]; | |
598 | u8 tcp_sn[0x20]; | |
599 | u8 tls_implicit_iv[0x20]; | |
600 | u8 tls_xor_iv[0x40]; | |
601 | u8 encryption_key[0x100]; | |
602 | u8 alg[4]; | |
603 | u8 reserved2[0x1c]; | |
604 | u8 reserved3[0x4a0]; | |
605 | }; | |
606 | ||
607 | struct mlx5_ifc_tls_resp_bits { | |
608 | u8 syndrome[0x20]; | |
609 | u8 stream_id[0x20]; | |
610 | u8 reserverd[0x40]; | |
611 | }; | |
612 | ||
613 | #define MLX5_TLS_COMMAND_SIZE (0x100) | |
614 | ||
e29341fb | 615 | #endif /* MLX5_IFC_FPGA_H */ |