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d29b796a | 1 | /* |
e281682b | 2 | * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. |
d29b796a EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
e281682b | 31 | */ |
d29b796a EC |
32 | #ifndef MLX5_IFC_H |
33 | #define MLX5_IFC_H | |
34 | ||
e281682b SM |
35 | enum { |
36 | MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, | |
37 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, | |
38 | MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, | |
39 | MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, | |
40 | MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, | |
41 | MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, | |
42 | MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, | |
43 | MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, | |
44 | MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, | |
45 | MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, | |
46 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, | |
47 | MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, | |
48 | MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, | |
49 | MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, | |
50 | MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, | |
51 | MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, | |
52 | MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, | |
53 | MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, | |
54 | MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, | |
55 | MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, | |
56 | MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, | |
57 | MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, | |
58 | MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, | |
59 | MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb | |
60 | }; | |
61 | ||
62 | enum { | |
63 | MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, | |
64 | MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, | |
65 | MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, | |
66 | MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 | |
67 | }; | |
68 | ||
d29b796a EC |
69 | enum { |
70 | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | |
71 | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | |
72 | MLX5_CMD_OP_INIT_HCA = 0x102, | |
73 | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | |
74 | MLX5_CMD_OP_ENABLE_HCA = 0x104, | |
75 | MLX5_CMD_OP_DISABLE_HCA = 0x105, | |
76 | MLX5_CMD_OP_QUERY_PAGES = 0x107, | |
77 | MLX5_CMD_OP_MANAGE_PAGES = 0x108, | |
78 | MLX5_CMD_OP_SET_HCA_CAP = 0x109, | |
e281682b SM |
79 | MLX5_CMD_OP_QUERY_ISSI = 0x10a, |
80 | MLX5_CMD_OP_SET_ISSI = 0x10b, | |
d29b796a EC |
81 | MLX5_CMD_OP_CREATE_MKEY = 0x200, |
82 | MLX5_CMD_OP_QUERY_MKEY = 0x201, | |
83 | MLX5_CMD_OP_DESTROY_MKEY = 0x202, | |
84 | MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, | |
85 | MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, | |
86 | MLX5_CMD_OP_CREATE_EQ = 0x301, | |
87 | MLX5_CMD_OP_DESTROY_EQ = 0x302, | |
88 | MLX5_CMD_OP_QUERY_EQ = 0x303, | |
89 | MLX5_CMD_OP_GEN_EQE = 0x304, | |
90 | MLX5_CMD_OP_CREATE_CQ = 0x400, | |
91 | MLX5_CMD_OP_DESTROY_CQ = 0x401, | |
92 | MLX5_CMD_OP_QUERY_CQ = 0x402, | |
93 | MLX5_CMD_OP_MODIFY_CQ = 0x403, | |
94 | MLX5_CMD_OP_CREATE_QP = 0x500, | |
95 | MLX5_CMD_OP_DESTROY_QP = 0x501, | |
96 | MLX5_CMD_OP_RST2INIT_QP = 0x502, | |
97 | MLX5_CMD_OP_INIT2RTR_QP = 0x503, | |
98 | MLX5_CMD_OP_RTR2RTS_QP = 0x504, | |
99 | MLX5_CMD_OP_RTS2RTS_QP = 0x505, | |
100 | MLX5_CMD_OP_SQERR2RTS_QP = 0x506, | |
101 | MLX5_CMD_OP_2ERR_QP = 0x507, | |
102 | MLX5_CMD_OP_2RST_QP = 0x50a, | |
103 | MLX5_CMD_OP_QUERY_QP = 0x50b, | |
e281682b | 104 | MLX5_CMD_OP_SQD_RTS_QP = 0x50c, |
d29b796a EC |
105 | MLX5_CMD_OP_INIT2INIT_QP = 0x50e, |
106 | MLX5_CMD_OP_CREATE_PSV = 0x600, | |
107 | MLX5_CMD_OP_DESTROY_PSV = 0x601, | |
108 | MLX5_CMD_OP_CREATE_SRQ = 0x700, | |
109 | MLX5_CMD_OP_DESTROY_SRQ = 0x701, | |
110 | MLX5_CMD_OP_QUERY_SRQ = 0x702, | |
111 | MLX5_CMD_OP_ARM_RQ = 0x703, | |
e281682b SM |
112 | MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, |
113 | MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, | |
114 | MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, | |
115 | MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, | |
d29b796a EC |
116 | MLX5_CMD_OP_CREATE_DCT = 0x710, |
117 | MLX5_CMD_OP_DESTROY_DCT = 0x711, | |
118 | MLX5_CMD_OP_DRAIN_DCT = 0x712, | |
119 | MLX5_CMD_OP_QUERY_DCT = 0x713, | |
120 | MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, | |
121 | MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, | |
122 | MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, | |
123 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, | |
124 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, | |
125 | MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, | |
126 | MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, | |
e281682b | 127 | MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, |
d29b796a | 128 | MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, |
e281682b SM |
129 | MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, |
130 | MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, | |
131 | MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, | |
132 | MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, | |
d29b796a EC |
133 | MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, |
134 | MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, | |
135 | MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, | |
136 | MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, | |
137 | MLX5_CMD_OP_ALLOC_PD = 0x800, | |
138 | MLX5_CMD_OP_DEALLOC_PD = 0x801, | |
139 | MLX5_CMD_OP_ALLOC_UAR = 0x802, | |
140 | MLX5_CMD_OP_DEALLOC_UAR = 0x803, | |
141 | MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, | |
142 | MLX5_CMD_OP_ACCESS_REG = 0x805, | |
143 | MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, | |
e281682b | 144 | MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, |
d29b796a EC |
145 | MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, |
146 | MLX5_CMD_OP_MAD_IFC = 0x50d, | |
147 | MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, | |
148 | MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, | |
149 | MLX5_CMD_OP_NOP = 0x80d, | |
150 | MLX5_CMD_OP_ALLOC_XRCD = 0x80e, | |
151 | MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, | |
e281682b SM |
152 | MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, |
153 | MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, | |
154 | MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, | |
155 | MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, | |
156 | MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, | |
157 | MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, | |
158 | MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, | |
159 | MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, | |
160 | MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, | |
161 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, | |
162 | MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, | |
163 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, | |
d29b796a EC |
164 | MLX5_CMD_OP_CREATE_TIR = 0x900, |
165 | MLX5_CMD_OP_MODIFY_TIR = 0x901, | |
166 | MLX5_CMD_OP_DESTROY_TIR = 0x902, | |
167 | MLX5_CMD_OP_QUERY_TIR = 0x903, | |
d29b796a EC |
168 | MLX5_CMD_OP_CREATE_SQ = 0x904, |
169 | MLX5_CMD_OP_MODIFY_SQ = 0x905, | |
170 | MLX5_CMD_OP_DESTROY_SQ = 0x906, | |
171 | MLX5_CMD_OP_QUERY_SQ = 0x907, | |
172 | MLX5_CMD_OP_CREATE_RQ = 0x908, | |
173 | MLX5_CMD_OP_MODIFY_RQ = 0x909, | |
174 | MLX5_CMD_OP_DESTROY_RQ = 0x90a, | |
175 | MLX5_CMD_OP_QUERY_RQ = 0x90b, | |
176 | MLX5_CMD_OP_CREATE_RMP = 0x90c, | |
177 | MLX5_CMD_OP_MODIFY_RMP = 0x90d, | |
178 | MLX5_CMD_OP_DESTROY_RMP = 0x90e, | |
179 | MLX5_CMD_OP_QUERY_RMP = 0x90f, | |
e281682b SM |
180 | MLX5_CMD_OP_CREATE_TIS = 0x912, |
181 | MLX5_CMD_OP_MODIFY_TIS = 0x913, | |
182 | MLX5_CMD_OP_DESTROY_TIS = 0x914, | |
183 | MLX5_CMD_OP_QUERY_TIS = 0x915, | |
184 | MLX5_CMD_OP_CREATE_RQT = 0x916, | |
185 | MLX5_CMD_OP_MODIFY_RQT = 0x917, | |
186 | MLX5_CMD_OP_DESTROY_RQT = 0x918, | |
187 | MLX5_CMD_OP_QUERY_RQT = 0x919, | |
188 | MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, | |
189 | MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, | |
190 | MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, | |
191 | MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, | |
192 | MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, | |
193 | MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, | |
194 | MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, | |
195 | MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, | |
196 | MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938 | |
197 | }; | |
198 | ||
199 | struct mlx5_ifc_flow_table_fields_supported_bits { | |
200 | u8 outer_dmac[0x1]; | |
201 | u8 outer_smac[0x1]; | |
202 | u8 outer_ether_type[0x1]; | |
203 | u8 reserved_0[0x1]; | |
204 | u8 outer_first_prio[0x1]; | |
205 | u8 outer_first_cfi[0x1]; | |
206 | u8 outer_first_vid[0x1]; | |
207 | u8 reserved_1[0x1]; | |
208 | u8 outer_second_prio[0x1]; | |
209 | u8 outer_second_cfi[0x1]; | |
210 | u8 outer_second_vid[0x1]; | |
211 | u8 reserved_2[0x1]; | |
212 | u8 outer_sip[0x1]; | |
213 | u8 outer_dip[0x1]; | |
214 | u8 outer_frag[0x1]; | |
215 | u8 outer_ip_protocol[0x1]; | |
216 | u8 outer_ip_ecn[0x1]; | |
217 | u8 outer_ip_dscp[0x1]; | |
218 | u8 outer_udp_sport[0x1]; | |
219 | u8 outer_udp_dport[0x1]; | |
220 | u8 outer_tcp_sport[0x1]; | |
221 | u8 outer_tcp_dport[0x1]; | |
222 | u8 outer_tcp_flags[0x1]; | |
223 | u8 outer_gre_protocol[0x1]; | |
224 | u8 outer_gre_key[0x1]; | |
225 | u8 outer_vxlan_vni[0x1]; | |
226 | u8 reserved_3[0x5]; | |
227 | u8 source_eswitch_port[0x1]; | |
228 | ||
229 | u8 inner_dmac[0x1]; | |
230 | u8 inner_smac[0x1]; | |
231 | u8 inner_ether_type[0x1]; | |
232 | u8 reserved_4[0x1]; | |
233 | u8 inner_first_prio[0x1]; | |
234 | u8 inner_first_cfi[0x1]; | |
235 | u8 inner_first_vid[0x1]; | |
236 | u8 reserved_5[0x1]; | |
237 | u8 inner_second_prio[0x1]; | |
238 | u8 inner_second_cfi[0x1]; | |
239 | u8 inner_second_vid[0x1]; | |
240 | u8 reserved_6[0x1]; | |
241 | u8 inner_sip[0x1]; | |
242 | u8 inner_dip[0x1]; | |
243 | u8 inner_frag[0x1]; | |
244 | u8 inner_ip_protocol[0x1]; | |
245 | u8 inner_ip_ecn[0x1]; | |
246 | u8 inner_ip_dscp[0x1]; | |
247 | u8 inner_udp_sport[0x1]; | |
248 | u8 inner_udp_dport[0x1]; | |
249 | u8 inner_tcp_sport[0x1]; | |
250 | u8 inner_tcp_dport[0x1]; | |
251 | u8 inner_tcp_flags[0x1]; | |
252 | u8 reserved_7[0x9]; | |
253 | ||
254 | u8 reserved_8[0x40]; | |
255 | }; | |
256 | ||
257 | struct mlx5_ifc_flow_table_prop_layout_bits { | |
258 | u8 ft_support[0x1]; | |
26a81453 MG |
259 | u8 reserved_0[0x2]; |
260 | u8 flow_modify_en[0x1]; | |
261 | u8 reserved_1[0x1c]; | |
e281682b | 262 | |
26a81453 | 263 | u8 reserved_2[0x2]; |
e281682b | 264 | u8 log_max_ft_size[0x6]; |
26a81453 | 265 | u8 reserved_3[0x10]; |
e281682b SM |
266 | u8 max_ft_level[0x8]; |
267 | ||
26a81453 | 268 | u8 reserved_4[0x20]; |
e281682b | 269 | |
26a81453 | 270 | u8 reserved_5[0x18]; |
e281682b SM |
271 | u8 log_max_ft_num[0x8]; |
272 | ||
26a81453 | 273 | u8 reserved_6[0x18]; |
e281682b SM |
274 | u8 log_max_destination[0x8]; |
275 | ||
26a81453 | 276 | u8 reserved_7[0x18]; |
e281682b SM |
277 | u8 log_max_flow[0x8]; |
278 | ||
26a81453 | 279 | u8 reserved_8[0x40]; |
e281682b SM |
280 | |
281 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; | |
282 | ||
283 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; | |
284 | }; | |
285 | ||
286 | struct mlx5_ifc_odp_per_transport_service_cap_bits { | |
287 | u8 send[0x1]; | |
288 | u8 receive[0x1]; | |
289 | u8 write[0x1]; | |
290 | u8 read[0x1]; | |
291 | u8 reserved_0[0x1]; | |
292 | u8 srq_receive[0x1]; | |
293 | u8 reserved_1[0x1a]; | |
294 | }; | |
295 | ||
296 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits { | |
297 | u8 smac_47_16[0x20]; | |
298 | ||
299 | u8 smac_15_0[0x10]; | |
300 | u8 ethertype[0x10]; | |
301 | ||
302 | u8 dmac_47_16[0x20]; | |
303 | ||
304 | u8 dmac_15_0[0x10]; | |
305 | u8 first_prio[0x3]; | |
306 | u8 first_cfi[0x1]; | |
307 | u8 first_vid[0xc]; | |
308 | ||
309 | u8 ip_protocol[0x8]; | |
310 | u8 ip_dscp[0x6]; | |
311 | u8 ip_ecn[0x2]; | |
312 | u8 vlan_tag[0x1]; | |
313 | u8 reserved_0[0x1]; | |
314 | u8 frag[0x1]; | |
315 | u8 reserved_1[0x4]; | |
316 | u8 tcp_flags[0x9]; | |
317 | ||
318 | u8 tcp_sport[0x10]; | |
319 | u8 tcp_dport[0x10]; | |
320 | ||
321 | u8 reserved_2[0x20]; | |
322 | ||
323 | u8 udp_sport[0x10]; | |
324 | u8 udp_dport[0x10]; | |
325 | ||
326 | u8 src_ip[4][0x20]; | |
327 | ||
328 | u8 dst_ip[4][0x20]; | |
329 | }; | |
330 | ||
331 | struct mlx5_ifc_fte_match_set_misc_bits { | |
332 | u8 reserved_0[0x20]; | |
333 | ||
334 | u8 reserved_1[0x10]; | |
335 | u8 source_port[0x10]; | |
336 | ||
337 | u8 outer_second_prio[0x3]; | |
338 | u8 outer_second_cfi[0x1]; | |
339 | u8 outer_second_vid[0xc]; | |
340 | u8 inner_second_prio[0x3]; | |
341 | u8 inner_second_cfi[0x1]; | |
342 | u8 inner_second_vid[0xc]; | |
343 | ||
344 | u8 outer_second_vlan_tag[0x1]; | |
345 | u8 inner_second_vlan_tag[0x1]; | |
346 | u8 reserved_2[0xe]; | |
347 | u8 gre_protocol[0x10]; | |
348 | ||
349 | u8 gre_key_h[0x18]; | |
350 | u8 gre_key_l[0x8]; | |
351 | ||
352 | u8 vxlan_vni[0x18]; | |
353 | u8 reserved_3[0x8]; | |
354 | ||
355 | u8 reserved_4[0x20]; | |
356 | ||
357 | u8 reserved_5[0xc]; | |
358 | u8 outer_ipv6_flow_label[0x14]; | |
359 | ||
360 | u8 reserved_6[0xc]; | |
361 | u8 inner_ipv6_flow_label[0x14]; | |
362 | ||
363 | u8 reserved_7[0xe0]; | |
364 | }; | |
365 | ||
366 | struct mlx5_ifc_cmd_pas_bits { | |
367 | u8 pa_h[0x20]; | |
368 | ||
369 | u8 pa_l[0x14]; | |
370 | u8 reserved_0[0xc]; | |
371 | }; | |
372 | ||
373 | struct mlx5_ifc_uint64_bits { | |
374 | u8 hi[0x20]; | |
375 | ||
376 | u8 lo[0x20]; | |
377 | }; | |
378 | ||
379 | enum { | |
380 | MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, | |
381 | MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, | |
382 | MLX5_ADS_STAT_RATE_10GBPS = 0x8, | |
383 | MLX5_ADS_STAT_RATE_30GBPS = 0x9, | |
384 | MLX5_ADS_STAT_RATE_5GBPS = 0xa, | |
385 | MLX5_ADS_STAT_RATE_20GBPS = 0xb, | |
386 | MLX5_ADS_STAT_RATE_40GBPS = 0xc, | |
387 | MLX5_ADS_STAT_RATE_60GBPS = 0xd, | |
388 | MLX5_ADS_STAT_RATE_80GBPS = 0xe, | |
389 | MLX5_ADS_STAT_RATE_120GBPS = 0xf, | |
390 | }; | |
391 | ||
392 | struct mlx5_ifc_ads_bits { | |
393 | u8 fl[0x1]; | |
394 | u8 free_ar[0x1]; | |
395 | u8 reserved_0[0xe]; | |
396 | u8 pkey_index[0x10]; | |
397 | ||
398 | u8 reserved_1[0x8]; | |
399 | u8 grh[0x1]; | |
400 | u8 mlid[0x7]; | |
401 | u8 rlid[0x10]; | |
402 | ||
403 | u8 ack_timeout[0x5]; | |
404 | u8 reserved_2[0x3]; | |
405 | u8 src_addr_index[0x8]; | |
406 | u8 reserved_3[0x4]; | |
407 | u8 stat_rate[0x4]; | |
408 | u8 hop_limit[0x8]; | |
409 | ||
410 | u8 reserved_4[0x4]; | |
411 | u8 tclass[0x8]; | |
412 | u8 flow_label[0x14]; | |
413 | ||
414 | u8 rgid_rip[16][0x8]; | |
415 | ||
416 | u8 reserved_5[0x4]; | |
417 | u8 f_dscp[0x1]; | |
418 | u8 f_ecn[0x1]; | |
419 | u8 reserved_6[0x1]; | |
420 | u8 f_eth_prio[0x1]; | |
421 | u8 ecn[0x2]; | |
422 | u8 dscp[0x6]; | |
423 | u8 udp_sport[0x10]; | |
424 | ||
425 | u8 dei_cfi[0x1]; | |
426 | u8 eth_prio[0x3]; | |
427 | u8 sl[0x4]; | |
428 | u8 port[0x8]; | |
429 | u8 rmac_47_32[0x10]; | |
430 | ||
431 | u8 rmac_31_0[0x20]; | |
432 | }; | |
433 | ||
434 | struct mlx5_ifc_flow_table_nic_cap_bits { | |
435 | u8 reserved_0[0x200]; | |
436 | ||
437 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; | |
438 | ||
439 | u8 reserved_1[0x200]; | |
440 | ||
441 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; | |
442 | ||
443 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; | |
444 | ||
445 | u8 reserved_2[0x200]; | |
446 | ||
447 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; | |
448 | ||
449 | u8 reserved_3[0x7200]; | |
450 | }; | |
451 | ||
495716b1 SM |
452 | struct mlx5_ifc_flow_table_eswitch_cap_bits { |
453 | u8 reserved_0[0x200]; | |
454 | ||
455 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; | |
456 | ||
457 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; | |
458 | ||
459 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; | |
460 | ||
461 | u8 reserved_1[0x7800]; | |
462 | }; | |
463 | ||
d6666753 SM |
464 | struct mlx5_ifc_e_switch_cap_bits { |
465 | u8 vport_svlan_strip[0x1]; | |
466 | u8 vport_cvlan_strip[0x1]; | |
467 | u8 vport_svlan_insert[0x1]; | |
468 | u8 vport_cvlan_insert_if_not_exist[0x1]; | |
469 | u8 vport_cvlan_insert_overwrite[0x1]; | |
470 | u8 reserved_0[0x1b]; | |
471 | ||
472 | u8 reserved_1[0x7e0]; | |
473 | }; | |
474 | ||
e281682b SM |
475 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits { |
476 | u8 csum_cap[0x1]; | |
477 | u8 vlan_cap[0x1]; | |
478 | u8 lro_cap[0x1]; | |
479 | u8 lro_psh_flag[0x1]; | |
480 | u8 lro_time_stamp[0x1]; | |
66189961 TT |
481 | u8 reserved_0[0x3]; |
482 | u8 self_lb_en_modifiable[0x1]; | |
483 | u8 reserved_1[0x2]; | |
e281682b | 484 | u8 max_lso_cap[0x5]; |
66189961 | 485 | u8 reserved_2[0x4]; |
e281682b | 486 | u8 rss_ind_tbl_cap[0x4]; |
66189961 | 487 | u8 reserved_3[0x3]; |
e281682b | 488 | u8 tunnel_lso_const_out_ip_id[0x1]; |
66189961 | 489 | u8 reserved_4[0x2]; |
e281682b SM |
490 | u8 tunnel_statless_gre[0x1]; |
491 | u8 tunnel_stateless_vxlan[0x1]; | |
492 | ||
66189961 | 493 | u8 reserved_5[0x20]; |
e281682b | 494 | |
66189961 | 495 | u8 reserved_6[0x10]; |
e281682b SM |
496 | u8 lro_min_mss_size[0x10]; |
497 | ||
66189961 | 498 | u8 reserved_7[0x120]; |
e281682b SM |
499 | |
500 | u8 lro_timer_supported_periods[4][0x20]; | |
501 | ||
66189961 | 502 | u8 reserved_8[0x600]; |
e281682b SM |
503 | }; |
504 | ||
505 | struct mlx5_ifc_roce_cap_bits { | |
506 | u8 roce_apm[0x1]; | |
507 | u8 reserved_0[0x1f]; | |
508 | ||
509 | u8 reserved_1[0x60]; | |
510 | ||
511 | u8 reserved_2[0xc]; | |
512 | u8 l3_type[0x4]; | |
513 | u8 reserved_3[0x8]; | |
514 | u8 roce_version[0x8]; | |
515 | ||
516 | u8 reserved_4[0x10]; | |
517 | u8 r_roce_dest_udp_port[0x10]; | |
518 | ||
519 | u8 r_roce_max_src_udp_port[0x10]; | |
520 | u8 r_roce_min_src_udp_port[0x10]; | |
521 | ||
522 | u8 reserved_5[0x10]; | |
523 | u8 roce_address_table_size[0x10]; | |
524 | ||
525 | u8 reserved_6[0x700]; | |
526 | }; | |
527 | ||
528 | enum { | |
529 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, | |
530 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, | |
531 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, | |
532 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, | |
533 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, | |
534 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, | |
535 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, | |
536 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, | |
537 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, | |
538 | }; | |
539 | ||
540 | enum { | |
541 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, | |
542 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, | |
543 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, | |
544 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, | |
545 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, | |
546 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, | |
547 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, | |
548 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, | |
549 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, | |
550 | }; | |
551 | ||
552 | struct mlx5_ifc_atomic_caps_bits { | |
553 | u8 reserved_0[0x40]; | |
554 | ||
555 | u8 atomic_req_endianness[0x1]; | |
556 | u8 reserved_1[0x1f]; | |
557 | ||
558 | u8 reserved_2[0x20]; | |
559 | ||
560 | u8 reserved_3[0x10]; | |
561 | u8 atomic_operations[0x10]; | |
562 | ||
563 | u8 reserved_4[0x10]; | |
564 | u8 atomic_size_qp[0x10]; | |
565 | ||
566 | u8 reserved_5[0x10]; | |
567 | u8 atomic_size_dc[0x10]; | |
568 | ||
569 | u8 reserved_6[0x720]; | |
570 | }; | |
571 | ||
572 | struct mlx5_ifc_odp_cap_bits { | |
573 | u8 reserved_0[0x40]; | |
574 | ||
575 | u8 sig[0x1]; | |
576 | u8 reserved_1[0x1f]; | |
577 | ||
578 | u8 reserved_2[0x20]; | |
579 | ||
580 | struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; | |
581 | ||
582 | struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; | |
583 | ||
584 | struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; | |
585 | ||
586 | u8 reserved_3[0x720]; | |
587 | }; | |
588 | ||
589 | enum { | |
590 | MLX5_WQ_TYPE_LINKED_LIST = 0x0, | |
591 | MLX5_WQ_TYPE_CYCLIC = 0x1, | |
592 | MLX5_WQ_TYPE_STRQ = 0x2, | |
593 | }; | |
594 | ||
595 | enum { | |
596 | MLX5_WQ_END_PAD_MODE_NONE = 0x0, | |
597 | MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, | |
598 | }; | |
599 | ||
600 | enum { | |
601 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, | |
602 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, | |
603 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, | |
604 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, | |
605 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, | |
606 | }; | |
607 | ||
608 | enum { | |
609 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, | |
610 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, | |
611 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, | |
612 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, | |
613 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, | |
614 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, | |
615 | }; | |
616 | ||
617 | enum { | |
618 | MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, | |
619 | MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, | |
620 | }; | |
621 | ||
622 | enum { | |
623 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, | |
624 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, | |
625 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, | |
626 | }; | |
627 | ||
628 | enum { | |
629 | MLX5_CAP_PORT_TYPE_IB = 0x0, | |
630 | MLX5_CAP_PORT_TYPE_ETH = 0x1, | |
d29b796a EC |
631 | }; |
632 | ||
b775516b EC |
633 | struct mlx5_ifc_cmd_hca_cap_bits { |
634 | u8 reserved_0[0x80]; | |
635 | ||
636 | u8 log_max_srq_sz[0x8]; | |
637 | u8 log_max_qp_sz[0x8]; | |
638 | u8 reserved_1[0xb]; | |
639 | u8 log_max_qp[0x5]; | |
640 | ||
e281682b SM |
641 | u8 reserved_2[0xb]; |
642 | u8 log_max_srq[0x5]; | |
b775516b EC |
643 | u8 reserved_3[0x10]; |
644 | ||
645 | u8 reserved_4[0x8]; | |
646 | u8 log_max_cq_sz[0x8]; | |
647 | u8 reserved_5[0xb]; | |
648 | u8 log_max_cq[0x5]; | |
649 | ||
650 | u8 log_max_eq_sz[0x8]; | |
651 | u8 reserved_6[0x2]; | |
652 | u8 log_max_mkey[0x6]; | |
653 | u8 reserved_7[0xc]; | |
654 | u8 log_max_eq[0x4]; | |
655 | ||
656 | u8 max_indirection[0x8]; | |
657 | u8 reserved_8[0x1]; | |
658 | u8 log_max_mrw_sz[0x7]; | |
659 | u8 reserved_9[0x2]; | |
660 | u8 log_max_bsf_list_size[0x6]; | |
661 | u8 reserved_10[0x2]; | |
662 | u8 log_max_klm_list_size[0x6]; | |
663 | ||
664 | u8 reserved_11[0xa]; | |
665 | u8 log_max_ra_req_dc[0x6]; | |
666 | u8 reserved_12[0xa]; | |
667 | u8 log_max_ra_res_dc[0x6]; | |
668 | ||
669 | u8 reserved_13[0xa]; | |
670 | u8 log_max_ra_req_qp[0x6]; | |
671 | u8 reserved_14[0xa]; | |
672 | u8 log_max_ra_res_qp[0x6]; | |
673 | ||
674 | u8 pad_cap[0x1]; | |
675 | u8 cc_query_allowed[0x1]; | |
676 | u8 cc_modify_allowed[0x1]; | |
e281682b SM |
677 | u8 reserved_15[0xd]; |
678 | u8 gid_table_size[0x10]; | |
b775516b | 679 | |
e281682b SM |
680 | u8 out_of_seq_cnt[0x1]; |
681 | u8 vport_counters[0x1]; | |
682 | u8 reserved_16[0x4]; | |
b775516b EC |
683 | u8 max_qp_cnt[0xa]; |
684 | u8 pkey_table_size[0x10]; | |
685 | ||
e281682b SM |
686 | u8 vport_group_manager[0x1]; |
687 | u8 vhca_group_manager[0x1]; | |
688 | u8 ib_virt[0x1]; | |
689 | u8 eth_virt[0x1]; | |
690 | u8 reserved_17[0x1]; | |
691 | u8 ets[0x1]; | |
692 | u8 nic_flow_table[0x1]; | |
54f0a411 | 693 | u8 eswitch_flow_table[0x1]; |
fc50db98 EC |
694 | u8 early_vf_enable; |
695 | u8 reserved_18[0x2]; | |
b775516b | 696 | u8 local_ca_ack_delay[0x5]; |
e281682b SM |
697 | u8 reserved_19[0x6]; |
698 | u8 port_type[0x2]; | |
b775516b EC |
699 | u8 num_ports[0x8]; |
700 | ||
e281682b | 701 | u8 reserved_20[0x3]; |
b775516b | 702 | u8 log_max_msg[0x5]; |
e281682b | 703 | u8 reserved_21[0x18]; |
b775516b EC |
704 | |
705 | u8 stat_rate_support[0x10]; | |
e281682b SM |
706 | u8 reserved_22[0xc]; |
707 | u8 cqe_version[0x4]; | |
b775516b | 708 | |
e281682b SM |
709 | u8 compact_address_vector[0x1]; |
710 | u8 reserved_23[0xe]; | |
711 | u8 drain_sigerr[0x1]; | |
b775516b EC |
712 | u8 cmdif_checksum[0x2]; |
713 | u8 sigerr_cqe[0x1]; | |
e281682b | 714 | u8 reserved_24[0x1]; |
b775516b EC |
715 | u8 wq_signature[0x1]; |
716 | u8 sctr_data_cqe[0x1]; | |
e281682b | 717 | u8 reserved_25[0x1]; |
b775516b EC |
718 | u8 sho[0x1]; |
719 | u8 tph[0x1]; | |
720 | u8 rf[0x1]; | |
e281682b SM |
721 | u8 dct[0x1]; |
722 | u8 reserved_26[0x1]; | |
723 | u8 eth_net_offloads[0x1]; | |
b775516b EC |
724 | u8 roce[0x1]; |
725 | u8 atomic[0x1]; | |
e281682b | 726 | u8 reserved_27[0x1]; |
b775516b EC |
727 | |
728 | u8 cq_oi[0x1]; | |
729 | u8 cq_resize[0x1]; | |
730 | u8 cq_moderation[0x1]; | |
e281682b SM |
731 | u8 reserved_28[0x3]; |
732 | u8 cq_eq_remap[0x1]; | |
b775516b EC |
733 | u8 pg[0x1]; |
734 | u8 block_lb_mc[0x1]; | |
e281682b SM |
735 | u8 reserved_29[0x1]; |
736 | u8 scqe_break_moderation[0x1]; | |
737 | u8 reserved_30[0x1]; | |
b775516b | 738 | u8 cd[0x1]; |
e281682b | 739 | u8 reserved_31[0x1]; |
b775516b | 740 | u8 apm[0x1]; |
e281682b | 741 | u8 reserved_32[0x7]; |
b775516b EC |
742 | u8 qkv[0x1]; |
743 | u8 pkv[0x1]; | |
e281682b | 744 | u8 reserved_33[0x4]; |
b775516b EC |
745 | u8 xrc[0x1]; |
746 | u8 ud[0x1]; | |
747 | u8 uc[0x1]; | |
748 | u8 rc[0x1]; | |
749 | ||
e281682b | 750 | u8 reserved_34[0xa]; |
b775516b | 751 | u8 uar_sz[0x6]; |
e281682b | 752 | u8 reserved_35[0x8]; |
b775516b EC |
753 | u8 log_pg_sz[0x8]; |
754 | ||
755 | u8 bf[0x1]; | |
e281682b SM |
756 | u8 reserved_36[0x1]; |
757 | u8 pad_tx_eth_packet[0x1]; | |
758 | u8 reserved_37[0x8]; | |
b775516b | 759 | u8 log_bf_reg_size[0x5]; |
e281682b | 760 | u8 reserved_38[0x10]; |
b775516b | 761 | |
e281682b | 762 | u8 reserved_39[0x10]; |
b775516b EC |
763 | u8 max_wqe_sz_sq[0x10]; |
764 | ||
e281682b | 765 | u8 reserved_40[0x10]; |
b775516b EC |
766 | u8 max_wqe_sz_rq[0x10]; |
767 | ||
e281682b | 768 | u8 reserved_41[0x10]; |
b775516b EC |
769 | u8 max_wqe_sz_sq_dc[0x10]; |
770 | ||
e281682b | 771 | u8 reserved_42[0x7]; |
b775516b EC |
772 | u8 max_qp_mcg[0x19]; |
773 | ||
e281682b | 774 | u8 reserved_43[0x18]; |
b775516b EC |
775 | u8 log_max_mcg[0x8]; |
776 | ||
e281682b SM |
777 | u8 reserved_44[0x3]; |
778 | u8 log_max_transport_domain[0x5]; | |
779 | u8 reserved_45[0x3]; | |
b775516b | 780 | u8 log_max_pd[0x5]; |
e281682b | 781 | u8 reserved_46[0xb]; |
b775516b EC |
782 | u8 log_max_xrcd[0x5]; |
783 | ||
e281682b | 784 | u8 reserved_47[0x20]; |
b775516b | 785 | |
e281682b | 786 | u8 reserved_48[0x3]; |
b775516b | 787 | u8 log_max_rq[0x5]; |
e281682b | 788 | u8 reserved_49[0x3]; |
b775516b | 789 | u8 log_max_sq[0x5]; |
e281682b | 790 | u8 reserved_50[0x3]; |
b775516b | 791 | u8 log_max_tir[0x5]; |
e281682b | 792 | u8 reserved_51[0x3]; |
b775516b EC |
793 | u8 log_max_tis[0x5]; |
794 | ||
e281682b SM |
795 | u8 basic_cyclic_rcv_wqe[0x1]; |
796 | u8 reserved_52[0x2]; | |
797 | u8 log_max_rmp[0x5]; | |
798 | u8 reserved_53[0x3]; | |
799 | u8 log_max_rqt[0x5]; | |
800 | u8 reserved_54[0x3]; | |
801 | u8 log_max_rqt_size[0x5]; | |
802 | u8 reserved_55[0x3]; | |
b775516b EC |
803 | u8 log_max_tis_per_sq[0x5]; |
804 | ||
e281682b SM |
805 | u8 reserved_56[0x3]; |
806 | u8 log_max_stride_sz_rq[0x5]; | |
807 | u8 reserved_57[0x3]; | |
808 | u8 log_min_stride_sz_rq[0x5]; | |
809 | u8 reserved_58[0x3]; | |
810 | u8 log_max_stride_sz_sq[0x5]; | |
811 | u8 reserved_59[0x3]; | |
812 | u8 log_min_stride_sz_sq[0x5]; | |
813 | ||
814 | u8 reserved_60[0x1b]; | |
815 | u8 log_max_wq_sz[0x5]; | |
816 | ||
54f0a411 SM |
817 | u8 nic_vport_change_event[0x1]; |
818 | u8 reserved_61[0xa]; | |
819 | u8 log_max_vlan_list[0x5]; | |
e281682b | 820 | u8 reserved_62[0x3]; |
54f0a411 SM |
821 | u8 log_max_current_mc_list[0x5]; |
822 | u8 reserved_63[0x3]; | |
823 | u8 log_max_current_uc_list[0x5]; | |
824 | ||
825 | u8 reserved_64[0x80]; | |
826 | ||
827 | u8 reserved_65[0x3]; | |
e281682b | 828 | u8 log_max_l2_table[0x5]; |
54f0a411 | 829 | u8 reserved_66[0x8]; |
b775516b EC |
830 | u8 log_uar_page_sz[0x10]; |
831 | ||
b0844444 EBE |
832 | u8 reserved_67[0x40]; |
833 | u8 device_frequency_khz[0x20]; | |
834 | u8 reserved_68[0x5f]; | |
b775516b EC |
835 | u8 cqe_zip[0x1]; |
836 | ||
837 | u8 cqe_zip_timeout[0x10]; | |
838 | u8 cqe_zip_max_num[0x10]; | |
839 | ||
54f0a411 | 840 | u8 reserved_69[0x220]; |
b775516b EC |
841 | }; |
842 | ||
81848731 SM |
843 | enum mlx5_flow_destination_type { |
844 | MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, | |
845 | MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, | |
846 | MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, | |
e281682b | 847 | }; |
b775516b | 848 | |
e281682b SM |
849 | struct mlx5_ifc_dest_format_struct_bits { |
850 | u8 destination_type[0x8]; | |
851 | u8 destination_id[0x18]; | |
b775516b | 852 | |
e281682b SM |
853 | u8 reserved_0[0x20]; |
854 | }; | |
855 | ||
856 | struct mlx5_ifc_fte_match_param_bits { | |
857 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; | |
858 | ||
859 | struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; | |
860 | ||
861 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; | |
b775516b | 862 | |
e281682b | 863 | u8 reserved_0[0xa00]; |
b775516b EC |
864 | }; |
865 | ||
e281682b SM |
866 | enum { |
867 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, | |
868 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, | |
869 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, | |
870 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, | |
871 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, | |
872 | }; | |
b775516b | 873 | |
e281682b SM |
874 | struct mlx5_ifc_rx_hash_field_select_bits { |
875 | u8 l3_prot_type[0x1]; | |
876 | u8 l4_prot_type[0x1]; | |
877 | u8 selected_fields[0x1e]; | |
878 | }; | |
b775516b | 879 | |
e281682b SM |
880 | enum { |
881 | MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, | |
882 | MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, | |
b775516b EC |
883 | }; |
884 | ||
e281682b SM |
885 | enum { |
886 | MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, | |
887 | MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, | |
888 | }; | |
889 | ||
890 | struct mlx5_ifc_wq_bits { | |
891 | u8 wq_type[0x4]; | |
892 | u8 wq_signature[0x1]; | |
893 | u8 end_padding_mode[0x2]; | |
894 | u8 cd_slave[0x1]; | |
b775516b EC |
895 | u8 reserved_0[0x18]; |
896 | ||
e281682b SM |
897 | u8 hds_skip_first_sge[0x1]; |
898 | u8 log2_hds_buf_size[0x3]; | |
899 | u8 reserved_1[0x7]; | |
900 | u8 page_offset[0x5]; | |
901 | u8 lwm[0x10]; | |
b775516b | 902 | |
e281682b SM |
903 | u8 reserved_2[0x8]; |
904 | u8 pd[0x18]; | |
905 | ||
906 | u8 reserved_3[0x8]; | |
907 | u8 uar_page[0x18]; | |
908 | ||
909 | u8 dbr_addr[0x40]; | |
910 | ||
911 | u8 hw_counter[0x20]; | |
912 | ||
913 | u8 sw_counter[0x20]; | |
914 | ||
915 | u8 reserved_4[0xc]; | |
916 | u8 log_wq_stride[0x4]; | |
917 | u8 reserved_5[0x3]; | |
918 | u8 log_wq_pg_sz[0x5]; | |
919 | u8 reserved_6[0x3]; | |
920 | u8 log_wq_sz[0x5]; | |
921 | ||
922 | u8 reserved_7[0x4e0]; | |
b775516b | 923 | |
e281682b | 924 | struct mlx5_ifc_cmd_pas_bits pas[0]; |
b775516b EC |
925 | }; |
926 | ||
e281682b SM |
927 | struct mlx5_ifc_rq_num_bits { |
928 | u8 reserved_0[0x8]; | |
929 | u8 rq_num[0x18]; | |
930 | }; | |
b775516b | 931 | |
e281682b SM |
932 | struct mlx5_ifc_mac_address_layout_bits { |
933 | u8 reserved_0[0x10]; | |
934 | u8 mac_addr_47_32[0x10]; | |
b775516b | 935 | |
e281682b SM |
936 | u8 mac_addr_31_0[0x20]; |
937 | }; | |
938 | ||
c0046cf7 SM |
939 | struct mlx5_ifc_vlan_layout_bits { |
940 | u8 reserved_0[0x14]; | |
941 | u8 vlan[0x0c]; | |
942 | ||
943 | u8 reserved_1[0x20]; | |
944 | }; | |
945 | ||
e281682b SM |
946 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { |
947 | u8 reserved_0[0xa0]; | |
948 | ||
949 | u8 min_time_between_cnps[0x20]; | |
950 | ||
951 | u8 reserved_1[0x12]; | |
952 | u8 cnp_dscp[0x6]; | |
953 | u8 reserved_2[0x5]; | |
954 | u8 cnp_802p_prio[0x3]; | |
955 | ||
956 | u8 reserved_3[0x720]; | |
957 | }; | |
958 | ||
959 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { | |
960 | u8 reserved_0[0x60]; | |
961 | ||
962 | u8 reserved_1[0x4]; | |
963 | u8 clamp_tgt_rate[0x1]; | |
964 | u8 reserved_2[0x3]; | |
965 | u8 clamp_tgt_rate_after_time_inc[0x1]; | |
966 | u8 reserved_3[0x17]; | |
967 | ||
968 | u8 reserved_4[0x20]; | |
969 | ||
970 | u8 rpg_time_reset[0x20]; | |
971 | ||
972 | u8 rpg_byte_reset[0x20]; | |
973 | ||
974 | u8 rpg_threshold[0x20]; | |
975 | ||
976 | u8 rpg_max_rate[0x20]; | |
977 | ||
978 | u8 rpg_ai_rate[0x20]; | |
979 | ||
980 | u8 rpg_hai_rate[0x20]; | |
981 | ||
982 | u8 rpg_gd[0x20]; | |
983 | ||
984 | u8 rpg_min_dec_fac[0x20]; | |
985 | ||
986 | u8 rpg_min_rate[0x20]; | |
987 | ||
988 | u8 reserved_5[0xe0]; | |
989 | ||
990 | u8 rate_to_set_on_first_cnp[0x20]; | |
991 | ||
992 | u8 dce_tcp_g[0x20]; | |
993 | ||
994 | u8 dce_tcp_rtt[0x20]; | |
995 | ||
996 | u8 rate_reduce_monitor_period[0x20]; | |
997 | ||
998 | u8 reserved_6[0x20]; | |
999 | ||
1000 | u8 initial_alpha_value[0x20]; | |
1001 | ||
1002 | u8 reserved_7[0x4a0]; | |
1003 | }; | |
1004 | ||
1005 | struct mlx5_ifc_cong_control_802_1qau_rp_bits { | |
1006 | u8 reserved_0[0x80]; | |
1007 | ||
1008 | u8 rppp_max_rps[0x20]; | |
1009 | ||
1010 | u8 rpg_time_reset[0x20]; | |
1011 | ||
1012 | u8 rpg_byte_reset[0x20]; | |
1013 | ||
1014 | u8 rpg_threshold[0x20]; | |
1015 | ||
1016 | u8 rpg_max_rate[0x20]; | |
1017 | ||
1018 | u8 rpg_ai_rate[0x20]; | |
1019 | ||
1020 | u8 rpg_hai_rate[0x20]; | |
1021 | ||
1022 | u8 rpg_gd[0x20]; | |
1023 | ||
1024 | u8 rpg_min_dec_fac[0x20]; | |
1025 | ||
1026 | u8 rpg_min_rate[0x20]; | |
1027 | ||
1028 | u8 reserved_1[0x640]; | |
1029 | }; | |
1030 | ||
1031 | enum { | |
1032 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, | |
1033 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, | |
1034 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, | |
1035 | }; | |
1036 | ||
1037 | struct mlx5_ifc_resize_field_select_bits { | |
1038 | u8 resize_field_select[0x20]; | |
1039 | }; | |
1040 | ||
1041 | enum { | |
1042 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, | |
1043 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, | |
1044 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, | |
1045 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, | |
1046 | }; | |
1047 | ||
1048 | struct mlx5_ifc_modify_field_select_bits { | |
1049 | u8 modify_field_select[0x20]; | |
1050 | }; | |
1051 | ||
1052 | struct mlx5_ifc_field_select_r_roce_np_bits { | |
1053 | u8 field_select_r_roce_np[0x20]; | |
1054 | }; | |
1055 | ||
1056 | struct mlx5_ifc_field_select_r_roce_rp_bits { | |
1057 | u8 field_select_r_roce_rp[0x20]; | |
1058 | }; | |
1059 | ||
1060 | enum { | |
1061 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, | |
1062 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, | |
1063 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, | |
1064 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, | |
1065 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, | |
1066 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, | |
1067 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, | |
1068 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, | |
1069 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, | |
1070 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, | |
1071 | }; | |
1072 | ||
1073 | struct mlx5_ifc_field_select_802_1qau_rp_bits { | |
1074 | u8 field_select_8021qaurp[0x20]; | |
1075 | }; | |
1076 | ||
1077 | struct mlx5_ifc_phys_layer_cntrs_bits { | |
1078 | u8 time_since_last_clear_high[0x20]; | |
1079 | ||
1080 | u8 time_since_last_clear_low[0x20]; | |
1081 | ||
1082 | u8 symbol_errors_high[0x20]; | |
1083 | ||
1084 | u8 symbol_errors_low[0x20]; | |
1085 | ||
1086 | u8 sync_headers_errors_high[0x20]; | |
1087 | ||
1088 | u8 sync_headers_errors_low[0x20]; | |
1089 | ||
1090 | u8 edpl_bip_errors_lane0_high[0x20]; | |
1091 | ||
1092 | u8 edpl_bip_errors_lane0_low[0x20]; | |
1093 | ||
1094 | u8 edpl_bip_errors_lane1_high[0x20]; | |
1095 | ||
1096 | u8 edpl_bip_errors_lane1_low[0x20]; | |
1097 | ||
1098 | u8 edpl_bip_errors_lane2_high[0x20]; | |
1099 | ||
1100 | u8 edpl_bip_errors_lane2_low[0x20]; | |
1101 | ||
1102 | u8 edpl_bip_errors_lane3_high[0x20]; | |
1103 | ||
1104 | u8 edpl_bip_errors_lane3_low[0x20]; | |
1105 | ||
1106 | u8 fc_fec_corrected_blocks_lane0_high[0x20]; | |
1107 | ||
1108 | u8 fc_fec_corrected_blocks_lane0_low[0x20]; | |
1109 | ||
1110 | u8 fc_fec_corrected_blocks_lane1_high[0x20]; | |
1111 | ||
1112 | u8 fc_fec_corrected_blocks_lane1_low[0x20]; | |
1113 | ||
1114 | u8 fc_fec_corrected_blocks_lane2_high[0x20]; | |
1115 | ||
1116 | u8 fc_fec_corrected_blocks_lane2_low[0x20]; | |
1117 | ||
1118 | u8 fc_fec_corrected_blocks_lane3_high[0x20]; | |
1119 | ||
1120 | u8 fc_fec_corrected_blocks_lane3_low[0x20]; | |
1121 | ||
1122 | u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; | |
1123 | ||
1124 | u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; | |
1125 | ||
1126 | u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; | |
1127 | ||
1128 | u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; | |
1129 | ||
1130 | u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; | |
1131 | ||
1132 | u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; | |
1133 | ||
1134 | u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; | |
1135 | ||
1136 | u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; | |
1137 | ||
1138 | u8 rs_fec_corrected_blocks_high[0x20]; | |
1139 | ||
1140 | u8 rs_fec_corrected_blocks_low[0x20]; | |
1141 | ||
1142 | u8 rs_fec_uncorrectable_blocks_high[0x20]; | |
1143 | ||
1144 | u8 rs_fec_uncorrectable_blocks_low[0x20]; | |
1145 | ||
1146 | u8 rs_fec_no_errors_blocks_high[0x20]; | |
1147 | ||
1148 | u8 rs_fec_no_errors_blocks_low[0x20]; | |
1149 | ||
1150 | u8 rs_fec_single_error_blocks_high[0x20]; | |
1151 | ||
1152 | u8 rs_fec_single_error_blocks_low[0x20]; | |
1153 | ||
1154 | u8 rs_fec_corrected_symbols_total_high[0x20]; | |
1155 | ||
1156 | u8 rs_fec_corrected_symbols_total_low[0x20]; | |
1157 | ||
1158 | u8 rs_fec_corrected_symbols_lane0_high[0x20]; | |
1159 | ||
1160 | u8 rs_fec_corrected_symbols_lane0_low[0x20]; | |
1161 | ||
1162 | u8 rs_fec_corrected_symbols_lane1_high[0x20]; | |
1163 | ||
1164 | u8 rs_fec_corrected_symbols_lane1_low[0x20]; | |
1165 | ||
1166 | u8 rs_fec_corrected_symbols_lane2_high[0x20]; | |
1167 | ||
1168 | u8 rs_fec_corrected_symbols_lane2_low[0x20]; | |
1169 | ||
1170 | u8 rs_fec_corrected_symbols_lane3_high[0x20]; | |
1171 | ||
1172 | u8 rs_fec_corrected_symbols_lane3_low[0x20]; | |
1173 | ||
1174 | u8 link_down_events[0x20]; | |
1175 | ||
1176 | u8 successful_recovery_events[0x20]; | |
1177 | ||
1178 | u8 reserved_0[0x180]; | |
1179 | }; | |
1180 | ||
1181 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { | |
1182 | u8 transmit_queue_high[0x20]; | |
1183 | ||
1184 | u8 transmit_queue_low[0x20]; | |
1185 | ||
1186 | u8 reserved_0[0x780]; | |
1187 | }; | |
1188 | ||
1189 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { | |
1190 | u8 rx_octets_high[0x20]; | |
1191 | ||
1192 | u8 rx_octets_low[0x20]; | |
1193 | ||
1194 | u8 reserved_0[0xc0]; | |
1195 | ||
1196 | u8 rx_frames_high[0x20]; | |
1197 | ||
1198 | u8 rx_frames_low[0x20]; | |
1199 | ||
1200 | u8 tx_octets_high[0x20]; | |
1201 | ||
1202 | u8 tx_octets_low[0x20]; | |
1203 | ||
1204 | u8 reserved_1[0xc0]; | |
1205 | ||
1206 | u8 tx_frames_high[0x20]; | |
1207 | ||
1208 | u8 tx_frames_low[0x20]; | |
1209 | ||
1210 | u8 rx_pause_high[0x20]; | |
1211 | ||
1212 | u8 rx_pause_low[0x20]; | |
1213 | ||
1214 | u8 rx_pause_duration_high[0x20]; | |
1215 | ||
1216 | u8 rx_pause_duration_low[0x20]; | |
1217 | ||
1218 | u8 tx_pause_high[0x20]; | |
1219 | ||
1220 | u8 tx_pause_low[0x20]; | |
1221 | ||
1222 | u8 tx_pause_duration_high[0x20]; | |
1223 | ||
1224 | u8 tx_pause_duration_low[0x20]; | |
1225 | ||
1226 | u8 rx_pause_transition_high[0x20]; | |
1227 | ||
1228 | u8 rx_pause_transition_low[0x20]; | |
1229 | ||
1230 | u8 reserved_2[0x400]; | |
1231 | }; | |
1232 | ||
1233 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { | |
1234 | u8 port_transmit_wait_high[0x20]; | |
1235 | ||
1236 | u8 port_transmit_wait_low[0x20]; | |
1237 | ||
1238 | u8 reserved_0[0x780]; | |
1239 | }; | |
1240 | ||
1241 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { | |
1242 | u8 dot3stats_alignment_errors_high[0x20]; | |
1243 | ||
1244 | u8 dot3stats_alignment_errors_low[0x20]; | |
1245 | ||
1246 | u8 dot3stats_fcs_errors_high[0x20]; | |
1247 | ||
1248 | u8 dot3stats_fcs_errors_low[0x20]; | |
1249 | ||
1250 | u8 dot3stats_single_collision_frames_high[0x20]; | |
1251 | ||
1252 | u8 dot3stats_single_collision_frames_low[0x20]; | |
1253 | ||
1254 | u8 dot3stats_multiple_collision_frames_high[0x20]; | |
1255 | ||
1256 | u8 dot3stats_multiple_collision_frames_low[0x20]; | |
1257 | ||
1258 | u8 dot3stats_sqe_test_errors_high[0x20]; | |
1259 | ||
1260 | u8 dot3stats_sqe_test_errors_low[0x20]; | |
1261 | ||
1262 | u8 dot3stats_deferred_transmissions_high[0x20]; | |
1263 | ||
1264 | u8 dot3stats_deferred_transmissions_low[0x20]; | |
1265 | ||
1266 | u8 dot3stats_late_collisions_high[0x20]; | |
1267 | ||
1268 | u8 dot3stats_late_collisions_low[0x20]; | |
1269 | ||
1270 | u8 dot3stats_excessive_collisions_high[0x20]; | |
1271 | ||
1272 | u8 dot3stats_excessive_collisions_low[0x20]; | |
1273 | ||
1274 | u8 dot3stats_internal_mac_transmit_errors_high[0x20]; | |
1275 | ||
1276 | u8 dot3stats_internal_mac_transmit_errors_low[0x20]; | |
1277 | ||
1278 | u8 dot3stats_carrier_sense_errors_high[0x20]; | |
1279 | ||
1280 | u8 dot3stats_carrier_sense_errors_low[0x20]; | |
1281 | ||
1282 | u8 dot3stats_frame_too_longs_high[0x20]; | |
1283 | ||
1284 | u8 dot3stats_frame_too_longs_low[0x20]; | |
1285 | ||
1286 | u8 dot3stats_internal_mac_receive_errors_high[0x20]; | |
1287 | ||
1288 | u8 dot3stats_internal_mac_receive_errors_low[0x20]; | |
1289 | ||
1290 | u8 dot3stats_symbol_errors_high[0x20]; | |
1291 | ||
1292 | u8 dot3stats_symbol_errors_low[0x20]; | |
1293 | ||
1294 | u8 dot3control_in_unknown_opcodes_high[0x20]; | |
1295 | ||
1296 | u8 dot3control_in_unknown_opcodes_low[0x20]; | |
1297 | ||
1298 | u8 dot3in_pause_frames_high[0x20]; | |
1299 | ||
1300 | u8 dot3in_pause_frames_low[0x20]; | |
1301 | ||
1302 | u8 dot3out_pause_frames_high[0x20]; | |
1303 | ||
1304 | u8 dot3out_pause_frames_low[0x20]; | |
1305 | ||
1306 | u8 reserved_0[0x3c0]; | |
1307 | }; | |
1308 | ||
1309 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { | |
1310 | u8 ether_stats_drop_events_high[0x20]; | |
1311 | ||
1312 | u8 ether_stats_drop_events_low[0x20]; | |
1313 | ||
1314 | u8 ether_stats_octets_high[0x20]; | |
1315 | ||
1316 | u8 ether_stats_octets_low[0x20]; | |
1317 | ||
1318 | u8 ether_stats_pkts_high[0x20]; | |
1319 | ||
1320 | u8 ether_stats_pkts_low[0x20]; | |
1321 | ||
1322 | u8 ether_stats_broadcast_pkts_high[0x20]; | |
1323 | ||
1324 | u8 ether_stats_broadcast_pkts_low[0x20]; | |
1325 | ||
1326 | u8 ether_stats_multicast_pkts_high[0x20]; | |
1327 | ||
1328 | u8 ether_stats_multicast_pkts_low[0x20]; | |
1329 | ||
1330 | u8 ether_stats_crc_align_errors_high[0x20]; | |
1331 | ||
1332 | u8 ether_stats_crc_align_errors_low[0x20]; | |
1333 | ||
1334 | u8 ether_stats_undersize_pkts_high[0x20]; | |
1335 | ||
1336 | u8 ether_stats_undersize_pkts_low[0x20]; | |
1337 | ||
1338 | u8 ether_stats_oversize_pkts_high[0x20]; | |
1339 | ||
1340 | u8 ether_stats_oversize_pkts_low[0x20]; | |
1341 | ||
1342 | u8 ether_stats_fragments_high[0x20]; | |
1343 | ||
1344 | u8 ether_stats_fragments_low[0x20]; | |
1345 | ||
1346 | u8 ether_stats_jabbers_high[0x20]; | |
1347 | ||
1348 | u8 ether_stats_jabbers_low[0x20]; | |
1349 | ||
1350 | u8 ether_stats_collisions_high[0x20]; | |
1351 | ||
1352 | u8 ether_stats_collisions_low[0x20]; | |
1353 | ||
1354 | u8 ether_stats_pkts64octets_high[0x20]; | |
1355 | ||
1356 | u8 ether_stats_pkts64octets_low[0x20]; | |
1357 | ||
1358 | u8 ether_stats_pkts65to127octets_high[0x20]; | |
1359 | ||
1360 | u8 ether_stats_pkts65to127octets_low[0x20]; | |
1361 | ||
1362 | u8 ether_stats_pkts128to255octets_high[0x20]; | |
1363 | ||
1364 | u8 ether_stats_pkts128to255octets_low[0x20]; | |
1365 | ||
1366 | u8 ether_stats_pkts256to511octets_high[0x20]; | |
1367 | ||
1368 | u8 ether_stats_pkts256to511octets_low[0x20]; | |
1369 | ||
1370 | u8 ether_stats_pkts512to1023octets_high[0x20]; | |
1371 | ||
1372 | u8 ether_stats_pkts512to1023octets_low[0x20]; | |
1373 | ||
1374 | u8 ether_stats_pkts1024to1518octets_high[0x20]; | |
1375 | ||
1376 | u8 ether_stats_pkts1024to1518octets_low[0x20]; | |
1377 | ||
1378 | u8 ether_stats_pkts1519to2047octets_high[0x20]; | |
1379 | ||
1380 | u8 ether_stats_pkts1519to2047octets_low[0x20]; | |
1381 | ||
1382 | u8 ether_stats_pkts2048to4095octets_high[0x20]; | |
1383 | ||
1384 | u8 ether_stats_pkts2048to4095octets_low[0x20]; | |
1385 | ||
1386 | u8 ether_stats_pkts4096to8191octets_high[0x20]; | |
1387 | ||
1388 | u8 ether_stats_pkts4096to8191octets_low[0x20]; | |
1389 | ||
1390 | u8 ether_stats_pkts8192to10239octets_high[0x20]; | |
1391 | ||
1392 | u8 ether_stats_pkts8192to10239octets_low[0x20]; | |
1393 | ||
1394 | u8 reserved_0[0x280]; | |
1395 | }; | |
1396 | ||
1397 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { | |
1398 | u8 if_in_octets_high[0x20]; | |
1399 | ||
1400 | u8 if_in_octets_low[0x20]; | |
1401 | ||
1402 | u8 if_in_ucast_pkts_high[0x20]; | |
1403 | ||
1404 | u8 if_in_ucast_pkts_low[0x20]; | |
1405 | ||
1406 | u8 if_in_discards_high[0x20]; | |
1407 | ||
1408 | u8 if_in_discards_low[0x20]; | |
1409 | ||
1410 | u8 if_in_errors_high[0x20]; | |
1411 | ||
1412 | u8 if_in_errors_low[0x20]; | |
1413 | ||
1414 | u8 if_in_unknown_protos_high[0x20]; | |
1415 | ||
1416 | u8 if_in_unknown_protos_low[0x20]; | |
1417 | ||
1418 | u8 if_out_octets_high[0x20]; | |
1419 | ||
1420 | u8 if_out_octets_low[0x20]; | |
1421 | ||
1422 | u8 if_out_ucast_pkts_high[0x20]; | |
1423 | ||
1424 | u8 if_out_ucast_pkts_low[0x20]; | |
1425 | ||
1426 | u8 if_out_discards_high[0x20]; | |
1427 | ||
1428 | u8 if_out_discards_low[0x20]; | |
1429 | ||
1430 | u8 if_out_errors_high[0x20]; | |
1431 | ||
1432 | u8 if_out_errors_low[0x20]; | |
1433 | ||
1434 | u8 if_in_multicast_pkts_high[0x20]; | |
1435 | ||
1436 | u8 if_in_multicast_pkts_low[0x20]; | |
1437 | ||
1438 | u8 if_in_broadcast_pkts_high[0x20]; | |
1439 | ||
1440 | u8 if_in_broadcast_pkts_low[0x20]; | |
1441 | ||
1442 | u8 if_out_multicast_pkts_high[0x20]; | |
1443 | ||
1444 | u8 if_out_multicast_pkts_low[0x20]; | |
1445 | ||
1446 | u8 if_out_broadcast_pkts_high[0x20]; | |
1447 | ||
1448 | u8 if_out_broadcast_pkts_low[0x20]; | |
1449 | ||
1450 | u8 reserved_0[0x480]; | |
1451 | }; | |
1452 | ||
1453 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { | |
1454 | u8 a_frames_transmitted_ok_high[0x20]; | |
1455 | ||
1456 | u8 a_frames_transmitted_ok_low[0x20]; | |
1457 | ||
1458 | u8 a_frames_received_ok_high[0x20]; | |
1459 | ||
1460 | u8 a_frames_received_ok_low[0x20]; | |
1461 | ||
1462 | u8 a_frame_check_sequence_errors_high[0x20]; | |
1463 | ||
1464 | u8 a_frame_check_sequence_errors_low[0x20]; | |
1465 | ||
1466 | u8 a_alignment_errors_high[0x20]; | |
1467 | ||
1468 | u8 a_alignment_errors_low[0x20]; | |
1469 | ||
1470 | u8 a_octets_transmitted_ok_high[0x20]; | |
1471 | ||
1472 | u8 a_octets_transmitted_ok_low[0x20]; | |
1473 | ||
1474 | u8 a_octets_received_ok_high[0x20]; | |
1475 | ||
1476 | u8 a_octets_received_ok_low[0x20]; | |
1477 | ||
1478 | u8 a_multicast_frames_xmitted_ok_high[0x20]; | |
1479 | ||
1480 | u8 a_multicast_frames_xmitted_ok_low[0x20]; | |
1481 | ||
1482 | u8 a_broadcast_frames_xmitted_ok_high[0x20]; | |
1483 | ||
1484 | u8 a_broadcast_frames_xmitted_ok_low[0x20]; | |
1485 | ||
1486 | u8 a_multicast_frames_received_ok_high[0x20]; | |
1487 | ||
1488 | u8 a_multicast_frames_received_ok_low[0x20]; | |
1489 | ||
1490 | u8 a_broadcast_frames_received_ok_high[0x20]; | |
1491 | ||
1492 | u8 a_broadcast_frames_received_ok_low[0x20]; | |
1493 | ||
1494 | u8 a_in_range_length_errors_high[0x20]; | |
1495 | ||
1496 | u8 a_in_range_length_errors_low[0x20]; | |
1497 | ||
1498 | u8 a_out_of_range_length_field_high[0x20]; | |
1499 | ||
1500 | u8 a_out_of_range_length_field_low[0x20]; | |
1501 | ||
1502 | u8 a_frame_too_long_errors_high[0x20]; | |
1503 | ||
1504 | u8 a_frame_too_long_errors_low[0x20]; | |
1505 | ||
1506 | u8 a_symbol_error_during_carrier_high[0x20]; | |
1507 | ||
1508 | u8 a_symbol_error_during_carrier_low[0x20]; | |
1509 | ||
1510 | u8 a_mac_control_frames_transmitted_high[0x20]; | |
1511 | ||
1512 | u8 a_mac_control_frames_transmitted_low[0x20]; | |
1513 | ||
1514 | u8 a_mac_control_frames_received_high[0x20]; | |
1515 | ||
1516 | u8 a_mac_control_frames_received_low[0x20]; | |
1517 | ||
1518 | u8 a_unsupported_opcodes_received_high[0x20]; | |
1519 | ||
1520 | u8 a_unsupported_opcodes_received_low[0x20]; | |
1521 | ||
1522 | u8 a_pause_mac_ctrl_frames_received_high[0x20]; | |
1523 | ||
1524 | u8 a_pause_mac_ctrl_frames_received_low[0x20]; | |
1525 | ||
1526 | u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; | |
1527 | ||
1528 | u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; | |
1529 | ||
1530 | u8 reserved_0[0x300]; | |
1531 | }; | |
1532 | ||
1533 | struct mlx5_ifc_cmd_inter_comp_event_bits { | |
1534 | u8 command_completion_vector[0x20]; | |
1535 | ||
1536 | u8 reserved_0[0xc0]; | |
1537 | }; | |
1538 | ||
1539 | struct mlx5_ifc_stall_vl_event_bits { | |
1540 | u8 reserved_0[0x18]; | |
1541 | u8 port_num[0x1]; | |
1542 | u8 reserved_1[0x3]; | |
1543 | u8 vl[0x4]; | |
1544 | ||
1545 | u8 reserved_2[0xa0]; | |
1546 | }; | |
1547 | ||
1548 | struct mlx5_ifc_db_bf_congestion_event_bits { | |
1549 | u8 event_subtype[0x8]; | |
1550 | u8 reserved_0[0x8]; | |
1551 | u8 congestion_level[0x8]; | |
1552 | u8 reserved_1[0x8]; | |
1553 | ||
1554 | u8 reserved_2[0xa0]; | |
1555 | }; | |
1556 | ||
1557 | struct mlx5_ifc_gpio_event_bits { | |
1558 | u8 reserved_0[0x60]; | |
1559 | ||
1560 | u8 gpio_event_hi[0x20]; | |
1561 | ||
1562 | u8 gpio_event_lo[0x20]; | |
1563 | ||
1564 | u8 reserved_1[0x40]; | |
1565 | }; | |
1566 | ||
1567 | struct mlx5_ifc_port_state_change_event_bits { | |
1568 | u8 reserved_0[0x40]; | |
1569 | ||
1570 | u8 port_num[0x4]; | |
1571 | u8 reserved_1[0x1c]; | |
1572 | ||
1573 | u8 reserved_2[0x80]; | |
1574 | }; | |
1575 | ||
1576 | struct mlx5_ifc_dropped_packet_logged_bits { | |
1577 | u8 reserved_0[0xe0]; | |
1578 | }; | |
1579 | ||
1580 | enum { | |
1581 | MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, | |
1582 | MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, | |
1583 | }; | |
1584 | ||
1585 | struct mlx5_ifc_cq_error_bits { | |
1586 | u8 reserved_0[0x8]; | |
1587 | u8 cqn[0x18]; | |
1588 | ||
1589 | u8 reserved_1[0x20]; | |
1590 | ||
1591 | u8 reserved_2[0x18]; | |
1592 | u8 syndrome[0x8]; | |
1593 | ||
1594 | u8 reserved_3[0x80]; | |
1595 | }; | |
1596 | ||
1597 | struct mlx5_ifc_rdma_page_fault_event_bits { | |
1598 | u8 bytes_committed[0x20]; | |
1599 | ||
1600 | u8 r_key[0x20]; | |
1601 | ||
1602 | u8 reserved_0[0x10]; | |
1603 | u8 packet_len[0x10]; | |
1604 | ||
1605 | u8 rdma_op_len[0x20]; | |
1606 | ||
1607 | u8 rdma_va[0x40]; | |
1608 | ||
1609 | u8 reserved_1[0x5]; | |
1610 | u8 rdma[0x1]; | |
1611 | u8 write[0x1]; | |
1612 | u8 requestor[0x1]; | |
1613 | u8 qp_number[0x18]; | |
1614 | }; | |
1615 | ||
1616 | struct mlx5_ifc_wqe_associated_page_fault_event_bits { | |
1617 | u8 bytes_committed[0x20]; | |
1618 | ||
1619 | u8 reserved_0[0x10]; | |
1620 | u8 wqe_index[0x10]; | |
1621 | ||
1622 | u8 reserved_1[0x10]; | |
1623 | u8 len[0x10]; | |
1624 | ||
1625 | u8 reserved_2[0x60]; | |
1626 | ||
1627 | u8 reserved_3[0x5]; | |
1628 | u8 rdma[0x1]; | |
1629 | u8 write_read[0x1]; | |
1630 | u8 requestor[0x1]; | |
1631 | u8 qpn[0x18]; | |
1632 | }; | |
1633 | ||
1634 | struct mlx5_ifc_qp_events_bits { | |
1635 | u8 reserved_0[0xa0]; | |
1636 | ||
1637 | u8 type[0x8]; | |
1638 | u8 reserved_1[0x18]; | |
1639 | ||
1640 | u8 reserved_2[0x8]; | |
1641 | u8 qpn_rqn_sqn[0x18]; | |
1642 | }; | |
1643 | ||
1644 | struct mlx5_ifc_dct_events_bits { | |
1645 | u8 reserved_0[0xc0]; | |
1646 | ||
1647 | u8 reserved_1[0x8]; | |
1648 | u8 dct_number[0x18]; | |
1649 | }; | |
1650 | ||
1651 | struct mlx5_ifc_comp_event_bits { | |
1652 | u8 reserved_0[0xc0]; | |
1653 | ||
1654 | u8 reserved_1[0x8]; | |
1655 | u8 cq_number[0x18]; | |
1656 | }; | |
1657 | ||
1658 | enum { | |
1659 | MLX5_QPC_STATE_RST = 0x0, | |
1660 | MLX5_QPC_STATE_INIT = 0x1, | |
1661 | MLX5_QPC_STATE_RTR = 0x2, | |
1662 | MLX5_QPC_STATE_RTS = 0x3, | |
1663 | MLX5_QPC_STATE_SQER = 0x4, | |
1664 | MLX5_QPC_STATE_ERR = 0x6, | |
1665 | MLX5_QPC_STATE_SQD = 0x7, | |
1666 | MLX5_QPC_STATE_SUSPENDED = 0x9, | |
1667 | }; | |
1668 | ||
1669 | enum { | |
1670 | MLX5_QPC_ST_RC = 0x0, | |
1671 | MLX5_QPC_ST_UC = 0x1, | |
1672 | MLX5_QPC_ST_UD = 0x2, | |
1673 | MLX5_QPC_ST_XRC = 0x3, | |
1674 | MLX5_QPC_ST_DCI = 0x5, | |
1675 | MLX5_QPC_ST_QP0 = 0x7, | |
1676 | MLX5_QPC_ST_QP1 = 0x8, | |
1677 | MLX5_QPC_ST_RAW_DATAGRAM = 0x9, | |
1678 | MLX5_QPC_ST_REG_UMR = 0xc, | |
1679 | }; | |
1680 | ||
1681 | enum { | |
1682 | MLX5_QPC_PM_STATE_ARMED = 0x0, | |
1683 | MLX5_QPC_PM_STATE_REARM = 0x1, | |
1684 | MLX5_QPC_PM_STATE_RESERVED = 0x2, | |
1685 | MLX5_QPC_PM_STATE_MIGRATED = 0x3, | |
1686 | }; | |
1687 | ||
1688 | enum { | |
1689 | MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, | |
1690 | MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, | |
1691 | }; | |
1692 | ||
1693 | enum { | |
1694 | MLX5_QPC_MTU_256_BYTES = 0x1, | |
1695 | MLX5_QPC_MTU_512_BYTES = 0x2, | |
1696 | MLX5_QPC_MTU_1K_BYTES = 0x3, | |
1697 | MLX5_QPC_MTU_2K_BYTES = 0x4, | |
1698 | MLX5_QPC_MTU_4K_BYTES = 0x5, | |
1699 | MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, | |
1700 | }; | |
1701 | ||
1702 | enum { | |
1703 | MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, | |
1704 | MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, | |
1705 | MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, | |
1706 | MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, | |
1707 | MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, | |
1708 | MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, | |
1709 | MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, | |
1710 | MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, | |
1711 | }; | |
1712 | ||
1713 | enum { | |
1714 | MLX5_QPC_CS_REQ_DISABLE = 0x0, | |
1715 | MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, | |
1716 | MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, | |
1717 | }; | |
1718 | ||
1719 | enum { | |
1720 | MLX5_QPC_CS_RES_DISABLE = 0x0, | |
1721 | MLX5_QPC_CS_RES_UP_TO_32B = 0x1, | |
1722 | MLX5_QPC_CS_RES_UP_TO_64B = 0x2, | |
1723 | }; | |
1724 | ||
1725 | struct mlx5_ifc_qpc_bits { | |
1726 | u8 state[0x4]; | |
1727 | u8 reserved_0[0x4]; | |
1728 | u8 st[0x8]; | |
1729 | u8 reserved_1[0x3]; | |
1730 | u8 pm_state[0x2]; | |
1731 | u8 reserved_2[0x7]; | |
1732 | u8 end_padding_mode[0x2]; | |
1733 | u8 reserved_3[0x2]; | |
1734 | ||
1735 | u8 wq_signature[0x1]; | |
1736 | u8 block_lb_mc[0x1]; | |
1737 | u8 atomic_like_write_en[0x1]; | |
1738 | u8 latency_sensitive[0x1]; | |
1739 | u8 reserved_4[0x1]; | |
1740 | u8 drain_sigerr[0x1]; | |
1741 | u8 reserved_5[0x2]; | |
1742 | u8 pd[0x18]; | |
1743 | ||
1744 | u8 mtu[0x3]; | |
1745 | u8 log_msg_max[0x5]; | |
1746 | u8 reserved_6[0x1]; | |
1747 | u8 log_rq_size[0x4]; | |
1748 | u8 log_rq_stride[0x3]; | |
1749 | u8 no_sq[0x1]; | |
1750 | u8 log_sq_size[0x4]; | |
1751 | u8 reserved_7[0x6]; | |
1752 | u8 rlky[0x1]; | |
1753 | u8 reserved_8[0x4]; | |
1754 | ||
1755 | u8 counter_set_id[0x8]; | |
1756 | u8 uar_page[0x18]; | |
1757 | ||
1758 | u8 reserved_9[0x8]; | |
1759 | u8 user_index[0x18]; | |
1760 | ||
1761 | u8 reserved_10[0x3]; | |
1762 | u8 log_page_size[0x5]; | |
1763 | u8 remote_qpn[0x18]; | |
1764 | ||
1765 | struct mlx5_ifc_ads_bits primary_address_path; | |
1766 | ||
1767 | struct mlx5_ifc_ads_bits secondary_address_path; | |
1768 | ||
1769 | u8 log_ack_req_freq[0x4]; | |
1770 | u8 reserved_11[0x4]; | |
1771 | u8 log_sra_max[0x3]; | |
1772 | u8 reserved_12[0x2]; | |
1773 | u8 retry_count[0x3]; | |
1774 | u8 rnr_retry[0x3]; | |
1775 | u8 reserved_13[0x1]; | |
1776 | u8 fre[0x1]; | |
1777 | u8 cur_rnr_retry[0x3]; | |
1778 | u8 cur_retry_count[0x3]; | |
1779 | u8 reserved_14[0x5]; | |
1780 | ||
1781 | u8 reserved_15[0x20]; | |
1782 | ||
1783 | u8 reserved_16[0x8]; | |
1784 | u8 next_send_psn[0x18]; | |
1785 | ||
1786 | u8 reserved_17[0x8]; | |
1787 | u8 cqn_snd[0x18]; | |
1788 | ||
1789 | u8 reserved_18[0x40]; | |
1790 | ||
1791 | u8 reserved_19[0x8]; | |
1792 | u8 last_acked_psn[0x18]; | |
1793 | ||
1794 | u8 reserved_20[0x8]; | |
1795 | u8 ssn[0x18]; | |
1796 | ||
1797 | u8 reserved_21[0x8]; | |
1798 | u8 log_rra_max[0x3]; | |
1799 | u8 reserved_22[0x1]; | |
1800 | u8 atomic_mode[0x4]; | |
1801 | u8 rre[0x1]; | |
1802 | u8 rwe[0x1]; | |
1803 | u8 rae[0x1]; | |
1804 | u8 reserved_23[0x1]; | |
1805 | u8 page_offset[0x6]; | |
1806 | u8 reserved_24[0x3]; | |
1807 | u8 cd_slave_receive[0x1]; | |
1808 | u8 cd_slave_send[0x1]; | |
1809 | u8 cd_master[0x1]; | |
1810 | ||
1811 | u8 reserved_25[0x3]; | |
1812 | u8 min_rnr_nak[0x5]; | |
1813 | u8 next_rcv_psn[0x18]; | |
1814 | ||
1815 | u8 reserved_26[0x8]; | |
1816 | u8 xrcd[0x18]; | |
1817 | ||
1818 | u8 reserved_27[0x8]; | |
1819 | u8 cqn_rcv[0x18]; | |
1820 | ||
1821 | u8 dbr_addr[0x40]; | |
1822 | ||
1823 | u8 q_key[0x20]; | |
1824 | ||
1825 | u8 reserved_28[0x5]; | |
1826 | u8 rq_type[0x3]; | |
1827 | u8 srqn_rmpn[0x18]; | |
1828 | ||
1829 | u8 reserved_29[0x8]; | |
1830 | u8 rmsn[0x18]; | |
1831 | ||
1832 | u8 hw_sq_wqebb_counter[0x10]; | |
1833 | u8 sw_sq_wqebb_counter[0x10]; | |
1834 | ||
1835 | u8 hw_rq_counter[0x20]; | |
1836 | ||
1837 | u8 sw_rq_counter[0x20]; | |
1838 | ||
1839 | u8 reserved_30[0x20]; | |
1840 | ||
1841 | u8 reserved_31[0xf]; | |
1842 | u8 cgs[0x1]; | |
1843 | u8 cs_req[0x8]; | |
1844 | u8 cs_res[0x8]; | |
1845 | ||
1846 | u8 dc_access_key[0x40]; | |
1847 | ||
1848 | u8 reserved_32[0xc0]; | |
1849 | }; | |
1850 | ||
1851 | struct mlx5_ifc_roce_addr_layout_bits { | |
1852 | u8 source_l3_address[16][0x8]; | |
1853 | ||
1854 | u8 reserved_0[0x3]; | |
1855 | u8 vlan_valid[0x1]; | |
1856 | u8 vlan_id[0xc]; | |
1857 | u8 source_mac_47_32[0x10]; | |
1858 | ||
1859 | u8 source_mac_31_0[0x20]; | |
1860 | ||
1861 | u8 reserved_1[0x14]; | |
1862 | u8 roce_l3_type[0x4]; | |
1863 | u8 roce_version[0x8]; | |
1864 | ||
1865 | u8 reserved_2[0x20]; | |
1866 | }; | |
1867 | ||
1868 | union mlx5_ifc_hca_cap_union_bits { | |
1869 | struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; | |
1870 | struct mlx5_ifc_odp_cap_bits odp_cap; | |
1871 | struct mlx5_ifc_atomic_caps_bits atomic_caps; | |
1872 | struct mlx5_ifc_roce_cap_bits roce_cap; | |
1873 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; | |
1874 | struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; | |
495716b1 | 1875 | struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; |
d6666753 | 1876 | struct mlx5_ifc_e_switch_cap_bits e_switch_cap; |
e281682b SM |
1877 | u8 reserved_0[0x8000]; |
1878 | }; | |
1879 | ||
1880 | enum { | |
1881 | MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, | |
1882 | MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, | |
1883 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, | |
1884 | }; | |
1885 | ||
1886 | struct mlx5_ifc_flow_context_bits { | |
1887 | u8 reserved_0[0x20]; | |
1888 | ||
1889 | u8 group_id[0x20]; | |
1890 | ||
1891 | u8 reserved_1[0x8]; | |
1892 | u8 flow_tag[0x18]; | |
1893 | ||
1894 | u8 reserved_2[0x10]; | |
1895 | u8 action[0x10]; | |
1896 | ||
1897 | u8 reserved_3[0x8]; | |
1898 | u8 destination_list_size[0x18]; | |
1899 | ||
1900 | u8 reserved_4[0x160]; | |
1901 | ||
1902 | struct mlx5_ifc_fte_match_param_bits match_value; | |
1903 | ||
1904 | u8 reserved_5[0x600]; | |
1905 | ||
1906 | struct mlx5_ifc_dest_format_struct_bits destination[0]; | |
1907 | }; | |
1908 | ||
1909 | enum { | |
1910 | MLX5_XRC_SRQC_STATE_GOOD = 0x0, | |
1911 | MLX5_XRC_SRQC_STATE_ERROR = 0x1, | |
1912 | }; | |
1913 | ||
1914 | struct mlx5_ifc_xrc_srqc_bits { | |
1915 | u8 state[0x4]; | |
1916 | u8 log_xrc_srq_size[0x4]; | |
1917 | u8 reserved_0[0x18]; | |
1918 | ||
1919 | u8 wq_signature[0x1]; | |
1920 | u8 cont_srq[0x1]; | |
1921 | u8 reserved_1[0x1]; | |
1922 | u8 rlky[0x1]; | |
1923 | u8 basic_cyclic_rcv_wqe[0x1]; | |
1924 | u8 log_rq_stride[0x3]; | |
1925 | u8 xrcd[0x18]; | |
1926 | ||
1927 | u8 page_offset[0x6]; | |
1928 | u8 reserved_2[0x2]; | |
1929 | u8 cqn[0x18]; | |
1930 | ||
1931 | u8 reserved_3[0x20]; | |
1932 | ||
1933 | u8 user_index_equal_xrc_srqn[0x1]; | |
1934 | u8 reserved_4[0x1]; | |
1935 | u8 log_page_size[0x6]; | |
1936 | u8 user_index[0x18]; | |
1937 | ||
1938 | u8 reserved_5[0x20]; | |
1939 | ||
1940 | u8 reserved_6[0x8]; | |
1941 | u8 pd[0x18]; | |
1942 | ||
1943 | u8 lwm[0x10]; | |
1944 | u8 wqe_cnt[0x10]; | |
1945 | ||
1946 | u8 reserved_7[0x40]; | |
1947 | ||
1948 | u8 db_record_addr_h[0x20]; | |
1949 | ||
1950 | u8 db_record_addr_l[0x1e]; | |
1951 | u8 reserved_8[0x2]; | |
1952 | ||
1953 | u8 reserved_9[0x80]; | |
1954 | }; | |
1955 | ||
1956 | struct mlx5_ifc_traffic_counter_bits { | |
1957 | u8 packets[0x40]; | |
1958 | ||
1959 | u8 octets[0x40]; | |
1960 | }; | |
1961 | ||
1962 | struct mlx5_ifc_tisc_bits { | |
1963 | u8 reserved_0[0xc]; | |
1964 | u8 prio[0x4]; | |
1965 | u8 reserved_1[0x10]; | |
1966 | ||
1967 | u8 reserved_2[0x100]; | |
1968 | ||
1969 | u8 reserved_3[0x8]; | |
1970 | u8 transport_domain[0x18]; | |
1971 | ||
1972 | u8 reserved_4[0x3c0]; | |
1973 | }; | |
1974 | ||
1975 | enum { | |
1976 | MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, | |
1977 | MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, | |
1978 | }; | |
1979 | ||
1980 | enum { | |
1981 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, | |
1982 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, | |
1983 | }; | |
1984 | ||
1985 | enum { | |
2be6967c SM |
1986 | MLX5_RX_HASH_FN_NONE = 0x0, |
1987 | MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, | |
1988 | MLX5_RX_HASH_FN_TOEPLITZ = 0x2, | |
e281682b SM |
1989 | }; |
1990 | ||
1991 | enum { | |
1992 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, | |
1993 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, | |
1994 | }; | |
1995 | ||
1996 | struct mlx5_ifc_tirc_bits { | |
1997 | u8 reserved_0[0x20]; | |
1998 | ||
1999 | u8 disp_type[0x4]; | |
2000 | u8 reserved_1[0x1c]; | |
2001 | ||
2002 | u8 reserved_2[0x40]; | |
2003 | ||
2004 | u8 reserved_3[0x4]; | |
2005 | u8 lro_timeout_period_usecs[0x10]; | |
2006 | u8 lro_enable_mask[0x4]; | |
2007 | u8 lro_max_ip_payload_size[0x8]; | |
2008 | ||
2009 | u8 reserved_4[0x40]; | |
2010 | ||
2011 | u8 reserved_5[0x8]; | |
2012 | u8 inline_rqn[0x18]; | |
2013 | ||
2014 | u8 rx_hash_symmetric[0x1]; | |
2015 | u8 reserved_6[0x1]; | |
2016 | u8 tunneled_offload_en[0x1]; | |
2017 | u8 reserved_7[0x5]; | |
2018 | u8 indirect_table[0x18]; | |
2019 | ||
2020 | u8 rx_hash_fn[0x4]; | |
2021 | u8 reserved_8[0x2]; | |
2022 | u8 self_lb_block[0x2]; | |
2023 | u8 transport_domain[0x18]; | |
2024 | ||
2025 | u8 rx_hash_toeplitz_key[10][0x20]; | |
2026 | ||
2027 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; | |
2028 | ||
2029 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; | |
2030 | ||
2031 | u8 reserved_9[0x4c0]; | |
2032 | }; | |
2033 | ||
2034 | enum { | |
2035 | MLX5_SRQC_STATE_GOOD = 0x0, | |
2036 | MLX5_SRQC_STATE_ERROR = 0x1, | |
2037 | }; | |
2038 | ||
2039 | struct mlx5_ifc_srqc_bits { | |
2040 | u8 state[0x4]; | |
2041 | u8 log_srq_size[0x4]; | |
2042 | u8 reserved_0[0x18]; | |
2043 | ||
2044 | u8 wq_signature[0x1]; | |
2045 | u8 cont_srq[0x1]; | |
2046 | u8 reserved_1[0x1]; | |
2047 | u8 rlky[0x1]; | |
2048 | u8 reserved_2[0x1]; | |
2049 | u8 log_rq_stride[0x3]; | |
2050 | u8 xrcd[0x18]; | |
2051 | ||
2052 | u8 page_offset[0x6]; | |
2053 | u8 reserved_3[0x2]; | |
2054 | u8 cqn[0x18]; | |
2055 | ||
2056 | u8 reserved_4[0x20]; | |
2057 | ||
2058 | u8 reserved_5[0x2]; | |
2059 | u8 log_page_size[0x6]; | |
2060 | u8 reserved_6[0x18]; | |
2061 | ||
2062 | u8 reserved_7[0x20]; | |
2063 | ||
2064 | u8 reserved_8[0x8]; | |
2065 | u8 pd[0x18]; | |
2066 | ||
2067 | u8 lwm[0x10]; | |
2068 | u8 wqe_cnt[0x10]; | |
2069 | ||
2070 | u8 reserved_9[0x40]; | |
2071 | ||
01949d01 | 2072 | u8 dbr_addr[0x40]; |
e281682b | 2073 | |
01949d01 | 2074 | u8 reserved_10[0x80]; |
e281682b SM |
2075 | }; |
2076 | ||
2077 | enum { | |
2078 | MLX5_SQC_STATE_RST = 0x0, | |
2079 | MLX5_SQC_STATE_RDY = 0x1, | |
2080 | MLX5_SQC_STATE_ERR = 0x3, | |
2081 | }; | |
2082 | ||
2083 | struct mlx5_ifc_sqc_bits { | |
2084 | u8 rlky[0x1]; | |
2085 | u8 cd_master[0x1]; | |
2086 | u8 fre[0x1]; | |
2087 | u8 flush_in_error_en[0x1]; | |
2088 | u8 reserved_0[0x4]; | |
2089 | u8 state[0x4]; | |
2090 | u8 reserved_1[0x14]; | |
2091 | ||
2092 | u8 reserved_2[0x8]; | |
2093 | u8 user_index[0x18]; | |
2094 | ||
2095 | u8 reserved_3[0x8]; | |
2096 | u8 cqn[0x18]; | |
2097 | ||
2098 | u8 reserved_4[0xa0]; | |
2099 | ||
2100 | u8 tis_lst_sz[0x10]; | |
2101 | u8 reserved_5[0x10]; | |
2102 | ||
2103 | u8 reserved_6[0x40]; | |
2104 | ||
2105 | u8 reserved_7[0x8]; | |
2106 | u8 tis_num_0[0x18]; | |
2107 | ||
2108 | struct mlx5_ifc_wq_bits wq; | |
2109 | }; | |
2110 | ||
2111 | struct mlx5_ifc_rqtc_bits { | |
2112 | u8 reserved_0[0xa0]; | |
2113 | ||
2114 | u8 reserved_1[0x10]; | |
2115 | u8 rqt_max_size[0x10]; | |
2116 | ||
2117 | u8 reserved_2[0x10]; | |
2118 | u8 rqt_actual_size[0x10]; | |
2119 | ||
2120 | u8 reserved_3[0x6a0]; | |
2121 | ||
2122 | struct mlx5_ifc_rq_num_bits rq_num[0]; | |
2123 | }; | |
2124 | ||
2125 | enum { | |
2126 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
2127 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, | |
2128 | }; | |
2129 | ||
2130 | enum { | |
2131 | MLX5_RQC_STATE_RST = 0x0, | |
2132 | MLX5_RQC_STATE_RDY = 0x1, | |
2133 | MLX5_RQC_STATE_ERR = 0x3, | |
2134 | }; | |
2135 | ||
2136 | struct mlx5_ifc_rqc_bits { | |
2137 | u8 rlky[0x1]; | |
2138 | u8 reserved_0[0x2]; | |
2139 | u8 vsd[0x1]; | |
2140 | u8 mem_rq_type[0x4]; | |
2141 | u8 state[0x4]; | |
2142 | u8 reserved_1[0x1]; | |
2143 | u8 flush_in_error_en[0x1]; | |
2144 | u8 reserved_2[0x12]; | |
2145 | ||
2146 | u8 reserved_3[0x8]; | |
2147 | u8 user_index[0x18]; | |
2148 | ||
2149 | u8 reserved_4[0x8]; | |
2150 | u8 cqn[0x18]; | |
2151 | ||
2152 | u8 counter_set_id[0x8]; | |
2153 | u8 reserved_5[0x18]; | |
2154 | ||
2155 | u8 reserved_6[0x8]; | |
2156 | u8 rmpn[0x18]; | |
2157 | ||
2158 | u8 reserved_7[0xe0]; | |
2159 | ||
2160 | struct mlx5_ifc_wq_bits wq; | |
2161 | }; | |
2162 | ||
2163 | enum { | |
2164 | MLX5_RMPC_STATE_RDY = 0x1, | |
2165 | MLX5_RMPC_STATE_ERR = 0x3, | |
2166 | }; | |
2167 | ||
2168 | struct mlx5_ifc_rmpc_bits { | |
2169 | u8 reserved_0[0x8]; | |
2170 | u8 state[0x4]; | |
2171 | u8 reserved_1[0x14]; | |
2172 | ||
2173 | u8 basic_cyclic_rcv_wqe[0x1]; | |
2174 | u8 reserved_2[0x1f]; | |
2175 | ||
2176 | u8 reserved_3[0x140]; | |
2177 | ||
2178 | struct mlx5_ifc_wq_bits wq; | |
2179 | }; | |
2180 | ||
e281682b SM |
2181 | struct mlx5_ifc_nic_vport_context_bits { |
2182 | u8 reserved_0[0x1f]; | |
2183 | u8 roce_en[0x1]; | |
2184 | ||
d82b7318 SM |
2185 | u8 arm_change_event[0x1]; |
2186 | u8 reserved_1[0x1a]; | |
2187 | u8 event_on_mtu[0x1]; | |
2188 | u8 event_on_promisc_change[0x1]; | |
2189 | u8 event_on_vlan_change[0x1]; | |
2190 | u8 event_on_mc_address_change[0x1]; | |
2191 | u8 event_on_uc_address_change[0x1]; | |
e281682b | 2192 | |
d82b7318 SM |
2193 | u8 reserved_2[0xf0]; |
2194 | ||
2195 | u8 mtu[0x10]; | |
2196 | ||
2197 | u8 reserved_3[0x640]; | |
2198 | ||
2199 | u8 promisc_uc[0x1]; | |
2200 | u8 promisc_mc[0x1]; | |
2201 | u8 promisc_all[0x1]; | |
2202 | u8 reserved_4[0x2]; | |
e281682b | 2203 | u8 allowed_list_type[0x3]; |
d82b7318 | 2204 | u8 reserved_5[0xc]; |
e281682b SM |
2205 | u8 allowed_list_size[0xc]; |
2206 | ||
2207 | struct mlx5_ifc_mac_address_layout_bits permanent_address; | |
2208 | ||
d82b7318 | 2209 | u8 reserved_6[0x20]; |
e281682b SM |
2210 | |
2211 | u8 current_uc_mac_address[0][0x40]; | |
2212 | }; | |
2213 | ||
2214 | enum { | |
2215 | MLX5_MKC_ACCESS_MODE_PA = 0x0, | |
2216 | MLX5_MKC_ACCESS_MODE_MTT = 0x1, | |
2217 | MLX5_MKC_ACCESS_MODE_KLMS = 0x2, | |
2218 | }; | |
2219 | ||
2220 | struct mlx5_ifc_mkc_bits { | |
2221 | u8 reserved_0[0x1]; | |
2222 | u8 free[0x1]; | |
2223 | u8 reserved_1[0xd]; | |
2224 | u8 small_fence_on_rdma_read_response[0x1]; | |
2225 | u8 umr_en[0x1]; | |
2226 | u8 a[0x1]; | |
2227 | u8 rw[0x1]; | |
2228 | u8 rr[0x1]; | |
2229 | u8 lw[0x1]; | |
2230 | u8 lr[0x1]; | |
2231 | u8 access_mode[0x2]; | |
2232 | u8 reserved_2[0x8]; | |
2233 | ||
2234 | u8 qpn[0x18]; | |
2235 | u8 mkey_7_0[0x8]; | |
2236 | ||
2237 | u8 reserved_3[0x20]; | |
2238 | ||
2239 | u8 length64[0x1]; | |
2240 | u8 bsf_en[0x1]; | |
2241 | u8 sync_umr[0x1]; | |
2242 | u8 reserved_4[0x2]; | |
2243 | u8 expected_sigerr_count[0x1]; | |
2244 | u8 reserved_5[0x1]; | |
2245 | u8 en_rinval[0x1]; | |
2246 | u8 pd[0x18]; | |
2247 | ||
2248 | u8 start_addr[0x40]; | |
2249 | ||
2250 | u8 len[0x40]; | |
2251 | ||
2252 | u8 bsf_octword_size[0x20]; | |
2253 | ||
2254 | u8 reserved_6[0x80]; | |
2255 | ||
2256 | u8 translations_octword_size[0x20]; | |
2257 | ||
2258 | u8 reserved_7[0x1b]; | |
2259 | u8 log_page_size[0x5]; | |
2260 | ||
2261 | u8 reserved_8[0x20]; | |
2262 | }; | |
2263 | ||
2264 | struct mlx5_ifc_pkey_bits { | |
2265 | u8 reserved_0[0x10]; | |
2266 | u8 pkey[0x10]; | |
2267 | }; | |
2268 | ||
2269 | struct mlx5_ifc_array128_auto_bits { | |
2270 | u8 array128_auto[16][0x8]; | |
2271 | }; | |
2272 | ||
2273 | struct mlx5_ifc_hca_vport_context_bits { | |
2274 | u8 field_select[0x20]; | |
2275 | ||
2276 | u8 reserved_0[0xe0]; | |
2277 | ||
2278 | u8 sm_virt_aware[0x1]; | |
2279 | u8 has_smi[0x1]; | |
2280 | u8 has_raw[0x1]; | |
2281 | u8 grh_required[0x1]; | |
707c4602 MD |
2282 | u8 reserved_1[0xc]; |
2283 | u8 port_physical_state[0x4]; | |
2284 | u8 vport_state_policy[0x4]; | |
2285 | u8 port_state[0x4]; | |
e281682b SM |
2286 | u8 vport_state[0x4]; |
2287 | ||
707c4602 MD |
2288 | u8 reserved_2[0x20]; |
2289 | ||
2290 | u8 system_image_guid[0x40]; | |
e281682b SM |
2291 | |
2292 | u8 port_guid[0x40]; | |
2293 | ||
2294 | u8 node_guid[0x40]; | |
2295 | ||
2296 | u8 cap_mask1[0x20]; | |
2297 | ||
2298 | u8 cap_mask1_field_select[0x20]; | |
2299 | ||
2300 | u8 cap_mask2[0x20]; | |
2301 | ||
2302 | u8 cap_mask2_field_select[0x20]; | |
2303 | ||
2304 | u8 reserved_3[0x80]; | |
2305 | ||
2306 | u8 lid[0x10]; | |
2307 | u8 reserved_4[0x4]; | |
2308 | u8 init_type_reply[0x4]; | |
2309 | u8 lmc[0x3]; | |
2310 | u8 subnet_timeout[0x5]; | |
2311 | ||
2312 | u8 sm_lid[0x10]; | |
2313 | u8 sm_sl[0x4]; | |
2314 | u8 reserved_5[0xc]; | |
2315 | ||
2316 | u8 qkey_violation_counter[0x10]; | |
2317 | u8 pkey_violation_counter[0x10]; | |
2318 | ||
2319 | u8 reserved_6[0xca0]; | |
2320 | }; | |
2321 | ||
d6666753 SM |
2322 | struct mlx5_ifc_esw_vport_context_bits { |
2323 | u8 reserved_0[0x3]; | |
2324 | u8 vport_svlan_strip[0x1]; | |
2325 | u8 vport_cvlan_strip[0x1]; | |
2326 | u8 vport_svlan_insert[0x1]; | |
2327 | u8 vport_cvlan_insert[0x2]; | |
2328 | u8 reserved_1[0x18]; | |
2329 | ||
2330 | u8 reserved_2[0x20]; | |
2331 | ||
2332 | u8 svlan_cfi[0x1]; | |
2333 | u8 svlan_pcp[0x3]; | |
2334 | u8 svlan_id[0xc]; | |
2335 | u8 cvlan_cfi[0x1]; | |
2336 | u8 cvlan_pcp[0x3]; | |
2337 | u8 cvlan_id[0xc]; | |
2338 | ||
2339 | u8 reserved_3[0x7a0]; | |
2340 | }; | |
2341 | ||
e281682b SM |
2342 | enum { |
2343 | MLX5_EQC_STATUS_OK = 0x0, | |
2344 | MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, | |
2345 | }; | |
2346 | ||
2347 | enum { | |
2348 | MLX5_EQC_ST_ARMED = 0x9, | |
2349 | MLX5_EQC_ST_FIRED = 0xa, | |
2350 | }; | |
2351 | ||
2352 | struct mlx5_ifc_eqc_bits { | |
2353 | u8 status[0x4]; | |
2354 | u8 reserved_0[0x9]; | |
2355 | u8 ec[0x1]; | |
2356 | u8 oi[0x1]; | |
2357 | u8 reserved_1[0x5]; | |
2358 | u8 st[0x4]; | |
2359 | u8 reserved_2[0x8]; | |
2360 | ||
2361 | u8 reserved_3[0x20]; | |
2362 | ||
2363 | u8 reserved_4[0x14]; | |
2364 | u8 page_offset[0x6]; | |
2365 | u8 reserved_5[0x6]; | |
2366 | ||
2367 | u8 reserved_6[0x3]; | |
2368 | u8 log_eq_size[0x5]; | |
2369 | u8 uar_page[0x18]; | |
2370 | ||
2371 | u8 reserved_7[0x20]; | |
2372 | ||
2373 | u8 reserved_8[0x18]; | |
2374 | u8 intr[0x8]; | |
2375 | ||
2376 | u8 reserved_9[0x3]; | |
2377 | u8 log_page_size[0x5]; | |
2378 | u8 reserved_10[0x18]; | |
2379 | ||
2380 | u8 reserved_11[0x60]; | |
2381 | ||
2382 | u8 reserved_12[0x8]; | |
2383 | u8 consumer_counter[0x18]; | |
2384 | ||
2385 | u8 reserved_13[0x8]; | |
2386 | u8 producer_counter[0x18]; | |
2387 | ||
2388 | u8 reserved_14[0x80]; | |
2389 | }; | |
2390 | ||
2391 | enum { | |
2392 | MLX5_DCTC_STATE_ACTIVE = 0x0, | |
2393 | MLX5_DCTC_STATE_DRAINING = 0x1, | |
2394 | MLX5_DCTC_STATE_DRAINED = 0x2, | |
2395 | }; | |
2396 | ||
2397 | enum { | |
2398 | MLX5_DCTC_CS_RES_DISABLE = 0x0, | |
2399 | MLX5_DCTC_CS_RES_NA = 0x1, | |
2400 | MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, | |
2401 | }; | |
2402 | ||
2403 | enum { | |
2404 | MLX5_DCTC_MTU_256_BYTES = 0x1, | |
2405 | MLX5_DCTC_MTU_512_BYTES = 0x2, | |
2406 | MLX5_DCTC_MTU_1K_BYTES = 0x3, | |
2407 | MLX5_DCTC_MTU_2K_BYTES = 0x4, | |
2408 | MLX5_DCTC_MTU_4K_BYTES = 0x5, | |
2409 | }; | |
2410 | ||
2411 | struct mlx5_ifc_dctc_bits { | |
2412 | u8 reserved_0[0x4]; | |
2413 | u8 state[0x4]; | |
2414 | u8 reserved_1[0x18]; | |
2415 | ||
2416 | u8 reserved_2[0x8]; | |
2417 | u8 user_index[0x18]; | |
2418 | ||
2419 | u8 reserved_3[0x8]; | |
2420 | u8 cqn[0x18]; | |
2421 | ||
2422 | u8 counter_set_id[0x8]; | |
2423 | u8 atomic_mode[0x4]; | |
2424 | u8 rre[0x1]; | |
2425 | u8 rwe[0x1]; | |
2426 | u8 rae[0x1]; | |
2427 | u8 atomic_like_write_en[0x1]; | |
2428 | u8 latency_sensitive[0x1]; | |
2429 | u8 rlky[0x1]; | |
2430 | u8 free_ar[0x1]; | |
2431 | u8 reserved_4[0xd]; | |
2432 | ||
2433 | u8 reserved_5[0x8]; | |
2434 | u8 cs_res[0x8]; | |
2435 | u8 reserved_6[0x3]; | |
2436 | u8 min_rnr_nak[0x5]; | |
2437 | u8 reserved_7[0x8]; | |
2438 | ||
2439 | u8 reserved_8[0x8]; | |
2440 | u8 srqn[0x18]; | |
2441 | ||
2442 | u8 reserved_9[0x8]; | |
2443 | u8 pd[0x18]; | |
2444 | ||
2445 | u8 tclass[0x8]; | |
2446 | u8 reserved_10[0x4]; | |
2447 | u8 flow_label[0x14]; | |
2448 | ||
2449 | u8 dc_access_key[0x40]; | |
2450 | ||
2451 | u8 reserved_11[0x5]; | |
2452 | u8 mtu[0x3]; | |
2453 | u8 port[0x8]; | |
2454 | u8 pkey_index[0x10]; | |
2455 | ||
2456 | u8 reserved_12[0x8]; | |
2457 | u8 my_addr_index[0x8]; | |
2458 | u8 reserved_13[0x8]; | |
2459 | u8 hop_limit[0x8]; | |
2460 | ||
2461 | u8 dc_access_key_violation_count[0x20]; | |
2462 | ||
2463 | u8 reserved_14[0x14]; | |
2464 | u8 dei_cfi[0x1]; | |
2465 | u8 eth_prio[0x3]; | |
2466 | u8 ecn[0x2]; | |
2467 | u8 dscp[0x6]; | |
2468 | ||
2469 | u8 reserved_15[0x40]; | |
2470 | }; | |
2471 | ||
2472 | enum { | |
2473 | MLX5_CQC_STATUS_OK = 0x0, | |
2474 | MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, | |
2475 | MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, | |
2476 | }; | |
2477 | ||
2478 | enum { | |
2479 | MLX5_CQC_CQE_SZ_64_BYTES = 0x0, | |
2480 | MLX5_CQC_CQE_SZ_128_BYTES = 0x1, | |
2481 | }; | |
2482 | ||
2483 | enum { | |
2484 | MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, | |
2485 | MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, | |
2486 | MLX5_CQC_ST_FIRED = 0xa, | |
2487 | }; | |
2488 | ||
2489 | struct mlx5_ifc_cqc_bits { | |
2490 | u8 status[0x4]; | |
2491 | u8 reserved_0[0x4]; | |
2492 | u8 cqe_sz[0x3]; | |
2493 | u8 cc[0x1]; | |
2494 | u8 reserved_1[0x1]; | |
2495 | u8 scqe_break_moderation_en[0x1]; | |
2496 | u8 oi[0x1]; | |
2497 | u8 reserved_2[0x2]; | |
2498 | u8 cqe_zip_en[0x1]; | |
2499 | u8 mini_cqe_res_format[0x2]; | |
2500 | u8 st[0x4]; | |
2501 | u8 reserved_3[0x8]; | |
2502 | ||
2503 | u8 reserved_4[0x20]; | |
2504 | ||
2505 | u8 reserved_5[0x14]; | |
2506 | u8 page_offset[0x6]; | |
2507 | u8 reserved_6[0x6]; | |
2508 | ||
2509 | u8 reserved_7[0x3]; | |
2510 | u8 log_cq_size[0x5]; | |
2511 | u8 uar_page[0x18]; | |
2512 | ||
2513 | u8 reserved_8[0x4]; | |
2514 | u8 cq_period[0xc]; | |
2515 | u8 cq_max_count[0x10]; | |
2516 | ||
2517 | u8 reserved_9[0x18]; | |
2518 | u8 c_eqn[0x8]; | |
2519 | ||
2520 | u8 reserved_10[0x3]; | |
2521 | u8 log_page_size[0x5]; | |
2522 | u8 reserved_11[0x18]; | |
2523 | ||
2524 | u8 reserved_12[0x20]; | |
2525 | ||
2526 | u8 reserved_13[0x8]; | |
2527 | u8 last_notified_index[0x18]; | |
2528 | ||
2529 | u8 reserved_14[0x8]; | |
2530 | u8 last_solicit_index[0x18]; | |
2531 | ||
2532 | u8 reserved_15[0x8]; | |
2533 | u8 consumer_counter[0x18]; | |
2534 | ||
2535 | u8 reserved_16[0x8]; | |
2536 | u8 producer_counter[0x18]; | |
2537 | ||
2538 | u8 reserved_17[0x40]; | |
2539 | ||
2540 | u8 dbr_addr[0x40]; | |
2541 | }; | |
2542 | ||
2543 | union mlx5_ifc_cong_control_roce_ecn_auto_bits { | |
2544 | struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; | |
2545 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; | |
2546 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; | |
2547 | u8 reserved_0[0x800]; | |
2548 | }; | |
2549 | ||
2550 | struct mlx5_ifc_query_adapter_param_block_bits { | |
211e6c80 | 2551 | u8 reserved_0[0xc0]; |
e281682b | 2552 | |
211e6c80 MD |
2553 | u8 reserved_1[0x8]; |
2554 | u8 ieee_vendor_id[0x18]; | |
2555 | ||
2556 | u8 reserved_2[0x10]; | |
e281682b SM |
2557 | u8 vsd_vendor_id[0x10]; |
2558 | ||
2559 | u8 vsd[208][0x8]; | |
2560 | ||
2561 | u8 vsd_contd_psid[16][0x8]; | |
2562 | }; | |
2563 | ||
2564 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { | |
2565 | struct mlx5_ifc_modify_field_select_bits modify_field_select; | |
2566 | struct mlx5_ifc_resize_field_select_bits resize_field_select; | |
2567 | u8 reserved_0[0x20]; | |
2568 | }; | |
2569 | ||
2570 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits { | |
2571 | struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; | |
2572 | struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; | |
2573 | struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; | |
2574 | u8 reserved_0[0x20]; | |
2575 | }; | |
2576 | ||
2577 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { | |
2578 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
2579 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
2580 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
2581 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
2582 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
2583 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
2584 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
2585 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; | |
2586 | u8 reserved_0[0x7c0]; | |
2587 | }; | |
2588 | ||
2589 | union mlx5_ifc_event_auto_bits { | |
2590 | struct mlx5_ifc_comp_event_bits comp_event; | |
2591 | struct mlx5_ifc_dct_events_bits dct_events; | |
2592 | struct mlx5_ifc_qp_events_bits qp_events; | |
2593 | struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; | |
2594 | struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; | |
2595 | struct mlx5_ifc_cq_error_bits cq_error; | |
2596 | struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; | |
2597 | struct mlx5_ifc_port_state_change_event_bits port_state_change_event; | |
2598 | struct mlx5_ifc_gpio_event_bits gpio_event; | |
2599 | struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; | |
2600 | struct mlx5_ifc_stall_vl_event_bits stall_vl_event; | |
2601 | struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; | |
2602 | u8 reserved_0[0xe0]; | |
2603 | }; | |
2604 | ||
2605 | struct mlx5_ifc_health_buffer_bits { | |
2606 | u8 reserved_0[0x100]; | |
2607 | ||
2608 | u8 assert_existptr[0x20]; | |
2609 | ||
2610 | u8 assert_callra[0x20]; | |
2611 | ||
2612 | u8 reserved_1[0x40]; | |
2613 | ||
2614 | u8 fw_version[0x20]; | |
2615 | ||
2616 | u8 hw_id[0x20]; | |
2617 | ||
2618 | u8 reserved_2[0x20]; | |
2619 | ||
2620 | u8 irisc_index[0x8]; | |
2621 | u8 synd[0x8]; | |
2622 | u8 ext_synd[0x10]; | |
2623 | }; | |
2624 | ||
2625 | struct mlx5_ifc_register_loopback_control_bits { | |
2626 | u8 no_lb[0x1]; | |
2627 | u8 reserved_0[0x7]; | |
2628 | u8 port[0x8]; | |
2629 | u8 reserved_1[0x10]; | |
2630 | ||
2631 | u8 reserved_2[0x60]; | |
2632 | }; | |
2633 | ||
2634 | struct mlx5_ifc_teardown_hca_out_bits { | |
2635 | u8 status[0x8]; | |
2636 | u8 reserved_0[0x18]; | |
2637 | ||
2638 | u8 syndrome[0x20]; | |
2639 | ||
2640 | u8 reserved_1[0x40]; | |
2641 | }; | |
2642 | ||
2643 | enum { | |
2644 | MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, | |
2645 | MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, | |
2646 | }; | |
2647 | ||
2648 | struct mlx5_ifc_teardown_hca_in_bits { | |
2649 | u8 opcode[0x10]; | |
2650 | u8 reserved_0[0x10]; | |
2651 | ||
2652 | u8 reserved_1[0x10]; | |
2653 | u8 op_mod[0x10]; | |
2654 | ||
2655 | u8 reserved_2[0x10]; | |
2656 | u8 profile[0x10]; | |
2657 | ||
2658 | u8 reserved_3[0x20]; | |
2659 | }; | |
2660 | ||
2661 | struct mlx5_ifc_sqerr2rts_qp_out_bits { | |
2662 | u8 status[0x8]; | |
2663 | u8 reserved_0[0x18]; | |
2664 | ||
2665 | u8 syndrome[0x20]; | |
2666 | ||
2667 | u8 reserved_1[0x40]; | |
2668 | }; | |
2669 | ||
2670 | struct mlx5_ifc_sqerr2rts_qp_in_bits { | |
2671 | u8 opcode[0x10]; | |
2672 | u8 reserved_0[0x10]; | |
2673 | ||
2674 | u8 reserved_1[0x10]; | |
2675 | u8 op_mod[0x10]; | |
2676 | ||
2677 | u8 reserved_2[0x8]; | |
2678 | u8 qpn[0x18]; | |
2679 | ||
2680 | u8 reserved_3[0x20]; | |
2681 | ||
2682 | u8 opt_param_mask[0x20]; | |
2683 | ||
2684 | u8 reserved_4[0x20]; | |
2685 | ||
2686 | struct mlx5_ifc_qpc_bits qpc; | |
2687 | ||
2688 | u8 reserved_5[0x80]; | |
2689 | }; | |
2690 | ||
2691 | struct mlx5_ifc_sqd2rts_qp_out_bits { | |
2692 | u8 status[0x8]; | |
2693 | u8 reserved_0[0x18]; | |
2694 | ||
2695 | u8 syndrome[0x20]; | |
2696 | ||
2697 | u8 reserved_1[0x40]; | |
2698 | }; | |
2699 | ||
2700 | struct mlx5_ifc_sqd2rts_qp_in_bits { | |
2701 | u8 opcode[0x10]; | |
2702 | u8 reserved_0[0x10]; | |
2703 | ||
2704 | u8 reserved_1[0x10]; | |
2705 | u8 op_mod[0x10]; | |
2706 | ||
2707 | u8 reserved_2[0x8]; | |
2708 | u8 qpn[0x18]; | |
2709 | ||
2710 | u8 reserved_3[0x20]; | |
2711 | ||
2712 | u8 opt_param_mask[0x20]; | |
2713 | ||
2714 | u8 reserved_4[0x20]; | |
2715 | ||
2716 | struct mlx5_ifc_qpc_bits qpc; | |
2717 | ||
2718 | u8 reserved_5[0x80]; | |
2719 | }; | |
2720 | ||
2721 | struct mlx5_ifc_set_roce_address_out_bits { | |
2722 | u8 status[0x8]; | |
2723 | u8 reserved_0[0x18]; | |
2724 | ||
2725 | u8 syndrome[0x20]; | |
2726 | ||
2727 | u8 reserved_1[0x40]; | |
2728 | }; | |
2729 | ||
2730 | struct mlx5_ifc_set_roce_address_in_bits { | |
2731 | u8 opcode[0x10]; | |
2732 | u8 reserved_0[0x10]; | |
2733 | ||
2734 | u8 reserved_1[0x10]; | |
2735 | u8 op_mod[0x10]; | |
2736 | ||
2737 | u8 roce_address_index[0x10]; | |
2738 | u8 reserved_2[0x10]; | |
2739 | ||
2740 | u8 reserved_3[0x20]; | |
2741 | ||
2742 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
2743 | }; | |
2744 | ||
2745 | struct mlx5_ifc_set_mad_demux_out_bits { | |
2746 | u8 status[0x8]; | |
2747 | u8 reserved_0[0x18]; | |
2748 | ||
2749 | u8 syndrome[0x20]; | |
2750 | ||
2751 | u8 reserved_1[0x40]; | |
2752 | }; | |
2753 | ||
2754 | enum { | |
2755 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, | |
2756 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, | |
2757 | }; | |
2758 | ||
2759 | struct mlx5_ifc_set_mad_demux_in_bits { | |
2760 | u8 opcode[0x10]; | |
2761 | u8 reserved_0[0x10]; | |
2762 | ||
2763 | u8 reserved_1[0x10]; | |
2764 | u8 op_mod[0x10]; | |
2765 | ||
2766 | u8 reserved_2[0x20]; | |
2767 | ||
2768 | u8 reserved_3[0x6]; | |
2769 | u8 demux_mode[0x2]; | |
2770 | u8 reserved_4[0x18]; | |
2771 | }; | |
2772 | ||
2773 | struct mlx5_ifc_set_l2_table_entry_out_bits { | |
2774 | u8 status[0x8]; | |
2775 | u8 reserved_0[0x18]; | |
2776 | ||
2777 | u8 syndrome[0x20]; | |
2778 | ||
2779 | u8 reserved_1[0x40]; | |
2780 | }; | |
2781 | ||
2782 | struct mlx5_ifc_set_l2_table_entry_in_bits { | |
2783 | u8 opcode[0x10]; | |
2784 | u8 reserved_0[0x10]; | |
2785 | ||
2786 | u8 reserved_1[0x10]; | |
2787 | u8 op_mod[0x10]; | |
2788 | ||
2789 | u8 reserved_2[0x60]; | |
2790 | ||
2791 | u8 reserved_3[0x8]; | |
2792 | u8 table_index[0x18]; | |
2793 | ||
2794 | u8 reserved_4[0x20]; | |
2795 | ||
2796 | u8 reserved_5[0x13]; | |
2797 | u8 vlan_valid[0x1]; | |
2798 | u8 vlan[0xc]; | |
2799 | ||
2800 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
2801 | ||
2802 | u8 reserved_6[0xc0]; | |
2803 | }; | |
2804 | ||
2805 | struct mlx5_ifc_set_issi_out_bits { | |
2806 | u8 status[0x8]; | |
2807 | u8 reserved_0[0x18]; | |
2808 | ||
2809 | u8 syndrome[0x20]; | |
2810 | ||
2811 | u8 reserved_1[0x40]; | |
2812 | }; | |
2813 | ||
2814 | struct mlx5_ifc_set_issi_in_bits { | |
2815 | u8 opcode[0x10]; | |
2816 | u8 reserved_0[0x10]; | |
2817 | ||
2818 | u8 reserved_1[0x10]; | |
2819 | u8 op_mod[0x10]; | |
2820 | ||
2821 | u8 reserved_2[0x10]; | |
2822 | u8 current_issi[0x10]; | |
2823 | ||
2824 | u8 reserved_3[0x20]; | |
2825 | }; | |
2826 | ||
2827 | struct mlx5_ifc_set_hca_cap_out_bits { | |
2828 | u8 status[0x8]; | |
2829 | u8 reserved_0[0x18]; | |
2830 | ||
2831 | u8 syndrome[0x20]; | |
2832 | ||
2833 | u8 reserved_1[0x40]; | |
2834 | }; | |
2835 | ||
2836 | struct mlx5_ifc_set_hca_cap_in_bits { | |
2837 | u8 opcode[0x10]; | |
2838 | u8 reserved_0[0x10]; | |
2839 | ||
2840 | u8 reserved_1[0x10]; | |
2841 | u8 op_mod[0x10]; | |
2842 | ||
2843 | u8 reserved_2[0x40]; | |
2844 | ||
2845 | union mlx5_ifc_hca_cap_union_bits capability; | |
2846 | }; | |
2847 | ||
26a81453 MG |
2848 | enum { |
2849 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, | |
2850 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, | |
2851 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, | |
2852 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 | |
2853 | }; | |
2854 | ||
e281682b SM |
2855 | struct mlx5_ifc_set_fte_out_bits { |
2856 | u8 status[0x8]; | |
2857 | u8 reserved_0[0x18]; | |
2858 | ||
2859 | u8 syndrome[0x20]; | |
2860 | ||
2861 | u8 reserved_1[0x40]; | |
2862 | }; | |
2863 | ||
2864 | struct mlx5_ifc_set_fte_in_bits { | |
2865 | u8 opcode[0x10]; | |
2866 | u8 reserved_0[0x10]; | |
2867 | ||
2868 | u8 reserved_1[0x10]; | |
2869 | u8 op_mod[0x10]; | |
2870 | ||
2871 | u8 reserved_2[0x40]; | |
2872 | ||
2873 | u8 table_type[0x8]; | |
2874 | u8 reserved_3[0x18]; | |
2875 | ||
2876 | u8 reserved_4[0x8]; | |
2877 | u8 table_id[0x18]; | |
2878 | ||
26a81453 MG |
2879 | u8 reserved_5[0x18]; |
2880 | u8 modify_enable_mask[0x8]; | |
2881 | ||
2882 | u8 reserved_6[0x20]; | |
e281682b SM |
2883 | |
2884 | u8 flow_index[0x20]; | |
2885 | ||
26a81453 | 2886 | u8 reserved_7[0xe0]; |
e281682b SM |
2887 | |
2888 | struct mlx5_ifc_flow_context_bits flow_context; | |
2889 | }; | |
2890 | ||
2891 | struct mlx5_ifc_rts2rts_qp_out_bits { | |
2892 | u8 status[0x8]; | |
2893 | u8 reserved_0[0x18]; | |
2894 | ||
2895 | u8 syndrome[0x20]; | |
2896 | ||
2897 | u8 reserved_1[0x40]; | |
2898 | }; | |
2899 | ||
2900 | struct mlx5_ifc_rts2rts_qp_in_bits { | |
2901 | u8 opcode[0x10]; | |
2902 | u8 reserved_0[0x10]; | |
2903 | ||
2904 | u8 reserved_1[0x10]; | |
2905 | u8 op_mod[0x10]; | |
2906 | ||
2907 | u8 reserved_2[0x8]; | |
2908 | u8 qpn[0x18]; | |
2909 | ||
2910 | u8 reserved_3[0x20]; | |
2911 | ||
2912 | u8 opt_param_mask[0x20]; | |
2913 | ||
2914 | u8 reserved_4[0x20]; | |
2915 | ||
2916 | struct mlx5_ifc_qpc_bits qpc; | |
2917 | ||
2918 | u8 reserved_5[0x80]; | |
2919 | }; | |
2920 | ||
2921 | struct mlx5_ifc_rtr2rts_qp_out_bits { | |
2922 | u8 status[0x8]; | |
2923 | u8 reserved_0[0x18]; | |
2924 | ||
2925 | u8 syndrome[0x20]; | |
2926 | ||
2927 | u8 reserved_1[0x40]; | |
2928 | }; | |
2929 | ||
2930 | struct mlx5_ifc_rtr2rts_qp_in_bits { | |
2931 | u8 opcode[0x10]; | |
2932 | u8 reserved_0[0x10]; | |
2933 | ||
2934 | u8 reserved_1[0x10]; | |
2935 | u8 op_mod[0x10]; | |
2936 | ||
2937 | u8 reserved_2[0x8]; | |
2938 | u8 qpn[0x18]; | |
2939 | ||
2940 | u8 reserved_3[0x20]; | |
2941 | ||
2942 | u8 opt_param_mask[0x20]; | |
2943 | ||
2944 | u8 reserved_4[0x20]; | |
2945 | ||
2946 | struct mlx5_ifc_qpc_bits qpc; | |
2947 | ||
2948 | u8 reserved_5[0x80]; | |
2949 | }; | |
2950 | ||
2951 | struct mlx5_ifc_rst2init_qp_out_bits { | |
2952 | u8 status[0x8]; | |
2953 | u8 reserved_0[0x18]; | |
2954 | ||
2955 | u8 syndrome[0x20]; | |
2956 | ||
2957 | u8 reserved_1[0x40]; | |
2958 | }; | |
2959 | ||
2960 | struct mlx5_ifc_rst2init_qp_in_bits { | |
2961 | u8 opcode[0x10]; | |
2962 | u8 reserved_0[0x10]; | |
2963 | ||
2964 | u8 reserved_1[0x10]; | |
2965 | u8 op_mod[0x10]; | |
2966 | ||
2967 | u8 reserved_2[0x8]; | |
2968 | u8 qpn[0x18]; | |
2969 | ||
2970 | u8 reserved_3[0x20]; | |
2971 | ||
2972 | u8 opt_param_mask[0x20]; | |
2973 | ||
2974 | u8 reserved_4[0x20]; | |
2975 | ||
2976 | struct mlx5_ifc_qpc_bits qpc; | |
2977 | ||
2978 | u8 reserved_5[0x80]; | |
2979 | }; | |
2980 | ||
2981 | struct mlx5_ifc_query_xrc_srq_out_bits { | |
2982 | u8 status[0x8]; | |
2983 | u8 reserved_0[0x18]; | |
2984 | ||
2985 | u8 syndrome[0x20]; | |
2986 | ||
2987 | u8 reserved_1[0x40]; | |
2988 | ||
2989 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
2990 | ||
2991 | u8 reserved_2[0x600]; | |
2992 | ||
2993 | u8 pas[0][0x40]; | |
2994 | }; | |
2995 | ||
2996 | struct mlx5_ifc_query_xrc_srq_in_bits { | |
2997 | u8 opcode[0x10]; | |
2998 | u8 reserved_0[0x10]; | |
2999 | ||
3000 | u8 reserved_1[0x10]; | |
3001 | u8 op_mod[0x10]; | |
3002 | ||
3003 | u8 reserved_2[0x8]; | |
3004 | u8 xrc_srqn[0x18]; | |
3005 | ||
3006 | u8 reserved_3[0x20]; | |
3007 | }; | |
3008 | ||
3009 | enum { | |
3010 | MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, | |
3011 | MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, | |
3012 | }; | |
3013 | ||
3014 | struct mlx5_ifc_query_vport_state_out_bits { | |
3015 | u8 status[0x8]; | |
3016 | u8 reserved_0[0x18]; | |
3017 | ||
3018 | u8 syndrome[0x20]; | |
3019 | ||
3020 | u8 reserved_1[0x20]; | |
3021 | ||
3022 | u8 reserved_2[0x18]; | |
3023 | u8 admin_state[0x4]; | |
3024 | u8 state[0x4]; | |
3025 | }; | |
3026 | ||
3027 | enum { | |
3028 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, | |
e7546514 | 3029 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, |
e281682b SM |
3030 | }; |
3031 | ||
3032 | struct mlx5_ifc_query_vport_state_in_bits { | |
3033 | u8 opcode[0x10]; | |
3034 | u8 reserved_0[0x10]; | |
3035 | ||
3036 | u8 reserved_1[0x10]; | |
3037 | u8 op_mod[0x10]; | |
3038 | ||
3039 | u8 other_vport[0x1]; | |
3040 | u8 reserved_2[0xf]; | |
3041 | u8 vport_number[0x10]; | |
3042 | ||
3043 | u8 reserved_3[0x20]; | |
3044 | }; | |
3045 | ||
3046 | struct mlx5_ifc_query_vport_counter_out_bits { | |
3047 | u8 status[0x8]; | |
3048 | u8 reserved_0[0x18]; | |
3049 | ||
3050 | u8 syndrome[0x20]; | |
3051 | ||
3052 | u8 reserved_1[0x40]; | |
3053 | ||
3054 | struct mlx5_ifc_traffic_counter_bits received_errors; | |
3055 | ||
3056 | struct mlx5_ifc_traffic_counter_bits transmit_errors; | |
3057 | ||
3058 | struct mlx5_ifc_traffic_counter_bits received_ib_unicast; | |
3059 | ||
3060 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; | |
3061 | ||
3062 | struct mlx5_ifc_traffic_counter_bits received_ib_multicast; | |
3063 | ||
3064 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; | |
3065 | ||
3066 | struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; | |
3067 | ||
3068 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; | |
3069 | ||
3070 | struct mlx5_ifc_traffic_counter_bits received_eth_unicast; | |
3071 | ||
3072 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; | |
3073 | ||
3074 | struct mlx5_ifc_traffic_counter_bits received_eth_multicast; | |
3075 | ||
3076 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; | |
3077 | ||
3078 | u8 reserved_2[0xa00]; | |
3079 | }; | |
3080 | ||
3081 | enum { | |
3082 | MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, | |
3083 | }; | |
3084 | ||
3085 | struct mlx5_ifc_query_vport_counter_in_bits { | |
3086 | u8 opcode[0x10]; | |
3087 | u8 reserved_0[0x10]; | |
3088 | ||
3089 | u8 reserved_1[0x10]; | |
3090 | u8 op_mod[0x10]; | |
3091 | ||
3092 | u8 other_vport[0x1]; | |
3093 | u8 reserved_2[0xf]; | |
3094 | u8 vport_number[0x10]; | |
3095 | ||
3096 | u8 reserved_3[0x60]; | |
3097 | ||
3098 | u8 clear[0x1]; | |
3099 | u8 reserved_4[0x1f]; | |
3100 | ||
3101 | u8 reserved_5[0x20]; | |
3102 | }; | |
3103 | ||
3104 | struct mlx5_ifc_query_tis_out_bits { | |
3105 | u8 status[0x8]; | |
3106 | u8 reserved_0[0x18]; | |
3107 | ||
3108 | u8 syndrome[0x20]; | |
3109 | ||
3110 | u8 reserved_1[0x40]; | |
3111 | ||
3112 | struct mlx5_ifc_tisc_bits tis_context; | |
3113 | }; | |
3114 | ||
3115 | struct mlx5_ifc_query_tis_in_bits { | |
3116 | u8 opcode[0x10]; | |
3117 | u8 reserved_0[0x10]; | |
3118 | ||
3119 | u8 reserved_1[0x10]; | |
3120 | u8 op_mod[0x10]; | |
3121 | ||
3122 | u8 reserved_2[0x8]; | |
3123 | u8 tisn[0x18]; | |
3124 | ||
3125 | u8 reserved_3[0x20]; | |
3126 | }; | |
3127 | ||
3128 | struct mlx5_ifc_query_tir_out_bits { | |
3129 | u8 status[0x8]; | |
3130 | u8 reserved_0[0x18]; | |
3131 | ||
3132 | u8 syndrome[0x20]; | |
3133 | ||
3134 | u8 reserved_1[0xc0]; | |
3135 | ||
3136 | struct mlx5_ifc_tirc_bits tir_context; | |
3137 | }; | |
3138 | ||
3139 | struct mlx5_ifc_query_tir_in_bits { | |
3140 | u8 opcode[0x10]; | |
3141 | u8 reserved_0[0x10]; | |
3142 | ||
3143 | u8 reserved_1[0x10]; | |
3144 | u8 op_mod[0x10]; | |
3145 | ||
3146 | u8 reserved_2[0x8]; | |
3147 | u8 tirn[0x18]; | |
3148 | ||
3149 | u8 reserved_3[0x20]; | |
3150 | }; | |
3151 | ||
3152 | struct mlx5_ifc_query_srq_out_bits { | |
3153 | u8 status[0x8]; | |
3154 | u8 reserved_0[0x18]; | |
3155 | ||
3156 | u8 syndrome[0x20]; | |
3157 | ||
3158 | u8 reserved_1[0x40]; | |
3159 | ||
3160 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
3161 | ||
3162 | u8 reserved_2[0x600]; | |
3163 | ||
3164 | u8 pas[0][0x40]; | |
3165 | }; | |
3166 | ||
3167 | struct mlx5_ifc_query_srq_in_bits { | |
3168 | u8 opcode[0x10]; | |
3169 | u8 reserved_0[0x10]; | |
3170 | ||
3171 | u8 reserved_1[0x10]; | |
3172 | u8 op_mod[0x10]; | |
3173 | ||
3174 | u8 reserved_2[0x8]; | |
3175 | u8 srqn[0x18]; | |
3176 | ||
3177 | u8 reserved_3[0x20]; | |
3178 | }; | |
3179 | ||
3180 | struct mlx5_ifc_query_sq_out_bits { | |
3181 | u8 status[0x8]; | |
3182 | u8 reserved_0[0x18]; | |
3183 | ||
3184 | u8 syndrome[0x20]; | |
3185 | ||
3186 | u8 reserved_1[0xc0]; | |
3187 | ||
3188 | struct mlx5_ifc_sqc_bits sq_context; | |
3189 | }; | |
3190 | ||
3191 | struct mlx5_ifc_query_sq_in_bits { | |
3192 | u8 opcode[0x10]; | |
3193 | u8 reserved_0[0x10]; | |
3194 | ||
3195 | u8 reserved_1[0x10]; | |
3196 | u8 op_mod[0x10]; | |
3197 | ||
3198 | u8 reserved_2[0x8]; | |
3199 | u8 sqn[0x18]; | |
3200 | ||
3201 | u8 reserved_3[0x20]; | |
3202 | }; | |
3203 | ||
3204 | struct mlx5_ifc_query_special_contexts_out_bits { | |
3205 | u8 status[0x8]; | |
3206 | u8 reserved_0[0x18]; | |
3207 | ||
3208 | u8 syndrome[0x20]; | |
3209 | ||
3210 | u8 reserved_1[0x20]; | |
3211 | ||
3212 | u8 resd_lkey[0x20]; | |
3213 | }; | |
3214 | ||
3215 | struct mlx5_ifc_query_special_contexts_in_bits { | |
3216 | u8 opcode[0x10]; | |
3217 | u8 reserved_0[0x10]; | |
3218 | ||
3219 | u8 reserved_1[0x10]; | |
3220 | u8 op_mod[0x10]; | |
3221 | ||
3222 | u8 reserved_2[0x40]; | |
3223 | }; | |
3224 | ||
3225 | struct mlx5_ifc_query_rqt_out_bits { | |
3226 | u8 status[0x8]; | |
3227 | u8 reserved_0[0x18]; | |
3228 | ||
3229 | u8 syndrome[0x20]; | |
3230 | ||
3231 | u8 reserved_1[0xc0]; | |
3232 | ||
3233 | struct mlx5_ifc_rqtc_bits rqt_context; | |
3234 | }; | |
3235 | ||
3236 | struct mlx5_ifc_query_rqt_in_bits { | |
3237 | u8 opcode[0x10]; | |
3238 | u8 reserved_0[0x10]; | |
3239 | ||
3240 | u8 reserved_1[0x10]; | |
3241 | u8 op_mod[0x10]; | |
3242 | ||
3243 | u8 reserved_2[0x8]; | |
3244 | u8 rqtn[0x18]; | |
3245 | ||
3246 | u8 reserved_3[0x20]; | |
3247 | }; | |
3248 | ||
3249 | struct mlx5_ifc_query_rq_out_bits { | |
3250 | u8 status[0x8]; | |
3251 | u8 reserved_0[0x18]; | |
3252 | ||
3253 | u8 syndrome[0x20]; | |
3254 | ||
3255 | u8 reserved_1[0xc0]; | |
3256 | ||
3257 | struct mlx5_ifc_rqc_bits rq_context; | |
3258 | }; | |
3259 | ||
3260 | struct mlx5_ifc_query_rq_in_bits { | |
3261 | u8 opcode[0x10]; | |
3262 | u8 reserved_0[0x10]; | |
3263 | ||
3264 | u8 reserved_1[0x10]; | |
3265 | u8 op_mod[0x10]; | |
3266 | ||
3267 | u8 reserved_2[0x8]; | |
3268 | u8 rqn[0x18]; | |
3269 | ||
3270 | u8 reserved_3[0x20]; | |
3271 | }; | |
3272 | ||
3273 | struct mlx5_ifc_query_roce_address_out_bits { | |
3274 | u8 status[0x8]; | |
3275 | u8 reserved_0[0x18]; | |
3276 | ||
3277 | u8 syndrome[0x20]; | |
3278 | ||
3279 | u8 reserved_1[0x40]; | |
3280 | ||
3281 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
3282 | }; | |
3283 | ||
3284 | struct mlx5_ifc_query_roce_address_in_bits { | |
3285 | u8 opcode[0x10]; | |
3286 | u8 reserved_0[0x10]; | |
3287 | ||
3288 | u8 reserved_1[0x10]; | |
3289 | u8 op_mod[0x10]; | |
3290 | ||
3291 | u8 roce_address_index[0x10]; | |
3292 | u8 reserved_2[0x10]; | |
3293 | ||
3294 | u8 reserved_3[0x20]; | |
3295 | }; | |
3296 | ||
3297 | struct mlx5_ifc_query_rmp_out_bits { | |
3298 | u8 status[0x8]; | |
3299 | u8 reserved_0[0x18]; | |
3300 | ||
3301 | u8 syndrome[0x20]; | |
3302 | ||
3303 | u8 reserved_1[0xc0]; | |
3304 | ||
3305 | struct mlx5_ifc_rmpc_bits rmp_context; | |
3306 | }; | |
3307 | ||
3308 | struct mlx5_ifc_query_rmp_in_bits { | |
3309 | u8 opcode[0x10]; | |
3310 | u8 reserved_0[0x10]; | |
3311 | ||
3312 | u8 reserved_1[0x10]; | |
3313 | u8 op_mod[0x10]; | |
3314 | ||
3315 | u8 reserved_2[0x8]; | |
3316 | u8 rmpn[0x18]; | |
3317 | ||
3318 | u8 reserved_3[0x20]; | |
3319 | }; | |
3320 | ||
3321 | struct mlx5_ifc_query_qp_out_bits { | |
3322 | u8 status[0x8]; | |
3323 | u8 reserved_0[0x18]; | |
3324 | ||
3325 | u8 syndrome[0x20]; | |
3326 | ||
3327 | u8 reserved_1[0x40]; | |
3328 | ||
3329 | u8 opt_param_mask[0x20]; | |
3330 | ||
3331 | u8 reserved_2[0x20]; | |
3332 | ||
3333 | struct mlx5_ifc_qpc_bits qpc; | |
3334 | ||
3335 | u8 reserved_3[0x80]; | |
3336 | ||
3337 | u8 pas[0][0x40]; | |
3338 | }; | |
3339 | ||
3340 | struct mlx5_ifc_query_qp_in_bits { | |
3341 | u8 opcode[0x10]; | |
3342 | u8 reserved_0[0x10]; | |
3343 | ||
3344 | u8 reserved_1[0x10]; | |
3345 | u8 op_mod[0x10]; | |
3346 | ||
3347 | u8 reserved_2[0x8]; | |
3348 | u8 qpn[0x18]; | |
3349 | ||
3350 | u8 reserved_3[0x20]; | |
3351 | }; | |
3352 | ||
3353 | struct mlx5_ifc_query_q_counter_out_bits { | |
3354 | u8 status[0x8]; | |
3355 | u8 reserved_0[0x18]; | |
3356 | ||
3357 | u8 syndrome[0x20]; | |
3358 | ||
3359 | u8 reserved_1[0x40]; | |
3360 | ||
3361 | u8 rx_write_requests[0x20]; | |
3362 | ||
3363 | u8 reserved_2[0x20]; | |
3364 | ||
3365 | u8 rx_read_requests[0x20]; | |
3366 | ||
3367 | u8 reserved_3[0x20]; | |
3368 | ||
3369 | u8 rx_atomic_requests[0x20]; | |
3370 | ||
3371 | u8 reserved_4[0x20]; | |
3372 | ||
3373 | u8 rx_dct_connect[0x20]; | |
3374 | ||
3375 | u8 reserved_5[0x20]; | |
3376 | ||
3377 | u8 out_of_buffer[0x20]; | |
3378 | ||
3379 | u8 reserved_6[0x20]; | |
3380 | ||
3381 | u8 out_of_sequence[0x20]; | |
3382 | ||
3383 | u8 reserved_7[0x620]; | |
3384 | }; | |
3385 | ||
3386 | struct mlx5_ifc_query_q_counter_in_bits { | |
3387 | u8 opcode[0x10]; | |
3388 | u8 reserved_0[0x10]; | |
3389 | ||
3390 | u8 reserved_1[0x10]; | |
3391 | u8 op_mod[0x10]; | |
3392 | ||
3393 | u8 reserved_2[0x80]; | |
3394 | ||
3395 | u8 clear[0x1]; | |
3396 | u8 reserved_3[0x1f]; | |
3397 | ||
3398 | u8 reserved_4[0x18]; | |
3399 | u8 counter_set_id[0x8]; | |
3400 | }; | |
3401 | ||
3402 | struct mlx5_ifc_query_pages_out_bits { | |
3403 | u8 status[0x8]; | |
3404 | u8 reserved_0[0x18]; | |
3405 | ||
3406 | u8 syndrome[0x20]; | |
3407 | ||
3408 | u8 reserved_1[0x10]; | |
3409 | u8 function_id[0x10]; | |
3410 | ||
3411 | u8 num_pages[0x20]; | |
3412 | }; | |
3413 | ||
3414 | enum { | |
3415 | MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, | |
3416 | MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, | |
3417 | MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, | |
3418 | }; | |
3419 | ||
3420 | struct mlx5_ifc_query_pages_in_bits { | |
3421 | u8 opcode[0x10]; | |
3422 | u8 reserved_0[0x10]; | |
3423 | ||
3424 | u8 reserved_1[0x10]; | |
3425 | u8 op_mod[0x10]; | |
3426 | ||
3427 | u8 reserved_2[0x10]; | |
3428 | u8 function_id[0x10]; | |
3429 | ||
3430 | u8 reserved_3[0x20]; | |
3431 | }; | |
3432 | ||
3433 | struct mlx5_ifc_query_nic_vport_context_out_bits { | |
3434 | u8 status[0x8]; | |
3435 | u8 reserved_0[0x18]; | |
3436 | ||
3437 | u8 syndrome[0x20]; | |
3438 | ||
3439 | u8 reserved_1[0x40]; | |
3440 | ||
3441 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
3442 | }; | |
3443 | ||
3444 | struct mlx5_ifc_query_nic_vport_context_in_bits { | |
3445 | u8 opcode[0x10]; | |
3446 | u8 reserved_0[0x10]; | |
3447 | ||
3448 | u8 reserved_1[0x10]; | |
3449 | u8 op_mod[0x10]; | |
3450 | ||
3451 | u8 other_vport[0x1]; | |
3452 | u8 reserved_2[0xf]; | |
3453 | u8 vport_number[0x10]; | |
3454 | ||
3455 | u8 reserved_3[0x5]; | |
3456 | u8 allowed_list_type[0x3]; | |
3457 | u8 reserved_4[0x18]; | |
3458 | }; | |
3459 | ||
3460 | struct mlx5_ifc_query_mkey_out_bits { | |
3461 | u8 status[0x8]; | |
3462 | u8 reserved_0[0x18]; | |
3463 | ||
3464 | u8 syndrome[0x20]; | |
3465 | ||
3466 | u8 reserved_1[0x40]; | |
3467 | ||
3468 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
3469 | ||
3470 | u8 reserved_2[0x600]; | |
3471 | ||
3472 | u8 bsf0_klm0_pas_mtt0_1[16][0x8]; | |
3473 | ||
3474 | u8 bsf1_klm1_pas_mtt2_3[16][0x8]; | |
3475 | }; | |
3476 | ||
3477 | struct mlx5_ifc_query_mkey_in_bits { | |
3478 | u8 opcode[0x10]; | |
3479 | u8 reserved_0[0x10]; | |
3480 | ||
3481 | u8 reserved_1[0x10]; | |
3482 | u8 op_mod[0x10]; | |
3483 | ||
3484 | u8 reserved_2[0x8]; | |
3485 | u8 mkey_index[0x18]; | |
3486 | ||
3487 | u8 pg_access[0x1]; | |
3488 | u8 reserved_3[0x1f]; | |
3489 | }; | |
3490 | ||
3491 | struct mlx5_ifc_query_mad_demux_out_bits { | |
3492 | u8 status[0x8]; | |
3493 | u8 reserved_0[0x18]; | |
3494 | ||
3495 | u8 syndrome[0x20]; | |
3496 | ||
3497 | u8 reserved_1[0x40]; | |
3498 | ||
3499 | u8 mad_dumux_parameters_block[0x20]; | |
3500 | }; | |
3501 | ||
3502 | struct mlx5_ifc_query_mad_demux_in_bits { | |
3503 | u8 opcode[0x10]; | |
3504 | u8 reserved_0[0x10]; | |
3505 | ||
3506 | u8 reserved_1[0x10]; | |
3507 | u8 op_mod[0x10]; | |
3508 | ||
3509 | u8 reserved_2[0x40]; | |
3510 | }; | |
3511 | ||
3512 | struct mlx5_ifc_query_l2_table_entry_out_bits { | |
3513 | u8 status[0x8]; | |
3514 | u8 reserved_0[0x18]; | |
3515 | ||
3516 | u8 syndrome[0x20]; | |
3517 | ||
3518 | u8 reserved_1[0xa0]; | |
3519 | ||
3520 | u8 reserved_2[0x13]; | |
3521 | u8 vlan_valid[0x1]; | |
3522 | u8 vlan[0xc]; | |
3523 | ||
3524 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
3525 | ||
3526 | u8 reserved_3[0xc0]; | |
3527 | }; | |
3528 | ||
3529 | struct mlx5_ifc_query_l2_table_entry_in_bits { | |
3530 | u8 opcode[0x10]; | |
3531 | u8 reserved_0[0x10]; | |
3532 | ||
3533 | u8 reserved_1[0x10]; | |
3534 | u8 op_mod[0x10]; | |
3535 | ||
3536 | u8 reserved_2[0x60]; | |
3537 | ||
3538 | u8 reserved_3[0x8]; | |
3539 | u8 table_index[0x18]; | |
3540 | ||
3541 | u8 reserved_4[0x140]; | |
3542 | }; | |
3543 | ||
3544 | struct mlx5_ifc_query_issi_out_bits { | |
3545 | u8 status[0x8]; | |
3546 | u8 reserved_0[0x18]; | |
3547 | ||
3548 | u8 syndrome[0x20]; | |
3549 | ||
3550 | u8 reserved_1[0x10]; | |
3551 | u8 current_issi[0x10]; | |
3552 | ||
3553 | u8 reserved_2[0xa0]; | |
3554 | ||
3555 | u8 supported_issi_reserved[76][0x8]; | |
3556 | u8 supported_issi_dw0[0x20]; | |
3557 | }; | |
3558 | ||
3559 | struct mlx5_ifc_query_issi_in_bits { | |
3560 | u8 opcode[0x10]; | |
3561 | u8 reserved_0[0x10]; | |
3562 | ||
3563 | u8 reserved_1[0x10]; | |
3564 | u8 op_mod[0x10]; | |
3565 | ||
3566 | u8 reserved_2[0x40]; | |
3567 | }; | |
3568 | ||
3569 | struct mlx5_ifc_query_hca_vport_pkey_out_bits { | |
3570 | u8 status[0x8]; | |
3571 | u8 reserved_0[0x18]; | |
3572 | ||
3573 | u8 syndrome[0x20]; | |
3574 | ||
3575 | u8 reserved_1[0x40]; | |
3576 | ||
3577 | struct mlx5_ifc_pkey_bits pkey[0]; | |
3578 | }; | |
3579 | ||
3580 | struct mlx5_ifc_query_hca_vport_pkey_in_bits { | |
3581 | u8 opcode[0x10]; | |
3582 | u8 reserved_0[0x10]; | |
3583 | ||
3584 | u8 reserved_1[0x10]; | |
3585 | u8 op_mod[0x10]; | |
3586 | ||
3587 | u8 other_vport[0x1]; | |
707c4602 MD |
3588 | u8 reserved_2[0xb]; |
3589 | u8 port_num[0x4]; | |
e281682b SM |
3590 | u8 vport_number[0x10]; |
3591 | ||
3592 | u8 reserved_3[0x10]; | |
3593 | u8 pkey_index[0x10]; | |
3594 | }; | |
3595 | ||
3596 | struct mlx5_ifc_query_hca_vport_gid_out_bits { | |
3597 | u8 status[0x8]; | |
3598 | u8 reserved_0[0x18]; | |
3599 | ||
3600 | u8 syndrome[0x20]; | |
3601 | ||
3602 | u8 reserved_1[0x20]; | |
3603 | ||
3604 | u8 gids_num[0x10]; | |
3605 | u8 reserved_2[0x10]; | |
3606 | ||
3607 | struct mlx5_ifc_array128_auto_bits gid[0]; | |
3608 | }; | |
3609 | ||
3610 | struct mlx5_ifc_query_hca_vport_gid_in_bits { | |
3611 | u8 opcode[0x10]; | |
3612 | u8 reserved_0[0x10]; | |
3613 | ||
3614 | u8 reserved_1[0x10]; | |
3615 | u8 op_mod[0x10]; | |
3616 | ||
3617 | u8 other_vport[0x1]; | |
707c4602 MD |
3618 | u8 reserved_2[0xb]; |
3619 | u8 port_num[0x4]; | |
e281682b SM |
3620 | u8 vport_number[0x10]; |
3621 | ||
3622 | u8 reserved_3[0x10]; | |
3623 | u8 gid_index[0x10]; | |
3624 | }; | |
3625 | ||
3626 | struct mlx5_ifc_query_hca_vport_context_out_bits { | |
3627 | u8 status[0x8]; | |
3628 | u8 reserved_0[0x18]; | |
3629 | ||
3630 | u8 syndrome[0x20]; | |
3631 | ||
3632 | u8 reserved_1[0x40]; | |
3633 | ||
3634 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
3635 | }; | |
3636 | ||
3637 | struct mlx5_ifc_query_hca_vport_context_in_bits { | |
3638 | u8 opcode[0x10]; | |
3639 | u8 reserved_0[0x10]; | |
3640 | ||
3641 | u8 reserved_1[0x10]; | |
3642 | u8 op_mod[0x10]; | |
3643 | ||
3644 | u8 other_vport[0x1]; | |
707c4602 MD |
3645 | u8 reserved_2[0xb]; |
3646 | u8 port_num[0x4]; | |
e281682b SM |
3647 | u8 vport_number[0x10]; |
3648 | ||
3649 | u8 reserved_3[0x20]; | |
3650 | }; | |
3651 | ||
3652 | struct mlx5_ifc_query_hca_cap_out_bits { | |
3653 | u8 status[0x8]; | |
3654 | u8 reserved_0[0x18]; | |
3655 | ||
3656 | u8 syndrome[0x20]; | |
3657 | ||
3658 | u8 reserved_1[0x40]; | |
3659 | ||
3660 | union mlx5_ifc_hca_cap_union_bits capability; | |
3661 | }; | |
3662 | ||
3663 | struct mlx5_ifc_query_hca_cap_in_bits { | |
3664 | u8 opcode[0x10]; | |
3665 | u8 reserved_0[0x10]; | |
3666 | ||
3667 | u8 reserved_1[0x10]; | |
3668 | u8 op_mod[0x10]; | |
3669 | ||
3670 | u8 reserved_2[0x40]; | |
3671 | }; | |
3672 | ||
3673 | struct mlx5_ifc_query_flow_table_out_bits { | |
3674 | u8 status[0x8]; | |
3675 | u8 reserved_0[0x18]; | |
3676 | ||
3677 | u8 syndrome[0x20]; | |
3678 | ||
3679 | u8 reserved_1[0x80]; | |
3680 | ||
3681 | u8 reserved_2[0x8]; | |
3682 | u8 level[0x8]; | |
3683 | u8 reserved_3[0x8]; | |
3684 | u8 log_size[0x8]; | |
3685 | ||
3686 | u8 reserved_4[0x120]; | |
3687 | }; | |
3688 | ||
3689 | struct mlx5_ifc_query_flow_table_in_bits { | |
3690 | u8 opcode[0x10]; | |
3691 | u8 reserved_0[0x10]; | |
3692 | ||
3693 | u8 reserved_1[0x10]; | |
3694 | u8 op_mod[0x10]; | |
3695 | ||
3696 | u8 reserved_2[0x40]; | |
3697 | ||
3698 | u8 table_type[0x8]; | |
3699 | u8 reserved_3[0x18]; | |
3700 | ||
3701 | u8 reserved_4[0x8]; | |
3702 | u8 table_id[0x18]; | |
3703 | ||
3704 | u8 reserved_5[0x140]; | |
3705 | }; | |
3706 | ||
3707 | struct mlx5_ifc_query_fte_out_bits { | |
3708 | u8 status[0x8]; | |
3709 | u8 reserved_0[0x18]; | |
3710 | ||
3711 | u8 syndrome[0x20]; | |
3712 | ||
3713 | u8 reserved_1[0x1c0]; | |
3714 | ||
3715 | struct mlx5_ifc_flow_context_bits flow_context; | |
3716 | }; | |
3717 | ||
3718 | struct mlx5_ifc_query_fte_in_bits { | |
3719 | u8 opcode[0x10]; | |
3720 | u8 reserved_0[0x10]; | |
3721 | ||
3722 | u8 reserved_1[0x10]; | |
3723 | u8 op_mod[0x10]; | |
3724 | ||
3725 | u8 reserved_2[0x40]; | |
3726 | ||
3727 | u8 table_type[0x8]; | |
3728 | u8 reserved_3[0x18]; | |
3729 | ||
3730 | u8 reserved_4[0x8]; | |
3731 | u8 table_id[0x18]; | |
3732 | ||
3733 | u8 reserved_5[0x40]; | |
3734 | ||
3735 | u8 flow_index[0x20]; | |
3736 | ||
3737 | u8 reserved_6[0xe0]; | |
3738 | }; | |
3739 | ||
3740 | enum { | |
3741 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
3742 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
3743 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
3744 | }; | |
3745 | ||
3746 | struct mlx5_ifc_query_flow_group_out_bits { | |
3747 | u8 status[0x8]; | |
3748 | u8 reserved_0[0x18]; | |
3749 | ||
3750 | u8 syndrome[0x20]; | |
3751 | ||
3752 | u8 reserved_1[0xa0]; | |
3753 | ||
3754 | u8 start_flow_index[0x20]; | |
3755 | ||
3756 | u8 reserved_2[0x20]; | |
3757 | ||
3758 | u8 end_flow_index[0x20]; | |
3759 | ||
3760 | u8 reserved_3[0xa0]; | |
3761 | ||
3762 | u8 reserved_4[0x18]; | |
3763 | u8 match_criteria_enable[0x8]; | |
3764 | ||
3765 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
3766 | ||
3767 | u8 reserved_5[0xe00]; | |
3768 | }; | |
3769 | ||
3770 | struct mlx5_ifc_query_flow_group_in_bits { | |
3771 | u8 opcode[0x10]; | |
3772 | u8 reserved_0[0x10]; | |
3773 | ||
3774 | u8 reserved_1[0x10]; | |
3775 | u8 op_mod[0x10]; | |
3776 | ||
3777 | u8 reserved_2[0x40]; | |
3778 | ||
3779 | u8 table_type[0x8]; | |
3780 | u8 reserved_3[0x18]; | |
3781 | ||
3782 | u8 reserved_4[0x8]; | |
3783 | u8 table_id[0x18]; | |
3784 | ||
3785 | u8 group_id[0x20]; | |
3786 | ||
3787 | u8 reserved_5[0x120]; | |
3788 | }; | |
3789 | ||
d6666753 SM |
3790 | struct mlx5_ifc_query_esw_vport_context_out_bits { |
3791 | u8 status[0x8]; | |
3792 | u8 reserved_0[0x18]; | |
3793 | ||
3794 | u8 syndrome[0x20]; | |
3795 | ||
3796 | u8 reserved_1[0x40]; | |
3797 | ||
3798 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
3799 | }; | |
3800 | ||
3801 | struct mlx5_ifc_query_esw_vport_context_in_bits { | |
3802 | u8 opcode[0x10]; | |
3803 | u8 reserved_0[0x10]; | |
3804 | ||
3805 | u8 reserved_1[0x10]; | |
3806 | u8 op_mod[0x10]; | |
3807 | ||
3808 | u8 other_vport[0x1]; | |
3809 | u8 reserved_2[0xf]; | |
3810 | u8 vport_number[0x10]; | |
3811 | ||
3812 | u8 reserved_3[0x20]; | |
3813 | }; | |
3814 | ||
3815 | struct mlx5_ifc_modify_esw_vport_context_out_bits { | |
3816 | u8 status[0x8]; | |
3817 | u8 reserved_0[0x18]; | |
3818 | ||
3819 | u8 syndrome[0x20]; | |
3820 | ||
3821 | u8 reserved_1[0x40]; | |
3822 | }; | |
3823 | ||
3824 | struct mlx5_ifc_esw_vport_context_fields_select_bits { | |
3825 | u8 reserved[0x1c]; | |
3826 | u8 vport_cvlan_insert[0x1]; | |
3827 | u8 vport_svlan_insert[0x1]; | |
3828 | u8 vport_cvlan_strip[0x1]; | |
3829 | u8 vport_svlan_strip[0x1]; | |
3830 | }; | |
3831 | ||
3832 | struct mlx5_ifc_modify_esw_vport_context_in_bits { | |
3833 | u8 opcode[0x10]; | |
3834 | u8 reserved_0[0x10]; | |
3835 | ||
3836 | u8 reserved_1[0x10]; | |
3837 | u8 op_mod[0x10]; | |
3838 | ||
3839 | u8 other_vport[0x1]; | |
3840 | u8 reserved_2[0xf]; | |
3841 | u8 vport_number[0x10]; | |
3842 | ||
3843 | struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; | |
3844 | ||
3845 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
3846 | }; | |
3847 | ||
e281682b SM |
3848 | struct mlx5_ifc_query_eq_out_bits { |
3849 | u8 status[0x8]; | |
3850 | u8 reserved_0[0x18]; | |
3851 | ||
3852 | u8 syndrome[0x20]; | |
3853 | ||
3854 | u8 reserved_1[0x40]; | |
3855 | ||
3856 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
3857 | ||
3858 | u8 reserved_2[0x40]; | |
3859 | ||
3860 | u8 event_bitmask[0x40]; | |
3861 | ||
3862 | u8 reserved_3[0x580]; | |
3863 | ||
3864 | u8 pas[0][0x40]; | |
3865 | }; | |
3866 | ||
3867 | struct mlx5_ifc_query_eq_in_bits { | |
3868 | u8 opcode[0x10]; | |
3869 | u8 reserved_0[0x10]; | |
3870 | ||
3871 | u8 reserved_1[0x10]; | |
3872 | u8 op_mod[0x10]; | |
3873 | ||
3874 | u8 reserved_2[0x18]; | |
3875 | u8 eq_number[0x8]; | |
3876 | ||
3877 | u8 reserved_3[0x20]; | |
3878 | }; | |
3879 | ||
3880 | struct mlx5_ifc_query_dct_out_bits { | |
3881 | u8 status[0x8]; | |
3882 | u8 reserved_0[0x18]; | |
3883 | ||
3884 | u8 syndrome[0x20]; | |
3885 | ||
3886 | u8 reserved_1[0x40]; | |
3887 | ||
3888 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
3889 | ||
3890 | u8 reserved_2[0x180]; | |
3891 | }; | |
3892 | ||
3893 | struct mlx5_ifc_query_dct_in_bits { | |
3894 | u8 opcode[0x10]; | |
3895 | u8 reserved_0[0x10]; | |
3896 | ||
3897 | u8 reserved_1[0x10]; | |
3898 | u8 op_mod[0x10]; | |
3899 | ||
3900 | u8 reserved_2[0x8]; | |
3901 | u8 dctn[0x18]; | |
3902 | ||
3903 | u8 reserved_3[0x20]; | |
3904 | }; | |
3905 | ||
3906 | struct mlx5_ifc_query_cq_out_bits { | |
3907 | u8 status[0x8]; | |
3908 | u8 reserved_0[0x18]; | |
3909 | ||
3910 | u8 syndrome[0x20]; | |
3911 | ||
3912 | u8 reserved_1[0x40]; | |
3913 | ||
3914 | struct mlx5_ifc_cqc_bits cq_context; | |
3915 | ||
3916 | u8 reserved_2[0x600]; | |
3917 | ||
3918 | u8 pas[0][0x40]; | |
3919 | }; | |
3920 | ||
3921 | struct mlx5_ifc_query_cq_in_bits { | |
3922 | u8 opcode[0x10]; | |
3923 | u8 reserved_0[0x10]; | |
3924 | ||
3925 | u8 reserved_1[0x10]; | |
3926 | u8 op_mod[0x10]; | |
3927 | ||
3928 | u8 reserved_2[0x8]; | |
3929 | u8 cqn[0x18]; | |
3930 | ||
3931 | u8 reserved_3[0x20]; | |
3932 | }; | |
3933 | ||
3934 | struct mlx5_ifc_query_cong_status_out_bits { | |
3935 | u8 status[0x8]; | |
3936 | u8 reserved_0[0x18]; | |
3937 | ||
3938 | u8 syndrome[0x20]; | |
3939 | ||
3940 | u8 reserved_1[0x20]; | |
3941 | ||
3942 | u8 enable[0x1]; | |
3943 | u8 tag_enable[0x1]; | |
3944 | u8 reserved_2[0x1e]; | |
3945 | }; | |
3946 | ||
3947 | struct mlx5_ifc_query_cong_status_in_bits { | |
3948 | u8 opcode[0x10]; | |
3949 | u8 reserved_0[0x10]; | |
3950 | ||
3951 | u8 reserved_1[0x10]; | |
3952 | u8 op_mod[0x10]; | |
3953 | ||
3954 | u8 reserved_2[0x18]; | |
3955 | u8 priority[0x4]; | |
3956 | u8 cong_protocol[0x4]; | |
3957 | ||
3958 | u8 reserved_3[0x20]; | |
3959 | }; | |
3960 | ||
3961 | struct mlx5_ifc_query_cong_statistics_out_bits { | |
3962 | u8 status[0x8]; | |
3963 | u8 reserved_0[0x18]; | |
3964 | ||
3965 | u8 syndrome[0x20]; | |
3966 | ||
3967 | u8 reserved_1[0x40]; | |
3968 | ||
3969 | u8 cur_flows[0x20]; | |
3970 | ||
3971 | u8 sum_flows[0x20]; | |
3972 | ||
3973 | u8 cnp_ignored_high[0x20]; | |
3974 | ||
3975 | u8 cnp_ignored_low[0x20]; | |
3976 | ||
3977 | u8 cnp_handled_high[0x20]; | |
3978 | ||
3979 | u8 cnp_handled_low[0x20]; | |
3980 | ||
3981 | u8 reserved_2[0x100]; | |
3982 | ||
3983 | u8 time_stamp_high[0x20]; | |
3984 | ||
3985 | u8 time_stamp_low[0x20]; | |
3986 | ||
3987 | u8 accumulators_period[0x20]; | |
3988 | ||
3989 | u8 ecn_marked_roce_packets_high[0x20]; | |
3990 | ||
3991 | u8 ecn_marked_roce_packets_low[0x20]; | |
3992 | ||
3993 | u8 cnps_sent_high[0x20]; | |
3994 | ||
3995 | u8 cnps_sent_low[0x20]; | |
3996 | ||
3997 | u8 reserved_3[0x560]; | |
3998 | }; | |
3999 | ||
4000 | struct mlx5_ifc_query_cong_statistics_in_bits { | |
4001 | u8 opcode[0x10]; | |
4002 | u8 reserved_0[0x10]; | |
4003 | ||
4004 | u8 reserved_1[0x10]; | |
4005 | u8 op_mod[0x10]; | |
4006 | ||
4007 | u8 clear[0x1]; | |
4008 | u8 reserved_2[0x1f]; | |
4009 | ||
4010 | u8 reserved_3[0x20]; | |
4011 | }; | |
4012 | ||
4013 | struct mlx5_ifc_query_cong_params_out_bits { | |
4014 | u8 status[0x8]; | |
4015 | u8 reserved_0[0x18]; | |
4016 | ||
4017 | u8 syndrome[0x20]; | |
4018 | ||
4019 | u8 reserved_1[0x40]; | |
4020 | ||
4021 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
4022 | }; | |
4023 | ||
4024 | struct mlx5_ifc_query_cong_params_in_bits { | |
4025 | u8 opcode[0x10]; | |
4026 | u8 reserved_0[0x10]; | |
4027 | ||
4028 | u8 reserved_1[0x10]; | |
4029 | u8 op_mod[0x10]; | |
4030 | ||
4031 | u8 reserved_2[0x1c]; | |
4032 | u8 cong_protocol[0x4]; | |
4033 | ||
4034 | u8 reserved_3[0x20]; | |
4035 | }; | |
4036 | ||
4037 | struct mlx5_ifc_query_adapter_out_bits { | |
4038 | u8 status[0x8]; | |
4039 | u8 reserved_0[0x18]; | |
4040 | ||
4041 | u8 syndrome[0x20]; | |
4042 | ||
4043 | u8 reserved_1[0x40]; | |
4044 | ||
4045 | struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; | |
4046 | }; | |
4047 | ||
4048 | struct mlx5_ifc_query_adapter_in_bits { | |
4049 | u8 opcode[0x10]; | |
4050 | u8 reserved_0[0x10]; | |
4051 | ||
4052 | u8 reserved_1[0x10]; | |
4053 | u8 op_mod[0x10]; | |
4054 | ||
4055 | u8 reserved_2[0x40]; | |
4056 | }; | |
4057 | ||
4058 | struct mlx5_ifc_qp_2rst_out_bits { | |
4059 | u8 status[0x8]; | |
4060 | u8 reserved_0[0x18]; | |
4061 | ||
4062 | u8 syndrome[0x20]; | |
4063 | ||
4064 | u8 reserved_1[0x40]; | |
4065 | }; | |
4066 | ||
4067 | struct mlx5_ifc_qp_2rst_in_bits { | |
4068 | u8 opcode[0x10]; | |
4069 | u8 reserved_0[0x10]; | |
4070 | ||
4071 | u8 reserved_1[0x10]; | |
4072 | u8 op_mod[0x10]; | |
4073 | ||
4074 | u8 reserved_2[0x8]; | |
4075 | u8 qpn[0x18]; | |
4076 | ||
4077 | u8 reserved_3[0x20]; | |
4078 | }; | |
4079 | ||
4080 | struct mlx5_ifc_qp_2err_out_bits { | |
4081 | u8 status[0x8]; | |
4082 | u8 reserved_0[0x18]; | |
4083 | ||
4084 | u8 syndrome[0x20]; | |
4085 | ||
4086 | u8 reserved_1[0x40]; | |
4087 | }; | |
4088 | ||
4089 | struct mlx5_ifc_qp_2err_in_bits { | |
4090 | u8 opcode[0x10]; | |
4091 | u8 reserved_0[0x10]; | |
4092 | ||
4093 | u8 reserved_1[0x10]; | |
4094 | u8 op_mod[0x10]; | |
4095 | ||
4096 | u8 reserved_2[0x8]; | |
4097 | u8 qpn[0x18]; | |
4098 | ||
4099 | u8 reserved_3[0x20]; | |
4100 | }; | |
4101 | ||
4102 | struct mlx5_ifc_page_fault_resume_out_bits { | |
4103 | u8 status[0x8]; | |
4104 | u8 reserved_0[0x18]; | |
4105 | ||
4106 | u8 syndrome[0x20]; | |
4107 | ||
4108 | u8 reserved_1[0x40]; | |
4109 | }; | |
4110 | ||
4111 | struct mlx5_ifc_page_fault_resume_in_bits { | |
4112 | u8 opcode[0x10]; | |
4113 | u8 reserved_0[0x10]; | |
4114 | ||
4115 | u8 reserved_1[0x10]; | |
4116 | u8 op_mod[0x10]; | |
4117 | ||
4118 | u8 error[0x1]; | |
4119 | u8 reserved_2[0x4]; | |
4120 | u8 rdma[0x1]; | |
4121 | u8 read_write[0x1]; | |
4122 | u8 req_res[0x1]; | |
4123 | u8 qpn[0x18]; | |
4124 | ||
4125 | u8 reserved_3[0x20]; | |
4126 | }; | |
4127 | ||
4128 | struct mlx5_ifc_nop_out_bits { | |
4129 | u8 status[0x8]; | |
4130 | u8 reserved_0[0x18]; | |
4131 | ||
4132 | u8 syndrome[0x20]; | |
4133 | ||
4134 | u8 reserved_1[0x40]; | |
4135 | }; | |
4136 | ||
4137 | struct mlx5_ifc_nop_in_bits { | |
4138 | u8 opcode[0x10]; | |
4139 | u8 reserved_0[0x10]; | |
4140 | ||
4141 | u8 reserved_1[0x10]; | |
4142 | u8 op_mod[0x10]; | |
4143 | ||
4144 | u8 reserved_2[0x40]; | |
4145 | }; | |
4146 | ||
4147 | struct mlx5_ifc_modify_vport_state_out_bits { | |
4148 | u8 status[0x8]; | |
4149 | u8 reserved_0[0x18]; | |
4150 | ||
4151 | u8 syndrome[0x20]; | |
4152 | ||
4153 | u8 reserved_1[0x40]; | |
4154 | }; | |
4155 | ||
4156 | struct mlx5_ifc_modify_vport_state_in_bits { | |
4157 | u8 opcode[0x10]; | |
4158 | u8 reserved_0[0x10]; | |
4159 | ||
4160 | u8 reserved_1[0x10]; | |
4161 | u8 op_mod[0x10]; | |
4162 | ||
4163 | u8 other_vport[0x1]; | |
4164 | u8 reserved_2[0xf]; | |
4165 | u8 vport_number[0x10]; | |
4166 | ||
4167 | u8 reserved_3[0x18]; | |
4168 | u8 admin_state[0x4]; | |
4169 | u8 reserved_4[0x4]; | |
4170 | }; | |
4171 | ||
4172 | struct mlx5_ifc_modify_tis_out_bits { | |
4173 | u8 status[0x8]; | |
4174 | u8 reserved_0[0x18]; | |
4175 | ||
4176 | u8 syndrome[0x20]; | |
4177 | ||
4178 | u8 reserved_1[0x40]; | |
4179 | }; | |
4180 | ||
4181 | struct mlx5_ifc_modify_tis_in_bits { | |
4182 | u8 opcode[0x10]; | |
4183 | u8 reserved_0[0x10]; | |
4184 | ||
4185 | u8 reserved_1[0x10]; | |
4186 | u8 op_mod[0x10]; | |
4187 | ||
4188 | u8 reserved_2[0x8]; | |
4189 | u8 tisn[0x18]; | |
4190 | ||
4191 | u8 reserved_3[0x20]; | |
4192 | ||
4193 | u8 modify_bitmask[0x40]; | |
4194 | ||
4195 | u8 reserved_4[0x40]; | |
4196 | ||
4197 | struct mlx5_ifc_tisc_bits ctx; | |
4198 | }; | |
4199 | ||
d9eea403 | 4200 | struct mlx5_ifc_modify_tir_bitmask_bits { |
66189961 | 4201 | u8 reserved_0[0x20]; |
d9eea403 | 4202 | |
66189961 TT |
4203 | u8 reserved_1[0x1b]; |
4204 | u8 self_lb_en[0x1]; | |
4205 | u8 reserved_2[0x3]; | |
d9eea403 AS |
4206 | u8 lro[0x1]; |
4207 | }; | |
4208 | ||
e281682b SM |
4209 | struct mlx5_ifc_modify_tir_out_bits { |
4210 | u8 status[0x8]; | |
4211 | u8 reserved_0[0x18]; | |
4212 | ||
4213 | u8 syndrome[0x20]; | |
4214 | ||
4215 | u8 reserved_1[0x40]; | |
4216 | }; | |
4217 | ||
4218 | struct mlx5_ifc_modify_tir_in_bits { | |
4219 | u8 opcode[0x10]; | |
4220 | u8 reserved_0[0x10]; | |
4221 | ||
4222 | u8 reserved_1[0x10]; | |
4223 | u8 op_mod[0x10]; | |
4224 | ||
4225 | u8 reserved_2[0x8]; | |
4226 | u8 tirn[0x18]; | |
4227 | ||
4228 | u8 reserved_3[0x20]; | |
4229 | ||
d9eea403 | 4230 | struct mlx5_ifc_modify_tir_bitmask_bits bitmask; |
e281682b SM |
4231 | |
4232 | u8 reserved_4[0x40]; | |
4233 | ||
4234 | struct mlx5_ifc_tirc_bits ctx; | |
4235 | }; | |
4236 | ||
4237 | struct mlx5_ifc_modify_sq_out_bits { | |
4238 | u8 status[0x8]; | |
4239 | u8 reserved_0[0x18]; | |
4240 | ||
4241 | u8 syndrome[0x20]; | |
4242 | ||
4243 | u8 reserved_1[0x40]; | |
4244 | }; | |
4245 | ||
4246 | struct mlx5_ifc_modify_sq_in_bits { | |
4247 | u8 opcode[0x10]; | |
4248 | u8 reserved_0[0x10]; | |
4249 | ||
4250 | u8 reserved_1[0x10]; | |
4251 | u8 op_mod[0x10]; | |
4252 | ||
4253 | u8 sq_state[0x4]; | |
4254 | u8 reserved_2[0x4]; | |
4255 | u8 sqn[0x18]; | |
4256 | ||
4257 | u8 reserved_3[0x20]; | |
4258 | ||
4259 | u8 modify_bitmask[0x40]; | |
4260 | ||
4261 | u8 reserved_4[0x40]; | |
4262 | ||
4263 | struct mlx5_ifc_sqc_bits ctx; | |
4264 | }; | |
4265 | ||
4266 | struct mlx5_ifc_modify_rqt_out_bits { | |
4267 | u8 status[0x8]; | |
4268 | u8 reserved_0[0x18]; | |
4269 | ||
4270 | u8 syndrome[0x20]; | |
4271 | ||
4272 | u8 reserved_1[0x40]; | |
4273 | }; | |
4274 | ||
5c50368f AS |
4275 | struct mlx5_ifc_rqt_bitmask_bits { |
4276 | u8 reserved[0x20]; | |
4277 | ||
4278 | u8 reserved1[0x1f]; | |
4279 | u8 rqn_list[0x1]; | |
4280 | }; | |
4281 | ||
e281682b SM |
4282 | struct mlx5_ifc_modify_rqt_in_bits { |
4283 | u8 opcode[0x10]; | |
4284 | u8 reserved_0[0x10]; | |
4285 | ||
4286 | u8 reserved_1[0x10]; | |
4287 | u8 op_mod[0x10]; | |
4288 | ||
4289 | u8 reserved_2[0x8]; | |
4290 | u8 rqtn[0x18]; | |
4291 | ||
4292 | u8 reserved_3[0x20]; | |
4293 | ||
5c50368f | 4294 | struct mlx5_ifc_rqt_bitmask_bits bitmask; |
e281682b SM |
4295 | |
4296 | u8 reserved_4[0x40]; | |
4297 | ||
4298 | struct mlx5_ifc_rqtc_bits ctx; | |
4299 | }; | |
4300 | ||
4301 | struct mlx5_ifc_modify_rq_out_bits { | |
4302 | u8 status[0x8]; | |
4303 | u8 reserved_0[0x18]; | |
4304 | ||
4305 | u8 syndrome[0x20]; | |
4306 | ||
4307 | u8 reserved_1[0x40]; | |
4308 | }; | |
4309 | ||
4310 | struct mlx5_ifc_modify_rq_in_bits { | |
4311 | u8 opcode[0x10]; | |
4312 | u8 reserved_0[0x10]; | |
4313 | ||
4314 | u8 reserved_1[0x10]; | |
4315 | u8 op_mod[0x10]; | |
4316 | ||
4317 | u8 rq_state[0x4]; | |
4318 | u8 reserved_2[0x4]; | |
4319 | u8 rqn[0x18]; | |
4320 | ||
4321 | u8 reserved_3[0x20]; | |
4322 | ||
4323 | u8 modify_bitmask[0x40]; | |
4324 | ||
4325 | u8 reserved_4[0x40]; | |
4326 | ||
4327 | struct mlx5_ifc_rqc_bits ctx; | |
4328 | }; | |
4329 | ||
4330 | struct mlx5_ifc_modify_rmp_out_bits { | |
4331 | u8 status[0x8]; | |
4332 | u8 reserved_0[0x18]; | |
4333 | ||
4334 | u8 syndrome[0x20]; | |
4335 | ||
4336 | u8 reserved_1[0x40]; | |
4337 | }; | |
4338 | ||
01949d01 HA |
4339 | struct mlx5_ifc_rmp_bitmask_bits { |
4340 | u8 reserved[0x20]; | |
4341 | ||
4342 | u8 reserved1[0x1f]; | |
4343 | u8 lwm[0x1]; | |
4344 | }; | |
4345 | ||
e281682b SM |
4346 | struct mlx5_ifc_modify_rmp_in_bits { |
4347 | u8 opcode[0x10]; | |
4348 | u8 reserved_0[0x10]; | |
4349 | ||
4350 | u8 reserved_1[0x10]; | |
4351 | u8 op_mod[0x10]; | |
4352 | ||
4353 | u8 rmp_state[0x4]; | |
4354 | u8 reserved_2[0x4]; | |
4355 | u8 rmpn[0x18]; | |
4356 | ||
4357 | u8 reserved_3[0x20]; | |
4358 | ||
01949d01 | 4359 | struct mlx5_ifc_rmp_bitmask_bits bitmask; |
e281682b SM |
4360 | |
4361 | u8 reserved_4[0x40]; | |
4362 | ||
4363 | struct mlx5_ifc_rmpc_bits ctx; | |
4364 | }; | |
4365 | ||
4366 | struct mlx5_ifc_modify_nic_vport_context_out_bits { | |
4367 | u8 status[0x8]; | |
4368 | u8 reserved_0[0x18]; | |
4369 | ||
4370 | u8 syndrome[0x20]; | |
4371 | ||
4372 | u8 reserved_1[0x40]; | |
4373 | }; | |
4374 | ||
4375 | struct mlx5_ifc_modify_nic_vport_field_select_bits { | |
d82b7318 SM |
4376 | u8 reserved_0[0x19]; |
4377 | u8 mtu[0x1]; | |
4378 | u8 change_event[0x1]; | |
4379 | u8 promisc[0x1]; | |
e281682b SM |
4380 | u8 permanent_address[0x1]; |
4381 | u8 addresses_list[0x1]; | |
4382 | u8 roce_en[0x1]; | |
4383 | u8 reserved_1[0x1]; | |
4384 | }; | |
4385 | ||
4386 | struct mlx5_ifc_modify_nic_vport_context_in_bits { | |
4387 | u8 opcode[0x10]; | |
4388 | u8 reserved_0[0x10]; | |
4389 | ||
4390 | u8 reserved_1[0x10]; | |
4391 | u8 op_mod[0x10]; | |
4392 | ||
4393 | u8 other_vport[0x1]; | |
4394 | u8 reserved_2[0xf]; | |
4395 | u8 vport_number[0x10]; | |
4396 | ||
4397 | struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; | |
4398 | ||
4399 | u8 reserved_3[0x780]; | |
4400 | ||
4401 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
4402 | }; | |
4403 | ||
4404 | struct mlx5_ifc_modify_hca_vport_context_out_bits { | |
4405 | u8 status[0x8]; | |
4406 | u8 reserved_0[0x18]; | |
4407 | ||
4408 | u8 syndrome[0x20]; | |
4409 | ||
4410 | u8 reserved_1[0x40]; | |
4411 | }; | |
4412 | ||
4413 | struct mlx5_ifc_modify_hca_vport_context_in_bits { | |
4414 | u8 opcode[0x10]; | |
4415 | u8 reserved_0[0x10]; | |
4416 | ||
4417 | u8 reserved_1[0x10]; | |
4418 | u8 op_mod[0x10]; | |
4419 | ||
4420 | u8 other_vport[0x1]; | |
707c4602 MD |
4421 | u8 reserved_2[0xb]; |
4422 | u8 port_num[0x4]; | |
e281682b SM |
4423 | u8 vport_number[0x10]; |
4424 | ||
4425 | u8 reserved_3[0x20]; | |
4426 | ||
4427 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
4428 | }; | |
4429 | ||
4430 | struct mlx5_ifc_modify_cq_out_bits { | |
4431 | u8 status[0x8]; | |
4432 | u8 reserved_0[0x18]; | |
4433 | ||
4434 | u8 syndrome[0x20]; | |
4435 | ||
4436 | u8 reserved_1[0x40]; | |
4437 | }; | |
4438 | ||
4439 | enum { | |
4440 | MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, | |
4441 | MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, | |
4442 | }; | |
4443 | ||
4444 | struct mlx5_ifc_modify_cq_in_bits { | |
4445 | u8 opcode[0x10]; | |
4446 | u8 reserved_0[0x10]; | |
4447 | ||
4448 | u8 reserved_1[0x10]; | |
4449 | u8 op_mod[0x10]; | |
4450 | ||
4451 | u8 reserved_2[0x8]; | |
4452 | u8 cqn[0x18]; | |
4453 | ||
4454 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; | |
4455 | ||
4456 | struct mlx5_ifc_cqc_bits cq_context; | |
4457 | ||
4458 | u8 reserved_3[0x600]; | |
4459 | ||
4460 | u8 pas[0][0x40]; | |
4461 | }; | |
4462 | ||
4463 | struct mlx5_ifc_modify_cong_status_out_bits { | |
4464 | u8 status[0x8]; | |
4465 | u8 reserved_0[0x18]; | |
4466 | ||
4467 | u8 syndrome[0x20]; | |
4468 | ||
4469 | u8 reserved_1[0x40]; | |
4470 | }; | |
4471 | ||
4472 | struct mlx5_ifc_modify_cong_status_in_bits { | |
4473 | u8 opcode[0x10]; | |
4474 | u8 reserved_0[0x10]; | |
4475 | ||
4476 | u8 reserved_1[0x10]; | |
4477 | u8 op_mod[0x10]; | |
4478 | ||
4479 | u8 reserved_2[0x18]; | |
4480 | u8 priority[0x4]; | |
4481 | u8 cong_protocol[0x4]; | |
4482 | ||
4483 | u8 enable[0x1]; | |
4484 | u8 tag_enable[0x1]; | |
4485 | u8 reserved_3[0x1e]; | |
4486 | }; | |
4487 | ||
4488 | struct mlx5_ifc_modify_cong_params_out_bits { | |
4489 | u8 status[0x8]; | |
4490 | u8 reserved_0[0x18]; | |
4491 | ||
4492 | u8 syndrome[0x20]; | |
4493 | ||
4494 | u8 reserved_1[0x40]; | |
4495 | }; | |
4496 | ||
4497 | struct mlx5_ifc_modify_cong_params_in_bits { | |
4498 | u8 opcode[0x10]; | |
4499 | u8 reserved_0[0x10]; | |
4500 | ||
4501 | u8 reserved_1[0x10]; | |
4502 | u8 op_mod[0x10]; | |
4503 | ||
4504 | u8 reserved_2[0x1c]; | |
4505 | u8 cong_protocol[0x4]; | |
4506 | ||
4507 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; | |
4508 | ||
4509 | u8 reserved_3[0x80]; | |
4510 | ||
4511 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
4512 | }; | |
4513 | ||
4514 | struct mlx5_ifc_manage_pages_out_bits { | |
4515 | u8 status[0x8]; | |
4516 | u8 reserved_0[0x18]; | |
4517 | ||
4518 | u8 syndrome[0x20]; | |
4519 | ||
4520 | u8 output_num_entries[0x20]; | |
4521 | ||
4522 | u8 reserved_1[0x20]; | |
4523 | ||
4524 | u8 pas[0][0x40]; | |
4525 | }; | |
4526 | ||
4527 | enum { | |
4528 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, | |
4529 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, | |
4530 | MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, | |
4531 | }; | |
4532 | ||
4533 | struct mlx5_ifc_manage_pages_in_bits { | |
4534 | u8 opcode[0x10]; | |
4535 | u8 reserved_0[0x10]; | |
4536 | ||
4537 | u8 reserved_1[0x10]; | |
4538 | u8 op_mod[0x10]; | |
4539 | ||
4540 | u8 reserved_2[0x10]; | |
4541 | u8 function_id[0x10]; | |
4542 | ||
4543 | u8 input_num_entries[0x20]; | |
4544 | ||
4545 | u8 pas[0][0x40]; | |
4546 | }; | |
4547 | ||
4548 | struct mlx5_ifc_mad_ifc_out_bits { | |
4549 | u8 status[0x8]; | |
4550 | u8 reserved_0[0x18]; | |
4551 | ||
4552 | u8 syndrome[0x20]; | |
4553 | ||
4554 | u8 reserved_1[0x40]; | |
4555 | ||
4556 | u8 response_mad_packet[256][0x8]; | |
4557 | }; | |
4558 | ||
4559 | struct mlx5_ifc_mad_ifc_in_bits { | |
4560 | u8 opcode[0x10]; | |
4561 | u8 reserved_0[0x10]; | |
4562 | ||
4563 | u8 reserved_1[0x10]; | |
4564 | u8 op_mod[0x10]; | |
4565 | ||
4566 | u8 remote_lid[0x10]; | |
4567 | u8 reserved_2[0x8]; | |
4568 | u8 port[0x8]; | |
4569 | ||
4570 | u8 reserved_3[0x20]; | |
4571 | ||
4572 | u8 mad[256][0x8]; | |
4573 | }; | |
4574 | ||
4575 | struct mlx5_ifc_init_hca_out_bits { | |
4576 | u8 status[0x8]; | |
4577 | u8 reserved_0[0x18]; | |
4578 | ||
4579 | u8 syndrome[0x20]; | |
4580 | ||
4581 | u8 reserved_1[0x40]; | |
4582 | }; | |
4583 | ||
4584 | struct mlx5_ifc_init_hca_in_bits { | |
4585 | u8 opcode[0x10]; | |
4586 | u8 reserved_0[0x10]; | |
4587 | ||
4588 | u8 reserved_1[0x10]; | |
4589 | u8 op_mod[0x10]; | |
4590 | ||
4591 | u8 reserved_2[0x40]; | |
4592 | }; | |
4593 | ||
4594 | struct mlx5_ifc_init2rtr_qp_out_bits { | |
4595 | u8 status[0x8]; | |
4596 | u8 reserved_0[0x18]; | |
4597 | ||
4598 | u8 syndrome[0x20]; | |
4599 | ||
4600 | u8 reserved_1[0x40]; | |
4601 | }; | |
4602 | ||
4603 | struct mlx5_ifc_init2rtr_qp_in_bits { | |
4604 | u8 opcode[0x10]; | |
4605 | u8 reserved_0[0x10]; | |
4606 | ||
4607 | u8 reserved_1[0x10]; | |
4608 | u8 op_mod[0x10]; | |
4609 | ||
4610 | u8 reserved_2[0x8]; | |
4611 | u8 qpn[0x18]; | |
4612 | ||
4613 | u8 reserved_3[0x20]; | |
4614 | ||
4615 | u8 opt_param_mask[0x20]; | |
4616 | ||
4617 | u8 reserved_4[0x20]; | |
4618 | ||
4619 | struct mlx5_ifc_qpc_bits qpc; | |
4620 | ||
4621 | u8 reserved_5[0x80]; | |
4622 | }; | |
4623 | ||
4624 | struct mlx5_ifc_init2init_qp_out_bits { | |
4625 | u8 status[0x8]; | |
4626 | u8 reserved_0[0x18]; | |
4627 | ||
4628 | u8 syndrome[0x20]; | |
4629 | ||
4630 | u8 reserved_1[0x40]; | |
4631 | }; | |
4632 | ||
4633 | struct mlx5_ifc_init2init_qp_in_bits { | |
4634 | u8 opcode[0x10]; | |
4635 | u8 reserved_0[0x10]; | |
4636 | ||
4637 | u8 reserved_1[0x10]; | |
4638 | u8 op_mod[0x10]; | |
4639 | ||
4640 | u8 reserved_2[0x8]; | |
4641 | u8 qpn[0x18]; | |
4642 | ||
4643 | u8 reserved_3[0x20]; | |
4644 | ||
4645 | u8 opt_param_mask[0x20]; | |
4646 | ||
4647 | u8 reserved_4[0x20]; | |
4648 | ||
4649 | struct mlx5_ifc_qpc_bits qpc; | |
4650 | ||
4651 | u8 reserved_5[0x80]; | |
4652 | }; | |
4653 | ||
4654 | struct mlx5_ifc_get_dropped_packet_log_out_bits { | |
4655 | u8 status[0x8]; | |
4656 | u8 reserved_0[0x18]; | |
4657 | ||
4658 | u8 syndrome[0x20]; | |
4659 | ||
4660 | u8 reserved_1[0x40]; | |
4661 | ||
4662 | u8 packet_headers_log[128][0x8]; | |
4663 | ||
4664 | u8 packet_syndrome[64][0x8]; | |
4665 | }; | |
4666 | ||
4667 | struct mlx5_ifc_get_dropped_packet_log_in_bits { | |
4668 | u8 opcode[0x10]; | |
4669 | u8 reserved_0[0x10]; | |
4670 | ||
4671 | u8 reserved_1[0x10]; | |
4672 | u8 op_mod[0x10]; | |
4673 | ||
4674 | u8 reserved_2[0x40]; | |
4675 | }; | |
4676 | ||
4677 | struct mlx5_ifc_gen_eqe_in_bits { | |
4678 | u8 opcode[0x10]; | |
4679 | u8 reserved_0[0x10]; | |
4680 | ||
4681 | u8 reserved_1[0x10]; | |
4682 | u8 op_mod[0x10]; | |
4683 | ||
4684 | u8 reserved_2[0x18]; | |
4685 | u8 eq_number[0x8]; | |
4686 | ||
4687 | u8 reserved_3[0x20]; | |
4688 | ||
4689 | u8 eqe[64][0x8]; | |
4690 | }; | |
4691 | ||
4692 | struct mlx5_ifc_gen_eq_out_bits { | |
4693 | u8 status[0x8]; | |
4694 | u8 reserved_0[0x18]; | |
4695 | ||
4696 | u8 syndrome[0x20]; | |
4697 | ||
4698 | u8 reserved_1[0x40]; | |
4699 | }; | |
4700 | ||
4701 | struct mlx5_ifc_enable_hca_out_bits { | |
4702 | u8 status[0x8]; | |
4703 | u8 reserved_0[0x18]; | |
4704 | ||
4705 | u8 syndrome[0x20]; | |
4706 | ||
4707 | u8 reserved_1[0x20]; | |
4708 | }; | |
4709 | ||
4710 | struct mlx5_ifc_enable_hca_in_bits { | |
4711 | u8 opcode[0x10]; | |
4712 | u8 reserved_0[0x10]; | |
4713 | ||
4714 | u8 reserved_1[0x10]; | |
4715 | u8 op_mod[0x10]; | |
4716 | ||
4717 | u8 reserved_2[0x10]; | |
4718 | u8 function_id[0x10]; | |
4719 | ||
4720 | u8 reserved_3[0x20]; | |
4721 | }; | |
4722 | ||
4723 | struct mlx5_ifc_drain_dct_out_bits { | |
4724 | u8 status[0x8]; | |
4725 | u8 reserved_0[0x18]; | |
4726 | ||
4727 | u8 syndrome[0x20]; | |
4728 | ||
4729 | u8 reserved_1[0x40]; | |
4730 | }; | |
4731 | ||
4732 | struct mlx5_ifc_drain_dct_in_bits { | |
4733 | u8 opcode[0x10]; | |
4734 | u8 reserved_0[0x10]; | |
4735 | ||
4736 | u8 reserved_1[0x10]; | |
4737 | u8 op_mod[0x10]; | |
4738 | ||
4739 | u8 reserved_2[0x8]; | |
4740 | u8 dctn[0x18]; | |
4741 | ||
4742 | u8 reserved_3[0x20]; | |
4743 | }; | |
4744 | ||
4745 | struct mlx5_ifc_disable_hca_out_bits { | |
4746 | u8 status[0x8]; | |
4747 | u8 reserved_0[0x18]; | |
4748 | ||
4749 | u8 syndrome[0x20]; | |
4750 | ||
4751 | u8 reserved_1[0x20]; | |
4752 | }; | |
4753 | ||
4754 | struct mlx5_ifc_disable_hca_in_bits { | |
4755 | u8 opcode[0x10]; | |
4756 | u8 reserved_0[0x10]; | |
4757 | ||
4758 | u8 reserved_1[0x10]; | |
4759 | u8 op_mod[0x10]; | |
4760 | ||
4761 | u8 reserved_2[0x10]; | |
4762 | u8 function_id[0x10]; | |
4763 | ||
4764 | u8 reserved_3[0x20]; | |
4765 | }; | |
4766 | ||
4767 | struct mlx5_ifc_detach_from_mcg_out_bits { | |
4768 | u8 status[0x8]; | |
4769 | u8 reserved_0[0x18]; | |
4770 | ||
4771 | u8 syndrome[0x20]; | |
4772 | ||
4773 | u8 reserved_1[0x40]; | |
4774 | }; | |
4775 | ||
4776 | struct mlx5_ifc_detach_from_mcg_in_bits { | |
4777 | u8 opcode[0x10]; | |
4778 | u8 reserved_0[0x10]; | |
4779 | ||
4780 | u8 reserved_1[0x10]; | |
4781 | u8 op_mod[0x10]; | |
4782 | ||
4783 | u8 reserved_2[0x8]; | |
4784 | u8 qpn[0x18]; | |
4785 | ||
4786 | u8 reserved_3[0x20]; | |
4787 | ||
4788 | u8 multicast_gid[16][0x8]; | |
4789 | }; | |
4790 | ||
4791 | struct mlx5_ifc_destroy_xrc_srq_out_bits { | |
4792 | u8 status[0x8]; | |
4793 | u8 reserved_0[0x18]; | |
4794 | ||
4795 | u8 syndrome[0x20]; | |
4796 | ||
4797 | u8 reserved_1[0x40]; | |
4798 | }; | |
4799 | ||
4800 | struct mlx5_ifc_destroy_xrc_srq_in_bits { | |
4801 | u8 opcode[0x10]; | |
4802 | u8 reserved_0[0x10]; | |
4803 | ||
4804 | u8 reserved_1[0x10]; | |
4805 | u8 op_mod[0x10]; | |
4806 | ||
4807 | u8 reserved_2[0x8]; | |
4808 | u8 xrc_srqn[0x18]; | |
4809 | ||
4810 | u8 reserved_3[0x20]; | |
4811 | }; | |
4812 | ||
4813 | struct mlx5_ifc_destroy_tis_out_bits { | |
4814 | u8 status[0x8]; | |
4815 | u8 reserved_0[0x18]; | |
4816 | ||
4817 | u8 syndrome[0x20]; | |
4818 | ||
4819 | u8 reserved_1[0x40]; | |
4820 | }; | |
4821 | ||
4822 | struct mlx5_ifc_destroy_tis_in_bits { | |
4823 | u8 opcode[0x10]; | |
4824 | u8 reserved_0[0x10]; | |
4825 | ||
4826 | u8 reserved_1[0x10]; | |
4827 | u8 op_mod[0x10]; | |
4828 | ||
4829 | u8 reserved_2[0x8]; | |
4830 | u8 tisn[0x18]; | |
4831 | ||
4832 | u8 reserved_3[0x20]; | |
4833 | }; | |
4834 | ||
4835 | struct mlx5_ifc_destroy_tir_out_bits { | |
4836 | u8 status[0x8]; | |
4837 | u8 reserved_0[0x18]; | |
4838 | ||
4839 | u8 syndrome[0x20]; | |
4840 | ||
4841 | u8 reserved_1[0x40]; | |
4842 | }; | |
4843 | ||
4844 | struct mlx5_ifc_destroy_tir_in_bits { | |
4845 | u8 opcode[0x10]; | |
4846 | u8 reserved_0[0x10]; | |
4847 | ||
4848 | u8 reserved_1[0x10]; | |
4849 | u8 op_mod[0x10]; | |
4850 | ||
4851 | u8 reserved_2[0x8]; | |
4852 | u8 tirn[0x18]; | |
4853 | ||
4854 | u8 reserved_3[0x20]; | |
4855 | }; | |
4856 | ||
4857 | struct mlx5_ifc_destroy_srq_out_bits { | |
4858 | u8 status[0x8]; | |
4859 | u8 reserved_0[0x18]; | |
4860 | ||
4861 | u8 syndrome[0x20]; | |
4862 | ||
4863 | u8 reserved_1[0x40]; | |
4864 | }; | |
4865 | ||
4866 | struct mlx5_ifc_destroy_srq_in_bits { | |
4867 | u8 opcode[0x10]; | |
4868 | u8 reserved_0[0x10]; | |
4869 | ||
4870 | u8 reserved_1[0x10]; | |
4871 | u8 op_mod[0x10]; | |
4872 | ||
4873 | u8 reserved_2[0x8]; | |
4874 | u8 srqn[0x18]; | |
4875 | ||
4876 | u8 reserved_3[0x20]; | |
4877 | }; | |
4878 | ||
4879 | struct mlx5_ifc_destroy_sq_out_bits { | |
4880 | u8 status[0x8]; | |
4881 | u8 reserved_0[0x18]; | |
4882 | ||
4883 | u8 syndrome[0x20]; | |
4884 | ||
4885 | u8 reserved_1[0x40]; | |
4886 | }; | |
4887 | ||
4888 | struct mlx5_ifc_destroy_sq_in_bits { | |
4889 | u8 opcode[0x10]; | |
4890 | u8 reserved_0[0x10]; | |
4891 | ||
4892 | u8 reserved_1[0x10]; | |
4893 | u8 op_mod[0x10]; | |
4894 | ||
4895 | u8 reserved_2[0x8]; | |
4896 | u8 sqn[0x18]; | |
4897 | ||
4898 | u8 reserved_3[0x20]; | |
4899 | }; | |
4900 | ||
4901 | struct mlx5_ifc_destroy_rqt_out_bits { | |
4902 | u8 status[0x8]; | |
4903 | u8 reserved_0[0x18]; | |
4904 | ||
4905 | u8 syndrome[0x20]; | |
4906 | ||
4907 | u8 reserved_1[0x40]; | |
4908 | }; | |
4909 | ||
4910 | struct mlx5_ifc_destroy_rqt_in_bits { | |
4911 | u8 opcode[0x10]; | |
4912 | u8 reserved_0[0x10]; | |
4913 | ||
4914 | u8 reserved_1[0x10]; | |
4915 | u8 op_mod[0x10]; | |
4916 | ||
4917 | u8 reserved_2[0x8]; | |
4918 | u8 rqtn[0x18]; | |
4919 | ||
4920 | u8 reserved_3[0x20]; | |
4921 | }; | |
4922 | ||
4923 | struct mlx5_ifc_destroy_rq_out_bits { | |
4924 | u8 status[0x8]; | |
4925 | u8 reserved_0[0x18]; | |
4926 | ||
4927 | u8 syndrome[0x20]; | |
4928 | ||
4929 | u8 reserved_1[0x40]; | |
4930 | }; | |
4931 | ||
4932 | struct mlx5_ifc_destroy_rq_in_bits { | |
4933 | u8 opcode[0x10]; | |
4934 | u8 reserved_0[0x10]; | |
4935 | ||
4936 | u8 reserved_1[0x10]; | |
4937 | u8 op_mod[0x10]; | |
4938 | ||
4939 | u8 reserved_2[0x8]; | |
4940 | u8 rqn[0x18]; | |
4941 | ||
4942 | u8 reserved_3[0x20]; | |
4943 | }; | |
4944 | ||
4945 | struct mlx5_ifc_destroy_rmp_out_bits { | |
4946 | u8 status[0x8]; | |
4947 | u8 reserved_0[0x18]; | |
4948 | ||
4949 | u8 syndrome[0x20]; | |
4950 | ||
4951 | u8 reserved_1[0x40]; | |
4952 | }; | |
4953 | ||
4954 | struct mlx5_ifc_destroy_rmp_in_bits { | |
4955 | u8 opcode[0x10]; | |
4956 | u8 reserved_0[0x10]; | |
4957 | ||
4958 | u8 reserved_1[0x10]; | |
4959 | u8 op_mod[0x10]; | |
4960 | ||
4961 | u8 reserved_2[0x8]; | |
4962 | u8 rmpn[0x18]; | |
4963 | ||
4964 | u8 reserved_3[0x20]; | |
4965 | }; | |
4966 | ||
4967 | struct mlx5_ifc_destroy_qp_out_bits { | |
4968 | u8 status[0x8]; | |
4969 | u8 reserved_0[0x18]; | |
4970 | ||
4971 | u8 syndrome[0x20]; | |
4972 | ||
4973 | u8 reserved_1[0x40]; | |
4974 | }; | |
4975 | ||
4976 | struct mlx5_ifc_destroy_qp_in_bits { | |
4977 | u8 opcode[0x10]; | |
4978 | u8 reserved_0[0x10]; | |
4979 | ||
4980 | u8 reserved_1[0x10]; | |
4981 | u8 op_mod[0x10]; | |
4982 | ||
4983 | u8 reserved_2[0x8]; | |
4984 | u8 qpn[0x18]; | |
4985 | ||
4986 | u8 reserved_3[0x20]; | |
4987 | }; | |
4988 | ||
4989 | struct mlx5_ifc_destroy_psv_out_bits { | |
4990 | u8 status[0x8]; | |
4991 | u8 reserved_0[0x18]; | |
4992 | ||
4993 | u8 syndrome[0x20]; | |
4994 | ||
4995 | u8 reserved_1[0x40]; | |
4996 | }; | |
4997 | ||
4998 | struct mlx5_ifc_destroy_psv_in_bits { | |
4999 | u8 opcode[0x10]; | |
5000 | u8 reserved_0[0x10]; | |
5001 | ||
5002 | u8 reserved_1[0x10]; | |
5003 | u8 op_mod[0x10]; | |
5004 | ||
5005 | u8 reserved_2[0x8]; | |
5006 | u8 psvn[0x18]; | |
5007 | ||
5008 | u8 reserved_3[0x20]; | |
5009 | }; | |
5010 | ||
5011 | struct mlx5_ifc_destroy_mkey_out_bits { | |
5012 | u8 status[0x8]; | |
5013 | u8 reserved_0[0x18]; | |
5014 | ||
5015 | u8 syndrome[0x20]; | |
5016 | ||
5017 | u8 reserved_1[0x40]; | |
5018 | }; | |
5019 | ||
5020 | struct mlx5_ifc_destroy_mkey_in_bits { | |
5021 | u8 opcode[0x10]; | |
5022 | u8 reserved_0[0x10]; | |
5023 | ||
5024 | u8 reserved_1[0x10]; | |
5025 | u8 op_mod[0x10]; | |
5026 | ||
5027 | u8 reserved_2[0x8]; | |
5028 | u8 mkey_index[0x18]; | |
5029 | ||
5030 | u8 reserved_3[0x20]; | |
5031 | }; | |
5032 | ||
5033 | struct mlx5_ifc_destroy_flow_table_out_bits { | |
5034 | u8 status[0x8]; | |
5035 | u8 reserved_0[0x18]; | |
5036 | ||
5037 | u8 syndrome[0x20]; | |
5038 | ||
5039 | u8 reserved_1[0x40]; | |
5040 | }; | |
5041 | ||
5042 | struct mlx5_ifc_destroy_flow_table_in_bits { | |
5043 | u8 opcode[0x10]; | |
5044 | u8 reserved_0[0x10]; | |
5045 | ||
5046 | u8 reserved_1[0x10]; | |
5047 | u8 op_mod[0x10]; | |
5048 | ||
5049 | u8 reserved_2[0x40]; | |
5050 | ||
5051 | u8 table_type[0x8]; | |
5052 | u8 reserved_3[0x18]; | |
5053 | ||
5054 | u8 reserved_4[0x8]; | |
5055 | u8 table_id[0x18]; | |
5056 | ||
5057 | u8 reserved_5[0x140]; | |
5058 | }; | |
5059 | ||
5060 | struct mlx5_ifc_destroy_flow_group_out_bits { | |
5061 | u8 status[0x8]; | |
5062 | u8 reserved_0[0x18]; | |
5063 | ||
5064 | u8 syndrome[0x20]; | |
5065 | ||
5066 | u8 reserved_1[0x40]; | |
5067 | }; | |
5068 | ||
5069 | struct mlx5_ifc_destroy_flow_group_in_bits { | |
5070 | u8 opcode[0x10]; | |
5071 | u8 reserved_0[0x10]; | |
5072 | ||
5073 | u8 reserved_1[0x10]; | |
5074 | u8 op_mod[0x10]; | |
5075 | ||
5076 | u8 reserved_2[0x40]; | |
5077 | ||
5078 | u8 table_type[0x8]; | |
5079 | u8 reserved_3[0x18]; | |
5080 | ||
5081 | u8 reserved_4[0x8]; | |
5082 | u8 table_id[0x18]; | |
5083 | ||
5084 | u8 group_id[0x20]; | |
5085 | ||
5086 | u8 reserved_5[0x120]; | |
5087 | }; | |
5088 | ||
5089 | struct mlx5_ifc_destroy_eq_out_bits { | |
5090 | u8 status[0x8]; | |
5091 | u8 reserved_0[0x18]; | |
5092 | ||
5093 | u8 syndrome[0x20]; | |
5094 | ||
5095 | u8 reserved_1[0x40]; | |
5096 | }; | |
5097 | ||
5098 | struct mlx5_ifc_destroy_eq_in_bits { | |
5099 | u8 opcode[0x10]; | |
5100 | u8 reserved_0[0x10]; | |
5101 | ||
5102 | u8 reserved_1[0x10]; | |
5103 | u8 op_mod[0x10]; | |
5104 | ||
5105 | u8 reserved_2[0x18]; | |
5106 | u8 eq_number[0x8]; | |
5107 | ||
5108 | u8 reserved_3[0x20]; | |
5109 | }; | |
5110 | ||
5111 | struct mlx5_ifc_destroy_dct_out_bits { | |
5112 | u8 status[0x8]; | |
5113 | u8 reserved_0[0x18]; | |
5114 | ||
5115 | u8 syndrome[0x20]; | |
5116 | ||
5117 | u8 reserved_1[0x40]; | |
5118 | }; | |
5119 | ||
5120 | struct mlx5_ifc_destroy_dct_in_bits { | |
5121 | u8 opcode[0x10]; | |
5122 | u8 reserved_0[0x10]; | |
5123 | ||
5124 | u8 reserved_1[0x10]; | |
5125 | u8 op_mod[0x10]; | |
5126 | ||
5127 | u8 reserved_2[0x8]; | |
5128 | u8 dctn[0x18]; | |
5129 | ||
5130 | u8 reserved_3[0x20]; | |
5131 | }; | |
5132 | ||
5133 | struct mlx5_ifc_destroy_cq_out_bits { | |
5134 | u8 status[0x8]; | |
5135 | u8 reserved_0[0x18]; | |
5136 | ||
5137 | u8 syndrome[0x20]; | |
5138 | ||
5139 | u8 reserved_1[0x40]; | |
5140 | }; | |
5141 | ||
5142 | struct mlx5_ifc_destroy_cq_in_bits { | |
5143 | u8 opcode[0x10]; | |
5144 | u8 reserved_0[0x10]; | |
5145 | ||
5146 | u8 reserved_1[0x10]; | |
5147 | u8 op_mod[0x10]; | |
5148 | ||
5149 | u8 reserved_2[0x8]; | |
5150 | u8 cqn[0x18]; | |
5151 | ||
5152 | u8 reserved_3[0x20]; | |
5153 | }; | |
5154 | ||
5155 | struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { | |
5156 | u8 status[0x8]; | |
5157 | u8 reserved_0[0x18]; | |
5158 | ||
5159 | u8 syndrome[0x20]; | |
5160 | ||
5161 | u8 reserved_1[0x40]; | |
5162 | }; | |
5163 | ||
5164 | struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { | |
5165 | u8 opcode[0x10]; | |
5166 | u8 reserved_0[0x10]; | |
5167 | ||
5168 | u8 reserved_1[0x10]; | |
5169 | u8 op_mod[0x10]; | |
5170 | ||
5171 | u8 reserved_2[0x20]; | |
5172 | ||
5173 | u8 reserved_3[0x10]; | |
5174 | u8 vxlan_udp_port[0x10]; | |
5175 | }; | |
5176 | ||
5177 | struct mlx5_ifc_delete_l2_table_entry_out_bits { | |
5178 | u8 status[0x8]; | |
5179 | u8 reserved_0[0x18]; | |
5180 | ||
5181 | u8 syndrome[0x20]; | |
5182 | ||
5183 | u8 reserved_1[0x40]; | |
5184 | }; | |
5185 | ||
5186 | struct mlx5_ifc_delete_l2_table_entry_in_bits { | |
5187 | u8 opcode[0x10]; | |
5188 | u8 reserved_0[0x10]; | |
5189 | ||
5190 | u8 reserved_1[0x10]; | |
5191 | u8 op_mod[0x10]; | |
5192 | ||
5193 | u8 reserved_2[0x60]; | |
5194 | ||
5195 | u8 reserved_3[0x8]; | |
5196 | u8 table_index[0x18]; | |
5197 | ||
5198 | u8 reserved_4[0x140]; | |
5199 | }; | |
5200 | ||
5201 | struct mlx5_ifc_delete_fte_out_bits { | |
5202 | u8 status[0x8]; | |
5203 | u8 reserved_0[0x18]; | |
5204 | ||
5205 | u8 syndrome[0x20]; | |
5206 | ||
5207 | u8 reserved_1[0x40]; | |
5208 | }; | |
5209 | ||
5210 | struct mlx5_ifc_delete_fte_in_bits { | |
5211 | u8 opcode[0x10]; | |
5212 | u8 reserved_0[0x10]; | |
5213 | ||
5214 | u8 reserved_1[0x10]; | |
5215 | u8 op_mod[0x10]; | |
5216 | ||
5217 | u8 reserved_2[0x40]; | |
5218 | ||
5219 | u8 table_type[0x8]; | |
5220 | u8 reserved_3[0x18]; | |
5221 | ||
5222 | u8 reserved_4[0x8]; | |
5223 | u8 table_id[0x18]; | |
5224 | ||
5225 | u8 reserved_5[0x40]; | |
5226 | ||
5227 | u8 flow_index[0x20]; | |
5228 | ||
5229 | u8 reserved_6[0xe0]; | |
5230 | }; | |
5231 | ||
5232 | struct mlx5_ifc_dealloc_xrcd_out_bits { | |
5233 | u8 status[0x8]; | |
5234 | u8 reserved_0[0x18]; | |
5235 | ||
5236 | u8 syndrome[0x20]; | |
5237 | ||
5238 | u8 reserved_1[0x40]; | |
5239 | }; | |
5240 | ||
5241 | struct mlx5_ifc_dealloc_xrcd_in_bits { | |
5242 | u8 opcode[0x10]; | |
5243 | u8 reserved_0[0x10]; | |
5244 | ||
5245 | u8 reserved_1[0x10]; | |
5246 | u8 op_mod[0x10]; | |
5247 | ||
5248 | u8 reserved_2[0x8]; | |
5249 | u8 xrcd[0x18]; | |
5250 | ||
5251 | u8 reserved_3[0x20]; | |
5252 | }; | |
5253 | ||
5254 | struct mlx5_ifc_dealloc_uar_out_bits { | |
5255 | u8 status[0x8]; | |
5256 | u8 reserved_0[0x18]; | |
5257 | ||
5258 | u8 syndrome[0x20]; | |
5259 | ||
5260 | u8 reserved_1[0x40]; | |
5261 | }; | |
5262 | ||
5263 | struct mlx5_ifc_dealloc_uar_in_bits { | |
5264 | u8 opcode[0x10]; | |
5265 | u8 reserved_0[0x10]; | |
5266 | ||
5267 | u8 reserved_1[0x10]; | |
5268 | u8 op_mod[0x10]; | |
5269 | ||
5270 | u8 reserved_2[0x8]; | |
5271 | u8 uar[0x18]; | |
5272 | ||
5273 | u8 reserved_3[0x20]; | |
5274 | }; | |
5275 | ||
5276 | struct mlx5_ifc_dealloc_transport_domain_out_bits { | |
5277 | u8 status[0x8]; | |
5278 | u8 reserved_0[0x18]; | |
5279 | ||
5280 | u8 syndrome[0x20]; | |
5281 | ||
5282 | u8 reserved_1[0x40]; | |
5283 | }; | |
5284 | ||
5285 | struct mlx5_ifc_dealloc_transport_domain_in_bits { | |
5286 | u8 opcode[0x10]; | |
5287 | u8 reserved_0[0x10]; | |
5288 | ||
5289 | u8 reserved_1[0x10]; | |
5290 | u8 op_mod[0x10]; | |
5291 | ||
5292 | u8 reserved_2[0x8]; | |
5293 | u8 transport_domain[0x18]; | |
5294 | ||
5295 | u8 reserved_3[0x20]; | |
5296 | }; | |
5297 | ||
5298 | struct mlx5_ifc_dealloc_q_counter_out_bits { | |
5299 | u8 status[0x8]; | |
5300 | u8 reserved_0[0x18]; | |
5301 | ||
5302 | u8 syndrome[0x20]; | |
5303 | ||
5304 | u8 reserved_1[0x40]; | |
5305 | }; | |
5306 | ||
5307 | struct mlx5_ifc_dealloc_q_counter_in_bits { | |
5308 | u8 opcode[0x10]; | |
5309 | u8 reserved_0[0x10]; | |
5310 | ||
5311 | u8 reserved_1[0x10]; | |
5312 | u8 op_mod[0x10]; | |
5313 | ||
5314 | u8 reserved_2[0x18]; | |
5315 | u8 counter_set_id[0x8]; | |
5316 | ||
5317 | u8 reserved_3[0x20]; | |
5318 | }; | |
5319 | ||
5320 | struct mlx5_ifc_dealloc_pd_out_bits { | |
5321 | u8 status[0x8]; | |
5322 | u8 reserved_0[0x18]; | |
5323 | ||
5324 | u8 syndrome[0x20]; | |
5325 | ||
5326 | u8 reserved_1[0x40]; | |
5327 | }; | |
5328 | ||
5329 | struct mlx5_ifc_dealloc_pd_in_bits { | |
5330 | u8 opcode[0x10]; | |
5331 | u8 reserved_0[0x10]; | |
5332 | ||
5333 | u8 reserved_1[0x10]; | |
5334 | u8 op_mod[0x10]; | |
5335 | ||
5336 | u8 reserved_2[0x8]; | |
5337 | u8 pd[0x18]; | |
5338 | ||
5339 | u8 reserved_3[0x20]; | |
5340 | }; | |
5341 | ||
5342 | struct mlx5_ifc_create_xrc_srq_out_bits { | |
5343 | u8 status[0x8]; | |
5344 | u8 reserved_0[0x18]; | |
5345 | ||
5346 | u8 syndrome[0x20]; | |
5347 | ||
5348 | u8 reserved_1[0x8]; | |
5349 | u8 xrc_srqn[0x18]; | |
5350 | ||
5351 | u8 reserved_2[0x20]; | |
5352 | }; | |
5353 | ||
5354 | struct mlx5_ifc_create_xrc_srq_in_bits { | |
5355 | u8 opcode[0x10]; | |
5356 | u8 reserved_0[0x10]; | |
5357 | ||
5358 | u8 reserved_1[0x10]; | |
5359 | u8 op_mod[0x10]; | |
5360 | ||
5361 | u8 reserved_2[0x40]; | |
5362 | ||
5363 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
5364 | ||
5365 | u8 reserved_3[0x600]; | |
5366 | ||
5367 | u8 pas[0][0x40]; | |
5368 | }; | |
5369 | ||
5370 | struct mlx5_ifc_create_tis_out_bits { | |
5371 | u8 status[0x8]; | |
5372 | u8 reserved_0[0x18]; | |
5373 | ||
5374 | u8 syndrome[0x20]; | |
5375 | ||
5376 | u8 reserved_1[0x8]; | |
5377 | u8 tisn[0x18]; | |
5378 | ||
5379 | u8 reserved_2[0x20]; | |
5380 | }; | |
5381 | ||
5382 | struct mlx5_ifc_create_tis_in_bits { | |
5383 | u8 opcode[0x10]; | |
5384 | u8 reserved_0[0x10]; | |
5385 | ||
5386 | u8 reserved_1[0x10]; | |
5387 | u8 op_mod[0x10]; | |
5388 | ||
5389 | u8 reserved_2[0xc0]; | |
5390 | ||
5391 | struct mlx5_ifc_tisc_bits ctx; | |
5392 | }; | |
5393 | ||
5394 | struct mlx5_ifc_create_tir_out_bits { | |
5395 | u8 status[0x8]; | |
5396 | u8 reserved_0[0x18]; | |
5397 | ||
5398 | u8 syndrome[0x20]; | |
5399 | ||
5400 | u8 reserved_1[0x8]; | |
5401 | u8 tirn[0x18]; | |
5402 | ||
5403 | u8 reserved_2[0x20]; | |
5404 | }; | |
5405 | ||
5406 | struct mlx5_ifc_create_tir_in_bits { | |
5407 | u8 opcode[0x10]; | |
5408 | u8 reserved_0[0x10]; | |
5409 | ||
5410 | u8 reserved_1[0x10]; | |
5411 | u8 op_mod[0x10]; | |
5412 | ||
5413 | u8 reserved_2[0xc0]; | |
5414 | ||
5415 | struct mlx5_ifc_tirc_bits ctx; | |
5416 | }; | |
5417 | ||
5418 | struct mlx5_ifc_create_srq_out_bits { | |
5419 | u8 status[0x8]; | |
5420 | u8 reserved_0[0x18]; | |
5421 | ||
5422 | u8 syndrome[0x20]; | |
5423 | ||
5424 | u8 reserved_1[0x8]; | |
5425 | u8 srqn[0x18]; | |
5426 | ||
5427 | u8 reserved_2[0x20]; | |
5428 | }; | |
5429 | ||
5430 | struct mlx5_ifc_create_srq_in_bits { | |
5431 | u8 opcode[0x10]; | |
5432 | u8 reserved_0[0x10]; | |
5433 | ||
5434 | u8 reserved_1[0x10]; | |
5435 | u8 op_mod[0x10]; | |
5436 | ||
5437 | u8 reserved_2[0x40]; | |
5438 | ||
5439 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
5440 | ||
5441 | u8 reserved_3[0x600]; | |
5442 | ||
5443 | u8 pas[0][0x40]; | |
5444 | }; | |
5445 | ||
5446 | struct mlx5_ifc_create_sq_out_bits { | |
5447 | u8 status[0x8]; | |
5448 | u8 reserved_0[0x18]; | |
5449 | ||
5450 | u8 syndrome[0x20]; | |
5451 | ||
5452 | u8 reserved_1[0x8]; | |
5453 | u8 sqn[0x18]; | |
5454 | ||
5455 | u8 reserved_2[0x20]; | |
5456 | }; | |
5457 | ||
5458 | struct mlx5_ifc_create_sq_in_bits { | |
5459 | u8 opcode[0x10]; | |
5460 | u8 reserved_0[0x10]; | |
5461 | ||
5462 | u8 reserved_1[0x10]; | |
5463 | u8 op_mod[0x10]; | |
5464 | ||
5465 | u8 reserved_2[0xc0]; | |
5466 | ||
5467 | struct mlx5_ifc_sqc_bits ctx; | |
5468 | }; | |
5469 | ||
5470 | struct mlx5_ifc_create_rqt_out_bits { | |
5471 | u8 status[0x8]; | |
5472 | u8 reserved_0[0x18]; | |
5473 | ||
5474 | u8 syndrome[0x20]; | |
5475 | ||
5476 | u8 reserved_1[0x8]; | |
5477 | u8 rqtn[0x18]; | |
5478 | ||
5479 | u8 reserved_2[0x20]; | |
5480 | }; | |
5481 | ||
5482 | struct mlx5_ifc_create_rqt_in_bits { | |
5483 | u8 opcode[0x10]; | |
5484 | u8 reserved_0[0x10]; | |
5485 | ||
5486 | u8 reserved_1[0x10]; | |
5487 | u8 op_mod[0x10]; | |
5488 | ||
5489 | u8 reserved_2[0xc0]; | |
5490 | ||
5491 | struct mlx5_ifc_rqtc_bits rqt_context; | |
5492 | }; | |
5493 | ||
5494 | struct mlx5_ifc_create_rq_out_bits { | |
5495 | u8 status[0x8]; | |
5496 | u8 reserved_0[0x18]; | |
5497 | ||
5498 | u8 syndrome[0x20]; | |
5499 | ||
5500 | u8 reserved_1[0x8]; | |
5501 | u8 rqn[0x18]; | |
5502 | ||
5503 | u8 reserved_2[0x20]; | |
5504 | }; | |
5505 | ||
5506 | struct mlx5_ifc_create_rq_in_bits { | |
5507 | u8 opcode[0x10]; | |
5508 | u8 reserved_0[0x10]; | |
5509 | ||
5510 | u8 reserved_1[0x10]; | |
5511 | u8 op_mod[0x10]; | |
5512 | ||
5513 | u8 reserved_2[0xc0]; | |
5514 | ||
5515 | struct mlx5_ifc_rqc_bits ctx; | |
5516 | }; | |
5517 | ||
5518 | struct mlx5_ifc_create_rmp_out_bits { | |
5519 | u8 status[0x8]; | |
5520 | u8 reserved_0[0x18]; | |
5521 | ||
5522 | u8 syndrome[0x20]; | |
5523 | ||
5524 | u8 reserved_1[0x8]; | |
5525 | u8 rmpn[0x18]; | |
5526 | ||
5527 | u8 reserved_2[0x20]; | |
5528 | }; | |
5529 | ||
5530 | struct mlx5_ifc_create_rmp_in_bits { | |
5531 | u8 opcode[0x10]; | |
5532 | u8 reserved_0[0x10]; | |
5533 | ||
5534 | u8 reserved_1[0x10]; | |
5535 | u8 op_mod[0x10]; | |
5536 | ||
5537 | u8 reserved_2[0xc0]; | |
5538 | ||
5539 | struct mlx5_ifc_rmpc_bits ctx; | |
5540 | }; | |
5541 | ||
5542 | struct mlx5_ifc_create_qp_out_bits { | |
5543 | u8 status[0x8]; | |
5544 | u8 reserved_0[0x18]; | |
5545 | ||
5546 | u8 syndrome[0x20]; | |
5547 | ||
5548 | u8 reserved_1[0x8]; | |
5549 | u8 qpn[0x18]; | |
5550 | ||
5551 | u8 reserved_2[0x20]; | |
5552 | }; | |
5553 | ||
5554 | struct mlx5_ifc_create_qp_in_bits { | |
5555 | u8 opcode[0x10]; | |
5556 | u8 reserved_0[0x10]; | |
5557 | ||
5558 | u8 reserved_1[0x10]; | |
5559 | u8 op_mod[0x10]; | |
5560 | ||
5561 | u8 reserved_2[0x40]; | |
5562 | ||
5563 | u8 opt_param_mask[0x20]; | |
5564 | ||
5565 | u8 reserved_3[0x20]; | |
5566 | ||
5567 | struct mlx5_ifc_qpc_bits qpc; | |
5568 | ||
5569 | u8 reserved_4[0x80]; | |
5570 | ||
5571 | u8 pas[0][0x40]; | |
5572 | }; | |
5573 | ||
5574 | struct mlx5_ifc_create_psv_out_bits { | |
5575 | u8 status[0x8]; | |
5576 | u8 reserved_0[0x18]; | |
5577 | ||
5578 | u8 syndrome[0x20]; | |
5579 | ||
5580 | u8 reserved_1[0x40]; | |
5581 | ||
5582 | u8 reserved_2[0x8]; | |
5583 | u8 psv0_index[0x18]; | |
5584 | ||
5585 | u8 reserved_3[0x8]; | |
5586 | u8 psv1_index[0x18]; | |
5587 | ||
5588 | u8 reserved_4[0x8]; | |
5589 | u8 psv2_index[0x18]; | |
5590 | ||
5591 | u8 reserved_5[0x8]; | |
5592 | u8 psv3_index[0x18]; | |
5593 | }; | |
5594 | ||
5595 | struct mlx5_ifc_create_psv_in_bits { | |
5596 | u8 opcode[0x10]; | |
5597 | u8 reserved_0[0x10]; | |
5598 | ||
5599 | u8 reserved_1[0x10]; | |
5600 | u8 op_mod[0x10]; | |
5601 | ||
5602 | u8 num_psv[0x4]; | |
5603 | u8 reserved_2[0x4]; | |
5604 | u8 pd[0x18]; | |
5605 | ||
5606 | u8 reserved_3[0x20]; | |
5607 | }; | |
5608 | ||
5609 | struct mlx5_ifc_create_mkey_out_bits { | |
5610 | u8 status[0x8]; | |
5611 | u8 reserved_0[0x18]; | |
5612 | ||
5613 | u8 syndrome[0x20]; | |
5614 | ||
5615 | u8 reserved_1[0x8]; | |
5616 | u8 mkey_index[0x18]; | |
5617 | ||
5618 | u8 reserved_2[0x20]; | |
5619 | }; | |
5620 | ||
5621 | struct mlx5_ifc_create_mkey_in_bits { | |
5622 | u8 opcode[0x10]; | |
5623 | u8 reserved_0[0x10]; | |
5624 | ||
5625 | u8 reserved_1[0x10]; | |
5626 | u8 op_mod[0x10]; | |
5627 | ||
5628 | u8 reserved_2[0x20]; | |
5629 | ||
5630 | u8 pg_access[0x1]; | |
5631 | u8 reserved_3[0x1f]; | |
5632 | ||
5633 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
5634 | ||
5635 | u8 reserved_4[0x80]; | |
5636 | ||
5637 | u8 translations_octword_actual_size[0x20]; | |
5638 | ||
5639 | u8 reserved_5[0x560]; | |
5640 | ||
5641 | u8 klm_pas_mtt[0][0x20]; | |
5642 | }; | |
5643 | ||
5644 | struct mlx5_ifc_create_flow_table_out_bits { | |
5645 | u8 status[0x8]; | |
5646 | u8 reserved_0[0x18]; | |
5647 | ||
5648 | u8 syndrome[0x20]; | |
5649 | ||
5650 | u8 reserved_1[0x8]; | |
5651 | u8 table_id[0x18]; | |
5652 | ||
5653 | u8 reserved_2[0x20]; | |
5654 | }; | |
5655 | ||
5656 | struct mlx5_ifc_create_flow_table_in_bits { | |
5657 | u8 opcode[0x10]; | |
5658 | u8 reserved_0[0x10]; | |
5659 | ||
5660 | u8 reserved_1[0x10]; | |
5661 | u8 op_mod[0x10]; | |
5662 | ||
5663 | u8 reserved_2[0x40]; | |
5664 | ||
5665 | u8 table_type[0x8]; | |
5666 | u8 reserved_3[0x18]; | |
5667 | ||
5668 | u8 reserved_4[0x20]; | |
5669 | ||
5670 | u8 reserved_5[0x8]; | |
5671 | u8 level[0x8]; | |
5672 | u8 reserved_6[0x8]; | |
5673 | u8 log_size[0x8]; | |
5674 | ||
5675 | u8 reserved_7[0x120]; | |
5676 | }; | |
5677 | ||
5678 | struct mlx5_ifc_create_flow_group_out_bits { | |
5679 | u8 status[0x8]; | |
5680 | u8 reserved_0[0x18]; | |
5681 | ||
5682 | u8 syndrome[0x20]; | |
5683 | ||
5684 | u8 reserved_1[0x8]; | |
5685 | u8 group_id[0x18]; | |
5686 | ||
5687 | u8 reserved_2[0x20]; | |
5688 | }; | |
5689 | ||
5690 | enum { | |
5691 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
5692 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
5693 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
5694 | }; | |
5695 | ||
5696 | struct mlx5_ifc_create_flow_group_in_bits { | |
5697 | u8 opcode[0x10]; | |
5698 | u8 reserved_0[0x10]; | |
5699 | ||
5700 | u8 reserved_1[0x10]; | |
5701 | u8 op_mod[0x10]; | |
5702 | ||
5703 | u8 reserved_2[0x40]; | |
5704 | ||
5705 | u8 table_type[0x8]; | |
5706 | u8 reserved_3[0x18]; | |
5707 | ||
5708 | u8 reserved_4[0x8]; | |
5709 | u8 table_id[0x18]; | |
5710 | ||
5711 | u8 reserved_5[0x20]; | |
5712 | ||
5713 | u8 start_flow_index[0x20]; | |
5714 | ||
5715 | u8 reserved_6[0x20]; | |
5716 | ||
5717 | u8 end_flow_index[0x20]; | |
5718 | ||
5719 | u8 reserved_7[0xa0]; | |
5720 | ||
5721 | u8 reserved_8[0x18]; | |
5722 | u8 match_criteria_enable[0x8]; | |
5723 | ||
5724 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
5725 | ||
5726 | u8 reserved_9[0xe00]; | |
5727 | }; | |
5728 | ||
5729 | struct mlx5_ifc_create_eq_out_bits { | |
5730 | u8 status[0x8]; | |
5731 | u8 reserved_0[0x18]; | |
5732 | ||
5733 | u8 syndrome[0x20]; | |
5734 | ||
5735 | u8 reserved_1[0x18]; | |
5736 | u8 eq_number[0x8]; | |
5737 | ||
5738 | u8 reserved_2[0x20]; | |
5739 | }; | |
5740 | ||
5741 | struct mlx5_ifc_create_eq_in_bits { | |
5742 | u8 opcode[0x10]; | |
5743 | u8 reserved_0[0x10]; | |
5744 | ||
5745 | u8 reserved_1[0x10]; | |
5746 | u8 op_mod[0x10]; | |
5747 | ||
5748 | u8 reserved_2[0x40]; | |
5749 | ||
5750 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
5751 | ||
5752 | u8 reserved_3[0x40]; | |
5753 | ||
5754 | u8 event_bitmask[0x40]; | |
5755 | ||
5756 | u8 reserved_4[0x580]; | |
5757 | ||
5758 | u8 pas[0][0x40]; | |
5759 | }; | |
5760 | ||
5761 | struct mlx5_ifc_create_dct_out_bits { | |
5762 | u8 status[0x8]; | |
5763 | u8 reserved_0[0x18]; | |
5764 | ||
5765 | u8 syndrome[0x20]; | |
5766 | ||
5767 | u8 reserved_1[0x8]; | |
5768 | u8 dctn[0x18]; | |
5769 | ||
5770 | u8 reserved_2[0x20]; | |
5771 | }; | |
5772 | ||
5773 | struct mlx5_ifc_create_dct_in_bits { | |
5774 | u8 opcode[0x10]; | |
5775 | u8 reserved_0[0x10]; | |
5776 | ||
5777 | u8 reserved_1[0x10]; | |
5778 | u8 op_mod[0x10]; | |
5779 | ||
5780 | u8 reserved_2[0x40]; | |
5781 | ||
5782 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
5783 | ||
5784 | u8 reserved_3[0x180]; | |
5785 | }; | |
5786 | ||
5787 | struct mlx5_ifc_create_cq_out_bits { | |
5788 | u8 status[0x8]; | |
5789 | u8 reserved_0[0x18]; | |
5790 | ||
5791 | u8 syndrome[0x20]; | |
5792 | ||
5793 | u8 reserved_1[0x8]; | |
5794 | u8 cqn[0x18]; | |
5795 | ||
5796 | u8 reserved_2[0x20]; | |
5797 | }; | |
5798 | ||
5799 | struct mlx5_ifc_create_cq_in_bits { | |
5800 | u8 opcode[0x10]; | |
5801 | u8 reserved_0[0x10]; | |
5802 | ||
5803 | u8 reserved_1[0x10]; | |
5804 | u8 op_mod[0x10]; | |
5805 | ||
5806 | u8 reserved_2[0x40]; | |
5807 | ||
5808 | struct mlx5_ifc_cqc_bits cq_context; | |
5809 | ||
5810 | u8 reserved_3[0x600]; | |
5811 | ||
5812 | u8 pas[0][0x40]; | |
5813 | }; | |
5814 | ||
5815 | struct mlx5_ifc_config_int_moderation_out_bits { | |
5816 | u8 status[0x8]; | |
5817 | u8 reserved_0[0x18]; | |
5818 | ||
5819 | u8 syndrome[0x20]; | |
5820 | ||
5821 | u8 reserved_1[0x4]; | |
5822 | u8 min_delay[0xc]; | |
5823 | u8 int_vector[0x10]; | |
5824 | ||
5825 | u8 reserved_2[0x20]; | |
5826 | }; | |
5827 | ||
5828 | enum { | |
5829 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, | |
5830 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, | |
5831 | }; | |
5832 | ||
5833 | struct mlx5_ifc_config_int_moderation_in_bits { | |
5834 | u8 opcode[0x10]; | |
5835 | u8 reserved_0[0x10]; | |
5836 | ||
5837 | u8 reserved_1[0x10]; | |
5838 | u8 op_mod[0x10]; | |
5839 | ||
5840 | u8 reserved_2[0x4]; | |
5841 | u8 min_delay[0xc]; | |
5842 | u8 int_vector[0x10]; | |
5843 | ||
5844 | u8 reserved_3[0x20]; | |
5845 | }; | |
5846 | ||
5847 | struct mlx5_ifc_attach_to_mcg_out_bits { | |
5848 | u8 status[0x8]; | |
5849 | u8 reserved_0[0x18]; | |
5850 | ||
5851 | u8 syndrome[0x20]; | |
5852 | ||
5853 | u8 reserved_1[0x40]; | |
5854 | }; | |
5855 | ||
5856 | struct mlx5_ifc_attach_to_mcg_in_bits { | |
5857 | u8 opcode[0x10]; | |
5858 | u8 reserved_0[0x10]; | |
5859 | ||
5860 | u8 reserved_1[0x10]; | |
5861 | u8 op_mod[0x10]; | |
5862 | ||
5863 | u8 reserved_2[0x8]; | |
5864 | u8 qpn[0x18]; | |
5865 | ||
5866 | u8 reserved_3[0x20]; | |
5867 | ||
5868 | u8 multicast_gid[16][0x8]; | |
5869 | }; | |
5870 | ||
5871 | struct mlx5_ifc_arm_xrc_srq_out_bits { | |
5872 | u8 status[0x8]; | |
5873 | u8 reserved_0[0x18]; | |
5874 | ||
5875 | u8 syndrome[0x20]; | |
5876 | ||
5877 | u8 reserved_1[0x40]; | |
5878 | }; | |
5879 | ||
5880 | enum { | |
5881 | MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, | |
5882 | }; | |
5883 | ||
5884 | struct mlx5_ifc_arm_xrc_srq_in_bits { | |
5885 | u8 opcode[0x10]; | |
5886 | u8 reserved_0[0x10]; | |
5887 | ||
5888 | u8 reserved_1[0x10]; | |
5889 | u8 op_mod[0x10]; | |
5890 | ||
5891 | u8 reserved_2[0x8]; | |
5892 | u8 xrc_srqn[0x18]; | |
5893 | ||
5894 | u8 reserved_3[0x10]; | |
5895 | u8 lwm[0x10]; | |
5896 | }; | |
5897 | ||
5898 | struct mlx5_ifc_arm_rq_out_bits { | |
5899 | u8 status[0x8]; | |
5900 | u8 reserved_0[0x18]; | |
5901 | ||
5902 | u8 syndrome[0x20]; | |
5903 | ||
5904 | u8 reserved_1[0x40]; | |
5905 | }; | |
5906 | ||
5907 | enum { | |
5908 | MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1, | |
5909 | }; | |
5910 | ||
5911 | struct mlx5_ifc_arm_rq_in_bits { | |
5912 | u8 opcode[0x10]; | |
5913 | u8 reserved_0[0x10]; | |
5914 | ||
5915 | u8 reserved_1[0x10]; | |
5916 | u8 op_mod[0x10]; | |
5917 | ||
5918 | u8 reserved_2[0x8]; | |
5919 | u8 srq_number[0x18]; | |
5920 | ||
5921 | u8 reserved_3[0x10]; | |
5922 | u8 lwm[0x10]; | |
5923 | }; | |
5924 | ||
5925 | struct mlx5_ifc_arm_dct_out_bits { | |
5926 | u8 status[0x8]; | |
5927 | u8 reserved_0[0x18]; | |
5928 | ||
5929 | u8 syndrome[0x20]; | |
5930 | ||
5931 | u8 reserved_1[0x40]; | |
5932 | }; | |
5933 | ||
5934 | struct mlx5_ifc_arm_dct_in_bits { | |
5935 | u8 opcode[0x10]; | |
5936 | u8 reserved_0[0x10]; | |
5937 | ||
5938 | u8 reserved_1[0x10]; | |
5939 | u8 op_mod[0x10]; | |
5940 | ||
5941 | u8 reserved_2[0x8]; | |
5942 | u8 dct_number[0x18]; | |
5943 | ||
5944 | u8 reserved_3[0x20]; | |
5945 | }; | |
5946 | ||
5947 | struct mlx5_ifc_alloc_xrcd_out_bits { | |
5948 | u8 status[0x8]; | |
5949 | u8 reserved_0[0x18]; | |
5950 | ||
5951 | u8 syndrome[0x20]; | |
5952 | ||
5953 | u8 reserved_1[0x8]; | |
5954 | u8 xrcd[0x18]; | |
5955 | ||
5956 | u8 reserved_2[0x20]; | |
5957 | }; | |
5958 | ||
5959 | struct mlx5_ifc_alloc_xrcd_in_bits { | |
5960 | u8 opcode[0x10]; | |
5961 | u8 reserved_0[0x10]; | |
5962 | ||
5963 | u8 reserved_1[0x10]; | |
5964 | u8 op_mod[0x10]; | |
5965 | ||
5966 | u8 reserved_2[0x40]; | |
5967 | }; | |
5968 | ||
5969 | struct mlx5_ifc_alloc_uar_out_bits { | |
5970 | u8 status[0x8]; | |
5971 | u8 reserved_0[0x18]; | |
5972 | ||
5973 | u8 syndrome[0x20]; | |
5974 | ||
5975 | u8 reserved_1[0x8]; | |
5976 | u8 uar[0x18]; | |
5977 | ||
5978 | u8 reserved_2[0x20]; | |
5979 | }; | |
5980 | ||
5981 | struct mlx5_ifc_alloc_uar_in_bits { | |
5982 | u8 opcode[0x10]; | |
5983 | u8 reserved_0[0x10]; | |
5984 | ||
5985 | u8 reserved_1[0x10]; | |
5986 | u8 op_mod[0x10]; | |
5987 | ||
5988 | u8 reserved_2[0x40]; | |
5989 | }; | |
5990 | ||
5991 | struct mlx5_ifc_alloc_transport_domain_out_bits { | |
5992 | u8 status[0x8]; | |
5993 | u8 reserved_0[0x18]; | |
5994 | ||
5995 | u8 syndrome[0x20]; | |
5996 | ||
5997 | u8 reserved_1[0x8]; | |
5998 | u8 transport_domain[0x18]; | |
5999 | ||
6000 | u8 reserved_2[0x20]; | |
6001 | }; | |
6002 | ||
6003 | struct mlx5_ifc_alloc_transport_domain_in_bits { | |
6004 | u8 opcode[0x10]; | |
6005 | u8 reserved_0[0x10]; | |
6006 | ||
6007 | u8 reserved_1[0x10]; | |
6008 | u8 op_mod[0x10]; | |
6009 | ||
6010 | u8 reserved_2[0x40]; | |
6011 | }; | |
6012 | ||
6013 | struct mlx5_ifc_alloc_q_counter_out_bits { | |
6014 | u8 status[0x8]; | |
6015 | u8 reserved_0[0x18]; | |
6016 | ||
6017 | u8 syndrome[0x20]; | |
6018 | ||
6019 | u8 reserved_1[0x18]; | |
6020 | u8 counter_set_id[0x8]; | |
6021 | ||
6022 | u8 reserved_2[0x20]; | |
6023 | }; | |
6024 | ||
6025 | struct mlx5_ifc_alloc_q_counter_in_bits { | |
6026 | u8 opcode[0x10]; | |
6027 | u8 reserved_0[0x10]; | |
6028 | ||
6029 | u8 reserved_1[0x10]; | |
6030 | u8 op_mod[0x10]; | |
6031 | ||
6032 | u8 reserved_2[0x40]; | |
6033 | }; | |
6034 | ||
6035 | struct mlx5_ifc_alloc_pd_out_bits { | |
6036 | u8 status[0x8]; | |
6037 | u8 reserved_0[0x18]; | |
6038 | ||
6039 | u8 syndrome[0x20]; | |
6040 | ||
6041 | u8 reserved_1[0x8]; | |
6042 | u8 pd[0x18]; | |
6043 | ||
6044 | u8 reserved_2[0x20]; | |
6045 | }; | |
6046 | ||
6047 | struct mlx5_ifc_alloc_pd_in_bits { | |
6048 | u8 opcode[0x10]; | |
6049 | u8 reserved_0[0x10]; | |
6050 | ||
6051 | u8 reserved_1[0x10]; | |
6052 | u8 op_mod[0x10]; | |
6053 | ||
6054 | u8 reserved_2[0x40]; | |
6055 | }; | |
6056 | ||
6057 | struct mlx5_ifc_add_vxlan_udp_dport_out_bits { | |
6058 | u8 status[0x8]; | |
6059 | u8 reserved_0[0x18]; | |
6060 | ||
6061 | u8 syndrome[0x20]; | |
6062 | ||
6063 | u8 reserved_1[0x40]; | |
6064 | }; | |
6065 | ||
6066 | struct mlx5_ifc_add_vxlan_udp_dport_in_bits { | |
6067 | u8 opcode[0x10]; | |
6068 | u8 reserved_0[0x10]; | |
6069 | ||
6070 | u8 reserved_1[0x10]; | |
6071 | u8 op_mod[0x10]; | |
6072 | ||
6073 | u8 reserved_2[0x20]; | |
6074 | ||
6075 | u8 reserved_3[0x10]; | |
6076 | u8 vxlan_udp_port[0x10]; | |
6077 | }; | |
6078 | ||
6079 | struct mlx5_ifc_access_register_out_bits { | |
6080 | u8 status[0x8]; | |
6081 | u8 reserved_0[0x18]; | |
6082 | ||
6083 | u8 syndrome[0x20]; | |
6084 | ||
6085 | u8 reserved_1[0x40]; | |
6086 | ||
6087 | u8 register_data[0][0x20]; | |
6088 | }; | |
6089 | ||
6090 | enum { | |
6091 | MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, | |
6092 | MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, | |
6093 | }; | |
6094 | ||
6095 | struct mlx5_ifc_access_register_in_bits { | |
6096 | u8 opcode[0x10]; | |
6097 | u8 reserved_0[0x10]; | |
6098 | ||
6099 | u8 reserved_1[0x10]; | |
6100 | u8 op_mod[0x10]; | |
6101 | ||
6102 | u8 reserved_2[0x10]; | |
6103 | u8 register_id[0x10]; | |
6104 | ||
6105 | u8 argument[0x20]; | |
6106 | ||
6107 | u8 register_data[0][0x20]; | |
6108 | }; | |
6109 | ||
6110 | struct mlx5_ifc_sltp_reg_bits { | |
6111 | u8 status[0x4]; | |
6112 | u8 version[0x4]; | |
6113 | u8 local_port[0x8]; | |
6114 | u8 pnat[0x2]; | |
6115 | u8 reserved_0[0x2]; | |
6116 | u8 lane[0x4]; | |
6117 | u8 reserved_1[0x8]; | |
6118 | ||
6119 | u8 reserved_2[0x20]; | |
6120 | ||
6121 | u8 reserved_3[0x7]; | |
6122 | u8 polarity[0x1]; | |
6123 | u8 ob_tap0[0x8]; | |
6124 | u8 ob_tap1[0x8]; | |
6125 | u8 ob_tap2[0x8]; | |
6126 | ||
6127 | u8 reserved_4[0xc]; | |
6128 | u8 ob_preemp_mode[0x4]; | |
6129 | u8 ob_reg[0x8]; | |
6130 | u8 ob_bias[0x8]; | |
6131 | ||
6132 | u8 reserved_5[0x20]; | |
6133 | }; | |
6134 | ||
6135 | struct mlx5_ifc_slrg_reg_bits { | |
6136 | u8 status[0x4]; | |
6137 | u8 version[0x4]; | |
6138 | u8 local_port[0x8]; | |
6139 | u8 pnat[0x2]; | |
6140 | u8 reserved_0[0x2]; | |
6141 | u8 lane[0x4]; | |
6142 | u8 reserved_1[0x8]; | |
6143 | ||
6144 | u8 time_to_link_up[0x10]; | |
6145 | u8 reserved_2[0xc]; | |
6146 | u8 grade_lane_speed[0x4]; | |
6147 | ||
6148 | u8 grade_version[0x8]; | |
6149 | u8 grade[0x18]; | |
6150 | ||
6151 | u8 reserved_3[0x4]; | |
6152 | u8 height_grade_type[0x4]; | |
6153 | u8 height_grade[0x18]; | |
6154 | ||
6155 | u8 height_dz[0x10]; | |
6156 | u8 height_dv[0x10]; | |
6157 | ||
6158 | u8 reserved_4[0x10]; | |
6159 | u8 height_sigma[0x10]; | |
6160 | ||
6161 | u8 reserved_5[0x20]; | |
6162 | ||
6163 | u8 reserved_6[0x4]; | |
6164 | u8 phase_grade_type[0x4]; | |
6165 | u8 phase_grade[0x18]; | |
6166 | ||
6167 | u8 reserved_7[0x8]; | |
6168 | u8 phase_eo_pos[0x8]; | |
6169 | u8 reserved_8[0x8]; | |
6170 | u8 phase_eo_neg[0x8]; | |
6171 | ||
6172 | u8 ffe_set_tested[0x10]; | |
6173 | u8 test_errors_per_lane[0x10]; | |
6174 | }; | |
6175 | ||
6176 | struct mlx5_ifc_pvlc_reg_bits { | |
6177 | u8 reserved_0[0x8]; | |
6178 | u8 local_port[0x8]; | |
6179 | u8 reserved_1[0x10]; | |
6180 | ||
6181 | u8 reserved_2[0x1c]; | |
6182 | u8 vl_hw_cap[0x4]; | |
6183 | ||
6184 | u8 reserved_3[0x1c]; | |
6185 | u8 vl_admin[0x4]; | |
6186 | ||
6187 | u8 reserved_4[0x1c]; | |
6188 | u8 vl_operational[0x4]; | |
6189 | }; | |
6190 | ||
6191 | struct mlx5_ifc_pude_reg_bits { | |
6192 | u8 swid[0x8]; | |
6193 | u8 local_port[0x8]; | |
6194 | u8 reserved_0[0x4]; | |
6195 | u8 admin_status[0x4]; | |
6196 | u8 reserved_1[0x4]; | |
6197 | u8 oper_status[0x4]; | |
6198 | ||
6199 | u8 reserved_2[0x60]; | |
6200 | }; | |
6201 | ||
6202 | struct mlx5_ifc_ptys_reg_bits { | |
6203 | u8 reserved_0[0x8]; | |
6204 | u8 local_port[0x8]; | |
6205 | u8 reserved_1[0xd]; | |
6206 | u8 proto_mask[0x3]; | |
6207 | ||
6208 | u8 reserved_2[0x40]; | |
6209 | ||
6210 | u8 eth_proto_capability[0x20]; | |
6211 | ||
6212 | u8 ib_link_width_capability[0x10]; | |
6213 | u8 ib_proto_capability[0x10]; | |
6214 | ||
6215 | u8 reserved_3[0x20]; | |
6216 | ||
6217 | u8 eth_proto_admin[0x20]; | |
6218 | ||
6219 | u8 ib_link_width_admin[0x10]; | |
6220 | u8 ib_proto_admin[0x10]; | |
6221 | ||
6222 | u8 reserved_4[0x20]; | |
6223 | ||
6224 | u8 eth_proto_oper[0x20]; | |
6225 | ||
6226 | u8 ib_link_width_oper[0x10]; | |
6227 | u8 ib_proto_oper[0x10]; | |
6228 | ||
6229 | u8 reserved_5[0x20]; | |
6230 | ||
6231 | u8 eth_proto_lp_advertise[0x20]; | |
6232 | ||
6233 | u8 reserved_6[0x60]; | |
6234 | }; | |
6235 | ||
6236 | struct mlx5_ifc_ptas_reg_bits { | |
6237 | u8 reserved_0[0x20]; | |
6238 | ||
6239 | u8 algorithm_options[0x10]; | |
6240 | u8 reserved_1[0x4]; | |
6241 | u8 repetitions_mode[0x4]; | |
6242 | u8 num_of_repetitions[0x8]; | |
6243 | ||
6244 | u8 grade_version[0x8]; | |
6245 | u8 height_grade_type[0x4]; | |
6246 | u8 phase_grade_type[0x4]; | |
6247 | u8 height_grade_weight[0x8]; | |
6248 | u8 phase_grade_weight[0x8]; | |
6249 | ||
6250 | u8 gisim_measure_bits[0x10]; | |
6251 | u8 adaptive_tap_measure_bits[0x10]; | |
6252 | ||
6253 | u8 ber_bath_high_error_threshold[0x10]; | |
6254 | u8 ber_bath_mid_error_threshold[0x10]; | |
6255 | ||
6256 | u8 ber_bath_low_error_threshold[0x10]; | |
6257 | u8 one_ratio_high_threshold[0x10]; | |
6258 | ||
6259 | u8 one_ratio_high_mid_threshold[0x10]; | |
6260 | u8 one_ratio_low_mid_threshold[0x10]; | |
6261 | ||
6262 | u8 one_ratio_low_threshold[0x10]; | |
6263 | u8 ndeo_error_threshold[0x10]; | |
6264 | ||
6265 | u8 mixer_offset_step_size[0x10]; | |
6266 | u8 reserved_2[0x8]; | |
6267 | u8 mix90_phase_for_voltage_bath[0x8]; | |
6268 | ||
6269 | u8 mixer_offset_start[0x10]; | |
6270 | u8 mixer_offset_end[0x10]; | |
6271 | ||
6272 | u8 reserved_3[0x15]; | |
6273 | u8 ber_test_time[0xb]; | |
6274 | }; | |
6275 | ||
6276 | struct mlx5_ifc_pspa_reg_bits { | |
6277 | u8 swid[0x8]; | |
6278 | u8 local_port[0x8]; | |
6279 | u8 sub_port[0x8]; | |
6280 | u8 reserved_0[0x8]; | |
6281 | ||
6282 | u8 reserved_1[0x20]; | |
6283 | }; | |
6284 | ||
6285 | struct mlx5_ifc_pqdr_reg_bits { | |
6286 | u8 reserved_0[0x8]; | |
6287 | u8 local_port[0x8]; | |
6288 | u8 reserved_1[0x5]; | |
6289 | u8 prio[0x3]; | |
6290 | u8 reserved_2[0x6]; | |
6291 | u8 mode[0x2]; | |
6292 | ||
6293 | u8 reserved_3[0x20]; | |
6294 | ||
6295 | u8 reserved_4[0x10]; | |
6296 | u8 min_threshold[0x10]; | |
6297 | ||
6298 | u8 reserved_5[0x10]; | |
6299 | u8 max_threshold[0x10]; | |
6300 | ||
6301 | u8 reserved_6[0x10]; | |
6302 | u8 mark_probability_denominator[0x10]; | |
6303 | ||
6304 | u8 reserved_7[0x60]; | |
6305 | }; | |
6306 | ||
6307 | struct mlx5_ifc_ppsc_reg_bits { | |
6308 | u8 reserved_0[0x8]; | |
6309 | u8 local_port[0x8]; | |
6310 | u8 reserved_1[0x10]; | |
6311 | ||
6312 | u8 reserved_2[0x60]; | |
6313 | ||
6314 | u8 reserved_3[0x1c]; | |
6315 | u8 wrps_admin[0x4]; | |
6316 | ||
6317 | u8 reserved_4[0x1c]; | |
6318 | u8 wrps_status[0x4]; | |
6319 | ||
6320 | u8 reserved_5[0x8]; | |
6321 | u8 up_threshold[0x8]; | |
6322 | u8 reserved_6[0x8]; | |
6323 | u8 down_threshold[0x8]; | |
6324 | ||
6325 | u8 reserved_7[0x20]; | |
6326 | ||
6327 | u8 reserved_8[0x1c]; | |
6328 | u8 srps_admin[0x4]; | |
6329 | ||
6330 | u8 reserved_9[0x1c]; | |
6331 | u8 srps_status[0x4]; | |
6332 | ||
6333 | u8 reserved_10[0x40]; | |
6334 | }; | |
6335 | ||
6336 | struct mlx5_ifc_pplr_reg_bits { | |
6337 | u8 reserved_0[0x8]; | |
6338 | u8 local_port[0x8]; | |
6339 | u8 reserved_1[0x10]; | |
6340 | ||
6341 | u8 reserved_2[0x8]; | |
6342 | u8 lb_cap[0x8]; | |
6343 | u8 reserved_3[0x8]; | |
6344 | u8 lb_en[0x8]; | |
6345 | }; | |
6346 | ||
6347 | struct mlx5_ifc_pplm_reg_bits { | |
6348 | u8 reserved_0[0x8]; | |
6349 | u8 local_port[0x8]; | |
6350 | u8 reserved_1[0x10]; | |
6351 | ||
6352 | u8 reserved_2[0x20]; | |
6353 | ||
6354 | u8 port_profile_mode[0x8]; | |
6355 | u8 static_port_profile[0x8]; | |
6356 | u8 active_port_profile[0x8]; | |
6357 | u8 reserved_3[0x8]; | |
6358 | ||
6359 | u8 retransmission_active[0x8]; | |
6360 | u8 fec_mode_active[0x18]; | |
6361 | ||
6362 | u8 reserved_4[0x20]; | |
6363 | }; | |
6364 | ||
6365 | struct mlx5_ifc_ppcnt_reg_bits { | |
6366 | u8 swid[0x8]; | |
6367 | u8 local_port[0x8]; | |
6368 | u8 pnat[0x2]; | |
6369 | u8 reserved_0[0x8]; | |
6370 | u8 grp[0x6]; | |
6371 | ||
6372 | u8 clr[0x1]; | |
6373 | u8 reserved_1[0x1c]; | |
6374 | u8 prio_tc[0x3]; | |
6375 | ||
6376 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; | |
6377 | }; | |
6378 | ||
6379 | struct mlx5_ifc_ppad_reg_bits { | |
6380 | u8 reserved_0[0x3]; | |
6381 | u8 single_mac[0x1]; | |
6382 | u8 reserved_1[0x4]; | |
6383 | u8 local_port[0x8]; | |
6384 | u8 mac_47_32[0x10]; | |
6385 | ||
6386 | u8 mac_31_0[0x20]; | |
6387 | ||
6388 | u8 reserved_2[0x40]; | |
6389 | }; | |
6390 | ||
6391 | struct mlx5_ifc_pmtu_reg_bits { | |
6392 | u8 reserved_0[0x8]; | |
6393 | u8 local_port[0x8]; | |
6394 | u8 reserved_1[0x10]; | |
6395 | ||
6396 | u8 max_mtu[0x10]; | |
6397 | u8 reserved_2[0x10]; | |
6398 | ||
6399 | u8 admin_mtu[0x10]; | |
6400 | u8 reserved_3[0x10]; | |
6401 | ||
6402 | u8 oper_mtu[0x10]; | |
6403 | u8 reserved_4[0x10]; | |
6404 | }; | |
6405 | ||
6406 | struct mlx5_ifc_pmpr_reg_bits { | |
6407 | u8 reserved_0[0x8]; | |
6408 | u8 module[0x8]; | |
6409 | u8 reserved_1[0x10]; | |
6410 | ||
6411 | u8 reserved_2[0x18]; | |
6412 | u8 attenuation_5g[0x8]; | |
6413 | ||
6414 | u8 reserved_3[0x18]; | |
6415 | u8 attenuation_7g[0x8]; | |
6416 | ||
6417 | u8 reserved_4[0x18]; | |
6418 | u8 attenuation_12g[0x8]; | |
6419 | }; | |
6420 | ||
6421 | struct mlx5_ifc_pmpe_reg_bits { | |
6422 | u8 reserved_0[0x8]; | |
6423 | u8 module[0x8]; | |
6424 | u8 reserved_1[0xc]; | |
6425 | u8 module_status[0x4]; | |
6426 | ||
6427 | u8 reserved_2[0x60]; | |
6428 | }; | |
6429 | ||
6430 | struct mlx5_ifc_pmpc_reg_bits { | |
6431 | u8 module_state_updated[32][0x8]; | |
6432 | }; | |
6433 | ||
6434 | struct mlx5_ifc_pmlpn_reg_bits { | |
6435 | u8 reserved_0[0x4]; | |
6436 | u8 mlpn_status[0x4]; | |
6437 | u8 local_port[0x8]; | |
6438 | u8 reserved_1[0x10]; | |
6439 | ||
6440 | u8 e[0x1]; | |
6441 | u8 reserved_2[0x1f]; | |
6442 | }; | |
6443 | ||
6444 | struct mlx5_ifc_pmlp_reg_bits { | |
6445 | u8 rxtx[0x1]; | |
6446 | u8 reserved_0[0x7]; | |
6447 | u8 local_port[0x8]; | |
6448 | u8 reserved_1[0x8]; | |
6449 | u8 width[0x8]; | |
6450 | ||
6451 | u8 lane0_module_mapping[0x20]; | |
6452 | ||
6453 | u8 lane1_module_mapping[0x20]; | |
6454 | ||
6455 | u8 lane2_module_mapping[0x20]; | |
6456 | ||
6457 | u8 lane3_module_mapping[0x20]; | |
6458 | ||
6459 | u8 reserved_2[0x160]; | |
6460 | }; | |
6461 | ||
6462 | struct mlx5_ifc_pmaos_reg_bits { | |
6463 | u8 reserved_0[0x8]; | |
6464 | u8 module[0x8]; | |
6465 | u8 reserved_1[0x4]; | |
6466 | u8 admin_status[0x4]; | |
6467 | u8 reserved_2[0x4]; | |
6468 | u8 oper_status[0x4]; | |
6469 | ||
6470 | u8 ase[0x1]; | |
6471 | u8 ee[0x1]; | |
6472 | u8 reserved_3[0x1c]; | |
6473 | u8 e[0x2]; | |
6474 | ||
6475 | u8 reserved_4[0x40]; | |
6476 | }; | |
6477 | ||
6478 | struct mlx5_ifc_plpc_reg_bits { | |
6479 | u8 reserved_0[0x4]; | |
6480 | u8 profile_id[0xc]; | |
6481 | u8 reserved_1[0x4]; | |
6482 | u8 proto_mask[0x4]; | |
6483 | u8 reserved_2[0x8]; | |
6484 | ||
6485 | u8 reserved_3[0x10]; | |
6486 | u8 lane_speed[0x10]; | |
6487 | ||
6488 | u8 reserved_4[0x17]; | |
6489 | u8 lpbf[0x1]; | |
6490 | u8 fec_mode_policy[0x8]; | |
6491 | ||
6492 | u8 retransmission_capability[0x8]; | |
6493 | u8 fec_mode_capability[0x18]; | |
6494 | ||
6495 | u8 retransmission_support_admin[0x8]; | |
6496 | u8 fec_mode_support_admin[0x18]; | |
6497 | ||
6498 | u8 retransmission_request_admin[0x8]; | |
6499 | u8 fec_mode_request_admin[0x18]; | |
6500 | ||
6501 | u8 reserved_5[0x80]; | |
6502 | }; | |
6503 | ||
6504 | struct mlx5_ifc_plib_reg_bits { | |
6505 | u8 reserved_0[0x8]; | |
6506 | u8 local_port[0x8]; | |
6507 | u8 reserved_1[0x8]; | |
6508 | u8 ib_port[0x8]; | |
6509 | ||
6510 | u8 reserved_2[0x60]; | |
6511 | }; | |
6512 | ||
6513 | struct mlx5_ifc_plbf_reg_bits { | |
6514 | u8 reserved_0[0x8]; | |
6515 | u8 local_port[0x8]; | |
6516 | u8 reserved_1[0xd]; | |
6517 | u8 lbf_mode[0x3]; | |
6518 | ||
6519 | u8 reserved_2[0x20]; | |
6520 | }; | |
6521 | ||
6522 | struct mlx5_ifc_pipg_reg_bits { | |
6523 | u8 reserved_0[0x8]; | |
6524 | u8 local_port[0x8]; | |
6525 | u8 reserved_1[0x10]; | |
6526 | ||
6527 | u8 dic[0x1]; | |
6528 | u8 reserved_2[0x19]; | |
6529 | u8 ipg[0x4]; | |
6530 | u8 reserved_3[0x2]; | |
6531 | }; | |
6532 | ||
6533 | struct mlx5_ifc_pifr_reg_bits { | |
6534 | u8 reserved_0[0x8]; | |
6535 | u8 local_port[0x8]; | |
6536 | u8 reserved_1[0x10]; | |
6537 | ||
6538 | u8 reserved_2[0xe0]; | |
6539 | ||
6540 | u8 port_filter[8][0x20]; | |
6541 | ||
6542 | u8 port_filter_update_en[8][0x20]; | |
6543 | }; | |
6544 | ||
6545 | struct mlx5_ifc_pfcc_reg_bits { | |
6546 | u8 reserved_0[0x8]; | |
6547 | u8 local_port[0x8]; | |
6548 | u8 reserved_1[0x10]; | |
6549 | ||
6550 | u8 ppan[0x4]; | |
6551 | u8 reserved_2[0x4]; | |
6552 | u8 prio_mask_tx[0x8]; | |
6553 | u8 reserved_3[0x8]; | |
6554 | u8 prio_mask_rx[0x8]; | |
6555 | ||
6556 | u8 pptx[0x1]; | |
6557 | u8 aptx[0x1]; | |
6558 | u8 reserved_4[0x6]; | |
6559 | u8 pfctx[0x8]; | |
6560 | u8 reserved_5[0x10]; | |
6561 | ||
6562 | u8 pprx[0x1]; | |
6563 | u8 aprx[0x1]; | |
6564 | u8 reserved_6[0x6]; | |
6565 | u8 pfcrx[0x8]; | |
6566 | u8 reserved_7[0x10]; | |
6567 | ||
6568 | u8 reserved_8[0x80]; | |
6569 | }; | |
6570 | ||
6571 | struct mlx5_ifc_pelc_reg_bits { | |
6572 | u8 op[0x4]; | |
6573 | u8 reserved_0[0x4]; | |
6574 | u8 local_port[0x8]; | |
6575 | u8 reserved_1[0x10]; | |
6576 | ||
6577 | u8 op_admin[0x8]; | |
6578 | u8 op_capability[0x8]; | |
6579 | u8 op_request[0x8]; | |
6580 | u8 op_active[0x8]; | |
6581 | ||
6582 | u8 admin[0x40]; | |
6583 | ||
6584 | u8 capability[0x40]; | |
6585 | ||
6586 | u8 request[0x40]; | |
6587 | ||
6588 | u8 active[0x40]; | |
6589 | ||
6590 | u8 reserved_2[0x80]; | |
6591 | }; | |
6592 | ||
6593 | struct mlx5_ifc_peir_reg_bits { | |
6594 | u8 reserved_0[0x8]; | |
6595 | u8 local_port[0x8]; | |
6596 | u8 reserved_1[0x10]; | |
6597 | ||
6598 | u8 reserved_2[0xc]; | |
6599 | u8 error_count[0x4]; | |
6600 | u8 reserved_3[0x10]; | |
6601 | ||
6602 | u8 reserved_4[0xc]; | |
6603 | u8 lane[0x4]; | |
6604 | u8 reserved_5[0x8]; | |
6605 | u8 error_type[0x8]; | |
6606 | }; | |
6607 | ||
6608 | struct mlx5_ifc_pcap_reg_bits { | |
6609 | u8 reserved_0[0x8]; | |
6610 | u8 local_port[0x8]; | |
6611 | u8 reserved_1[0x10]; | |
6612 | ||
6613 | u8 port_capability_mask[4][0x20]; | |
6614 | }; | |
6615 | ||
6616 | struct mlx5_ifc_paos_reg_bits { | |
6617 | u8 swid[0x8]; | |
6618 | u8 local_port[0x8]; | |
6619 | u8 reserved_0[0x4]; | |
6620 | u8 admin_status[0x4]; | |
6621 | u8 reserved_1[0x4]; | |
6622 | u8 oper_status[0x4]; | |
6623 | ||
6624 | u8 ase[0x1]; | |
6625 | u8 ee[0x1]; | |
6626 | u8 reserved_2[0x1c]; | |
6627 | u8 e[0x2]; | |
6628 | ||
6629 | u8 reserved_3[0x40]; | |
6630 | }; | |
6631 | ||
6632 | struct mlx5_ifc_pamp_reg_bits { | |
6633 | u8 reserved_0[0x8]; | |
6634 | u8 opamp_group[0x8]; | |
6635 | u8 reserved_1[0xc]; | |
6636 | u8 opamp_group_type[0x4]; | |
6637 | ||
6638 | u8 start_index[0x10]; | |
6639 | u8 reserved_2[0x4]; | |
6640 | u8 num_of_indices[0xc]; | |
6641 | ||
6642 | u8 index_data[18][0x10]; | |
6643 | }; | |
6644 | ||
6645 | struct mlx5_ifc_lane_2_module_mapping_bits { | |
6646 | u8 reserved_0[0x6]; | |
6647 | u8 rx_lane[0x2]; | |
6648 | u8 reserved_1[0x6]; | |
6649 | u8 tx_lane[0x2]; | |
6650 | u8 reserved_2[0x8]; | |
6651 | u8 module[0x8]; | |
6652 | }; | |
6653 | ||
6654 | struct mlx5_ifc_bufferx_reg_bits { | |
6655 | u8 reserved_0[0x6]; | |
6656 | u8 lossy[0x1]; | |
6657 | u8 epsb[0x1]; | |
6658 | u8 reserved_1[0xc]; | |
6659 | u8 size[0xc]; | |
6660 | ||
6661 | u8 xoff_threshold[0x10]; | |
6662 | u8 xon_threshold[0x10]; | |
6663 | }; | |
6664 | ||
6665 | struct mlx5_ifc_set_node_in_bits { | |
6666 | u8 node_description[64][0x8]; | |
6667 | }; | |
6668 | ||
6669 | struct mlx5_ifc_register_power_settings_bits { | |
6670 | u8 reserved_0[0x18]; | |
6671 | u8 power_settings_level[0x8]; | |
6672 | ||
6673 | u8 reserved_1[0x60]; | |
6674 | }; | |
6675 | ||
6676 | struct mlx5_ifc_register_host_endianness_bits { | |
6677 | u8 he[0x1]; | |
6678 | u8 reserved_0[0x1f]; | |
6679 | ||
6680 | u8 reserved_1[0x60]; | |
6681 | }; | |
6682 | ||
6683 | struct mlx5_ifc_umr_pointer_desc_argument_bits { | |
6684 | u8 reserved_0[0x20]; | |
6685 | ||
6686 | u8 mkey[0x20]; | |
6687 | ||
6688 | u8 addressh_63_32[0x20]; | |
6689 | ||
6690 | u8 addressl_31_0[0x20]; | |
6691 | }; | |
6692 | ||
6693 | struct mlx5_ifc_ud_adrs_vector_bits { | |
6694 | u8 dc_key[0x40]; | |
6695 | ||
6696 | u8 ext[0x1]; | |
6697 | u8 reserved_0[0x7]; | |
6698 | u8 destination_qp_dct[0x18]; | |
6699 | ||
6700 | u8 static_rate[0x4]; | |
6701 | u8 sl_eth_prio[0x4]; | |
6702 | u8 fl[0x1]; | |
6703 | u8 mlid[0x7]; | |
6704 | u8 rlid_udp_sport[0x10]; | |
6705 | ||
6706 | u8 reserved_1[0x20]; | |
6707 | ||
6708 | u8 rmac_47_16[0x20]; | |
6709 | ||
6710 | u8 rmac_15_0[0x10]; | |
6711 | u8 tclass[0x8]; | |
6712 | u8 hop_limit[0x8]; | |
6713 | ||
6714 | u8 reserved_2[0x1]; | |
6715 | u8 grh[0x1]; | |
6716 | u8 reserved_3[0x2]; | |
6717 | u8 src_addr_index[0x8]; | |
6718 | u8 flow_label[0x14]; | |
6719 | ||
6720 | u8 rgid_rip[16][0x8]; | |
6721 | }; | |
6722 | ||
6723 | struct mlx5_ifc_pages_req_event_bits { | |
6724 | u8 reserved_0[0x10]; | |
6725 | u8 function_id[0x10]; | |
6726 | ||
6727 | u8 num_pages[0x20]; | |
6728 | ||
6729 | u8 reserved_1[0xa0]; | |
6730 | }; | |
6731 | ||
6732 | struct mlx5_ifc_eqe_bits { | |
6733 | u8 reserved_0[0x8]; | |
6734 | u8 event_type[0x8]; | |
6735 | u8 reserved_1[0x8]; | |
6736 | u8 event_sub_type[0x8]; | |
6737 | ||
6738 | u8 reserved_2[0xe0]; | |
6739 | ||
6740 | union mlx5_ifc_event_auto_bits event_data; | |
6741 | ||
6742 | u8 reserved_3[0x10]; | |
6743 | u8 signature[0x8]; | |
6744 | u8 reserved_4[0x7]; | |
6745 | u8 owner[0x1]; | |
6746 | }; | |
6747 | ||
6748 | enum { | |
6749 | MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, | |
6750 | }; | |
6751 | ||
6752 | struct mlx5_ifc_cmd_queue_entry_bits { | |
6753 | u8 type[0x8]; | |
6754 | u8 reserved_0[0x18]; | |
6755 | ||
6756 | u8 input_length[0x20]; | |
6757 | ||
6758 | u8 input_mailbox_pointer_63_32[0x20]; | |
6759 | ||
6760 | u8 input_mailbox_pointer_31_9[0x17]; | |
6761 | u8 reserved_1[0x9]; | |
6762 | ||
6763 | u8 command_input_inline_data[16][0x8]; | |
6764 | ||
6765 | u8 command_output_inline_data[16][0x8]; | |
6766 | ||
6767 | u8 output_mailbox_pointer_63_32[0x20]; | |
6768 | ||
6769 | u8 output_mailbox_pointer_31_9[0x17]; | |
6770 | u8 reserved_2[0x9]; | |
6771 | ||
6772 | u8 output_length[0x20]; | |
6773 | ||
6774 | u8 token[0x8]; | |
6775 | u8 signature[0x8]; | |
6776 | u8 reserved_3[0x8]; | |
6777 | u8 status[0x7]; | |
6778 | u8 ownership[0x1]; | |
6779 | }; | |
6780 | ||
6781 | struct mlx5_ifc_cmd_out_bits { | |
6782 | u8 status[0x8]; | |
6783 | u8 reserved_0[0x18]; | |
6784 | ||
6785 | u8 syndrome[0x20]; | |
6786 | ||
6787 | u8 command_output[0x20]; | |
6788 | }; | |
6789 | ||
6790 | struct mlx5_ifc_cmd_in_bits { | |
6791 | u8 opcode[0x10]; | |
6792 | u8 reserved_0[0x10]; | |
6793 | ||
6794 | u8 reserved_1[0x10]; | |
6795 | u8 op_mod[0x10]; | |
6796 | ||
6797 | u8 command[0][0x20]; | |
6798 | }; | |
6799 | ||
6800 | struct mlx5_ifc_cmd_if_box_bits { | |
6801 | u8 mailbox_data[512][0x8]; | |
6802 | ||
6803 | u8 reserved_0[0x180]; | |
6804 | ||
6805 | u8 next_pointer_63_32[0x20]; | |
6806 | ||
6807 | u8 next_pointer_31_10[0x16]; | |
6808 | u8 reserved_1[0xa]; | |
6809 | ||
6810 | u8 block_number[0x20]; | |
6811 | ||
6812 | u8 reserved_2[0x8]; | |
6813 | u8 token[0x8]; | |
6814 | u8 ctrl_signature[0x8]; | |
6815 | u8 signature[0x8]; | |
6816 | }; | |
6817 | ||
6818 | struct mlx5_ifc_mtt_bits { | |
6819 | u8 ptag_63_32[0x20]; | |
6820 | ||
6821 | u8 ptag_31_8[0x18]; | |
6822 | u8 reserved_0[0x6]; | |
6823 | u8 wr_en[0x1]; | |
6824 | u8 rd_en[0x1]; | |
6825 | }; | |
6826 | ||
6827 | enum { | |
6828 | MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, | |
6829 | MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, | |
6830 | MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, | |
6831 | }; | |
6832 | ||
6833 | enum { | |
6834 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, | |
6835 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, | |
6836 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, | |
6837 | }; | |
6838 | ||
6839 | enum { | |
6840 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, | |
6841 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, | |
6842 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, | |
6843 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, | |
6844 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, | |
6845 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, | |
6846 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, | |
6847 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, | |
6848 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, | |
6849 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, | |
6850 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, | |
6851 | }; | |
6852 | ||
6853 | struct mlx5_ifc_initial_seg_bits { | |
6854 | u8 fw_rev_minor[0x10]; | |
6855 | u8 fw_rev_major[0x10]; | |
6856 | ||
6857 | u8 cmd_interface_rev[0x10]; | |
6858 | u8 fw_rev_subminor[0x10]; | |
6859 | ||
6860 | u8 reserved_0[0x40]; | |
6861 | ||
6862 | u8 cmdq_phy_addr_63_32[0x20]; | |
6863 | ||
6864 | u8 cmdq_phy_addr_31_12[0x14]; | |
6865 | u8 reserved_1[0x2]; | |
6866 | u8 nic_interface[0x2]; | |
6867 | u8 log_cmdq_size[0x4]; | |
6868 | u8 log_cmdq_stride[0x4]; | |
6869 | ||
6870 | u8 command_doorbell_vector[0x20]; | |
6871 | ||
6872 | u8 reserved_2[0xf00]; | |
6873 | ||
6874 | u8 initializing[0x1]; | |
6875 | u8 reserved_3[0x4]; | |
6876 | u8 nic_interface_supported[0x3]; | |
6877 | u8 reserved_4[0x18]; | |
6878 | ||
6879 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
6880 | ||
6881 | u8 no_dram_nic_offset[0x20]; | |
6882 | ||
6883 | u8 reserved_5[0x6e40]; | |
6884 | ||
6885 | u8 reserved_6[0x1f]; | |
6886 | u8 clear_int[0x1]; | |
6887 | ||
6888 | u8 health_syndrome[0x8]; | |
6889 | u8 health_counter[0x18]; | |
6890 | ||
6891 | u8 reserved_7[0x17fc0]; | |
6892 | }; | |
6893 | ||
6894 | union mlx5_ifc_ports_control_registers_document_bits { | |
6895 | struct mlx5_ifc_bufferx_reg_bits bufferx_reg; | |
6896 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
6897 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
6898 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
6899 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
6900 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
6901 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
6902 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
6903 | struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; | |
6904 | struct mlx5_ifc_pamp_reg_bits pamp_reg; | |
6905 | struct mlx5_ifc_paos_reg_bits paos_reg; | |
6906 | struct mlx5_ifc_pcap_reg_bits pcap_reg; | |
6907 | struct mlx5_ifc_peir_reg_bits peir_reg; | |
6908 | struct mlx5_ifc_pelc_reg_bits pelc_reg; | |
6909 | struct mlx5_ifc_pfcc_reg_bits pfcc_reg; | |
6910 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; | |
6911 | struct mlx5_ifc_pifr_reg_bits pifr_reg; | |
6912 | struct mlx5_ifc_pipg_reg_bits pipg_reg; | |
6913 | struct mlx5_ifc_plbf_reg_bits plbf_reg; | |
6914 | struct mlx5_ifc_plib_reg_bits plib_reg; | |
6915 | struct mlx5_ifc_plpc_reg_bits plpc_reg; | |
6916 | struct mlx5_ifc_pmaos_reg_bits pmaos_reg; | |
6917 | struct mlx5_ifc_pmlp_reg_bits pmlp_reg; | |
6918 | struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; | |
6919 | struct mlx5_ifc_pmpc_reg_bits pmpc_reg; | |
6920 | struct mlx5_ifc_pmpe_reg_bits pmpe_reg; | |
6921 | struct mlx5_ifc_pmpr_reg_bits pmpr_reg; | |
6922 | struct mlx5_ifc_pmtu_reg_bits pmtu_reg; | |
6923 | struct mlx5_ifc_ppad_reg_bits ppad_reg; | |
6924 | struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; | |
6925 | struct mlx5_ifc_pplm_reg_bits pplm_reg; | |
6926 | struct mlx5_ifc_pplr_reg_bits pplr_reg; | |
6927 | struct mlx5_ifc_ppsc_reg_bits ppsc_reg; | |
6928 | struct mlx5_ifc_pqdr_reg_bits pqdr_reg; | |
6929 | struct mlx5_ifc_pspa_reg_bits pspa_reg; | |
6930 | struct mlx5_ifc_ptas_reg_bits ptas_reg; | |
6931 | struct mlx5_ifc_ptys_reg_bits ptys_reg; | |
6932 | struct mlx5_ifc_pude_reg_bits pude_reg; | |
6933 | struct mlx5_ifc_pvlc_reg_bits pvlc_reg; | |
6934 | struct mlx5_ifc_slrg_reg_bits slrg_reg; | |
6935 | struct mlx5_ifc_sltp_reg_bits sltp_reg; | |
6936 | u8 reserved_0[0x60e0]; | |
6937 | }; | |
6938 | ||
6939 | union mlx5_ifc_debug_enhancements_document_bits { | |
6940 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
6941 | u8 reserved_0[0x200]; | |
6942 | }; | |
6943 | ||
6944 | union mlx5_ifc_uplink_pci_interface_document_bits { | |
6945 | struct mlx5_ifc_initial_seg_bits initial_seg; | |
6946 | u8 reserved_0[0x20060]; | |
b775516b EC |
6947 | }; |
6948 | ||
d29b796a | 6949 | #endif /* MLX5_IFC_H */ |