projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IB/hfi1: Fix sdma.h tx->num_descs off-by-one errors
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
f91e6d89
EBE		 66enum {
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
df268f6c 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20,
8d1ac895 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25,
f91e6d89
EBE		 73};
74
38b7ca92 75enum {
2acc7957 76 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 77};
78
9fba2b9b
AL		 79enum {
80 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
81};
82
83enum {
84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
8385c51f 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
b169e64a
YK		 88};
89
90enum {
91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
1892a3d4 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
e7e2519e 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
a1be74c5 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
e4075c44
YH		 96 MLX5_OBJ_TYPE_MKEY = 0xff01,
97 MLX5_OBJ_TYPE_QP = 0xff02,
98 MLX5_OBJ_TYPE_PSV = 0xff03,
99 MLX5_OBJ_TYPE_RMP = 0xff04,
100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
101 MLX5_OBJ_TYPE_RQ = 0xff06,
102 MLX5_OBJ_TYPE_SQ = 0xff07,
103 MLX5_OBJ_TYPE_TIR = 0xff08,
104 MLX5_OBJ_TYPE_TIS = 0xff09,
105 MLX5_OBJ_TYPE_DCT = 0xff0a,
106 MLX5_OBJ_TYPE_XRQ = 0xff0b,
107 MLX5_OBJ_TYPE_RQT = 0xff0e,
108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
109 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 110};
111
d29b796a
EC		 112enum {
113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
115 MLX5_CMD_OP_INIT_HCA = 0x102,
116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
117 MLX5_CMD_OP_ENABLE_HCA = 0x104,
118 MLX5_CMD_OP_DISABLE_HCA = 0x105,
119 MLX5_CMD_OP_QUERY_PAGES = 0x107,
120 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
121 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
123 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
126 MLX5_CMD_OP_ALLOC_SF = 0x113,
127 MLX5_CMD_OP_DEALLOC_SF = 0x114,
adfdaff3
YH		 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
129 MLX5_CMD_OP_RESUME_VHCA = 0x116,
130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
d29b796a
EC		 133 MLX5_CMD_OP_CREATE_MKEY = 0x200,
134 MLX5_CMD_OP_QUERY_MKEY = 0x201,
135 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
63f9c44b 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
d29b796a
EC		 141 MLX5_CMD_OP_CREATE_EQ = 0x301,
142 MLX5_CMD_OP_DESTROY_EQ = 0x302,
143 MLX5_CMD_OP_QUERY_EQ = 0x303,
144 MLX5_CMD_OP_GEN_EQE = 0x304,
145 MLX5_CMD_OP_CREATE_CQ = 0x400,
146 MLX5_CMD_OP_DESTROY_CQ = 0x401,
147 MLX5_CMD_OP_QUERY_CQ = 0x402,
148 MLX5_CMD_OP_MODIFY_CQ = 0x403,
149 MLX5_CMD_OP_CREATE_QP = 0x500,
150 MLX5_CMD_OP_DESTROY_QP = 0x501,
151 MLX5_CMD_OP_RST2INIT_QP = 0x502,
152 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
153 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
154 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
156 MLX5_CMD_OP_2ERR_QP = 0x507,
157 MLX5_CMD_OP_2RST_QP = 0x50a,
158 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
161 MLX5_CMD_OP_CREATE_PSV = 0x600,
162 MLX5_CMD_OP_DESTROY_PSV = 0x601,
163 MLX5_CMD_OP_CREATE_SRQ = 0x700,
164 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
165 MLX5_CMD_OP_QUERY_SRQ = 0x702,
166 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 171 MLX5_CMD_OP_CREATE_DCT = 0x710,
172 MLX5_CMD_OP_DESTROY_DCT = 0x711,
173 MLX5_CMD_OP_DRAIN_DCT = 0x712,
174 MLX5_CMD_OP_QUERY_DCT = 0x713,
175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 176 MLX5_CMD_OP_CREATE_XRQ = 0x717,
177 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
178 MLX5_CMD_OP_QUERY_XRQ = 0x719,
179 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 213 MLX5_CMD_OP_ALLOC_PD = 0x800,
214 MLX5_CMD_OP_DEALLOC_PD = 0x801,
215 MLX5_CMD_OP_ALLOC_UAR = 0x802,
216 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
218 MLX5_CMD_OP_ACCESS_REG = 0x805,
219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
222 MLX5_CMD_OP_MAD_IFC = 0x50d,
223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
225 MLX5_CMD_OP_NOP = 0x80d,
226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 242 MLX5_CMD_OP_CREATE_LAG = 0x840,
243 MLX5_CMD_OP_MODIFY_LAG = 0x841,
244 MLX5_CMD_OP_QUERY_LAG = 0x842,
245 MLX5_CMD_OP_DESTROY_LAG = 0x843,
246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 248 MLX5_CMD_OP_CREATE_TIR = 0x900,
249 MLX5_CMD_OP_MODIFY_TIR = 0x901,
250 MLX5_CMD_OP_DESTROY_TIR = 0x902,
251 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 252 MLX5_CMD_OP_CREATE_SQ = 0x904,
253 MLX5_CMD_OP_MODIFY_SQ = 0x905,
254 MLX5_CMD_OP_DESTROY_SQ = 0x906,
255 MLX5_CMD_OP_QUERY_SQ = 0x907,
256 MLX5_CMD_OP_CREATE_RQ = 0x908,
257 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
260 MLX5_CMD_OP_QUERY_RQ = 0x90b,
261 MLX5_CMD_OP_CREATE_RMP = 0x90c,
262 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
263 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
264 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 265 MLX5_CMD_OP_CREATE_TIS = 0x912,
266 MLX5_CMD_OP_MODIFY_TIS = 0x913,
267 MLX5_CMD_OP_DESTROY_TIS = 0x914,
268 MLX5_CMD_OP_QUERY_TIS = 0x915,
269 MLX5_CMD_OP_CREATE_RQT = 0x916,
270 MLX5_CMD_OP_MODIFY_RQT = 0x917,
271 MLX5_CMD_OP_DESTROY_RQT = 0x918,
272 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
304 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 309 MLX5_CMD_OP_MAX
e281682b
SM		 310};
311
719598c9
YH		 312/* Valid range for general commands that don't work over an object */
313enum {
314 MLX5_CMD_OP_GENERAL_START = 0xb00,
315 MLX5_CMD_OP_GENERAL_END = 0xd00,
316};
317
7368f221
PH		 318enum {
319 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
320 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
321};
322
e281682b
SM		 323struct mlx5_ifc_flow_table_fields_supported_bits {
324 u8 outer_dmac[0x1];
325 u8 outer_smac[0x1];
326 u8 outer_ether_type[0x1];
19cc7524 327 u8 outer_ip_version[0x1];
e281682b
SM		 328 u8 outer_first_prio[0x1];
329 u8 outer_first_cfi[0x1];
330 u8 outer_first_vid[0x1];
a8ade55f 331 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 332 u8 outer_second_prio[0x1];
333 u8 outer_second_cfi[0x1];
334 u8 outer_second_vid[0x1];
b4ff3a36 335 u8 reserved_at_b[0x1];
e281682b
SM		 336 u8 outer_sip[0x1];
337 u8 outer_dip[0x1];
338 u8 outer_frag[0x1];
339 u8 outer_ip_protocol[0x1];
340 u8 outer_ip_ecn[0x1];
341 u8 outer_ip_dscp[0x1];
342 u8 outer_udp_sport[0x1];
343 u8 outer_udp_dport[0x1];
344 u8 outer_tcp_sport[0x1];
345 u8 outer_tcp_dport[0x1];
346 u8 outer_tcp_flags[0x1];
347 u8 outer_gre_protocol[0x1];
348 u8 outer_gre_key[0x1];
349 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 350 u8 outer_geneve_vni[0x1];
351 u8 outer_geneve_oam[0x1];
352 u8 outer_geneve_protocol_type[0x1];
353 u8 outer_geneve_opt_len[0x1];
8208461d 354 u8 source_vhca_port[0x1];
e281682b
SM		 355 u8 source_eswitch_port[0x1];
356
357 u8 inner_dmac[0x1];
358 u8 inner_smac[0x1];
359 u8 inner_ether_type[0x1];
19cc7524 360 u8 inner_ip_version[0x1];
e281682b
SM		 361 u8 inner_first_prio[0x1];
362 u8 inner_first_cfi[0x1];
363 u8 inner_first_vid[0x1];
b4ff3a36 364 u8 reserved_at_27[0x1];
e281682b
SM		 365 u8 inner_second_prio[0x1];
366 u8 inner_second_cfi[0x1];
367 u8 inner_second_vid[0x1];
b4ff3a36 368 u8 reserved_at_2b[0x1];
e281682b
SM		 369 u8 inner_sip[0x1];
370 u8 inner_dip[0x1];
371 u8 inner_frag[0x1];
372 u8 inner_ip_protocol[0x1];
373 u8 inner_ip_ecn[0x1];
374 u8 inner_ip_dscp[0x1];
375 u8 inner_udp_sport[0x1];
376 u8 inner_udp_dport[0x1];
377 u8 inner_tcp_sport[0x1];
378 u8 inner_tcp_dport[0x1];
379 u8 inner_tcp_flags[0x1];
b4ff3a36 380 u8 reserved_at_37[0x9];
71c6e863 381
b169e64a 382 u8 geneve_tlv_option_0_data[0x1];
f59464e2
YK		 383 u8 geneve_tlv_option_0_exist[0x1];
384 u8 reserved_at_42[0x3];
71c6e863
AL		 385 u8 outer_first_mpls_over_udp[0x4];
386 u8 outer_first_mpls_over_gre[0x4];
387 u8 inner_first_mpls[0x4];
388 u8 outer_first_mpls[0x4];
389 u8 reserved_at_55[0x2];
3346c487 390 u8 outer_esp_spi[0x1];
71c6e863 391 u8 reserved_at_58[0x2];
a550ddfc 392 u8 bth_dst_qp[0x1];
822e114b 393 u8 reserved_at_5b[0x5];
e281682b 394
822e114b
PB		 395 u8 reserved_at_60[0x18];
396 u8 metadata_reg_c_7[0x1];
397 u8 metadata_reg_c_6[0x1];
398 u8 metadata_reg_c_5[0x1];
399 u8 metadata_reg_c_4[0x1];
400 u8 metadata_reg_c_3[0x1];
401 u8 metadata_reg_c_2[0x1];
402 u8 metadata_reg_c_1[0x1];
403 u8 metadata_reg_c_0[0x1];
e281682b
SM		 404};
405
8208461d
AL		 406struct mlx5_ifc_flow_table_fields_supported_2_bits {
407 u8 reserved_at_0[0xe];
408 u8 bth_opcode[0x1];
409 u8 reserved_at_f[0x11];
410
411 u8 reserved_at_20[0x60];
412};
413
e281682b
SM		 414struct mlx5_ifc_flow_table_prop_layout_bits {
415 u8 ft_support[0x1];
9dc0b289
AV		 416 u8 reserved_at_1[0x1];
417 u8 flow_counter[0x1];
26a81453 418 u8 flow_modify_en[0x1];
2cc43b49 419 u8 modify_root[0x1];
34a40e68
MG		 420 u8 identified_miss_table_mode[0x1];
421 u8 flow_table_modify[0x1];
60786f09 422 u8 reformat[0x1];
7adbde20 423 u8 decap[0x1];
0c06897a
OG		 424 u8 reserved_at_9[0x1];
425 u8 pop_vlan[0x1];
426 u8 push_vlan[0x1];
8da6fe2a
JL		 427 u8 reserved_at_c[0x1];
428 u8 pop_vlan_2[0x1];
429 u8 push_vlan_2[0x1];
bea4e1f6 430 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 431 u8 reserved_at_10[0x1];
432 u8 sw_owner[0x1];
bea4e1f6
MB		 433 u8 reformat_l3_tunnel_to_l2[0x1];
434 u8 reformat_l2_to_l3_tunnel[0x1];
435 u8 reformat_and_modify_action[0x1];
822e114b
PB		 436 u8 ignore_flow_level[0x1];
437 u8 reserved_at_16[0x1];
f6f7d6b5 438 u8 table_miss_action_domain[0x1];
c6d4e45d 439 u8 termination_table[0x1];
e0ebd8eb 440 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 441 u8 reserved_at_1a[0x2];
442 u8 ipsec_encrypt[0x1];
443 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 444 u8 sw_owner_v2[0x1];
445 u8 reserved_at_1f[0x1];
78fb6122 446
613f53fe
EC		 447 u8 termination_table_raw_traffic[0x1];
448 u8 reserved_at_21[0x1];
e281682b 449 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 450 u8 log_max_modify_header_context[0x8];
451 u8 max_modify_header_actions[0x8];
e281682b
SM		 452 u8 max_ft_level[0x8];
453
3afee4ed
LR		 454 u8 reformat_add_esp_trasport[0x1];
455 u8 reserved_at_41[0x2];
456 u8 reformat_del_esp_trasport[0x1];
457 u8 reserved_at_44[0x2];
f5d23ee1
JL		 458 u8 execute_aso[0x1];
459 u8 reserved_at_47[0x19];
e281682b 460
67133eaa
YK		 461 u8 reserved_at_60[0x2];
462 u8 reformat_insert[0x1];
463 u8 reformat_remove[0x1];
8385c51f
LN		 464 u8 macsec_encrypt[0x1];
465 u8 macsec_decrypt[0x1];
466 u8 reserved_at_66[0x2];
467 u8 reformat_add_macsec[0x1];
468 u8 reformat_remove_macsec[0x1];
469 u8 reserved_at_6a[0xe];
e281682b
SM		 470 u8 log_max_ft_num[0x8];
471
a14587df
RS		 472 u8 reserved_at_80[0x10];
473 u8 log_max_flow_counter[0x8];
e281682b
SM		 474 u8 log_max_destination[0x8];
475
a14587df 476 u8 reserved_at_a0[0x18];
e281682b
SM		 477 u8 log_max_flow[0x8];
478
b4ff3a36 479 u8 reserved_at_c0[0x40];
e281682b
SM		 480
481 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
482
483 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
484};
485
486struct mlx5_ifc_odp_per_transport_service_cap_bits {
487 u8 send[0x1];
488 u8 receive[0x1];
489 u8 write[0x1];
490 u8 read[0x1];
17d2f88f 491 u8 atomic[0x1];
e281682b 492 u8 srq_receive[0x1];
b4ff3a36 493 u8 reserved_at_6[0x1a];
e281682b
SM		 494};
495
9175d810
LR		 496struct mlx5_ifc_ipv4_layout_bits {
497 u8 reserved_at_0[0x60];
498
499 u8 ipv4[0x20];
500};
501
502struct mlx5_ifc_ipv6_layout_bits {
503 u8 ipv6[16][0x8];
504};
505
506union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
507 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
508 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
509 u8 reserved_at_0[0x80];
510};
511
e281682b
SM		 512struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
513 u8 smac_47_16[0x20];
514
515 u8 smac_15_0[0x10];
516 u8 ethertype[0x10];
517
518 u8 dmac_47_16[0x20];
519
520 u8 dmac_15_0[0x10];
521 u8 first_prio[0x3];
522 u8 first_cfi[0x1];
523 u8 first_vid[0xc];
524
525 u8 ip_protocol[0x8];
526 u8 ip_dscp[0x6];
527 u8 ip_ecn[0x2];
10543365
MHY		 528 u8 cvlan_tag[0x1];
529 u8 svlan_tag[0x1];
e281682b 530 u8 frag[0x1];
19cc7524 531 u8 ip_version[0x4];
e281682b
SM		 532 u8 tcp_flags[0x9];
533
534 u8 tcp_sport[0x10];
535 u8 tcp_dport[0x10];
536
5c422bfa
YK		 537 u8 reserved_at_c0[0x10];
538 u8 ipv4_ihl[0x4];
539 u8 reserved_at_c4[0x4];
540
a8ade55f 541 u8 ttl_hoplimit[0x8];
e281682b
SM		 542
543 u8 udp_sport[0x10];
544 u8 udp_dport[0x10];
545
b4d1f032 546 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 547
b4d1f032 548 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 549};
550
5886a96a
OS		 551struct mlx5_ifc_nvgre_key_bits {
552 u8 hi[0x18];
553 u8 lo[0x8];
554};
555
556union mlx5_ifc_gre_key_bits {
557 struct mlx5_ifc_nvgre_key_bits nvgre;
558 u8 key[0x20];
559};
560
e281682b 561struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 562 u8 gre_c_present[0x1];
d32d7c52 563 u8 reserved_at_1[0x1];
97b5484e
AV		 564 u8 gre_k_present[0x1];
565 u8 gre_s_present[0x1];
566 u8 source_vhca_port[0x4];
7486216b 567 u8 source_sqn[0x18];
e281682b 568
3e99df87 569 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 570 u8 source_port[0x10];
571
572 u8 outer_second_prio[0x3];
573 u8 outer_second_cfi[0x1];
574 u8 outer_second_vid[0xc];
575 u8 inner_second_prio[0x3];
576 u8 inner_second_cfi[0x1];
577 u8 inner_second_vid[0xc];
578
10543365
MHY		 579 u8 outer_second_cvlan_tag[0x1];
580 u8 inner_second_cvlan_tag[0x1];
581 u8 outer_second_svlan_tag[0x1];
582 u8 inner_second_svlan_tag[0x1];
583 u8 reserved_at_64[0xc];
e281682b
SM		 584 u8 gre_protocol[0x10];
585
5886a96a 586 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 587
588 u8 vxlan_vni[0x18];
8208461d 589 u8 bth_opcode[0x8];
e281682b 590
75d90e7d 591 u8 geneve_vni[0x18];
f59464e2
YK		 592 u8 reserved_at_d8[0x6];
593 u8 geneve_tlv_option_0_exist[0x1];
75d90e7d 594 u8 geneve_oam[0x1];
e281682b 595
b4ff3a36 596 u8 reserved_at_e0[0xc];
e281682b
SM		 597 u8 outer_ipv6_flow_label[0x14];
598
b4ff3a36 599 u8 reserved_at_100[0xc];
e281682b
SM		 600 u8 inner_ipv6_flow_label[0x14];
601
75d90e7d
YK		 602 u8 reserved_at_120[0xa];
603 u8 geneve_opt_len[0x6];
604 u8 geneve_protocol_type[0x10];
605
606 u8 reserved_at_140[0x8];
a550ddfc 607 u8 bth_dst_qp[0x18];
3346c487
BP		 608 u8 reserved_at_160[0x20];
609 u8 outer_esp_spi[0x20];
610 u8 reserved_at_1a0[0x60];
e281682b
SM		 611};
612
71c6e863
AL		 613struct mlx5_ifc_fte_match_mpls_bits {
614 u8 mpls_label[0x14];
615 u8 mpls_exp[0x3];
616 u8 mpls_s_bos[0x1];
617 u8 mpls_ttl[0x8];
618};
619
620struct mlx5_ifc_fte_match_set_misc2_bits {
621 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
622
623 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
624
625 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
626
627 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
628
65c0f2c1
JL		 629 u8 metadata_reg_c_7[0x20];
630
631 u8 metadata_reg_c_6[0x20];
632
633 u8 metadata_reg_c_5[0x20];
634
635 u8 metadata_reg_c_4[0x20];
636
637 u8 metadata_reg_c_3[0x20];
638
639 u8 metadata_reg_c_2[0x20];
640
641 u8 metadata_reg_c_1[0x20];
642
643 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 644
645 u8 metadata_reg_a[0x20];
646
8385c51f
LN		 647 u8 reserved_at_1a0[0x8];
648
649 u8 macsec_syndrome[0x8];
3afee4ed
LR		 650 u8 ipsec_syndrome[0x8];
651 u8 reserved_at_1b8[0x8];
8385c51f 652
3afee4ed 653 u8 reserved_at_1c0[0x40];
71c6e863
AL		 654};
655
b169e64a 656struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 657 u8 inner_tcp_seq_num[0x20];
658
659 u8 outer_tcp_seq_num[0x20];
660
661 u8 inner_tcp_ack_num[0x20];
662
663 u8 outer_tcp_ack_num[0x20];
664
665 u8 reserved_at_80[0x8];
666 u8 outer_vxlan_gpe_vni[0x18];
667
668 u8 outer_vxlan_gpe_next_protocol[0x8];
669 u8 outer_vxlan_gpe_flags[0x8];
670 u8 reserved_at_b0[0x10];
671
672 u8 icmp_header_data[0x20];
673
674 u8 icmpv6_header_data[0x20];
675
676 u8 icmp_type[0x8];
677 u8 icmp_code[0x8];
678 u8 icmpv6_type[0x8];
679 u8 icmpv6_code[0x8];
680
b169e64a 681 u8 geneve_tlv_option_0_data[0x20];
97b5484e 682
704cfecd
YK		 683 u8 gtpu_teid[0x20];
684
685 u8 gtpu_msg_type[0x8];
686 u8 gtpu_msg_flags[0x8];
687 u8 reserved_at_170[0x10];
688
689 u8 gtpu_dw_2[0x20];
690
691 u8 gtpu_first_ext_dw_0[0x20];
692
693 u8 gtpu_dw_0[0x20];
694
695 u8 reserved_at_1e0[0x20];
b169e64a
YK		 696};
697
7da3ad6c
MS		 698struct mlx5_ifc_fte_match_set_misc4_bits {
699 u8 prog_sample_field_value_0[0x20];
700
701 u8 prog_sample_field_id_0[0x20];
702
703 u8 prog_sample_field_value_1[0x20];
704
705 u8 prog_sample_field_id_1[0x20];
706
707 u8 prog_sample_field_value_2[0x20];
708
709 u8 prog_sample_field_id_2[0x20];
710
711 u8 prog_sample_field_value_3[0x20];
712
713 u8 prog_sample_field_id_3[0x20];
714
715 u8 reserved_at_100[0x100];
716};
717
0f2a6c3b
MS		 718struct mlx5_ifc_fte_match_set_misc5_bits {
719 u8 macsec_tag_0[0x20];
720
721 u8 macsec_tag_1[0x20];
722
723 u8 macsec_tag_2[0x20];
724
725 u8 macsec_tag_3[0x20];
726
727 u8 tunnel_header_0[0x20];
728
729 u8 tunnel_header_1[0x20];
730
731 u8 tunnel_header_2[0x20];
732
733 u8 tunnel_header_3[0x20];
734
735 u8 reserved_at_100[0x100];
736};
737
e281682b
SM		 738struct mlx5_ifc_cmd_pas_bits {
739 u8 pa_h[0x20];
740
741 u8 pa_l[0x14];
b4ff3a36 742 u8 reserved_at_34[0xc];
e281682b
SM		 743};
744
745struct mlx5_ifc_uint64_bits {
746 u8 hi[0x20];
747
748 u8 lo[0x20];
749};
750
751enum {
752 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
753 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
754 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
755 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
756 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
757 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
758 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
759 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
760 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
761 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
762};
763
764struct mlx5_ifc_ads_bits {
765 u8 fl[0x1];
766 u8 free_ar[0x1];
b4ff3a36 767 u8 reserved_at_2[0xe];
e281682b
SM		 768 u8 pkey_index[0x10];
769
b4ff3a36 770 u8 reserved_at_20[0x8];
e281682b
SM		 771 u8 grh[0x1];
772 u8 mlid[0x7];
773 u8 rlid[0x10];
774
775 u8 ack_timeout[0x5];
b4ff3a36 776 u8 reserved_at_45[0x3];
e281682b 777 u8 src_addr_index[0x8];
b4ff3a36 778 u8 reserved_at_50[0x4];
e281682b
SM		 779 u8 stat_rate[0x4];
780 u8 hop_limit[0x8];
781
b4ff3a36 782 u8 reserved_at_60[0x4];
e281682b
SM		 783 u8 tclass[0x8];
784 u8 flow_label[0x14];
785
786 u8 rgid_rip[16][0x8];
787
b4ff3a36 788 u8 reserved_at_100[0x4];
e281682b
SM		 789 u8 f_dscp[0x1];
790 u8 f_ecn[0x1];
b4ff3a36 791 u8 reserved_at_106[0x1];
e281682b
SM		 792 u8 f_eth_prio[0x1];
793 u8 ecn[0x2];
794 u8 dscp[0x6];
795 u8 udp_sport[0x10];
796
797 u8 dei_cfi[0x1];
798 u8 eth_prio[0x3];
799 u8 sl[0x4];
32f69e4b 800 u8 vhca_port_num[0x8];
e281682b
SM		 801 u8 rmac_47_32[0x10];
802
803 u8 rmac_31_0[0x20];
804};
805
806struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 807 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 808 u8 nic_rx_multi_path_tirs_fts[0x1];
809 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 810 u8 reserved_at_3[0x4];
811 u8 sw_owner_reformat_supported[0x1];
812 u8 reserved_at_8[0x18];
813
bea4e1f6
MB		 814 u8 encap_general_header[0x1];
815 u8 reserved_at_21[0xa];
816 u8 log_max_packet_reformat_context[0x5];
817 u8 reserved_at_30[0x6];
818 u8 max_encap_header_size[0xa];
819 u8 reserved_at_40[0x1c0];
e281682b
SM		 820
821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
822
d83eb50e 823 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 824
825 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
826
827 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
828
24670b1a 829 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 830
831 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
832
8208461d
AL		 833 u8 reserved_at_e00[0x700];
834
835 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
836
837 u8 reserved_at_1580[0x280];
838
839 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
840
841 u8 reserved_at_1880[0x780];
97b5484e
AV		 842
843 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
844
845 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
846
847 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
848
849 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 850};
851
425a563a
MG		 852struct mlx5_ifc_port_selection_cap_bits {
853 u8 reserved_at_0[0x10];
854 u8 port_select_flow_table[0x1];
8d1ac895
LC		 855 u8 reserved_at_11[0x1];
856 u8 port_select_flow_table_bypass[0x1];
857 u8 reserved_at_13[0xd];
425a563a
MG		 858
859 u8 reserved_at_20[0x1e0];
860
861 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
862
863 u8 reserved_at_400[0x7c00];
864};
865
65c0f2c1
JL		 866enum {
867 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
868 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
869 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
870 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
871 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
872 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
873 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
874 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
875};
876
495716b1 877struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 878 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 879 u8 reserved_at_8[0xd];
880 u8 fdb_modify_header_fwd_to_table[0x1];
4ff725e1 881 u8 fdb_ipv4_ttl_modify[0x1];
65c0f2c1
JL		 882 u8 flow_source[0x1];
883 u8 reserved_at_18[0x2];
b9aa0ba1 884 u8 multi_fdb_encap[0x1];
86f5d0f3 885 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 886 u8 fdb_multi_path_to_table[0x1];
887 u8 reserved_at_1d[0x3];
888
889 u8 reserved_at_20[0x1e0];
495716b1
SM		 890
891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
892
893 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
894
895 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
896
97b5484e
AV		 897 u8 reserved_at_800[0x1000];
898
899 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
900
901 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
902
903 u8 sw_steering_uplink_icm_address_rx[0x40];
904
905 u8 sw_steering_uplink_icm_address_tx[0x40];
906
907 u8 reserved_at_1900[0x6700];
495716b1
SM		 908};
909
8bb957d2
SK		 910enum {
911 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
912 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
913};
914
d6666753
SM		 915struct mlx5_ifc_e_switch_cap_bits {
916 u8 vport_svlan_strip[0x1];
917 u8 vport_cvlan_strip[0x1];
918 u8 vport_svlan_insert[0x1];
919 u8 vport_cvlan_insert_if_not_exist[0x1];
920 u8 vport_cvlan_insert_overwrite[0x1];
1f0ae22a
MS		 921 u8 reserved_at_5[0x1];
922 u8 vport_cvlan_insert_always[0x1];
c3e666f1 923 u8 esw_shared_ingress_acl[0x1];
65c0f2c1 924 u8 esw_uplink_ingress_acl[0x1];
c3e666f1
MB		 925 u8 root_ft_on_other_esw[0x1];
926 u8 reserved_at_a[0xf];
6706a3b9
VP		 927 u8 esw_functions_changed[0x1];
928 u8 reserved_at_1a[0x1];
81cd229c 929 u8 ecpf_vport_exists[0x1];
8bb957d2 930 u8 counter_eswitch_affinity[0x1];
a6d04569 931 u8 merged_eswitch[0x1];
23898c76
NO		 932 u8 nic_vport_node_guid_modify[0x1];
933 u8 nic_vport_port_guid_modify[0x1];
d6666753 934
7adbde20
HHZ		 935 u8 vxlan_encap_decap[0x1];
936 u8 nvgre_encap_decap[0x1];
1b115498
EB		 937 u8 reserved_at_22[0x1];
938 u8 log_max_fdb_encap_uplink[0x5];
939 u8 reserved_at_21[0x3];
60786f09 940 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 941 u8 reserved_2b[0x6];
942 u8 max_encap_header_size[0xa];
943
1759d322
PP		 944 u8 reserved_at_40[0xb];
945 u8 log_max_esw_sf[0x5];
946 u8 esw_sf_base_id[0x10];
947
948 u8 reserved_at_60[0x7a0];
7adbde20 949
d6666753
SM		 950};
951
7486216b
SM		 952struct mlx5_ifc_qos_cap_bits {
953 u8 packet_pacing[0x1];
813f8540 954 u8 esw_scheduling[0x1];
c9497c98
MHY		 955 u8 esw_bw_share[0x1];
956 u8 esw_rate_limit[0x1];
05d3ac97
BW		 957 u8 reserved_at_4[0x1];
958 u8 packet_pacing_burst_bound[0x1];
959 u8 packet_pacing_typical_size[0x1];
214baf22
MM		 960 u8 reserved_at_7[0x1];
961 u8 nic_sq_scheduling[0x1];
962 u8 nic_bw_share[0x1];
963 u8 nic_rate_limit[0x1];
1326034b 964 u8 packet_pacing_uid[0x1];
1ae258f8
DL		 965 u8 log_esw_max_sched_depth[0x4];
966 u8 reserved_at_10[0x10];
813f8540 967
214baf22
MM		 968 u8 reserved_at_20[0xb];
969 u8 log_max_qos_nic_queue_group[0x5];
970 u8 reserved_at_30[0x10];
813f8540 971
7486216b 972 u8 packet_pacing_max_rate[0x20];
813f8540 973
7486216b 974 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 975
976 u8 reserved_at_80[0x10];
7486216b 977 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 978
979 u8 esw_element_type[0x10];
980 u8 esw_tsar_type[0x10];
981
982 u8 reserved_at_c0[0x10];
983 u8 max_qos_para_vport[0x10];
984
985 u8 max_tsar_bw_share[0x20];
986
f5d23ee1
JL		 987 u8 reserved_at_100[0x20];
988
989 u8 reserved_at_120[0x3];
990 u8 log_meter_aso_granularity[0x5];
991 u8 reserved_at_128[0x3];
992 u8 log_meter_aso_max_alloc[0x5];
993 u8 reserved_at_130[0x3];
994 u8 log_max_num_meter_aso[0x5];
995 u8 reserved_at_138[0x8];
996
997 u8 reserved_at_140[0x6c0];
7486216b
SM		 998};
999
2fcb12df 1000struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 1001 u8 core_dump_general[0x1];
1002 u8 core_dump_qp[0x1];
609b8272
AL		 1003 u8 reserved_at_2[0x7];
1004 u8 resource_dump[0x1];
1005 u8 reserved_at_a[0x16];
2fcb12df
IK		 1006
1007 u8 reserved_at_20[0x2];
1008 u8 stall_detect[0x1];
1009 u8 reserved_at_23[0x1d];
1010
1011 u8 reserved_at_40[0x7c0];
1012};
1013
e281682b
SM		 1014struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1015 u8 csum_cap[0x1];
1016 u8 vlan_cap[0x1];
1017 u8 lro_cap[0x1];
1018 u8 lro_psh_flag[0x1];
1019 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 1020 u8 reserved_at_5[0x2];
1021 u8 wqe_vlan_insert[0x1];
66189961 1022 u8 self_lb_en_modifiable[0x1];
b4ff3a36 1023 u8 reserved_at_9[0x2];
e281682b 1024 u8 max_lso_cap[0x5];
c226dc22 1025 u8 multi_pkt_send_wqe[0x2];
cff92d7c 1026 u8 wqe_inline_mode[0x2];
e281682b 1027 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 1028 u8 reg_umr_sq[0x1];
1029 u8 scatter_fcs[0x1];
050da902 1030 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 1031 u8 tunnel_lso_const_out_ip_id[0x1];
26ab7b38
MM		 1032 u8 tunnel_lro_gre[0x1];
1033 u8 tunnel_lro_vxlan[0x1];
27299841 1034 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 1035 u8 tunnel_stateless_vxlan[0x1];
1036
547eede0
IT		 1037 u8 swp[0x1];
1038 u8 swp_csum[0x1];
1039 u8 swp_lso[0x1];
db849faa 1040 u8 cqe_checksum_full[0x1];
41e684ef
AV		 1041 u8 tunnel_stateless_geneve_tx[0x1];
1042 u8 tunnel_stateless_mpls_over_udp[0x1];
1043 u8 tunnel_stateless_mpls_over_gre[0x1];
1044 u8 tunnel_stateless_vxlan_gpe[0x1];
1045 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 1046 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 1047 u8 insert_trailer[0x1];
21adf05d
AL		 1048 u8 reserved_at_2b[0x1];
1049 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1050 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1051 u8 reserved_at_2e[0x2];
22a65aa8
GP		 1052 u8 max_vxlan_udp_ports[0x8];
1053 u8 reserved_at_38[0x6];
4d350f1f
MG		 1054 u8 max_geneve_opt_len[0x1];
1055 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 1056
b4ff3a36 1057 u8 reserved_at_40[0x10];
e281682b
SM		 1058 u8 lro_min_mss_size[0x10];
1059
b4ff3a36 1060 u8 reserved_at_60[0x120];
e281682b
SM		 1061
1062 u8 lro_timer_supported_periods[4][0x20];
1063
b4ff3a36 1064 u8 reserved_at_200[0x600];
e281682b
SM		 1065};
1066
a6a217dd 1067enum {
9a1ac95a
AL		 1068 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1069 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1070 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
a6a217dd
AL		 1071};
1072
e281682b
SM		 1073struct mlx5_ifc_roce_cap_bits {
1074 u8 roce_apm[0x1];
59e9e8e4
MZ		 1075 u8 reserved_at_1[0x3];
1076 u8 sw_r_roce_src_udp_port[0x1];
7304d603
YK		 1077 u8 fl_rc_qp_when_roce_disabled[0x1];
1078 u8 fl_rc_qp_when_roce_enabled[0x1];
1079 u8 reserved_at_7[0x17];
a6a217dd 1080 u8 qp_ts_format[0x2];
e281682b 1081
b4ff3a36 1082 u8 reserved_at_20[0x60];
e281682b 1083
b4ff3a36 1084 u8 reserved_at_80[0xc];
e281682b 1085 u8 l3_type[0x4];
b4ff3a36 1086 u8 reserved_at_90[0x8];
e281682b
SM		 1087 u8 roce_version[0x8];
1088
b4ff3a36 1089 u8 reserved_at_a0[0x10];
e281682b
SM		 1090 u8 r_roce_dest_udp_port[0x10];
1091
1092 u8 r_roce_max_src_udp_port[0x10];
1093 u8 r_roce_min_src_udp_port[0x10];
1094
b4ff3a36 1095 u8 reserved_at_e0[0x10];
e281682b
SM		 1096 u8 roce_address_table_size[0x10];
1097
b4ff3a36 1098 u8 reserved_at_100[0x700];
e281682b
SM		 1099};
1100
97b5484e
AV		 1101struct mlx5_ifc_sync_steering_in_bits {
1102 u8 opcode[0x10];
1103 u8 uid[0x10];
1104
1105 u8 reserved_at_20[0x10];
1106 u8 op_mod[0x10];
1107
1108 u8 reserved_at_40[0xc0];
1109};
1110
1111struct mlx5_ifc_sync_steering_out_bits {
1112 u8 status[0x8];
1113 u8 reserved_at_8[0x18];
1114
1115 u8 syndrome[0x20];
1116
1117 u8 reserved_at_40[0x40];
1118};
1119
e72bd817
AL		 1120struct mlx5_ifc_device_mem_cap_bits {
1121 u8 memic[0x1];
1122 u8 reserved_at_1[0x1f];
1123
1124 u8 reserved_at_20[0xb];
1125 u8 log_min_memic_alloc_size[0x5];
1126 u8 reserved_at_30[0x8];
1127 u8 log_max_memic_addr_alignment[0x8];
1128
1129 u8 memic_bar_start_addr[0x40];
1130
1131 u8 memic_bar_size[0x20];
1132
1133 u8 max_memic_size[0x20];
1134
9fba2b9b
AL		 1135 u8 steering_sw_icm_start_address[0x40];
1136
1137 u8 reserved_at_100[0x8];
1138 u8 log_header_modify_sw_icm_size[0x8];
1139 u8 reserved_at_110[0x2];
1140 u8 log_sw_icm_alloc_granularity[0x6];
1141 u8 log_steering_sw_icm_size[0x8];
1142
795e10b4
YK		 1143 u8 reserved_at_120[0x18];
1144 u8 log_header_modify_pattern_sw_icm_size[0x8];
9fba2b9b
AL		 1145
1146 u8 header_modify_sw_icm_start_address[0x40];
1147
795e10b4
YK		 1148 u8 reserved_at_180[0x40];
1149
1150 u8 header_modify_pattern_sw_icm_start_address[0x40];
63f9c44b
MG		 1151
1152 u8 memic_operations[0x20];
1153
1154 u8 reserved_at_220[0x5e0];
e72bd817
AL		 1155};
1156
b9a7ba55
YH		 1157struct mlx5_ifc_device_event_cap_bits {
1158 u8 user_affiliated_events[4][0x40];
1159
1160 u8 user_unaffiliated_events[4][0x40];
1161};
1162
8a06a79b
EC		 1163struct mlx5_ifc_virtio_emulation_cap_bits {
1164 u8 desc_tunnel_offload_type[0x1];
1165 u8 eth_frame_offload_type[0x1];
1166 u8 virtio_version_1_0[0x1];
1167 u8 device_features_bits_mask[0xd];
1168 u8 event_mode[0x8];
1169 u8 virtio_queue_type[0x8];
90fbca59 1170
8a06a79b
EC		 1171 u8 max_tunnel_desc[0x10];
1172 u8 reserved_at_30[0x3];
90fbca59
YH		 1173 u8 log_doorbell_stride[0x5];
1174 u8 reserved_at_38[0x3];
1175 u8 log_doorbell_bar_size[0x5];
1176
1177 u8 doorbell_bar_offset[0x40];
1178
8a06a79b
EC		 1179 u8 max_emulated_devices[0x8];
1180 u8 max_num_virtio_queues[0x18];
1181
1182 u8 reserved_at_a0[0x60];
1183
1184 u8 umem_1_buffer_param_a[0x20];
1185
1186 u8 umem_1_buffer_param_b[0x20];
1187
1188 u8 umem_2_buffer_param_a[0x20];
1189
1190 u8 umem_2_buffer_param_b[0x20];
1191
1192 u8 umem_3_buffer_param_a[0x20];
1193
1194 u8 umem_3_buffer_param_b[0x20];
1195
1196 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1197};
1198
e281682b
SM		 1199enum {
1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1209};
1210
1211enum {
1212 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1213 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1214 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1215 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1216 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1217 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1218 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1219 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1220 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1221};
1222
1223struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1224 u8 reserved_at_0[0x40];
e281682b 1225
bd10838a 1226 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1227 u8 reserved_at_42[0x4];
bd10838a 1228 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1229
b4ff3a36 1230 u8 reserved_at_47[0x19];
e281682b 1231
b4ff3a36 1232 u8 reserved_at_60[0x20];
e281682b 1233
b4ff3a36 1234 u8 reserved_at_80[0x10];
f91e6d89 1235 u8 atomic_operations[0x10];
e281682b 1236
b4ff3a36 1237 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1238 u8 atomic_size_qp[0x10];
1239
b4ff3a36 1240 u8 reserved_at_c0[0x10];
e281682b
SM		 1241 u8 atomic_size_dc[0x10];
1242
b4ff3a36 1243 u8 reserved_at_e0[0x720];
e281682b
SM		 1244};
1245
1246struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1247 u8 reserved_at_0[0x40];
e281682b
SM		 1248
1249 u8 sig[0x1];
b4ff3a36 1250 u8 reserved_at_41[0x1f];
e281682b 1251
b4ff3a36 1252 u8 reserved_at_60[0x20];
e281682b
SM		 1253
1254 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1255
1256 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1257
1258 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1259
dda7a817
MS		 1260 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1261
00679b63
MG		 1262 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1263
1264 u8 reserved_at_120[0x6E0];
e281682b
SM		 1265};
1266
3f0393a5
SG		 1267struct mlx5_ifc_calc_op {
1268 u8 reserved_at_0[0x10];
1269 u8 reserved_at_10[0x9];
1270 u8 op_swap_endianness[0x1];
1271 u8 op_min[0x1];
1272 u8 op_xor[0x1];
1273 u8 op_or[0x1];
1274 u8 op_and[0x1];
1275 u8 op_max[0x1];
1276 u8 op_add[0x1];
1277};
1278
1279struct mlx5_ifc_vector_calc_cap_bits {
1280 u8 calc_matrix[0x1];
1281 u8 reserved_at_1[0x1f];
1282 u8 reserved_at_20[0x8];
1283 u8 max_vec_count[0x8];
1284 u8 reserved_at_30[0xd];
1285 u8 max_chunk_size[0x3];
1286 struct mlx5_ifc_calc_op calc0;
1287 struct mlx5_ifc_calc_op calc1;
1288 struct mlx5_ifc_calc_op calc2;
1289 struct mlx5_ifc_calc_op calc3;
1290
c74d90c1 1291 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1292};
1293
a12ff35e
EBE		 1294struct mlx5_ifc_tls_cap_bits {
1295 u8 tls_1_2_aes_gcm_128[0x1];
1296 u8 tls_1_3_aes_gcm_128[0x1];
1297 u8 tls_1_2_aes_gcm_256[0x1];
1298 u8 tls_1_3_aes_gcm_256[0x1];
1299 u8 reserved_at_4[0x1c];
1300
1301 u8 reserved_at_20[0x7e0];
1302};
1303
2b58f6d9
RS		 1304struct mlx5_ifc_ipsec_cap_bits {
1305 u8 ipsec_full_offload[0x1];
1306 u8 ipsec_crypto_offload[0x1];
1307 u8 ipsec_esn[0x1];
1308 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1309 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1310 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1311 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1312 u8 reserved_at_7[0x4];
1313 u8 log_max_ipsec_offload[0x5];
1314 u8 reserved_at_10[0x10];
1315
1316 u8 min_log_ipsec_full_replay_window[0x8];
1317 u8 max_log_ipsec_full_replay_window[0x8];
1318 u8 reserved_at_30[0x7d0];
1319};
1320
8385c51f
LN		 1321struct mlx5_ifc_macsec_cap_bits {
1322 u8 macsec_epn[0x1];
1323 u8 reserved_at_1[0x2];
1324 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1325 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1326 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1327 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1328 u8 reserved_at_7[0x4];
1329 u8 log_max_macsec_offload[0x5];
1330 u8 reserved_at_10[0x10];
1331
1332 u8 min_log_macsec_full_replay_window[0x8];
1333 u8 max_log_macsec_full_replay_window[0x8];
1334 u8 reserved_at_30[0x10];
1335
1336 u8 reserved_at_40[0x7c0];
1337};
1338
e281682b
SM		 1339enum {
1340 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1341 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1342 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1343 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1344};
1345
1346enum {
1347 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1348 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1349};
1350
1351enum {
1352 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1353 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1354 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1355 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1356 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1357};
1358
1359enum {
1360 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1361 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1362 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1363 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1364 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1365 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1366};
1367
1368enum {
1369 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1370 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1371};
1372
1373enum {
1374 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1375 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1376 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1377};
1378
1379enum {
1380 MLX5_CAP_PORT_TYPE_IB = 0x0,
1381 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1382};
1383
1410a90a
MG		 1384enum {
1385 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1386 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1387 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1388};
1389
97b5484e 1390enum {
a18fab48 1391 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
704cfecd 1392 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
c3fb0e28 1393 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
97b5484e
AV		 1394 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1395 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1396 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
704cfecd
YK		 1397 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1398 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1399 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1400 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1401 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1402 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
97b5484e
AV		 1403};
1404
9d43faac
YH		 1405enum {
1406 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1407 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1408};
1409
8536a6bf
GT		 1410#define MLX5_FC_BULK_SIZE_FACTOR 128
1411
1412enum mlx5_fc_bulk_alloc_bitmask {
1413 MLX5_FC_BULK_128 = (1 << 0),
1414 MLX5_FC_BULK_256 = (1 << 1),
1415 MLX5_FC_BULK_512 = (1 << 2),
1416 MLX5_FC_BULK_1024 = (1 << 3),
1417 MLX5_FC_BULK_2048 = (1 << 4),
1418 MLX5_FC_BULK_4096 = (1 << 5),
1419 MLX5_FC_BULK_8192 = (1 << 6),
1420 MLX5_FC_BULK_16384 = (1 << 7),
1421};
1422
1423#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1424
216214c6
YK		 1425#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1426
d421e466
YK		 1427enum {
1428 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1429 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
6862c787 1430 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
d421e466
YK		 1431};
1432
b775516b 1433struct mlx5_ifc_cmd_hca_cap_bits {
f484da84
MB		 1434 u8 reserved_at_0[0x10];
1435 u8 shared_object_to_user_object_allowed[0x1];
1436 u8 reserved_at_13[0xe];
959af556 1437 u8 vhca_resource_manager[0x1];
349125ba 1438
67133eaa 1439 u8 hca_cap_2[0x1];
94db3317 1440 u8 create_lag_when_not_master_up[0x1];
4b2c5fa9 1441 u8 dtor[0x1];
349125ba
PP		 1442 u8 event_on_vhca_state_teardown_request[0x1];
1443 u8 event_on_vhca_state_in_use[0x1];
1444 u8 event_on_vhca_state_active[0x1];
1445 u8 event_on_vhca_state_allocated[0x1];
1446 u8 event_on_vhca_state_invalid[0x1];
1447 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1448 u8 vhca_id[0x10];
1449
1450 u8 reserved_at_40[0x40];
b775516b
EC		 1451
1452 u8 log_max_srq_sz[0x8];
1453 u8 log_max_qp_sz[0x8];
b9a7ba55 1454 u8 event_cap[0x1];
aeacb52a
YK		 1455 u8 reserved_at_91[0x2];
1456 u8 isolate_vl_tc_new[0x1];
1457 u8 reserved_at_94[0x4];
316793fb
EB		 1458 u8 prio_tag_required[0x1];
1459 u8 reserved_at_99[0x2];
b775516b
EC		 1460 u8 log_max_qp[0x5];
1461
6b646a7e
LR		 1462 u8 reserved_at_a0[0x3];
1463 u8 ece_support[0x1];
838b00a2
PB		 1464 u8 reserved_at_a4[0x5];
1465 u8 reg_c_preserve[0x1];
1466 u8 reserved_at_aa[0x1];
e281682b 1467 u8 log_max_srq[0x5];
9c9be85f
AL		 1468 u8 reserved_at_b0[0x1];
1469 u8 uplink_follow[0x1];
59d2ae1d 1470 u8 ts_cqe_to_dest_cqn[0x1];
7025329d
BBI		 1471 u8 reserved_at_b3[0x7];
1472 u8 shampo[0x1];
1473 u8 reserved_at_bb[0x5];
b775516b 1474
7d47433c 1475 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1476 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1477 u8 relaxed_ordering_write_umr[0x1];
1478 u8 relaxed_ordering_read_umr[0x1];
1479 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1480 u8 virtio_net_device_emualtion_manager[0x1];
1481 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1482 u8 log_max_cq[0x5];
1483
1484 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1485 u8 relaxed_ordering_write[0x1];
1486 u8 relaxed_ordering_read[0x1];
b775516b 1487 u8 log_max_mkey[0x6];
4b7296aa
OHT		 1488 u8 reserved_at_f0[0x6];
1489 u8 terminate_scatter_list_mkey[0x1];
1490 u8 repeated_mkey[0x1];
b183ee27 1491 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1492 u8 reserved_at_f9[0x2];
1493 u8 fast_teardown[0x1];
b775516b
EC		 1494 u8 log_max_eq[0x4];
1495
1496 u8 max_indirection[0x8];
bcda1aca 1497 u8 fixed_buffer_size[0x1];
b775516b 1498 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1499 u8 force_teardown[0x1];
1500 u8 reserved_at_111[0x1];
b775516b 1501 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1502 u8 umr_extended_translation_offset[0x1];
1503 u8 null_mkey[0x1];
b775516b
EC		 1504 u8 log_max_klm_list_size[0x6];
1505
9b2e3723
PH		 1506 u8 reserved_at_120[0x2];
1507 u8 qpc_extension[0x1];
1508 u8 reserved_at_123[0x7];
b775516b 1509 u8 log_max_ra_req_dc[0x6];
16ab85e7
GP		 1510 u8 reserved_at_130[0x2];
1511 u8 eth_wqe_too_small[0x1];
1512 u8 reserved_at_133[0x6];
3e94e61b 1513 u8 vnic_env_cq_overrun[0x1];
b775516b
EC		 1514 u8 log_max_ra_res_dc[0x6];
1515
d2cb8dda 1516 u8 reserved_at_140[0x5];
0e1533bb 1517 u8 release_all_pages[0x1];
d2cb8dda 1518 u8 must_not_use[0x1];
0e1533bb 1519 u8 reserved_at_147[0x2];
8fd5b75d 1520 u8 roce_accl[0x1];
b775516b 1521 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1522 u8 reserved_at_150[0xa];
b775516b
EC		 1523 u8 log_max_ra_res_qp[0x6];
1524
f32f5bd2 1525 u8 end_pad[0x1];
b775516b
EC		 1526 u8 cc_query_allowed[0x1];
1527 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1528 u8 start_pad[0x1];
1529 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1530 u8 reserved_at_165[0x4];
1531 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1532 u8 reserved_at_16a[0x2];
1533 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1534 u8 sbcam_reg[0x1];
1535 u8 reserved_at_16e[0x1];
c02762eb 1536 u8 qcam_reg[0x1];
e281682b 1537 u8 gid_table_size[0x10];
b775516b 1538
e281682b
SM		 1539 u8 out_of_seq_cnt[0x1];
1540 u8 vport_counters[0x1];
7486216b 1541 u8 retransmission_q_counters[0x1];
2fcb12df 1542 u8 debug[0x1];
83b502a1 1543 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1544 u8 rq_delay_drop[0x1];
b775516b
EC		 1545 u8 max_qp_cnt[0xa];
1546 u8 pkey_table_size[0x10];
1547
e281682b
SM		 1548 u8 vport_group_manager[0x1];
1549 u8 vhca_group_manager[0x1];
1550 u8 ib_virt[0x1];
1551 u8 eth_virt[0x1];
61c5b5c9 1552 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1553 u8 ets[0x1];
1554 u8 nic_flow_table[0x1];
0efc8562 1555 u8 eswitch_manager[0x1];
e72bd817 1556 u8 device_memory[0x1];
cfdcbcea
GP		 1557 u8 mcam_reg[0x1];
1558 u8 pcam_reg[0x1];
b775516b 1559 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1560 u8 port_module_event[0x1];
58dcb60a 1561 u8 enhanced_error_q_counters[0x1];
7d5e1423 1562 u8 ports_check[0x1];
7b13558f 1563 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1564 u8 disable_link_up[0x1];
1565 u8 beacon_led[0x1];
e281682b 1566 u8 port_type[0x2];
b775516b
EC		 1567 u8 num_ports[0x8];
1568
f9a1ef72
EE		 1569 u8 reserved_at_1c0[0x1];
1570 u8 pps[0x1];
1571 u8 pps_modify[0x1];
b775516b 1572 u8 log_max_msg[0x5];
e1c9c62b 1573 u8 reserved_at_1c8[0x4];
4f3961ee 1574 u8 max_tc[0x4];
1865ea9a 1575 u8 temp_warn_event[0x1];
7486216b 1576 u8 dcbx[0x1];
246ac981
MG		 1577 u8 general_notification_event[0x1];
1578 u8 reserved_at_1d3[0x2];
e29341fb 1579 u8 fpga[0x1];
928cfe87
TT		 1580 u8 rol_s[0x1];
1581 u8 rol_g[0x1];
e1c9c62b 1582 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1583 u8 wol_s[0x1];
1584 u8 wol_g[0x1];
1585 u8 wol_a[0x1];
1586 u8 wol_b[0x1];
1587 u8 wol_m[0x1];
1588 u8 wol_u[0x1];
1589 u8 wol_p[0x1];
b775516b
EC		 1590
1591 u8 stat_rate_support[0x10];
3df01077
MS		 1592 u8 reserved_at_1f0[0x1];
1593 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1594 u8 reserved_at_1f2[0x6];
1595 u8 init2_lag_tx_port_affinity[0x1];
1596 u8 reserved_at_1fa[0x3];
e281682b 1597 u8 cqe_version[0x4];
b775516b 1598
e281682b 1599 u8 compact_address_vector[0x1];
7d5e1423 1600 u8 striding_rq[0x1];
500a3d0d
ES		 1601 u8 reserved_at_202[0x1];
1602 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1603 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1604 u8 reserved_at_205[0x1];
1605 u8 repeated_block_disabled[0x1];
1606 u8 umr_modify_entity_size_disabled[0x1];
1607 u8 umr_modify_atomic_disabled[0x1];
1608 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1609 u8 umr_fence[0x2];
94a04d1d
YC		 1610 u8 dc_req_scat_data_cqe[0x1];
1611 u8 reserved_at_20d[0x2];
e281682b 1612 u8 drain_sigerr[0x1];
b775516b
EC		 1613 u8 cmdif_checksum[0x2];
1614 u8 sigerr_cqe[0x1];
e1c9c62b 1615 u8 reserved_at_213[0x1];
b775516b
EC		 1616 u8 wq_signature[0x1];
1617 u8 sctr_data_cqe[0x1];
e1c9c62b 1618 u8 reserved_at_216[0x1];
b775516b
EC		 1619 u8 sho[0x1];
1620 u8 tph[0x1];
1621 u8 rf[0x1];
e281682b 1622 u8 dct[0x1];
7486216b 1623 u8 qos[0x1];
e281682b 1624 u8 eth_net_offloads[0x1];
b775516b
EC		 1625 u8 roce[0x1];
1626 u8 atomic[0x1];
e1c9c62b 1627 u8 reserved_at_21f[0x1];
b775516b
EC		 1628
1629 u8 cq_oi[0x1];
1630 u8 cq_resize[0x1];
1631 u8 cq_moderation[0x1];
e1c9c62b 1632 u8 reserved_at_223[0x3];
e281682b 1633 u8 cq_eq_remap[0x1];
b775516b
EC		 1634 u8 pg[0x1];
1635 u8 block_lb_mc[0x1];
e1c9c62b 1636 u8 reserved_at_229[0x1];
e281682b 1637 u8 scqe_break_moderation[0x1];
7d5e1423 1638 u8 cq_period_start_from_cqe[0x1];
b775516b 1639 u8 cd[0x1];
e1c9c62b 1640 u8 reserved_at_22d[0x1];
b775516b 1641 u8 apm[0x1];
3f0393a5 1642 u8 vector_calc[0x1];
7d5e1423 1643 u8 umr_ptr_rlky[0x1];
d2370e0a 1644 u8 imaicl[0x1];
3fd3c80a
DG		 1645 u8 qp_packet_based[0x1];
1646 u8 reserved_at_233[0x3];
b775516b
EC		 1647 u8 qkv[0x1];
1648 u8 pkv[0x1];
b11a4f9c
HE		 1649 u8 set_deth_sqpn[0x1];
1650 u8 reserved_at_239[0x3];
b775516b
EC		 1651 u8 xrc[0x1];
1652 u8 ud[0x1];
1653 u8 uc[0x1];
1654 u8 rc[0x1];
1655
a6d51b68
EC		 1656 u8 uar_4k[0x1];
1657 u8 reserved_at_241[0x9];
b775516b 1658 u8 uar_sz[0x6];
425a563a
MG		 1659 u8 port_selection_cap[0x1];
1660 u8 reserved_at_248[0x1];
e13cd45d
EC		 1661 u8 umem_uid_0[0x1];
1662 u8 reserved_at_250[0x5];
b775516b
EC		 1663 u8 log_pg_sz[0x8];
1664
1665 u8 bf[0x1];
0dbc6fe0 1666 u8 driver_version[0x1];
e281682b 1667 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1668 u8 reserved_at_263[0x3];
1669 u8 mkey_by_name[0x1];
1670 u8 reserved_at_267[0x4];
1671
b775516b 1672 u8 log_bf_reg_size[0x5];
84df61eb 1673
9b2e3723
PH		 1674 u8 reserved_at_270[0x3];
1675 u8 qp_error_syndrome[0x1];
1676 u8 reserved_at_274[0x2];
7c4b1ab9 1677 u8 lag_dct[0x2];
1eba383f 1678 u8 lag_tx_port_affinity[0x1];
c3e666f1
MB		 1679 u8 lag_native_fdb_selection[0x1];
1680 u8 reserved_at_27a[0x1];
84df61eb
AH		 1681 u8 lag_master[0x1];
1682 u8 num_lag_ports[0x4];
b775516b 1683
e1c9c62b 1684 u8 reserved_at_280[0x10];
b775516b
EC		 1685 u8 max_wqe_sz_sq[0x10];
1686
e1c9c62b 1687 u8 reserved_at_2a0[0x10];
b775516b
EC		 1688 u8 max_wqe_sz_rq[0x10];
1689
a8ffcc74 1690 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1691 u8 max_wqe_sz_sq_dc[0x10];
1692
e1c9c62b 1693 u8 reserved_at_2e0[0x7];
b775516b
EC		 1694 u8 max_qp_mcg[0x19];
1695
8536a6bf
GT		 1696 u8 reserved_at_300[0x10];
1697 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1698 u8 log_max_mcg[0x8];
1699
e1c9c62b 1700 u8 reserved_at_320[0x3];
e281682b 1701 u8 log_max_transport_domain[0x5];
e1c9c62b 1702 u8 reserved_at_328[0x3];
b775516b 1703 u8 log_max_pd[0x5];
e1c9c62b 1704 u8 reserved_at_330[0xb];
b775516b
EC		 1705 u8 log_max_xrcd[0x5];
1706
5c298143 1707 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1708 u8 receive_discard_vport_down[0x1];
1709 u8 transmit_discard_vport_down[0x1];
3e94e61b
SM		 1710 u8 eq_overrun_count[0x1];
1711 u8 reserved_at_344[0x1];
1712 u8 invalid_command_count[0x1];
1713 u8 quota_exceeded_count[0x1];
1714 u8 reserved_at_347[0x1];
a351a1b0 1715 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1716 u8 max_flow_counter_15_0[0x10];
a351a1b0 1717
b775516b 1718
e1c9c62b 1719 u8 reserved_at_360[0x3];
b775516b 1720 u8 log_max_rq[0x5];
e1c9c62b 1721 u8 reserved_at_368[0x3];
b775516b 1722 u8 log_max_sq[0x5];
e1c9c62b 1723 u8 reserved_at_370[0x3];
b775516b 1724 u8 log_max_tir[0x5];
e1c9c62b 1725 u8 reserved_at_378[0x3];
b775516b
EC		 1726 u8 log_max_tis[0x5];
1727
e281682b 1728 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1729 u8 reserved_at_381[0x2];
e281682b 1730 u8 log_max_rmp[0x5];
e1c9c62b 1731 u8 reserved_at_388[0x3];
e281682b 1732 u8 log_max_rqt[0x5];
e1c9c62b 1733 u8 reserved_at_390[0x3];
e281682b 1734 u8 log_max_rqt_size[0x5];
e1c9c62b 1735 u8 reserved_at_398[0x3];
b775516b
EC		 1736 u8 log_max_tis_per_sq[0x5];
1737
619a8f2a 1738 u8 ext_stride_num_range[0x1];
fbfa97b4 1739 u8 roce_rw_supported[0x1];
685b1afd 1740 u8 log_max_current_uc_list_wr_supported[0x1];
e281682b 1741 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1742 u8 reserved_at_3a8[0x3];
e281682b 1743 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1744 u8 reserved_at_3b0[0x3];
e281682b 1745 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1746 u8 reserved_at_3b8[0x3];
e281682b
SM		 1747 u8 log_min_stride_sz_sq[0x5];
1748
40817cdb
OG		 1749 u8 hairpin[0x1];
1750 u8 reserved_at_3c1[0x2];
1751 u8 log_max_hairpin_queues[0x5];
1752 u8 reserved_at_3c8[0x3];
1753 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1754 u8 reserved_at_3d0[0x3];
1755 u8 log_max_hairpin_num_packets[0x5];
1756 u8 reserved_at_3d8[0x3];
e281682b
SM		 1757 u8 log_max_wq_sz[0x5];
1758
54f0a411 1759 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1760 u8 disable_local_lb_uc[0x1];
1761 u8 disable_local_lb_mc[0x1];
40817cdb 1762 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1763 u8 reserved_at_3e8[0x2];
1764 u8 vhca_state[0x1];
54f0a411 1765 u8 log_max_vlan_list[0x5];
e1c9c62b 1766 u8 reserved_at_3f0[0x3];
54f0a411 1767 u8 log_max_current_mc_list[0x5];
e1c9c62b 1768 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1769 u8 log_max_current_uc_list[0x5];
1770
38b7ca92
YH		 1771 u8 general_obj_types[0x40];
1772
a6a217dd
AL		 1773 u8 sq_ts_format[0x2];
1774 u8 rq_ts_format[0x2];
d421e466
YK		 1775 u8 steering_format_version[0x4];
1776 u8 create_qp_start_hint[0x18];
342ac844 1777
4bf207d7
JG		 1778 u8 reserved_at_460[0x1];
1779 u8 ats[0x1];
1780 u8 reserved_at_462[0x1];
6e3722ba 1781 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1782 u8 reserved_at_468[0x2];
1783 u8 ipsec_offload[0x1];
6e3722ba 1784 u8 log_max_umem[0x5];
342ac844 1785 u8 max_num_eqs[0x10];
54f0a411 1786
61c00cca
TT		 1787 u8 reserved_at_480[0x1];
1788 u8 tls_tx[0x1];
ee5cdf7a 1789 u8 tls_rx[0x1];
e281682b 1790 u8 log_max_l2_table[0x5];
e1c9c62b 1791 u8 reserved_at_488[0x8];
b775516b
EC		 1792 u8 log_uar_page_sz[0x10];
1793
e1c9c62b 1794 u8 reserved_at_4a0[0x20];
048ccca8 1795 u8 device_frequency_mhz[0x20];
b0844444 1796 u8 device_frequency_khz[0x20];
e1c9c62b 1797
a6d51b68
EC		 1798 u8 reserved_at_500[0x20];
1799 u8 num_of_uars_per_page[0x20];
e1c9c62b 1800
e818e255 1801 u8 flex_parser_protocols[0x20];
e1c9c62b 1802
b169e64a
YK		 1803 u8 max_geneve_tlv_options[0x8];
1804 u8 reserved_at_568[0x3];
1805 u8 max_geneve_tlv_option_data_len[0x5];
a1be74c5
YH		 1806 u8 reserved_at_570[0x9];
1807 u8 adv_virtualization[0x1];
1808 u8 reserved_at_57a[0x6];
e1c9c62b 1809
96cd2dd6
LN		 1810 u8 reserved_at_580[0xb];
1811 u8 log_max_dci_stream_channels[0x5];
1812 u8 reserved_at_590[0x3];
1813 u8 log_max_dci_errored_streams[0x5];
1814 u8 reserved_at_598[0x8];
1815
cdcdce94
OL		 1816 u8 reserved_at_5a0[0x10];
1817 u8 enhanced_cqe_compression[0x1];
1818 u8 reserved_at_5b1[0x2];
a12ff35e
EBE		 1819 u8 log_max_dek[0x5];
1820 u8 reserved_at_5b8[0x4];
ab741b2e 1821 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1822 u8 cqe_128_always[0x1];
1823 u8 cqe_compression_128[0x1];
7d5e1423 1824 u8 cqe_compression[0x1];
b775516b 1825
7d5e1423
SM		 1826 u8 cqe_compression_timeout[0x10];
1827 u8 cqe_compression_max_num[0x10];
b775516b 1828
704cfecd
YK		 1829 u8 reserved_at_5e0[0x8];
1830 u8 flex_parser_id_gtpu_dw_0[0x4];
1831 u8 reserved_at_5ec[0x4];
7486216b
SM		 1832 u8 tag_matching[0x1];
1833 u8 rndv_offload_rc[0x1];
1834 u8 rndv_offload_dc[0x1];
1835 u8 log_tag_matching_list_sz[0x5];
7b13558f 1836 u8 reserved_at_5f8[0x3];
7486216b
SM		 1837 u8 log_max_xrq[0x5];
1838
32f69e4b
DJ		 1839 u8 affiliate_nic_vport_criteria[0x8];
1840 u8 native_port_num[0x8];
1841 u8 num_vhca_ports[0x8];
704cfecd
YK		 1842 u8 flex_parser_id_gtpu_teid[0x4];
1843 u8 reserved_at_61c[0x2];
32f69e4b 1844 u8 sw_owner_id[0x1];
9d43faac
YH		 1845 u8 reserved_at_61f[0x1];
1846
fd4572b3
ED		 1847 u8 max_num_of_monitor_counters[0x10];
1848 u8 num_ppcnt_monitor_counters[0x10];
1849
349125ba 1850 u8 max_num_sf[0x10];
fd4572b3
ED		 1851 u8 num_q_monitor_counters[0x10];
1852
1759d322
PP		 1853 u8 reserved_at_660[0x20];
1854
1855 u8 sf[0x1];
1856 u8 sf_set_partition[0x1];
1857 u8 reserved_at_682[0x1];
1858 u8 log_max_sf[0x5];
7232c132 1859 u8 apu[0x1];
adfdaff3
YH		 1860 u8 reserved_at_689[0x4];
1861 u8 migration[0x1];
1862 u8 reserved_at_68e[0x2];
1759d322
PP		 1863 u8 log_min_sf_size[0x8];
1864 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1865
1866 u8 uctx_cap[0x20];
1867
b169e64a
YK		 1868 u8 reserved_at_6c0[0x4];
1869 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1870 u8 flex_parser_id_icmp_dw1[0x4];
1871 u8 flex_parser_id_icmp_dw0[0x4];
1872 u8 flex_parser_id_icmpv6_dw1[0x4];
1873 u8 flex_parser_id_icmpv6_dw0[0x4];
1874 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1875 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1876
e7e2519e 1877 u8 max_num_match_definer[0x10];
1759d322
PP		 1878 u8 sf_base_id[0x10];
1879
704cfecd
YK		 1880 u8 flex_parser_id_gtpu_dw_2[0x4];
1881 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
0b989c1e
LR		 1882 u8 num_total_dynamic_vf_msix[0x18];
1883 u8 reserved_at_720[0x14];
1884 u8 dynamic_msix_table_size[0xc];
1885 u8 reserved_at_740[0xc];
1886 u8 min_dynamic_vf_msix_table_size[0x4];
1887 u8 reserved_at_750[0x4];
1888 u8 max_dynamic_vf_msix_table_size[0xc];
1889
1890 u8 reserved_at_760[0x20];
1dd7382b 1891 u8 vhca_tunnel_commands[0x40];
e7e2519e 1892 u8 match_definer_format_supported[0x40];
b775516b
EC		 1893};
1894
67133eaa 1895struct mlx5_ifc_cmd_hca_cap_2_bits {
df268f6c
YH		 1896 u8 reserved_at_0[0x80];
1897
1898 u8 migratable[0x1];
1899 u8 reserved_at_81[0x1f];
67133eaa
YK		 1900
1901 u8 max_reformat_insert_size[0x8];
1902 u8 max_reformat_insert_offset[0x8];
1903 u8 max_reformat_remove_size[0x8];
1904 u8 max_reformat_remove_offset[0x8];
1905
c943a937
SD		 1906 u8 reserved_at_c0[0x8];
1907 u8 migration_multi_load[0x1];
1908 u8 migration_tracking_state[0x1];
1909 u8 reserved_at_ca[0x16];
1910
1911 u8 reserved_at_e0[0xc0];
40b72108 1912
7368f221
PH		 1913 u8 flow_table_type_2_type[0x8];
1914 u8 reserved_at_1a8[0x3];
40b72108
MM		 1915 u8 log_min_mkey_entity_size[0x5];
1916 u8 reserved_at_1b0[0x10];
1917
1918 u8 reserved_at_1c0[0x60];
0372c546
YH		 1919
1920 u8 reserved_at_220[0x1];
1921 u8 sw_vhca_id_valid[0x1];
1922 u8 sw_vhca_id[0xe];
1923 u8 reserved_at_230[0x10];
1924
2e5e4185
AL		 1925 u8 reserved_at_240[0xb];
1926 u8 ts_cqe_metadata_size2wqe_counter[0x5];
1927 u8 reserved_at_250[0x10];
1928
1929 u8 reserved_at_260[0x5a0];
67133eaa
YK		 1930};
1931
d639af62
MB		 1932enum mlx5_ifc_flow_destination_type {
1933 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1934 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1935 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1936 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1937 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
7368f221 1938 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
e281682b 1939};
b775516b 1940
f6f7d6b5
MG		 1941enum mlx5_flow_table_miss_action {
1942 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1943 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1944 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1945};
1946
e281682b
SM		 1947struct mlx5_ifc_dest_format_struct_bits {
1948 u8 destination_type[0x8];
1949 u8 destination_id[0x18];
1b115498 1950
b17f7fc1 1951 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498 1952 u8 packet_reformat[0x1];
7368f221
PH		 1953 u8 reserved_at_22[0x6];
1954 u8 destination_table_type[0x8];
b17f7fc1 1955 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1956};
1957
9dc0b289 1958struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1959 u8 flow_counter_id[0x20];
9dc0b289
AV		 1960
1961 u8 reserved_at_20[0x20];
1962};
1963
1b115498
EB		 1964struct mlx5_ifc_extended_dest_format_bits {
1965 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1966
1967 u8 packet_reformat_id[0x20];
1968
1969 u8 reserved_at_60[0x20];
1970};
1971
9dc0b289 1972union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1973 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1974 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1975};
1976
e281682b
SM		 1977struct mlx5_ifc_fte_match_param_bits {
1978 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1979
1980 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1981
1982 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1983
71c6e863
AL		 1984 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1985
b169e64a
YK		 1986 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1987
7da3ad6c
MS		 1988 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1989
0f2a6c3b
MS		 1990 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1991
1992 u8 reserved_at_e00[0x200];
b775516b
EC		 1993};
1994
e281682b
SM		 1995enum {
1996 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1997 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1998 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1999 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2000 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2001};
b775516b 2002
e281682b
SM		 2003struct mlx5_ifc_rx_hash_field_select_bits {
2004 u8 l3_prot_type[0x1];
2005 u8 l4_prot_type[0x1];
2006 u8 selected_fields[0x1e];
2007};
b775516b 2008
e281682b
SM		 2009enum {
2010 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
2011 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 2012};
2013
e281682b
SM		 2014enum {
2015 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
2016 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
2017};
2018
2019struct mlx5_ifc_wq_bits {
2020 u8 wq_type[0x4];
2021 u8 wq_signature[0x1];
2022 u8 end_padding_mode[0x2];
2023 u8 cd_slave[0x1];
b4ff3a36 2024 u8 reserved_at_8[0x18];
b775516b 2025
e281682b
SM		 2026 u8 hds_skip_first_sge[0x1];
2027 u8 log2_hds_buf_size[0x3];
b4ff3a36 2028 u8 reserved_at_24[0x7];
e281682b
SM		 2029 u8 page_offset[0x5];
2030 u8 lwm[0x10];
b775516b 2031
b4ff3a36 2032 u8 reserved_at_40[0x8];
e281682b
SM		 2033 u8 pd[0x18];
2034
b4ff3a36 2035 u8 reserved_at_60[0x8];
e281682b
SM		 2036 u8 uar_page[0x18];
2037
2038 u8 dbr_addr[0x40];
2039
2040 u8 hw_counter[0x20];
2041
2042 u8 sw_counter[0x20];
2043
b4ff3a36 2044 u8 reserved_at_100[0xc];
e281682b 2045 u8 log_wq_stride[0x4];
b4ff3a36 2046 u8 reserved_at_110[0x3];
e281682b 2047 u8 log_wq_pg_sz[0x5];
b4ff3a36 2048 u8 reserved_at_118[0x3];
e281682b
SM		 2049 u8 log_wq_sz[0x5];
2050
bd371975
LR		 2051 u8 dbr_umem_valid[0x1];
2052 u8 wq_umem_valid[0x1];
2053 u8 reserved_at_122[0x1];
4d533e0f
OG		 2054 u8 log_hairpin_num_packets[0x5];
2055 u8 reserved_at_128[0x3];
40817cdb 2056 u8 log_hairpin_data_sz[0x5];
40817cdb 2057
619a8f2a
TT		 2058 u8 reserved_at_130[0x4];
2059 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 2060 u8 two_byte_shift_en[0x1];
2061 u8 reserved_at_139[0x4];
2062 u8 log_wqe_stride_size[0x3];
2063
7025329d
BBI		 2064 u8 reserved_at_140[0x80];
2065
2066 u8 headers_mkey[0x20];
2067
2068 u8 shampo_enable[0x1];
2069 u8 reserved_at_1e1[0x4];
2070 u8 log_reservation_size[0x3];
2071 u8 reserved_at_1e8[0x5];
2072 u8 log_max_num_of_packets_per_reservation[0x3];
2073 u8 reserved_at_1f0[0x6];
2074 u8 log_headers_entry_size[0x2];
2075 u8 reserved_at_1f8[0x4];
2076 u8 log_headers_buffer_entry_num[0x4];
2077
2078 u8 reserved_at_200[0x400];
b775516b 2079
b6ca09cb 2080 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 2081};
2082
e281682b 2083struct mlx5_ifc_rq_num_bits {
b4ff3a36 2084 u8 reserved_at_0[0x8];
e281682b
SM		 2085 u8 rq_num[0x18];
2086};
b775516b 2087
e281682b 2088struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 2089 u8 reserved_at_0[0x10];
e281682b 2090 u8 mac_addr_47_32[0x10];
b775516b 2091
e281682b
SM		 2092 u8 mac_addr_31_0[0x20];
2093};
2094
c0046cf7 2095struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 2096 u8 reserved_at_0[0x14];
c0046cf7
SM		 2097 u8 vlan[0x0c];
2098
b4ff3a36 2099 u8 reserved_at_20[0x20];
c0046cf7
SM		 2100};
2101
e281682b 2102struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 2103 u8 reserved_at_0[0xa0];
e281682b
SM		 2104
2105 u8 min_time_between_cnps[0x20];
2106
b4ff3a36 2107 u8 reserved_at_c0[0x12];
e281682b 2108 u8 cnp_dscp[0x6];
4a2da0b8
PP		 2109 u8 reserved_at_d8[0x4];
2110 u8 cnp_prio_mode[0x1];
e281682b
SM		 2111 u8 cnp_802p_prio[0x3];
2112
b4ff3a36 2113 u8 reserved_at_e0[0x720];
e281682b
SM		 2114};
2115
2116struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 2117 u8 reserved_at_0[0x60];
e281682b 2118
b4ff3a36 2119 u8 reserved_at_60[0x4];
e281682b 2120 u8 clamp_tgt_rate[0x1];
b4ff3a36 2121 u8 reserved_at_65[0x3];
e281682b 2122 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 2123 u8 reserved_at_69[0x17];
e281682b 2124
b4ff3a36 2125 u8 reserved_at_80[0x20];
e281682b
SM		 2126
2127 u8 rpg_time_reset[0x20];
2128
2129 u8 rpg_byte_reset[0x20];
2130
2131 u8 rpg_threshold[0x20];
2132
2133 u8 rpg_max_rate[0x20];
2134
2135 u8 rpg_ai_rate[0x20];
2136
2137 u8 rpg_hai_rate[0x20];
2138
2139 u8 rpg_gd[0x20];
2140
2141 u8 rpg_min_dec_fac[0x20];
2142
2143 u8 rpg_min_rate[0x20];
2144
b4ff3a36 2145 u8 reserved_at_1c0[0xe0];
e281682b
SM		 2146
2147 u8 rate_to_set_on_first_cnp[0x20];
2148
2149 u8 dce_tcp_g[0x20];
2150
2151 u8 dce_tcp_rtt[0x20];
2152
2153 u8 rate_reduce_monitor_period[0x20];
2154
b4ff3a36 2155 u8 reserved_at_320[0x20];
e281682b
SM		 2156
2157 u8 initial_alpha_value[0x20];
2158
b4ff3a36 2159 u8 reserved_at_360[0x4a0];
e281682b
SM		 2160};
2161
2162struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 2163 u8 reserved_at_0[0x80];
e281682b
SM		 2164
2165 u8 rppp_max_rps[0x20];
2166
2167 u8 rpg_time_reset[0x20];
2168
2169 u8 rpg_byte_reset[0x20];
2170
2171 u8 rpg_threshold[0x20];
2172
2173 u8 rpg_max_rate[0x20];
2174
2175 u8 rpg_ai_rate[0x20];
2176
2177 u8 rpg_hai_rate[0x20];
2178
2179 u8 rpg_gd[0x20];
2180
2181 u8 rpg_min_dec_fac[0x20];
2182
2183 u8 rpg_min_rate[0x20];
2184
b4ff3a36 2185 u8 reserved_at_1c0[0x640];
e281682b
SM		 2186};
2187
2188enum {
2189 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2190 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2191 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2192};
2193
2194struct mlx5_ifc_resize_field_select_bits {
2195 u8 resize_field_select[0x20];
2196};
2197
609b8272
AL		 2198struct mlx5_ifc_resource_dump_bits {
2199 u8 more_dump[0x1];
2200 u8 inline_dump[0x1];
2201 u8 reserved_at_2[0xa];
2202 u8 seq_num[0x4];
2203 u8 segment_type[0x10];
2204
2205 u8 reserved_at_20[0x10];
2206 u8 vhca_id[0x10];
2207
2208 u8 index1[0x20];
2209
2210 u8 index2[0x20];
2211
2212 u8 num_of_obj1[0x10];
2213 u8 num_of_obj2[0x10];
2214
2215 u8 reserved_at_a0[0x20];
2216
2217 u8 device_opaque[0x40];
2218
2219 u8 mkey[0x20];
2220
2221 u8 size[0x20];
2222
2223 u8 address[0x40];
2224
2225 u8 inline_data[52][0x20];
2226};
2227
2228struct mlx5_ifc_resource_dump_menu_record_bits {
2229 u8 reserved_at_0[0x4];
2230 u8 num_of_obj2_supports_active[0x1];
2231 u8 num_of_obj2_supports_all[0x1];
2232 u8 must_have_num_of_obj2[0x1];
2233 u8 support_num_of_obj2[0x1];
2234 u8 num_of_obj1_supports_active[0x1];
2235 u8 num_of_obj1_supports_all[0x1];
2236 u8 must_have_num_of_obj1[0x1];
2237 u8 support_num_of_obj1[0x1];
2238 u8 must_have_index2[0x1];
2239 u8 support_index2[0x1];
2240 u8 must_have_index1[0x1];
2241 u8 support_index1[0x1];
2242 u8 segment_type[0x10];
2243
2244 u8 segment_name[4][0x20];
2245
2246 u8 index1_name[4][0x20];
2247
2248 u8 index2_name[4][0x20];
2249};
2250
2251struct mlx5_ifc_resource_dump_segment_header_bits {
2252 u8 length_dw[0x10];
2253 u8 segment_type[0x10];
2254};
2255
2256struct mlx5_ifc_resource_dump_command_segment_bits {
2257 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2258
2259 u8 segment_called[0x10];
2260 u8 vhca_id[0x10];
2261
2262 u8 index1[0x20];
2263
2264 u8 index2[0x20];
2265
2266 u8 num_of_obj1[0x10];
2267 u8 num_of_obj2[0x10];
2268};
2269
2270struct mlx5_ifc_resource_dump_error_segment_bits {
2271 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2272
2273 u8 reserved_at_20[0x10];
2274 u8 syndrome_id[0x10];
2275
2276 u8 reserved_at_40[0x40];
2277
2278 u8 error[8][0x20];
2279};
2280
2281struct mlx5_ifc_resource_dump_info_segment_bits {
2282 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2283
2284 u8 reserved_at_20[0x18];
2285 u8 dump_version[0x8];
2286
2287 u8 hw_version[0x20];
2288
2289 u8 fw_version[0x20];
2290};
2291
2292struct mlx5_ifc_resource_dump_menu_segment_bits {
2293 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2294
2295 u8 reserved_at_20[0x10];
2296 u8 num_of_records[0x10];
2297
b6ca09cb 2298 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2299};
2300
2301struct mlx5_ifc_resource_dump_resource_segment_bits {
2302 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2303
2304 u8 reserved_at_20[0x20];
2305
2306 u8 index1[0x20];
2307
2308 u8 index2[0x20];
2309
b6ca09cb 2310 u8 payload[][0x20];
609b8272
AL		 2311};
2312
2313struct mlx5_ifc_resource_dump_terminate_segment_bits {
2314 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2315};
2316
2317struct mlx5_ifc_menu_resource_dump_response_bits {
2318 struct mlx5_ifc_resource_dump_info_segment_bits info;
2319 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2320 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2321 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2322};
2323
e281682b
SM		 2324enum {
2325 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2326 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2327 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2328 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2329};
2330
2331struct mlx5_ifc_modify_field_select_bits {
2332 u8 modify_field_select[0x20];
2333};
2334
2335struct mlx5_ifc_field_select_r_roce_np_bits {
2336 u8 field_select_r_roce_np[0x20];
2337};
2338
2339struct mlx5_ifc_field_select_r_roce_rp_bits {
2340 u8 field_select_r_roce_rp[0x20];
2341};
2342
2343enum {
2344 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2345 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2346 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2347 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2348 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2349 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2350 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2351 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2352 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2353 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2354};
2355
2356struct mlx5_ifc_field_select_802_1qau_rp_bits {
2357 u8 field_select_8021qaurp[0x20];
2358};
2359
2360struct mlx5_ifc_phys_layer_cntrs_bits {
2361 u8 time_since_last_clear_high[0x20];
2362
2363 u8 time_since_last_clear_low[0x20];
2364
2365 u8 symbol_errors_high[0x20];
2366
2367 u8 symbol_errors_low[0x20];
2368
2369 u8 sync_headers_errors_high[0x20];
2370
2371 u8 sync_headers_errors_low[0x20];
2372
2373 u8 edpl_bip_errors_lane0_high[0x20];
2374
2375 u8 edpl_bip_errors_lane0_low[0x20];
2376
2377 u8 edpl_bip_errors_lane1_high[0x20];
2378
2379 u8 edpl_bip_errors_lane1_low[0x20];
2380
2381 u8 edpl_bip_errors_lane2_high[0x20];
2382
2383 u8 edpl_bip_errors_lane2_low[0x20];
2384
2385 u8 edpl_bip_errors_lane3_high[0x20];
2386
2387 u8 edpl_bip_errors_lane3_low[0x20];
2388
2389 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2390
2391 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2392
2393 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2394
2395 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2396
2397 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2398
2399 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2400
2401 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2402
2403 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2404
2405 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2406
2407 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2408
2409 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2410
2411 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2412
2413 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2414
2415 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2416
2417 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2418
2419 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2420
2421 u8 rs_fec_corrected_blocks_high[0x20];
2422
2423 u8 rs_fec_corrected_blocks_low[0x20];
2424
2425 u8 rs_fec_uncorrectable_blocks_high[0x20];
2426
2427 u8 rs_fec_uncorrectable_blocks_low[0x20];
2428
2429 u8 rs_fec_no_errors_blocks_high[0x20];
2430
2431 u8 rs_fec_no_errors_blocks_low[0x20];
2432
2433 u8 rs_fec_single_error_blocks_high[0x20];
2434
2435 u8 rs_fec_single_error_blocks_low[0x20];
2436
2437 u8 rs_fec_corrected_symbols_total_high[0x20];
2438
2439 u8 rs_fec_corrected_symbols_total_low[0x20];
2440
2441 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2442
2443 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2444
2445 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2446
2447 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2448
2449 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2450
2451 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2452
2453 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2454
2455 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2456
2457 u8 link_down_events[0x20];
2458
2459 u8 successful_recovery_events[0x20];
2460
b4ff3a36 2461 u8 reserved_at_640[0x180];
e281682b
SM		 2462};
2463
d8dc0508
GP		 2464struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2465 u8 time_since_last_clear_high[0x20];
2466
2467 u8 time_since_last_clear_low[0x20];
2468
2469 u8 phy_received_bits_high[0x20];
2470
2471 u8 phy_received_bits_low[0x20];
2472
2473 u8 phy_symbol_errors_high[0x20];
2474
2475 u8 phy_symbol_errors_low[0x20];
2476
2477 u8 phy_corrected_bits_high[0x20];
2478
2479 u8 phy_corrected_bits_low[0x20];
2480
2481 u8 phy_corrected_bits_lane0_high[0x20];
2482
2483 u8 phy_corrected_bits_lane0_low[0x20];
2484
2485 u8 phy_corrected_bits_lane1_high[0x20];
2486
2487 u8 phy_corrected_bits_lane1_low[0x20];
2488
2489 u8 phy_corrected_bits_lane2_high[0x20];
2490
2491 u8 phy_corrected_bits_lane2_low[0x20];
2492
2493 u8 phy_corrected_bits_lane3_high[0x20];
2494
2495 u8 phy_corrected_bits_lane3_low[0x20];
2496
2497 u8 reserved_at_200[0x5c0];
2498};
2499
1c64bf6f
MY		 2500struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2501 u8 symbol_error_counter[0x10];
2502
2503 u8 link_error_recovery_counter[0x8];
2504
2505 u8 link_downed_counter[0x8];
2506
2507 u8 port_rcv_errors[0x10];
2508
2509 u8 port_rcv_remote_physical_errors[0x10];
2510
2511 u8 port_rcv_switch_relay_errors[0x10];
2512
2513 u8 port_xmit_discards[0x10];
2514
2515 u8 port_xmit_constraint_errors[0x8];
2516
2517 u8 port_rcv_constraint_errors[0x8];
2518
2519 u8 reserved_at_70[0x8];
2520
2521 u8 link_overrun_errors[0x8];
2522
2523 u8 reserved_at_80[0x10];
2524
2525 u8 vl_15_dropped[0x10];
2526
133bea04
TW		 2527 u8 reserved_at_a0[0x80];
2528
2529 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2530};
2531
948d3f90 2532struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2533 u8 transmit_queue_high[0x20];
2534
2535 u8 transmit_queue_low[0x20];
2536
948d3f90
AL		 2537 u8 no_buffer_discard_uc_high[0x20];
2538
2539 u8 no_buffer_discard_uc_low[0x20];
2540
2541 u8 reserved_at_80[0x740];
2542};
2543
2544struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2545 u8 wred_discard_high[0x20];
2546
2547 u8 wred_discard_low[0x20];
2548
2549 u8 ecn_marked_tc_high[0x20];
2550
2551 u8 ecn_marked_tc_low[0x20];
2552
2553 u8 reserved_at_80[0x740];
e281682b
SM		 2554};
2555
2556struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2557 u8 rx_octets_high[0x20];
2558
2559 u8 rx_octets_low[0x20];
2560
b4ff3a36 2561 u8 reserved_at_40[0xc0];
e281682b
SM		 2562
2563 u8 rx_frames_high[0x20];
2564
2565 u8 rx_frames_low[0x20];
2566
2567 u8 tx_octets_high[0x20];
2568
2569 u8 tx_octets_low[0x20];
2570
b4ff3a36 2571 u8 reserved_at_180[0xc0];
e281682b
SM		 2572
2573 u8 tx_frames_high[0x20];
2574
2575 u8 tx_frames_low[0x20];
2576
2577 u8 rx_pause_high[0x20];
2578
2579 u8 rx_pause_low[0x20];
2580
2581 u8 rx_pause_duration_high[0x20];
2582
2583 u8 rx_pause_duration_low[0x20];
2584
2585 u8 tx_pause_high[0x20];
2586
2587 u8 tx_pause_low[0x20];
2588
2589 u8 tx_pause_duration_high[0x20];
2590
2591 u8 tx_pause_duration_low[0x20];
2592
2593 u8 rx_pause_transition_high[0x20];
2594
2595 u8 rx_pause_transition_low[0x20];
2596
827a8cb2
AL		 2597 u8 rx_discards_high[0x20];
2598
2599 u8 rx_discards_low[0x20];
2fcb12df
IK		 2600
2601 u8 device_stall_minor_watermark_cnt_high[0x20];
2602
2603 u8 device_stall_minor_watermark_cnt_low[0x20];
2604
2605 u8 device_stall_critical_watermark_cnt_high[0x20];
2606
2607 u8 device_stall_critical_watermark_cnt_low[0x20];
2608
2609 u8 reserved_at_480[0x340];
e281682b
SM		 2610};
2611
2612struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2613 u8 port_transmit_wait_high[0x20];
2614
2615 u8 port_transmit_wait_low[0x20];
2616
2dba0797
GP		 2617 u8 reserved_at_40[0x100];
2618
2619 u8 rx_buffer_almost_full_high[0x20];
2620
2621 u8 rx_buffer_almost_full_low[0x20];
2622
2623 u8 rx_buffer_full_high[0x20];
2624
2625 u8 rx_buffer_full_low[0x20];
2626
0af5107c
TB		 2627 u8 rx_icrc_encapsulated_high[0x20];
2628
2629 u8 rx_icrc_encapsulated_low[0x20];
2630
2631 u8 reserved_at_200[0x5c0];
e281682b
SM		 2632};
2633
2634struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2635 u8 dot3stats_alignment_errors_high[0x20];
2636
2637 u8 dot3stats_alignment_errors_low[0x20];
2638
2639 u8 dot3stats_fcs_errors_high[0x20];
2640
2641 u8 dot3stats_fcs_errors_low[0x20];
2642
2643 u8 dot3stats_single_collision_frames_high[0x20];
2644
2645 u8 dot3stats_single_collision_frames_low[0x20];
2646
2647 u8 dot3stats_multiple_collision_frames_high[0x20];
2648
2649 u8 dot3stats_multiple_collision_frames_low[0x20];
2650
2651 u8 dot3stats_sqe_test_errors_high[0x20];
2652
2653 u8 dot3stats_sqe_test_errors_low[0x20];
2654
2655 u8 dot3stats_deferred_transmissions_high[0x20];
2656
2657 u8 dot3stats_deferred_transmissions_low[0x20];
2658
2659 u8 dot3stats_late_collisions_high[0x20];
2660
2661 u8 dot3stats_late_collisions_low[0x20];
2662
2663 u8 dot3stats_excessive_collisions_high[0x20];
2664
2665 u8 dot3stats_excessive_collisions_low[0x20];
2666
2667 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2668
2669 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2670
2671 u8 dot3stats_carrier_sense_errors_high[0x20];
2672
2673 u8 dot3stats_carrier_sense_errors_low[0x20];
2674
2675 u8 dot3stats_frame_too_longs_high[0x20];
2676
2677 u8 dot3stats_frame_too_longs_low[0x20];
2678
2679 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2680
2681 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2682
2683 u8 dot3stats_symbol_errors_high[0x20];
2684
2685 u8 dot3stats_symbol_errors_low[0x20];
2686
2687 u8 dot3control_in_unknown_opcodes_high[0x20];
2688
2689 u8 dot3control_in_unknown_opcodes_low[0x20];
2690
2691 u8 dot3in_pause_frames_high[0x20];
2692
2693 u8 dot3in_pause_frames_low[0x20];
2694
2695 u8 dot3out_pause_frames_high[0x20];
2696
2697 u8 dot3out_pause_frames_low[0x20];
2698
b4ff3a36 2699 u8 reserved_at_400[0x3c0];
e281682b
SM		 2700};
2701
2702struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2703 u8 ether_stats_drop_events_high[0x20];
2704
2705 u8 ether_stats_drop_events_low[0x20];
2706
2707 u8 ether_stats_octets_high[0x20];
2708
2709 u8 ether_stats_octets_low[0x20];
2710
2711 u8 ether_stats_pkts_high[0x20];
2712
2713 u8 ether_stats_pkts_low[0x20];
2714
2715 u8 ether_stats_broadcast_pkts_high[0x20];
2716
2717 u8 ether_stats_broadcast_pkts_low[0x20];
2718
2719 u8 ether_stats_multicast_pkts_high[0x20];
2720
2721 u8 ether_stats_multicast_pkts_low[0x20];
2722
2723 u8 ether_stats_crc_align_errors_high[0x20];
2724
2725 u8 ether_stats_crc_align_errors_low[0x20];
2726
2727 u8 ether_stats_undersize_pkts_high[0x20];
2728
2729 u8 ether_stats_undersize_pkts_low[0x20];
2730
2731 u8 ether_stats_oversize_pkts_high[0x20];
2732
2733 u8 ether_stats_oversize_pkts_low[0x20];
2734
2735 u8 ether_stats_fragments_high[0x20];
2736
2737 u8 ether_stats_fragments_low[0x20];
2738
2739 u8 ether_stats_jabbers_high[0x20];
2740
2741 u8 ether_stats_jabbers_low[0x20];
2742
2743 u8 ether_stats_collisions_high[0x20];
2744
2745 u8 ether_stats_collisions_low[0x20];
2746
2747 u8 ether_stats_pkts64octets_high[0x20];
2748
2749 u8 ether_stats_pkts64octets_low[0x20];
2750
2751 u8 ether_stats_pkts65to127octets_high[0x20];
2752
2753 u8 ether_stats_pkts65to127octets_low[0x20];
2754
2755 u8 ether_stats_pkts128to255octets_high[0x20];
2756
2757 u8 ether_stats_pkts128to255octets_low[0x20];
2758
2759 u8 ether_stats_pkts256to511octets_high[0x20];
2760
2761 u8 ether_stats_pkts256to511octets_low[0x20];
2762
2763 u8 ether_stats_pkts512to1023octets_high[0x20];
2764
2765 u8 ether_stats_pkts512to1023octets_low[0x20];
2766
2767 u8 ether_stats_pkts1024to1518octets_high[0x20];
2768
2769 u8 ether_stats_pkts1024to1518octets_low[0x20];
2770
2771 u8 ether_stats_pkts1519to2047octets_high[0x20];
2772
2773 u8 ether_stats_pkts1519to2047octets_low[0x20];
2774
2775 u8 ether_stats_pkts2048to4095octets_high[0x20];
2776
2777 u8 ether_stats_pkts2048to4095octets_low[0x20];
2778
2779 u8 ether_stats_pkts4096to8191octets_high[0x20];
2780
2781 u8 ether_stats_pkts4096to8191octets_low[0x20];
2782
2783 u8 ether_stats_pkts8192to10239octets_high[0x20];
2784
2785 u8 ether_stats_pkts8192to10239octets_low[0x20];
2786
b4ff3a36 2787 u8 reserved_at_540[0x280];
e281682b
SM		 2788};
2789
2790struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2791 u8 if_in_octets_high[0x20];
2792
2793 u8 if_in_octets_low[0x20];
2794
2795 u8 if_in_ucast_pkts_high[0x20];
2796
2797 u8 if_in_ucast_pkts_low[0x20];
2798
2799 u8 if_in_discards_high[0x20];
2800
2801 u8 if_in_discards_low[0x20];
2802
2803 u8 if_in_errors_high[0x20];
2804
2805 u8 if_in_errors_low[0x20];
2806
2807 u8 if_in_unknown_protos_high[0x20];
2808
2809 u8 if_in_unknown_protos_low[0x20];
2810
2811 u8 if_out_octets_high[0x20];
2812
2813 u8 if_out_octets_low[0x20];
2814
2815 u8 if_out_ucast_pkts_high[0x20];
2816
2817 u8 if_out_ucast_pkts_low[0x20];
2818
2819 u8 if_out_discards_high[0x20];
2820
2821 u8 if_out_discards_low[0x20];
2822
2823 u8 if_out_errors_high[0x20];
2824
2825 u8 if_out_errors_low[0x20];
2826
2827 u8 if_in_multicast_pkts_high[0x20];
2828
2829 u8 if_in_multicast_pkts_low[0x20];
2830
2831 u8 if_in_broadcast_pkts_high[0x20];
2832
2833 u8 if_in_broadcast_pkts_low[0x20];
2834
2835 u8 if_out_multicast_pkts_high[0x20];
2836
2837 u8 if_out_multicast_pkts_low[0x20];
2838
2839 u8 if_out_broadcast_pkts_high[0x20];
2840
2841 u8 if_out_broadcast_pkts_low[0x20];
2842
b4ff3a36 2843 u8 reserved_at_340[0x480];
e281682b
SM		 2844};
2845
2846struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2847 u8 a_frames_transmitted_ok_high[0x20];
2848
2849 u8 a_frames_transmitted_ok_low[0x20];
2850
2851 u8 a_frames_received_ok_high[0x20];
2852
2853 u8 a_frames_received_ok_low[0x20];
2854
2855 u8 a_frame_check_sequence_errors_high[0x20];
2856
2857 u8 a_frame_check_sequence_errors_low[0x20];
2858
2859 u8 a_alignment_errors_high[0x20];
2860
2861 u8 a_alignment_errors_low[0x20];
2862
2863 u8 a_octets_transmitted_ok_high[0x20];
2864
2865 u8 a_octets_transmitted_ok_low[0x20];
2866
2867 u8 a_octets_received_ok_high[0x20];
2868
2869 u8 a_octets_received_ok_low[0x20];
2870
2871 u8 a_multicast_frames_xmitted_ok_high[0x20];
2872
2873 u8 a_multicast_frames_xmitted_ok_low[0x20];
2874
2875 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2876
2877 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2878
2879 u8 a_multicast_frames_received_ok_high[0x20];
2880
2881 u8 a_multicast_frames_received_ok_low[0x20];
2882
2883 u8 a_broadcast_frames_received_ok_high[0x20];
2884
2885 u8 a_broadcast_frames_received_ok_low[0x20];
2886
2887 u8 a_in_range_length_errors_high[0x20];
2888
2889 u8 a_in_range_length_errors_low[0x20];
2890
2891 u8 a_out_of_range_length_field_high[0x20];
2892
2893 u8 a_out_of_range_length_field_low[0x20];
2894
2895 u8 a_frame_too_long_errors_high[0x20];
2896
2897 u8 a_frame_too_long_errors_low[0x20];
2898
2899 u8 a_symbol_error_during_carrier_high[0x20];
2900
2901 u8 a_symbol_error_during_carrier_low[0x20];
2902
2903 u8 a_mac_control_frames_transmitted_high[0x20];
2904
2905 u8 a_mac_control_frames_transmitted_low[0x20];
2906
2907 u8 a_mac_control_frames_received_high[0x20];
2908
2909 u8 a_mac_control_frames_received_low[0x20];
2910
2911 u8 a_unsupported_opcodes_received_high[0x20];
2912
2913 u8 a_unsupported_opcodes_received_low[0x20];
2914
2915 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2916
2917 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2918
2919 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2920
2921 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2922
b4ff3a36 2923 u8 reserved_at_4c0[0x300];
e281682b
SM		 2924};
2925
8ed1a630
GP		 2926struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2927 u8 life_time_counter_high[0x20];
2928
2929 u8 life_time_counter_low[0x20];
2930
2931 u8 rx_errors[0x20];
2932
2933 u8 tx_errors[0x20];
2934
2935 u8 l0_to_recovery_eieos[0x20];
2936
2937 u8 l0_to_recovery_ts[0x20];
2938
2939 u8 l0_to_recovery_framing[0x20];
2940
2941 u8 l0_to_recovery_retrain[0x20];
2942
2943 u8 crc_error_dllp[0x20];
2944
2945 u8 crc_error_tlp[0x20];
2946
efae7f78
EBE		 2947 u8 tx_overflow_buffer_pkt_high[0x20];
2948
2949 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2950
2951 u8 outbound_stalled_reads[0x20];
2952
2953 u8 outbound_stalled_writes[0x20];
2954
2955 u8 outbound_stalled_reads_events[0x20];
2956
2957 u8 outbound_stalled_writes_events[0x20];
2958
2959 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2960};
2961
e281682b
SM		 2962struct mlx5_ifc_cmd_inter_comp_event_bits {
2963 u8 command_completion_vector[0x20];
2964
b4ff3a36 2965 u8 reserved_at_20[0xc0];
e281682b
SM		 2966};
2967
2968struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2969 u8 reserved_at_0[0x18];
e281682b 2970 u8 port_num[0x1];
b4ff3a36 2971 u8 reserved_at_19[0x3];
e281682b
SM		 2972 u8 vl[0x4];
2973
b4ff3a36 2974 u8 reserved_at_20[0xa0];
e281682b
SM		 2975};
2976
2977struct mlx5_ifc_db_bf_congestion_event_bits {
2978 u8 event_subtype[0x8];
b4ff3a36 2979 u8 reserved_at_8[0x8];
e281682b 2980 u8 congestion_level[0x8];
b4ff3a36 2981 u8 reserved_at_18[0x8];
e281682b 2982
b4ff3a36 2983 u8 reserved_at_20[0xa0];
e281682b
SM		 2984};
2985
2986struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2987 u8 reserved_at_0[0x60];
e281682b
SM		 2988
2989 u8 gpio_event_hi[0x20];
2990
2991 u8 gpio_event_lo[0x20];
2992
b4ff3a36 2993 u8 reserved_at_a0[0x40];
e281682b
SM		 2994};
2995
2996struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2997 u8 reserved_at_0[0x40];
e281682b
SM		 2998
2999 u8 port_num[0x4];
b4ff3a36 3000 u8 reserved_at_44[0x1c];
e281682b 3001
b4ff3a36 3002 u8 reserved_at_60[0x80];
e281682b
SM		 3003};
3004
3005struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 3006 u8 reserved_at_0[0xe0];
e281682b
SM		 3007};
3008
4b2c5fa9
AT		 3009struct mlx5_ifc_default_timeout_bits {
3010 u8 to_multiplier[0x3];
3011 u8 reserved_at_3[0x9];
3012 u8 to_value[0x14];
3013};
3014
3015struct mlx5_ifc_dtor_reg_bits {
3016 u8 reserved_at_0[0x20];
3017
3018 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3019
3020 u8 reserved_at_40[0x60];
3021
3022 struct mlx5_ifc_default_timeout_bits health_poll_to;
3023
3024 struct mlx5_ifc_default_timeout_bits full_crdump_to;
3025
3026 struct mlx5_ifc_default_timeout_bits fw_reset_to;
3027
3028 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3029
3030 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3031
3032 struct mlx5_ifc_default_timeout_bits tear_down_to;
3033
3034 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3035
3036 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3037
3038 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3039
3040 u8 reserved_at_1c0[0x40];
3041};
3042
e281682b
SM		 3043enum {
3044 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3045 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3046};
3047
3048struct mlx5_ifc_cq_error_bits {
b4ff3a36 3049 u8 reserved_at_0[0x8];
e281682b
SM		 3050 u8 cqn[0x18];
3051
b4ff3a36 3052 u8 reserved_at_20[0x20];
e281682b 3053
b4ff3a36 3054 u8 reserved_at_40[0x18];
e281682b
SM		 3055 u8 syndrome[0x8];
3056
b4ff3a36 3057 u8 reserved_at_60[0x80];
e281682b
SM		 3058};
3059
3060struct mlx5_ifc_rdma_page_fault_event_bits {
3061 u8 bytes_committed[0x20];
3062
3063 u8 r_key[0x20];
3064
b4ff3a36 3065 u8 reserved_at_40[0x10];
e281682b
SM		 3066 u8 packet_len[0x10];
3067
3068 u8 rdma_op_len[0x20];
3069
3070 u8 rdma_va[0x40];
3071
b4ff3a36 3072 u8 reserved_at_c0[0x5];
e281682b
SM		 3073 u8 rdma[0x1];
3074 u8 write[0x1];
3075 u8 requestor[0x1];
3076 u8 qp_number[0x18];
3077};
3078
3079struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3080 u8 bytes_committed[0x20];
3081
b4ff3a36 3082 u8 reserved_at_20[0x10];
e281682b
SM		 3083 u8 wqe_index[0x10];
3084
b4ff3a36 3085 u8 reserved_at_40[0x10];
e281682b
SM		 3086 u8 len[0x10];
3087
b4ff3a36 3088 u8 reserved_at_60[0x60];
e281682b 3089
b4ff3a36 3090 u8 reserved_at_c0[0x5];
e281682b
SM		 3091 u8 rdma[0x1];
3092 u8 write_read[0x1];
3093 u8 requestor[0x1];
3094 u8 qpn[0x18];
3095};
3096
3097struct mlx5_ifc_qp_events_bits {
b4ff3a36 3098 u8 reserved_at_0[0xa0];
e281682b
SM		 3099
3100 u8 type[0x8];
b4ff3a36 3101 u8 reserved_at_a8[0x18];
e281682b 3102
b4ff3a36 3103 u8 reserved_at_c0[0x8];
e281682b
SM		 3104 u8 qpn_rqn_sqn[0x18];
3105};
3106
3107struct mlx5_ifc_dct_events_bits {
b4ff3a36 3108 u8 reserved_at_0[0xc0];
e281682b 3109
b4ff3a36 3110 u8 reserved_at_c0[0x8];
e281682b
SM		 3111 u8 dct_number[0x18];
3112};
3113
3114struct mlx5_ifc_comp_event_bits {
b4ff3a36 3115 u8 reserved_at_0[0xc0];
e281682b 3116
b4ff3a36 3117 u8 reserved_at_c0[0x8];
e281682b
SM		 3118 u8 cq_number[0x18];
3119};
3120
3121enum {
3122 MLX5_QPC_STATE_RST = 0x0,
3123 MLX5_QPC_STATE_INIT = 0x1,
3124 MLX5_QPC_STATE_RTR = 0x2,
3125 MLX5_QPC_STATE_RTS = 0x3,
3126 MLX5_QPC_STATE_SQER = 0x4,
3127 MLX5_QPC_STATE_ERR = 0x6,
3128 MLX5_QPC_STATE_SQD = 0x7,
3129 MLX5_QPC_STATE_SUSPENDED = 0x9,
3130};
3131
3132enum {
3133 MLX5_QPC_ST_RC = 0x0,
3134 MLX5_QPC_ST_UC = 0x1,
3135 MLX5_QPC_ST_UD = 0x2,
3136 MLX5_QPC_ST_XRC = 0x3,
3137 MLX5_QPC_ST_DCI = 0x5,
3138 MLX5_QPC_ST_QP0 = 0x7,
3139 MLX5_QPC_ST_QP1 = 0x8,
3140 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3141 MLX5_QPC_ST_REG_UMR = 0xc,
3142};
3143
3144enum {
3145 MLX5_QPC_PM_STATE_ARMED = 0x0,
3146 MLX5_QPC_PM_STATE_REARM = 0x1,
3147 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3148 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3149};
3150
6e44636a
AK		 3151enum {
3152 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3153};
3154
e281682b
SM		 3155enum {
3156 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3157 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3158};
3159
3160enum {
3161 MLX5_QPC_MTU_256_BYTES = 0x1,
3162 MLX5_QPC_MTU_512_BYTES = 0x2,
3163 MLX5_QPC_MTU_1K_BYTES = 0x3,
3164 MLX5_QPC_MTU_2K_BYTES = 0x4,
3165 MLX5_QPC_MTU_4K_BYTES = 0x5,
3166 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3167};
3168
3169enum {
3170 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3171 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3172 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3173 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3174 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3175 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3176 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3177 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3178};
3179
3180enum {
3181 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3182 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3183 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3184};
3185
3186enum {
3187 MLX5_QPC_CS_RES_DISABLE = 0x0,
3188 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3189 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3190};
3191
a6a217dd 3192enum {
9a1ac95a
AL		 3193 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3194 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3195 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
a6a217dd
AL		 3196};
3197
e281682b
SM		 3198struct mlx5_ifc_qpc_bits {
3199 u8 state[0x4];
84df61eb 3200 u8 lag_tx_port_affinity[0x4];
e281682b 3201 u8 st[0x8];
7304d603
YK		 3202 u8 reserved_at_10[0x2];
3203 u8 isolate_vl_tc[0x1];
e281682b 3204 u8 pm_state[0x2];
3fd3c80a
DG		 3205 u8 reserved_at_15[0x1];
3206 u8 req_e2e_credit_mode[0x2];
6e44636a 3207 u8 offload_type[0x4];
e281682b 3208 u8 end_padding_mode[0x2];
b4ff3a36 3209 u8 reserved_at_1e[0x2];
e281682b
SM		 3210
3211 u8 wq_signature[0x1];
3212 u8 block_lb_mc[0x1];
3213 u8 atomic_like_write_en[0x1];
3214 u8 latency_sensitive[0x1];
b4ff3a36 3215 u8 reserved_at_24[0x1];
e281682b 3216 u8 drain_sigerr[0x1];
b4ff3a36 3217 u8 reserved_at_26[0x2];
e281682b
SM		 3218 u8 pd[0x18];
3219
3220 u8 mtu[0x3];
3221 u8 log_msg_max[0x5];
b4ff3a36 3222 u8 reserved_at_48[0x1];
e281682b
SM		 3223 u8 log_rq_size[0x4];
3224 u8 log_rq_stride[0x3];
3225 u8 no_sq[0x1];
3226 u8 log_sq_size[0x4];
a6a217dd
AL		 3227 u8 reserved_at_55[0x3];
3228 u8 ts_format[0x2];
3229 u8 reserved_at_5a[0x1];
e281682b 3230 u8 rlky[0x1];
1015c2e8 3231 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 3232
3233 u8 counter_set_id[0x8];
3234 u8 uar_page[0x18];
3235
b4ff3a36 3236 u8 reserved_at_80[0x8];
e281682b
SM		 3237 u8 user_index[0x18];
3238
b4ff3a36 3239 u8 reserved_at_a0[0x3];
e281682b
SM		 3240 u8 log_page_size[0x5];
3241 u8 remote_qpn[0x18];
3242
3243 struct mlx5_ifc_ads_bits primary_address_path;
3244
3245 struct mlx5_ifc_ads_bits secondary_address_path;
3246
3247 u8 log_ack_req_freq[0x4];
b4ff3a36 3248 u8 reserved_at_384[0x4];
e281682b 3249 u8 log_sra_max[0x3];
b4ff3a36 3250 u8 reserved_at_38b[0x2];
e281682b
SM		 3251 u8 retry_count[0x3];
3252 u8 rnr_retry[0x3];
b4ff3a36 3253 u8 reserved_at_393[0x1];
e281682b
SM		 3254 u8 fre[0x1];
3255 u8 cur_rnr_retry[0x3];
3256 u8 cur_retry_count[0x3];
b4ff3a36 3257 u8 reserved_at_39b[0x5];
e281682b 3258
b4ff3a36 3259 u8 reserved_at_3a0[0x20];
e281682b 3260
b4ff3a36 3261 u8 reserved_at_3c0[0x8];
e281682b
SM		 3262 u8 next_send_psn[0x18];
3263
96cd2dd6
LN		 3264 u8 reserved_at_3e0[0x3];
3265 u8 log_num_dci_stream_channels[0x5];
e281682b
SM		 3266 u8 cqn_snd[0x18];
3267
96cd2dd6
LN		 3268 u8 reserved_at_400[0x3];
3269 u8 log_num_dci_errored_streams[0x5];
09a7d9ec
SM		 3270 u8 deth_sqpn[0x18];
3271
3272 u8 reserved_at_420[0x20];
e281682b 3273
b4ff3a36 3274 u8 reserved_at_440[0x8];
e281682b
SM		 3275 u8 last_acked_psn[0x18];
3276
b4ff3a36 3277 u8 reserved_at_460[0x8];
e281682b
SM		 3278 u8 ssn[0x18];
3279
b4ff3a36 3280 u8 reserved_at_480[0x8];
e281682b 3281 u8 log_rra_max[0x3];
b4ff3a36 3282 u8 reserved_at_48b[0x1];
e281682b
SM		 3283 u8 atomic_mode[0x4];
3284 u8 rre[0x1];
3285 u8 rwe[0x1];
3286 u8 rae[0x1];
b4ff3a36 3287 u8 reserved_at_493[0x1];
e281682b 3288 u8 page_offset[0x6];
b4ff3a36 3289 u8 reserved_at_49a[0x3];
e281682b
SM		 3290 u8 cd_slave_receive[0x1];
3291 u8 cd_slave_send[0x1];
3292 u8 cd_master[0x1];
3293
b4ff3a36 3294 u8 reserved_at_4a0[0x3];
e281682b
SM		 3295 u8 min_rnr_nak[0x5];
3296 u8 next_rcv_psn[0x18];
3297
b4ff3a36 3298 u8 reserved_at_4c0[0x8];
e281682b
SM		 3299 u8 xrcd[0x18];
3300
b4ff3a36 3301 u8 reserved_at_4e0[0x8];
e281682b
SM		 3302 u8 cqn_rcv[0x18];
3303
3304 u8 dbr_addr[0x40];
3305
3306 u8 q_key[0x20];
3307
b4ff3a36 3308 u8 reserved_at_560[0x5];
e281682b 3309 u8 rq_type[0x3];
7486216b 3310 u8 srqn_rmpn_xrqn[0x18];
e281682b 3311
b4ff3a36 3312 u8 reserved_at_580[0x8];
e281682b
SM		 3313 u8 rmsn[0x18];
3314
3315 u8 hw_sq_wqebb_counter[0x10];
3316 u8 sw_sq_wqebb_counter[0x10];
3317
3318 u8 hw_rq_counter[0x20];
3319
3320 u8 sw_rq_counter[0x20];
3321
b4ff3a36 3322 u8 reserved_at_600[0x20];
e281682b 3323
b4ff3a36 3324 u8 reserved_at_620[0xf];
e281682b
SM		 3325 u8 cgs[0x1];
3326 u8 cs_req[0x8];
3327 u8 cs_res[0x8];
3328
3329 u8 dc_access_key[0x40];
3330
bd371975
LR		 3331 u8 reserved_at_680[0x3];
3332 u8 dbr_umem_valid[0x1];
3333
3334 u8 reserved_at_684[0xbc];
e281682b
SM		 3335};
3336
3337struct mlx5_ifc_roce_addr_layout_bits {
3338 u8 source_l3_address[16][0x8];
3339
b4ff3a36 3340 u8 reserved_at_80[0x3];
e281682b
SM		 3341 u8 vlan_valid[0x1];
3342 u8 vlan_id[0xc];
3343 u8 source_mac_47_32[0x10];
3344
3345 u8 source_mac_31_0[0x20];
3346
b4ff3a36 3347 u8 reserved_at_c0[0x14];
e281682b
SM		 3348 u8 roce_l3_type[0x4];
3349 u8 roce_version[0x8];
3350
b4ff3a36 3351 u8 reserved_at_e0[0x20];
e281682b
SM		 3352};
3353
7025329d
BBI		 3354struct mlx5_ifc_shampo_cap_bits {
3355 u8 reserved_at_0[0x3];
3356 u8 shampo_log_max_reservation_size[0x5];
3357 u8 reserved_at_8[0x3];
3358 u8 shampo_log_min_reservation_size[0x5];
3359 u8 shampo_min_mss_size[0x10];
3360
3361 u8 reserved_at_20[0x3];
3362 u8 shampo_max_log_headers_entry_size[0x5];
3363 u8 reserved_at_28[0x18];
3364
3365 u8 reserved_at_40[0x7c0];
3366};
3367
e281682b
SM		 3368union mlx5_ifc_hca_cap_union_bits {
3369 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
67133eaa 3370 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
e281682b
SM		 3371 struct mlx5_ifc_odp_cap_bits odp_cap;
3372 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3373 struct mlx5_ifc_roce_cap_bits roce_cap;
3374 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3375 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3376 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3377 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
425a563a 3378 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3f0393a5 3379 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3380 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3381 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3382 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3383 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3384 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3385 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
7025329d 3386 struct mlx5_ifc_shampo_cap_bits shampo_cap;
8385c51f 3387 struct mlx5_ifc_macsec_cap_bits macsec_cap;
b4ff3a36 3388 u8 reserved_at_0[0x8000];
e281682b
SM		 3389};
3390
3391enum {
3392 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3393 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3394 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3395 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3396 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3397 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3398 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3399 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3400 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3401 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3402 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
e227ee99
LN		 3403 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3404 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
f5d23ee1 3405 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
0c06897a
OG		 3406};
3407
65c0f2c1
JL		 3408enum {
3409 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3410 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3411 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3412};
3413
e227ee99
LN		 3414enum {
3415 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
8385c51f 3416 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
e227ee99
LN		 3417};
3418
0c06897a
OG		 3419struct mlx5_ifc_vlan_bits {
3420 u8 ethtype[0x10];
3421 u8 prio[0x3];
3422 u8 cfi[0x1];
3423 u8 vid[0xc];
e281682b
SM		 3424};
3425
f5d23ee1
JL		 3426enum {
3427 MLX5_FLOW_METER_COLOR_RED = 0x0,
3428 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3429 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3430 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3431};
3432
3433enum {
3434 MLX5_EXE_ASO_FLOW_METER = 0x2,
3435};
3436
3437struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3438 u8 return_reg_id[0x4];
3439 u8 aso_type[0x4];
3440 u8 reserved_at_8[0x14];
3441 u8 action[0x1];
3442 u8 init_color[0x2];
3443 u8 meter_id[0x1];
3444};
3445
3446union mlx5_ifc_exe_aso_ctrl {
3447 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3448};
3449
3450struct mlx5_ifc_execute_aso_bits {
3451 u8 valid[0x1];
3452 u8 reserved_at_1[0x7];
3453 u8 aso_object_id[0x18];
3454
3455 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3456};
3457
e281682b 3458struct mlx5_ifc_flow_context_bits {
0c06897a 3459 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3460
3461 u8 group_id[0x20];
3462
b4ff3a36 3463 u8 reserved_at_40[0x8];
e281682b
SM		 3464 u8 flow_tag[0x18];
3465
b4ff3a36 3466 u8 reserved_at_60[0x10];
e281682b
SM		 3467 u8 action[0x10];
3468
1b115498 3469 u8 extended_destination[0x1];
65c0f2c1
JL		 3470 u8 reserved_at_81[0x1];
3471 u8 flow_source[0x2];
e227ee99 3472 u8 encrypt_decrypt_type[0x4];
e281682b
SM		 3473 u8 destination_list_size[0x18];
3474
9dc0b289
AV		 3475 u8 reserved_at_a0[0x8];
3476 u8 flow_counter_list_size[0x18];
3477
60786f09 3478 u8 packet_reformat_id[0x20];
7adbde20 3479
2a69cb9f
OG		 3480 u8 modify_header_id[0x20];
3481
8da6fe2a
JL		 3482 struct mlx5_ifc_vlan_bits push_vlan_2;
3483
e227ee99 3484 u8 encrypt_decrypt_obj_id[0x20];
78fb6122 3485 u8 reserved_at_140[0xc0];
e281682b
SM		 3486
3487 struct mlx5_ifc_fte_match_param_bits match_value;
3488
f5d23ee1
JL		 3489 struct mlx5_ifc_execute_aso_bits execute_aso[4];
3490
3491 u8 reserved_at_1300[0x500];
e281682b 3492
b6ca09cb 3493 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3494};
3495
3496enum {
3497 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3498 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3499};
3500
3501struct mlx5_ifc_xrc_srqc_bits {
3502 u8 state[0x4];
3503 u8 log_xrc_srq_size[0x4];
b4ff3a36 3504 u8 reserved_at_8[0x18];
e281682b
SM		 3505
3506 u8 wq_signature[0x1];
3507 u8 cont_srq[0x1];
99b77fef 3508 u8 reserved_at_22[0x1];
e281682b
SM		 3509 u8 rlky[0x1];
3510 u8 basic_cyclic_rcv_wqe[0x1];
3511 u8 log_rq_stride[0x3];
3512 u8 xrcd[0x18];
3513
3514 u8 page_offset[0x6];
99b77fef
YH		 3515 u8 reserved_at_46[0x1];
3516 u8 dbr_umem_valid[0x1];
e281682b
SM		 3517 u8 cqn[0x18];
3518
b4ff3a36 3519 u8 reserved_at_60[0x20];
e281682b
SM		 3520
3521 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3522 u8 reserved_at_81[0x1];
e281682b
SM		 3523 u8 log_page_size[0x6];
3524 u8 user_index[0x18];
3525
b4ff3a36 3526 u8 reserved_at_a0[0x20];
e281682b 3527
b4ff3a36 3528 u8 reserved_at_c0[0x8];
e281682b
SM		 3529 u8 pd[0x18];
3530
3531 u8 lwm[0x10];
3532 u8 wqe_cnt[0x10];
3533
b4ff3a36 3534 u8 reserved_at_100[0x40];
e281682b
SM		 3535
3536 u8 db_record_addr_h[0x20];
3537
3538 u8 db_record_addr_l[0x1e];
b4ff3a36 3539 u8 reserved_at_17e[0x2];
e281682b 3540
b4ff3a36 3541 u8 reserved_at_180[0x80];
e281682b
SM		 3542};
3543
61c5b5c9
MS		 3544struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3545 u8 counter_error_queues[0x20];
3546
3547 u8 total_error_queues[0x20];
3548
3549 u8 send_queue_priority_update_flow[0x20];
3550
3551 u8 reserved_at_60[0x20];
3552
3553 u8 nic_receive_steering_discard[0x40];
3554
3555 u8 receive_discard_vport_down[0x40];
3556
3557 u8 transmit_discard_vport_down[0x40];
3558
3e94e61b
SM		 3559 u8 async_eq_overrun[0x20];
3560
3561 u8 comp_eq_overrun[0x20];
3562
3563 u8 reserved_at_180[0x20];
3564
3565 u8 invalid_command[0x20];
3566
3567 u8 quota_exceeded_command[0x20];
30b10e89
MS		 3568
3569 u8 internal_rq_out_of_buffer[0x20];
3570
3e94e61b
SM		 3571 u8 cq_overrun[0x20];
3572
16ab85e7
GP		 3573 u8 eth_wqe_too_small[0x20];
3574
3575 u8 reserved_at_220[0xdc0];
61c5b5c9
MS		 3576};
3577
e281682b
SM		 3578struct mlx5_ifc_traffic_counter_bits {
3579 u8 packets[0x40];
3580
3581 u8 octets[0x40];
3582};
3583
3584struct mlx5_ifc_tisc_bits {
84df61eb 3585 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3586 u8 tls_en[0x1];
7761f9ee 3587 u8 reserved_at_2[0x2];
84df61eb
AH		 3588 u8 lag_tx_port_affinity[0x04];
3589
3590 u8 reserved_at_8[0x4];
e281682b 3591 u8 prio[0x4];
b4ff3a36 3592 u8 reserved_at_10[0x10];
e281682b 3593
b4ff3a36 3594 u8 reserved_at_20[0x100];
e281682b 3595
b4ff3a36 3596 u8 reserved_at_120[0x8];
e281682b
SM		 3597 u8 transport_domain[0x18];
3598
500a3d0d
ES		 3599 u8 reserved_at_140[0x8];
3600 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3601
3602 u8 reserved_at_160[0x8];
3603 u8 pd[0x18];
3604
3605 u8 reserved_at_180[0x380];
e281682b
SM		 3606};
3607
3608enum {
3609 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3610 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3611};
3612
3613enum {
50f477fe
BBI		 3614 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3615 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
e281682b
SM		 3616};
3617
3618enum {
2be6967c
SM		 3619 MLX5_RX_HASH_FN_NONE = 0x0,
3620 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3621 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3622};
3623
3624enum {
5d773ff4
MB		 3625 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3626 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3627};
3628
3629struct mlx5_ifc_tirc_bits {
b4ff3a36 3630 u8 reserved_at_0[0x20];
e281682b
SM		 3631
3632 u8 disp_type[0x4];
ee5cdf7a
TT		 3633 u8 tls_en[0x1];
3634 u8 reserved_at_25[0x1b];
e281682b 3635
b4ff3a36 3636 u8 reserved_at_40[0x40];
e281682b 3637
b4ff3a36 3638 u8 reserved_at_80[0x4];
e281682b 3639 u8 lro_timeout_period_usecs[0x10];
50f477fe 3640 u8 packet_merge_mask[0x4];
e281682b
SM		 3641 u8 lro_max_ip_payload_size[0x8];
3642
b4ff3a36 3643 u8 reserved_at_a0[0x40];
e281682b 3644
b4ff3a36 3645 u8 reserved_at_e0[0x8];
e281682b
SM		 3646 u8 inline_rqn[0x18];
3647
3648 u8 rx_hash_symmetric[0x1];
b4ff3a36 3649 u8 reserved_at_101[0x1];
e281682b 3650 u8 tunneled_offload_en[0x1];
b4ff3a36 3651 u8 reserved_at_103[0x5];
e281682b
SM		 3652 u8 indirect_table[0x18];
3653
3654 u8 rx_hash_fn[0x4];
b4ff3a36 3655 u8 reserved_at_124[0x2];
e281682b
SM		 3656 u8 self_lb_block[0x2];
3657 u8 transport_domain[0x18];
3658
3659 u8 rx_hash_toeplitz_key[10][0x20];
3660
3661 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3662
3663 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3664
b4ff3a36 3665 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3666};
3667
3668enum {
3669 MLX5_SRQC_STATE_GOOD = 0x0,
3670 MLX5_SRQC_STATE_ERROR = 0x1,
3671};
3672
3673struct mlx5_ifc_srqc_bits {
3674 u8 state[0x4];
3675 u8 log_srq_size[0x4];
b4ff3a36 3676 u8 reserved_at_8[0x18];
e281682b
SM		 3677
3678 u8 wq_signature[0x1];
3679 u8 cont_srq[0x1];
b4ff3a36 3680 u8 reserved_at_22[0x1];
e281682b 3681 u8 rlky[0x1];
b4ff3a36 3682 u8 reserved_at_24[0x1];
e281682b
SM		 3683 u8 log_rq_stride[0x3];
3684 u8 xrcd[0x18];
3685
3686 u8 page_offset[0x6];
b4ff3a36 3687 u8 reserved_at_46[0x2];
e281682b
SM		 3688 u8 cqn[0x18];
3689
b4ff3a36 3690 u8 reserved_at_60[0x20];
e281682b 3691
b4ff3a36 3692 u8 reserved_at_80[0x2];
e281682b 3693 u8 log_page_size[0x6];
b4ff3a36 3694 u8 reserved_at_88[0x18];
e281682b 3695
b4ff3a36 3696 u8 reserved_at_a0[0x20];
e281682b 3697
b4ff3a36 3698 u8 reserved_at_c0[0x8];
e281682b
SM		 3699 u8 pd[0x18];
3700
3701 u8 lwm[0x10];
3702 u8 wqe_cnt[0x10];
3703
b4ff3a36 3704 u8 reserved_at_100[0x40];
e281682b 3705
01949d01 3706 u8 dbr_addr[0x40];
e281682b 3707
b4ff3a36 3708 u8 reserved_at_180[0x80];
e281682b
SM		 3709};
3710
3711enum {
3712 MLX5_SQC_STATE_RST = 0x0,
3713 MLX5_SQC_STATE_RDY = 0x1,
3714 MLX5_SQC_STATE_ERR = 0x3,
3715};
3716
3717struct mlx5_ifc_sqc_bits {
3718 u8 rlky[0x1];
3719 u8 cd_master[0x1];
3720 u8 fre[0x1];
3721 u8 flush_in_error_en[0x1];
795b609c 3722 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3723 u8 min_wqe_inline_mode[0x3];
e281682b 3724 u8 state[0x4];
7d5e1423 3725 u8 reg_umr[0x1];
547eede0 3726 u8 allow_swp[0x1];
40817cdb 3727 u8 hairpin[0x1];
a6a217dd
AL		 3728 u8 reserved_at_f[0xb];
3729 u8 ts_format[0x2];
3730 u8 reserved_at_1c[0x4];
e281682b 3731
b4ff3a36 3732 u8 reserved_at_20[0x8];
e281682b
SM		 3733 u8 user_index[0x18];
3734
b4ff3a36 3735 u8 reserved_at_40[0x8];
e281682b
SM		 3736 u8 cqn[0x18];
3737
40817cdb
OG		 3738 u8 reserved_at_60[0x8];
3739 u8 hairpin_peer_rq[0x18];
3740
3741 u8 reserved_at_80[0x10];
3742 u8 hairpin_peer_vhca[0x10];
3743
59d2ae1d 3744 u8 reserved_at_a0[0x20];
e281682b 3745
59d2ae1d
EBE		 3746 u8 reserved_at_c0[0x8];
3747 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3748
59d2ae1d 3749 u8 reserved_at_e0[0x10];
7486216b 3750 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3751 u8 tis_lst_sz[0x10];
214baf22 3752 u8 qos_queue_group_id[0x10];
e281682b 3753
b4ff3a36 3754 u8 reserved_at_120[0x40];
e281682b 3755
b4ff3a36 3756 u8 reserved_at_160[0x8];
e281682b
SM		 3757 u8 tis_num_0[0x18];
3758
3759 struct mlx5_ifc_wq_bits wq;
3760};
3761
813f8540
MHY		 3762enum {
3763 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3764 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3765 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3766 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
214baf22 3767 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
813f8540
MHY		 3768};
3769
6cedde45
EC		 3770enum {
3771 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3772 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3773 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3774 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3775};
3776
813f8540
MHY		 3777struct mlx5_ifc_scheduling_context_bits {
3778 u8 element_type[0x8];
3779 u8 reserved_at_8[0x18];
3780
3781 u8 element_attributes[0x20];
3782
3783 u8 parent_element_id[0x20];
3784
3785 u8 reserved_at_60[0x40];
3786
3787 u8 bw_share[0x20];
3788
3789 u8 max_average_bw[0x20];
3790
3791 u8 reserved_at_e0[0x120];
3792};
3793
e281682b 3794struct mlx5_ifc_rqtc_bits {
8a06a79b 3795 u8 reserved_at_0[0xa0];
e281682b 3796
8a06a79b
EC		 3797 u8 reserved_at_a0[0x5];
3798 u8 list_q_type[0x3];
3799 u8 reserved_at_a8[0x8];
3800 u8 rqt_max_size[0x10];
e281682b 3801
8a06a79b
EC		 3802 u8 rq_vhca_id_format[0x1];
3803 u8 reserved_at_c1[0xf];
3804 u8 rqt_actual_size[0x10];
e281682b 3805
8a06a79b 3806 u8 reserved_at_e0[0x6a0];
e281682b 3807
b6ca09cb 3808 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3809};
3810
3811enum {
3812 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3813 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3814};
3815
3816enum {
3817 MLX5_RQC_STATE_RST = 0x0,
3818 MLX5_RQC_STATE_RDY = 0x1,
3819 MLX5_RQC_STATE_ERR = 0x3,
3820};
3821
7025329d
BBI		 3822enum {
3823 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3824 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3825 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3826};
3827
3828enum {
3829 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3830 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3831 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3832};
3833
e281682b
SM		 3834struct mlx5_ifc_rqc_bits {
3835 u8 rlky[0x1];
03404e8a 3836 u8 delay_drop_en[0x1];
7d5e1423 3837 u8 scatter_fcs[0x1];
e281682b
SM		 3838 u8 vsd[0x1];
3839 u8 mem_rq_type[0x4];
3840 u8 state[0x4];
b4ff3a36 3841 u8 reserved_at_c[0x1];
e281682b 3842 u8 flush_in_error_en[0x1];
40817cdb 3843 u8 hairpin[0x1];
a6a217dd
AL		 3844 u8 reserved_at_f[0xb];
3845 u8 ts_format[0x2];
3846 u8 reserved_at_1c[0x4];
e281682b 3847
b4ff3a36 3848 u8 reserved_at_20[0x8];
e281682b
SM		 3849 u8 user_index[0x18];
3850
b4ff3a36 3851 u8 reserved_at_40[0x8];
e281682b
SM		 3852 u8 cqn[0x18];
3853
3854 u8 counter_set_id[0x8];
b4ff3a36 3855 u8 reserved_at_68[0x18];
e281682b 3856
b4ff3a36 3857 u8 reserved_at_80[0x8];
e281682b
SM		 3858 u8 rmpn[0x18];
3859
40817cdb
OG		 3860 u8 reserved_at_a0[0x8];
3861 u8 hairpin_peer_sq[0x18];
3862
3863 u8 reserved_at_c0[0x10];
3864 u8 hairpin_peer_vhca[0x10];
3865
7025329d
BBI		 3866 u8 reserved_at_e0[0x46];
3867 u8 shampo_no_match_alignment_granularity[0x2];
3868 u8 reserved_at_128[0x6];
3869 u8 shampo_match_criteria_type[0x2];
3870 u8 reservation_timeout[0x10];
3871
3872 u8 reserved_at_140[0x40];
e281682b
SM		 3873
3874 struct mlx5_ifc_wq_bits wq;
3875};
3876
3877enum {
3878 MLX5_RMPC_STATE_RDY = 0x1,
3879 MLX5_RMPC_STATE_ERR = 0x3,
3880};
3881
3882struct mlx5_ifc_rmpc_bits {
b4ff3a36 3883 u8 reserved_at_0[0x8];
e281682b 3884 u8 state[0x4];
b4ff3a36 3885 u8 reserved_at_c[0x14];
e281682b
SM		 3886
3887 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3888 u8 reserved_at_21[0x1f];
e281682b 3889
b4ff3a36 3890 u8 reserved_at_40[0x140];
e281682b
SM		 3891
3892 struct mlx5_ifc_wq_bits wq;
3893};
3894
0372c546
YH		 3895enum {
3896 VHCA_ID_TYPE_HW = 0,
3897 VHCA_ID_TYPE_SW = 1,
3898};
3899
e281682b 3900struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3901 u8 reserved_at_0[0x5];
3902 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3903 u8 reserved_at_8[0x15];
3904 u8 disable_mc_local_lb[0x1];
3905 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3906 u8 roce_en[0x1];
3907
d82b7318 3908 u8 arm_change_event[0x1];
b4ff3a36 3909 u8 reserved_at_21[0x1a];
d82b7318
SM		 3910 u8 event_on_mtu[0x1];
3911 u8 event_on_promisc_change[0x1];
3912 u8 event_on_vlan_change[0x1];
3913 u8 event_on_mc_address_change[0x1];
3914 u8 event_on_uc_address_change[0x1];
e281682b 3915
0372c546
YH		 3916 u8 vhca_id_type[0x1];
3917 u8 reserved_at_41[0xb];
32f69e4b
DJ		 3918 u8 affiliation_criteria[0x4];
3919 u8 affiliated_vhca_id[0x10];
3920
3921 u8 reserved_at_60[0xd0];
d82b7318
SM		 3922
3923 u8 mtu[0x10];
3924
9efa7525
AS		 3925 u8 system_image_guid[0x40];
3926 u8 port_guid[0x40];
3927 u8 node_guid[0x40];
3928
b4ff3a36 3929 u8 reserved_at_200[0x140];
9efa7525 3930 u8 qkey_violation_counter[0x10];
b4ff3a36 3931 u8 reserved_at_350[0x430];
d82b7318
SM		 3932
3933 u8 promisc_uc[0x1];
3934 u8 promisc_mc[0x1];
3935 u8 promisc_all[0x1];
b4ff3a36 3936 u8 reserved_at_783[0x2];
e281682b 3937 u8 allowed_list_type[0x3];
b4ff3a36 3938 u8 reserved_at_788[0xc];
e281682b
SM		 3939 u8 allowed_list_size[0xc];
3940
3941 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3942
b4ff3a36 3943 u8 reserved_at_7e0[0x20];
e281682b 3944
b6ca09cb 3945 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3946};
3947
3948enum {
3949 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3950 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3951 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3952 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3953 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3954 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3955};
3956
3957struct mlx5_ifc_mkc_bits {
b4ff3a36 3958 u8 reserved_at_0[0x1];
e281682b 3959 u8 free[0x1];
cdbd0d2b
AL		 3960 u8 reserved_at_2[0x1];
3961 u8 access_mode_4_2[0x3];
3962 u8 reserved_at_6[0x7];
3963 u8 relaxed_ordering_write[0x1];
3964 u8 reserved_at_e[0x1];
e281682b
SM		 3965 u8 small_fence_on_rdma_read_response[0x1];
3966 u8 umr_en[0x1];
3967 u8 a[0x1];
3968 u8 rw[0x1];
3969 u8 rr[0x1];
3970 u8 lw[0x1];
3971 u8 lr[0x1];
cdbd0d2b 3972 u8 access_mode_1_0[0x2];
4bf207d7
JG		 3973 u8 reserved_at_18[0x2];
3974 u8 ma_translation_mode[0x2];
3975 u8 reserved_at_1c[0x4];
e281682b
SM		 3976
3977 u8 qpn[0x18];
3978 u8 mkey_7_0[0x8];
3979
b4ff3a36 3980 u8 reserved_at_40[0x20];
e281682b
SM		 3981
3982 u8 length64[0x1];
3983 u8 bsf_en[0x1];
3984 u8 sync_umr[0x1];
b4ff3a36 3985 u8 reserved_at_63[0x2];
e281682b 3986 u8 expected_sigerr_count[0x1];
b4ff3a36 3987 u8 reserved_at_66[0x1];
e281682b
SM		 3988 u8 en_rinval[0x1];
3989 u8 pd[0x18];
3990
3991 u8 start_addr[0x40];
3992
3993 u8 len[0x40];
3994
3995 u8 bsf_octword_size[0x20];
3996
b4ff3a36 3997 u8 reserved_at_120[0x80];
e281682b
SM		 3998
3999 u8 translations_octword_size[0x20];
4000
a880a6dd
MG		 4001 u8 reserved_at_1c0[0x19];
4002 u8 relaxed_ordering_read[0x1];
4003 u8 reserved_at_1d9[0x1];
e281682b
SM		 4004 u8 log_page_size[0x5];
4005
b4ff3a36 4006 u8 reserved_at_1e0[0x20];
e281682b
SM		 4007};
4008
4009struct mlx5_ifc_pkey_bits {
b4ff3a36 4010 u8 reserved_at_0[0x10];
e281682b
SM		 4011 u8 pkey[0x10];
4012};
4013
4014struct mlx5_ifc_array128_auto_bits {
4015 u8 array128_auto[16][0x8];
4016};
4017
4018struct mlx5_ifc_hca_vport_context_bits {
4019 u8 field_select[0x20];
4020
b4ff3a36 4021 u8 reserved_at_20[0xe0];
e281682b
SM		 4022
4023 u8 sm_virt_aware[0x1];
4024 u8 has_smi[0x1];
4025 u8 has_raw[0x1];
4026 u8 grh_required[0x1];
b4ff3a36 4027 u8 reserved_at_104[0xc];
707c4602
MD		 4028 u8 port_physical_state[0x4];
4029 u8 vport_state_policy[0x4];
4030 u8 port_state[0x4];
e281682b
SM		 4031 u8 vport_state[0x4];
4032
b4ff3a36 4033 u8 reserved_at_120[0x20];
707c4602
MD		 4034
4035 u8 system_image_guid[0x40];
e281682b
SM		 4036
4037 u8 port_guid[0x40];
4038
4039 u8 node_guid[0x40];
4040
4041 u8 cap_mask1[0x20];
4042
4043 u8 cap_mask1_field_select[0x20];
4044
4045 u8 cap_mask2[0x20];
4046
4047 u8 cap_mask2_field_select[0x20];
4048
b4ff3a36 4049 u8 reserved_at_280[0x80];
e281682b
SM		 4050
4051 u8 lid[0x10];
b4ff3a36 4052 u8 reserved_at_310[0x4];
e281682b
SM		 4053 u8 init_type_reply[0x4];
4054 u8 lmc[0x3];
4055 u8 subnet_timeout[0x5];
4056
4057 u8 sm_lid[0x10];
4058 u8 sm_sl[0x4];
b4ff3a36 4059 u8 reserved_at_334[0xc];
e281682b
SM		 4060
4061 u8 qkey_violation_counter[0x10];
4062 u8 pkey_violation_counter[0x10];
4063
b4ff3a36 4064 u8 reserved_at_360[0xca0];
e281682b
SM		 4065};
4066
d6666753 4067struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 4068 u8 fdb_to_vport_reg_c[0x1];
4069 u8 reserved_at_1[0x2];
d6666753
SM		 4070 u8 vport_svlan_strip[0x1];
4071 u8 vport_cvlan_strip[0x1];
4072 u8 vport_svlan_insert[0x1];
4073 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 4074 u8 fdb_to_vport_reg_c_id[0x8];
4075 u8 reserved_at_10[0x10];
d6666753 4076
b4ff3a36 4077 u8 reserved_at_20[0x20];
d6666753
SM		 4078
4079 u8 svlan_cfi[0x1];
4080 u8 svlan_pcp[0x3];
4081 u8 svlan_id[0xc];
4082 u8 cvlan_cfi[0x1];
4083 u8 cvlan_pcp[0x3];
4084 u8 cvlan_id[0xc];
4085
97b5484e
AV		 4086 u8 reserved_at_60[0x720];
4087
4088 u8 sw_steering_vport_icm_address_rx[0x40];
4089
4090 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 4091};
4092
e281682b
SM		 4093enum {
4094 MLX5_EQC_STATUS_OK = 0x0,
4095 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4096};
4097
4098enum {
4099 MLX5_EQC_ST_ARMED = 0x9,
4100 MLX5_EQC_ST_FIRED = 0xa,
4101};
4102
4103struct mlx5_ifc_eqc_bits {
4104 u8 status[0x4];
b4ff3a36 4105 u8 reserved_at_4[0x9];
e281682b
SM		 4106 u8 ec[0x1];
4107 u8 oi[0x1];
b4ff3a36 4108 u8 reserved_at_f[0x5];
e281682b 4109 u8 st[0x4];
b4ff3a36 4110 u8 reserved_at_18[0x8];
e281682b 4111
b4ff3a36 4112 u8 reserved_at_20[0x20];
e281682b 4113
b4ff3a36 4114 u8 reserved_at_40[0x14];
e281682b 4115 u8 page_offset[0x6];
b4ff3a36 4116 u8 reserved_at_5a[0x6];
e281682b 4117
b4ff3a36 4118 u8 reserved_at_60[0x3];
e281682b
SM		 4119 u8 log_eq_size[0x5];
4120 u8 uar_page[0x18];
4121
b4ff3a36 4122 u8 reserved_at_80[0x20];
e281682b 4123
3af26495
SD		 4124 u8 reserved_at_a0[0x14];
4125 u8 intr[0xc];
e281682b 4126
b4ff3a36 4127 u8 reserved_at_c0[0x3];
e281682b 4128 u8 log_page_size[0x5];
b4ff3a36 4129 u8 reserved_at_c8[0x18];
e281682b 4130
b4ff3a36 4131 u8 reserved_at_e0[0x60];
e281682b 4132
b4ff3a36 4133 u8 reserved_at_140[0x8];
e281682b
SM		 4134 u8 consumer_counter[0x18];
4135
b4ff3a36 4136 u8 reserved_at_160[0x8];
e281682b
SM		 4137 u8 producer_counter[0x18];
4138
b4ff3a36 4139 u8 reserved_at_180[0x80];
e281682b
SM		 4140};
4141
4142enum {
4143 MLX5_DCTC_STATE_ACTIVE = 0x0,
4144 MLX5_DCTC_STATE_DRAINING = 0x1,
4145 MLX5_DCTC_STATE_DRAINED = 0x2,
4146};
4147
4148enum {
4149 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4150 MLX5_DCTC_CS_RES_NA = 0x1,
4151 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4152};
4153
4154enum {
4155 MLX5_DCTC_MTU_256_BYTES = 0x1,
4156 MLX5_DCTC_MTU_512_BYTES = 0x2,
4157 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4158 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4159 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4160};
4161
4162struct mlx5_ifc_dctc_bits {
b4ff3a36 4163 u8 reserved_at_0[0x4];
e281682b 4164 u8 state[0x4];
b4ff3a36 4165 u8 reserved_at_8[0x18];
e281682b 4166
b4ff3a36 4167 u8 reserved_at_20[0x8];
e281682b
SM		 4168 u8 user_index[0x18];
4169
b4ff3a36 4170 u8 reserved_at_40[0x8];
e281682b
SM		 4171 u8 cqn[0x18];
4172
4173 u8 counter_set_id[0x8];
4174 u8 atomic_mode[0x4];
4175 u8 rre[0x1];
4176 u8 rwe[0x1];
4177 u8 rae[0x1];
4178 u8 atomic_like_write_en[0x1];
4179 u8 latency_sensitive[0x1];
4180 u8 rlky[0x1];
4181 u8 free_ar[0x1];
b4ff3a36 4182 u8 reserved_at_73[0xd];
e281682b 4183
b4ff3a36 4184 u8 reserved_at_80[0x8];
e281682b 4185 u8 cs_res[0x8];
b4ff3a36 4186 u8 reserved_at_90[0x3];
e281682b 4187 u8 min_rnr_nak[0x5];
b4ff3a36 4188 u8 reserved_at_98[0x8];
e281682b 4189
b4ff3a36 4190 u8 reserved_at_a0[0x8];
7486216b 4191 u8 srqn_xrqn[0x18];
e281682b 4192
b4ff3a36 4193 u8 reserved_at_c0[0x8];
e281682b
SM		 4194 u8 pd[0x18];
4195
4196 u8 tclass[0x8];
b4ff3a36 4197 u8 reserved_at_e8[0x4];
e281682b
SM		 4198 u8 flow_label[0x14];
4199
4200 u8 dc_access_key[0x40];
4201
b4ff3a36 4202 u8 reserved_at_140[0x5];
e281682b
SM		 4203 u8 mtu[0x3];
4204 u8 port[0x8];
4205 u8 pkey_index[0x10];
4206
b4ff3a36 4207 u8 reserved_at_160[0x8];
e281682b 4208 u8 my_addr_index[0x8];
b4ff3a36 4209 u8 reserved_at_170[0x8];
e281682b
SM		 4210 u8 hop_limit[0x8];
4211
4212 u8 dc_access_key_violation_count[0x20];
4213
b4ff3a36 4214 u8 reserved_at_1a0[0x14];
e281682b
SM		 4215 u8 dei_cfi[0x1];
4216 u8 eth_prio[0x3];
4217 u8 ecn[0x2];
4218 u8 dscp[0x6];
4219
a645a89d
LR		 4220 u8 reserved_at_1c0[0x20];
4221 u8 ece[0x20];
e281682b
SM		 4222};
4223
4224enum {
4225 MLX5_CQC_STATUS_OK = 0x0,
4226 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4227 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4228};
4229
4230enum {
4231 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4232 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4233};
4234
4235enum {
4236 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4237 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4238 MLX5_CQC_ST_FIRED = 0xa,
4239};
4240
7d5e1423
SM		 4241enum {
4242 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4243 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 4244 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 4245};
4246
e281682b
SM		 4247struct mlx5_ifc_cqc_bits {
4248 u8 status[0x4];
bd371975
LR		 4249 u8 reserved_at_4[0x2];
4250 u8 dbr_umem_valid[0x1];
616d5769 4251 u8 apu_cq[0x1];
e281682b
SM		 4252 u8 cqe_sz[0x3];
4253 u8 cc[0x1];
b4ff3a36 4254 u8 reserved_at_c[0x1];
e281682b
SM		 4255 u8 scqe_break_moderation_en[0x1];
4256 u8 oi[0x1];
7d5e1423
SM		 4257 u8 cq_period_mode[0x2];
4258 u8 cqe_comp_en[0x1];
e281682b
SM		 4259 u8 mini_cqe_res_format[0x2];
4260 u8 st[0x4];
cdcdce94
OL		 4261 u8 reserved_at_18[0x6];
4262 u8 cqe_compression_layout[0x2];
e281682b 4263
b4ff3a36 4264 u8 reserved_at_20[0x20];
e281682b 4265
b4ff3a36 4266 u8 reserved_at_40[0x14];
e281682b 4267 u8 page_offset[0x6];
b4ff3a36 4268 u8 reserved_at_5a[0x6];
e281682b 4269
b4ff3a36 4270 u8 reserved_at_60[0x3];
e281682b
SM		 4271 u8 log_cq_size[0x5];
4272 u8 uar_page[0x18];
4273
b4ff3a36 4274 u8 reserved_at_80[0x4];
e281682b
SM		 4275 u8 cq_period[0xc];
4276 u8 cq_max_count[0x10];
4277
616d5769 4278 u8 c_eqn_or_apu_element[0x20];
e281682b 4279
b4ff3a36 4280 u8 reserved_at_c0[0x3];
e281682b 4281 u8 log_page_size[0x5];
b4ff3a36 4282 u8 reserved_at_c8[0x18];
e281682b 4283
b4ff3a36 4284 u8 reserved_at_e0[0x20];
e281682b 4285
b4ff3a36 4286 u8 reserved_at_100[0x8];
e281682b
SM		 4287 u8 last_notified_index[0x18];
4288
b4ff3a36 4289 u8 reserved_at_120[0x8];
e281682b
SM		 4290 u8 last_solicit_index[0x18];
4291
b4ff3a36 4292 u8 reserved_at_140[0x8];
e281682b
SM		 4293 u8 consumer_counter[0x18];
4294
b4ff3a36 4295 u8 reserved_at_160[0x8];
e281682b
SM		 4296 u8 producer_counter[0x18];
4297
b4ff3a36 4298 u8 reserved_at_180[0x40];
e281682b
SM		 4299
4300 u8 dbr_addr[0x40];
4301};
4302
4303union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4304 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4305 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4306 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 4307 u8 reserved_at_0[0x800];
e281682b
SM		 4308};
4309
4310struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 4311 u8 reserved_at_0[0xc0];
e281682b 4312
b4ff3a36 4313 u8 reserved_at_c0[0x8];
211e6c80
MD		 4314 u8 ieee_vendor_id[0x18];
4315
b4ff3a36 4316 u8 reserved_at_e0[0x10];
e281682b
SM		 4317 u8 vsd_vendor_id[0x10];
4318
4319 u8 vsd[208][0x8];
4320
4321 u8 vsd_contd_psid[16][0x8];
4322};
4323
7486216b
SM		 4324enum {
4325 MLX5_XRQC_STATE_GOOD = 0x0,
4326 MLX5_XRQC_STATE_ERROR = 0x1,
4327};
4328
4329enum {
4330 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4331 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4332};
4333
4334enum {
4335 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4336};
4337
4338struct mlx5_ifc_tag_matching_topology_context_bits {
4339 u8 log_matching_list_sz[0x4];
4340 u8 reserved_at_4[0xc];
4341 u8 append_next_index[0x10];
4342
4343 u8 sw_phase_cnt[0x10];
4344 u8 hw_phase_cnt[0x10];
4345
4346 u8 reserved_at_40[0x40];
4347};
4348
4349struct mlx5_ifc_xrqc_bits {
4350 u8 state[0x4];
4351 u8 rlkey[0x1];
4352 u8 reserved_at_5[0xf];
4353 u8 topology[0x4];
4354 u8 reserved_at_18[0x4];
4355 u8 offload[0x4];
4356
4357 u8 reserved_at_20[0x8];
4358 u8 user_index[0x18];
4359
4360 u8 reserved_at_40[0x8];
4361 u8 cqn[0x18];
4362
4363 u8 reserved_at_60[0xa0];
4364
4365 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4366
6e44636a 4367 u8 reserved_at_180[0x280];
7486216b
SM		 4368
4369 struct mlx5_ifc_wq_bits wq;
4370};
4371
e281682b
SM		 4372union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4373 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4374 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 4375 u8 reserved_at_0[0x20];
e281682b
SM		 4376};
4377
4378union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4379 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4380 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4381 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 4382 u8 reserved_at_0[0x20];
e281682b
SM		 4383};
4384
4385union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4386 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4387 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4388 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4389 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4390 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4391 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 4392 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4393 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 4394 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 4395 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 4396 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 4397 u8 reserved_at_0[0x7c0];
e281682b
SM		 4398};
4399
8ed1a630
GP		 4400union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4401 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4402 u8 reserved_at_0[0x7c0];
4403};
4404
e281682b
SM		 4405union mlx5_ifc_event_auto_bits {
4406 struct mlx5_ifc_comp_event_bits comp_event;
4407 struct mlx5_ifc_dct_events_bits dct_events;
4408 struct mlx5_ifc_qp_events_bits qp_events;
4409 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4410 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4411 struct mlx5_ifc_cq_error_bits cq_error;
4412 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4413 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4414 struct mlx5_ifc_gpio_event_bits gpio_event;
4415 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4416 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4417 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 4418 u8 reserved_at_0[0xe0];
e281682b
SM		 4419};
4420
4421struct mlx5_ifc_health_buffer_bits {
b4ff3a36 4422 u8 reserved_at_0[0x100];
e281682b
SM		 4423
4424 u8 assert_existptr[0x20];
4425
4426 u8 assert_callra[0x20];
4427
cb464ba5
AL		 4428 u8 reserved_at_140[0x20];
4429
4430 u8 time[0x20];
e281682b
SM		 4431
4432 u8 fw_version[0x20];
4433
4434 u8 hw_id[0x20];
4435
cb464ba5
AL		 4436 u8 rfr[0x1];
4437 u8 reserved_at_1c1[0x3];
4438 u8 valid[0x1];
4439 u8 severity[0x3];
4440 u8 reserved_at_1c8[0x18];
e281682b
SM		 4441
4442 u8 irisc_index[0x8];
4443 u8 synd[0x8];
4444 u8 ext_synd[0x10];
4445};
4446
4447struct mlx5_ifc_register_loopback_control_bits {
4448 u8 no_lb[0x1];
b4ff3a36 4449 u8 reserved_at_1[0x7];
e281682b 4450 u8 port[0x8];
b4ff3a36 4451 u8 reserved_at_10[0x10];
e281682b 4452
b4ff3a36 4453 u8 reserved_at_20[0x60];
e281682b
SM		 4454};
4455
813f8540
MHY		 4456struct mlx5_ifc_vport_tc_element_bits {
4457 u8 traffic_class[0x4];
4458 u8 reserved_at_4[0xc];
4459 u8 vport_number[0x10];
4460};
4461
4462struct mlx5_ifc_vport_element_bits {
4463 u8 reserved_at_0[0x10];
4464 u8 vport_number[0x10];
4465};
4466
4467enum {
4468 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4469 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4470 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4471};
4472
4473struct mlx5_ifc_tsar_element_bits {
4474 u8 reserved_at_0[0x8];
4475 u8 tsar_type[0x8];
4476 u8 reserved_at_10[0x10];
4477};
4478
8812c24d
MD		 4479enum {
4480 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4481 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4482};
4483
e281682b
SM		 4484struct mlx5_ifc_teardown_hca_out_bits {
4485 u8 status[0x8];
b4ff3a36 4486 u8 reserved_at_8[0x18];
e281682b
SM		 4487
4488 u8 syndrome[0x20];
4489
8812c24d
MD		 4490 u8 reserved_at_40[0x3f];
4491
fcd29ad1 4492 u8 state[0x1];
e281682b
SM		 4493};
4494
4495enum {
4496 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4497 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4498 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4499};
4500
4501struct mlx5_ifc_teardown_hca_in_bits {
4502 u8 opcode[0x10];
b4ff3a36 4503 u8 reserved_at_10[0x10];
e281682b 4504
b4ff3a36 4505 u8 reserved_at_20[0x10];
e281682b
SM		 4506 u8 op_mod[0x10];
4507
b4ff3a36 4508 u8 reserved_at_40[0x10];
e281682b
SM		 4509 u8 profile[0x10];
4510
b4ff3a36 4511 u8 reserved_at_60[0x20];
e281682b
SM		 4512};
4513
4514struct mlx5_ifc_sqerr2rts_qp_out_bits {
4515 u8 status[0x8];
b4ff3a36 4516 u8 reserved_at_8[0x18];
e281682b
SM		 4517
4518 u8 syndrome[0x20];
4519
b4ff3a36 4520 u8 reserved_at_40[0x40];
e281682b
SM		 4521};
4522
4523struct mlx5_ifc_sqerr2rts_qp_in_bits {
4524 u8 opcode[0x10];
4ac63ec7 4525 u8 uid[0x10];
e281682b 4526
b4ff3a36 4527 u8 reserved_at_20[0x10];
e281682b
SM		 4528 u8 op_mod[0x10];
4529
b4ff3a36 4530 u8 reserved_at_40[0x8];
e281682b
SM		 4531 u8 qpn[0x18];
4532
b4ff3a36 4533 u8 reserved_at_60[0x20];
e281682b
SM		 4534
4535 u8 opt_param_mask[0x20];
4536
b4ff3a36 4537 u8 reserved_at_a0[0x20];
e281682b
SM		 4538
4539 struct mlx5_ifc_qpc_bits qpc;
4540
b4ff3a36 4541 u8 reserved_at_800[0x80];
e281682b
SM		 4542};
4543
4544struct mlx5_ifc_sqd2rts_qp_out_bits {
4545 u8 status[0x8];
b4ff3a36 4546 u8 reserved_at_8[0x18];
e281682b
SM		 4547
4548 u8 syndrome[0x20];
4549
b4ff3a36 4550 u8 reserved_at_40[0x40];
e281682b
SM		 4551};
4552
4553struct mlx5_ifc_sqd2rts_qp_in_bits {
4554 u8 opcode[0x10];
4ac63ec7 4555 u8 uid[0x10];
e281682b 4556
b4ff3a36 4557 u8 reserved_at_20[0x10];
e281682b
SM		 4558 u8 op_mod[0x10];
4559
b4ff3a36 4560 u8 reserved_at_40[0x8];
e281682b
SM		 4561 u8 qpn[0x18];
4562
b4ff3a36 4563 u8 reserved_at_60[0x20];
e281682b
SM		 4564
4565 u8 opt_param_mask[0x20];
4566
b4ff3a36 4567 u8 reserved_at_a0[0x20];
e281682b
SM		 4568
4569 struct mlx5_ifc_qpc_bits qpc;
4570
b4ff3a36 4571 u8 reserved_at_800[0x80];
e281682b
SM		 4572};
4573
4574struct mlx5_ifc_set_roce_address_out_bits {
4575 u8 status[0x8];
b4ff3a36 4576 u8 reserved_at_8[0x18];
e281682b
SM		 4577
4578 u8 syndrome[0x20];
4579
b4ff3a36 4580 u8 reserved_at_40[0x40];
e281682b
SM		 4581};
4582
4583struct mlx5_ifc_set_roce_address_in_bits {
4584 u8 opcode[0x10];
b4ff3a36 4585 u8 reserved_at_10[0x10];
e281682b 4586
b4ff3a36 4587 u8 reserved_at_20[0x10];
e281682b
SM		 4588 u8 op_mod[0x10];
4589
4590 u8 roce_address_index[0x10];
32f69e4b
DJ		 4591 u8 reserved_at_50[0xc];
4592 u8 vhca_port_num[0x4];
e281682b 4593
b4ff3a36 4594 u8 reserved_at_60[0x20];
e281682b
SM		 4595
4596 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4597};
4598
4599struct mlx5_ifc_set_mad_demux_out_bits {
4600 u8 status[0x8];
b4ff3a36 4601 u8 reserved_at_8[0x18];
e281682b
SM		 4602
4603 u8 syndrome[0x20];
4604
b4ff3a36 4605 u8 reserved_at_40[0x40];
e281682b
SM		 4606};
4607
4608enum {
4609 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4610 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4611};
4612
4613struct mlx5_ifc_set_mad_demux_in_bits {
4614 u8 opcode[0x10];
b4ff3a36 4615 u8 reserved_at_10[0x10];
e281682b 4616
b4ff3a36 4617 u8 reserved_at_20[0x10];
e281682b
SM		 4618 u8 op_mod[0x10];
4619
b4ff3a36 4620 u8 reserved_at_40[0x20];
e281682b 4621
b4ff3a36 4622 u8 reserved_at_60[0x6];
e281682b 4623 u8 demux_mode[0x2];
b4ff3a36 4624 u8 reserved_at_68[0x18];
e281682b
SM		 4625};
4626
4627struct mlx5_ifc_set_l2_table_entry_out_bits {
4628 u8 status[0x8];
b4ff3a36 4629 u8 reserved_at_8[0x18];
e281682b
SM		 4630
4631 u8 syndrome[0x20];
4632
b4ff3a36 4633 u8 reserved_at_40[0x40];
e281682b
SM		 4634};
4635
4636struct mlx5_ifc_set_l2_table_entry_in_bits {
4637 u8 opcode[0x10];
b4ff3a36 4638 u8 reserved_at_10[0x10];
e281682b 4639
b4ff3a36 4640 u8 reserved_at_20[0x10];
e281682b
SM		 4641 u8 op_mod[0x10];
4642
b4ff3a36 4643 u8 reserved_at_40[0x60];
e281682b 4644
b4ff3a36 4645 u8 reserved_at_a0[0x8];
e281682b
SM		 4646 u8 table_index[0x18];
4647
b4ff3a36 4648 u8 reserved_at_c0[0x20];
e281682b 4649
b4ff3a36 4650 u8 reserved_at_e0[0x13];
e281682b
SM		 4651 u8 vlan_valid[0x1];
4652 u8 vlan[0xc];
4653
4654 struct mlx5_ifc_mac_address_layout_bits mac_address;
4655
b4ff3a36 4656 u8 reserved_at_140[0xc0];
e281682b
SM		 4657};
4658
4659struct mlx5_ifc_set_issi_out_bits {
4660 u8 status[0x8];
b4ff3a36 4661 u8 reserved_at_8[0x18];
e281682b
SM		 4662
4663 u8 syndrome[0x20];
4664
b4ff3a36 4665 u8 reserved_at_40[0x40];
e281682b
SM		 4666};
4667
4668struct mlx5_ifc_set_issi_in_bits {
4669 u8 opcode[0x10];
b4ff3a36 4670 u8 reserved_at_10[0x10];
e281682b 4671
b4ff3a36 4672 u8 reserved_at_20[0x10];
e281682b
SM		 4673 u8 op_mod[0x10];
4674
b4ff3a36 4675 u8 reserved_at_40[0x10];
e281682b
SM		 4676 u8 current_issi[0x10];
4677
b4ff3a36 4678 u8 reserved_at_60[0x20];
e281682b
SM		 4679};
4680
4681struct mlx5_ifc_set_hca_cap_out_bits {
4682 u8 status[0x8];
b4ff3a36 4683 u8 reserved_at_8[0x18];
e281682b
SM		 4684
4685 u8 syndrome[0x20];
4686
b4ff3a36 4687 u8 reserved_at_40[0x40];
e281682b
SM		 4688};
4689
4690struct mlx5_ifc_set_hca_cap_in_bits {
4691 u8 opcode[0x10];
b4ff3a36 4692 u8 reserved_at_10[0x10];
e281682b 4693
b4ff3a36 4694 u8 reserved_at_20[0x10];
e281682b
SM		 4695 u8 op_mod[0x10];
4696
959af556
YH		 4697 u8 other_function[0x1];
4698 u8 reserved_at_41[0xf];
4699 u8 function_id[0x10];
4700
4701 u8 reserved_at_60[0x20];
e281682b
SM		 4702
4703 union mlx5_ifc_hca_cap_union_bits capability;
4704};
4705
26a81453
MG		 4706enum {
4707 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4708 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4709 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4710 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4711 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4712};
4713
e281682b
SM		 4714struct mlx5_ifc_set_fte_out_bits {
4715 u8 status[0x8];
b4ff3a36 4716 u8 reserved_at_8[0x18];
e281682b
SM		 4717
4718 u8 syndrome[0x20];
4719
b4ff3a36 4720 u8 reserved_at_40[0x40];
e281682b
SM		 4721};
4722
4723struct mlx5_ifc_set_fte_in_bits {
4724 u8 opcode[0x10];
b4ff3a36 4725 u8 reserved_at_10[0x10];
e281682b 4726
b4ff3a36 4727 u8 reserved_at_20[0x10];
e281682b
SM		 4728 u8 op_mod[0x10];
4729
7d5e1423
SM		 4730 u8 other_vport[0x1];
4731 u8 reserved_at_41[0xf];
4732 u8 vport_number[0x10];
4733
4734 u8 reserved_at_60[0x20];
e281682b
SM		 4735
4736 u8 table_type[0x8];
b4ff3a36 4737 u8 reserved_at_88[0x18];
e281682b 4738
b4ff3a36 4739 u8 reserved_at_a0[0x8];
e281682b
SM		 4740 u8 table_id[0x18];
4741
822e114b
PB		 4742 u8 ignore_flow_level[0x1];
4743 u8 reserved_at_c1[0x17];
26a81453
MG		 4744 u8 modify_enable_mask[0x8];
4745
b4ff3a36 4746 u8 reserved_at_e0[0x20];
e281682b
SM		 4747
4748 u8 flow_index[0x20];
4749
b4ff3a36 4750 u8 reserved_at_120[0xe0];
e281682b
SM		 4751
4752 struct mlx5_ifc_flow_context_bits flow_context;
4753};
4754
4755struct mlx5_ifc_rts2rts_qp_out_bits {
4756 u8 status[0x8];
b4ff3a36 4757 u8 reserved_at_8[0x18];
e281682b
SM		 4758
4759 u8 syndrome[0x20];
4760
6b646a7e
LR		 4761 u8 reserved_at_40[0x20];
4762 u8 ece[0x20];
e281682b
SM		 4763};
4764
4765struct mlx5_ifc_rts2rts_qp_in_bits {
4766 u8 opcode[0x10];
4ac63ec7 4767 u8 uid[0x10];
e281682b 4768
b4ff3a36 4769 u8 reserved_at_20[0x10];
e281682b
SM		 4770 u8 op_mod[0x10];
4771
b4ff3a36 4772 u8 reserved_at_40[0x8];
e281682b
SM		 4773 u8 qpn[0x18];
4774
b4ff3a36 4775 u8 reserved_at_60[0x20];
e281682b
SM		 4776
4777 u8 opt_param_mask[0x20];
4778
6b646a7e 4779 u8 ece[0x20];
e281682b
SM		 4780
4781 struct mlx5_ifc_qpc_bits qpc;
4782
b4ff3a36 4783 u8 reserved_at_800[0x80];
e281682b
SM		 4784};
4785
4786struct mlx5_ifc_rtr2rts_qp_out_bits {
4787 u8 status[0x8];
b4ff3a36 4788 u8 reserved_at_8[0x18];
e281682b
SM		 4789
4790 u8 syndrome[0x20];
4791
6b646a7e
LR		 4792 u8 reserved_at_40[0x20];
4793 u8 ece[0x20];
e281682b
SM		 4794};
4795
4796struct mlx5_ifc_rtr2rts_qp_in_bits {
4797 u8 opcode[0x10];
4ac63ec7 4798 u8 uid[0x10];
e281682b 4799
b4ff3a36 4800 u8 reserved_at_20[0x10];
e281682b
SM		 4801 u8 op_mod[0x10];
4802
b4ff3a36 4803 u8 reserved_at_40[0x8];
e281682b
SM		 4804 u8 qpn[0x18];
4805
b4ff3a36 4806 u8 reserved_at_60[0x20];
e281682b
SM		 4807
4808 u8 opt_param_mask[0x20];
4809
6b646a7e 4810 u8 ece[0x20];
e281682b
SM		 4811
4812 struct mlx5_ifc_qpc_bits qpc;
4813
b4ff3a36 4814 u8 reserved_at_800[0x80];
e281682b
SM		 4815};
4816
4817struct mlx5_ifc_rst2init_qp_out_bits {
4818 u8 status[0x8];
b4ff3a36 4819 u8 reserved_at_8[0x18];
e281682b
SM		 4820
4821 u8 syndrome[0x20];
4822
ab183d46
LR		 4823 u8 reserved_at_40[0x20];
4824 u8 ece[0x20];
e281682b
SM		 4825};
4826
4827struct mlx5_ifc_rst2init_qp_in_bits {
4828 u8 opcode[0x10];
4ac63ec7 4829 u8 uid[0x10];
e281682b 4830
b4ff3a36 4831 u8 reserved_at_20[0x10];
e281682b
SM		 4832 u8 op_mod[0x10];
4833
b4ff3a36 4834 u8 reserved_at_40[0x8];
e281682b
SM		 4835 u8 qpn[0x18];
4836
b4ff3a36 4837 u8 reserved_at_60[0x20];
e281682b
SM		 4838
4839 u8 opt_param_mask[0x20];
4840
ab183d46 4841 u8 ece[0x20];
e281682b
SM		 4842
4843 struct mlx5_ifc_qpc_bits qpc;
4844
b4ff3a36 4845 u8 reserved_at_800[0x80];
e281682b
SM		 4846};
4847
7486216b
SM		 4848struct mlx5_ifc_query_xrq_out_bits {
4849 u8 status[0x8];
4850 u8 reserved_at_8[0x18];
4851
4852 u8 syndrome[0x20];
4853
4854 u8 reserved_at_40[0x40];
4855
4856 struct mlx5_ifc_xrqc_bits xrq_context;
4857};
4858
4859struct mlx5_ifc_query_xrq_in_bits {
4860 u8 opcode[0x10];
4861 u8 reserved_at_10[0x10];
4862
4863 u8 reserved_at_20[0x10];
4864 u8 op_mod[0x10];
4865
4866 u8 reserved_at_40[0x8];
4867 u8 xrqn[0x18];
4868
4869 u8 reserved_at_60[0x20];
4870};
4871
e281682b
SM		 4872struct mlx5_ifc_query_xrc_srq_out_bits {
4873 u8 status[0x8];
b4ff3a36 4874 u8 reserved_at_8[0x18];
e281682b
SM		 4875
4876 u8 syndrome[0x20];
4877
b4ff3a36 4878 u8 reserved_at_40[0x40];
e281682b
SM		 4879
4880 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4881
b4ff3a36 4882 u8 reserved_at_280[0x600];
e281682b 4883
b6ca09cb 4884 u8 pas[][0x40];
e281682b
SM		 4885};
4886
4887struct mlx5_ifc_query_xrc_srq_in_bits {
4888 u8 opcode[0x10];
b4ff3a36 4889 u8 reserved_at_10[0x10];
e281682b 4890
b4ff3a36 4891 u8 reserved_at_20[0x10];
e281682b
SM		 4892 u8 op_mod[0x10];
4893
b4ff3a36 4894 u8 reserved_at_40[0x8];
e281682b
SM		 4895 u8 xrc_srqn[0x18];
4896
b4ff3a36 4897 u8 reserved_at_60[0x20];
e281682b
SM		 4898};
4899
4900enum {
4901 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4902 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4903};
4904
4905struct mlx5_ifc_query_vport_state_out_bits {
4906 u8 status[0x8];
b4ff3a36 4907 u8 reserved_at_8[0x18];
e281682b
SM		 4908
4909 u8 syndrome[0x20];
4910
b4ff3a36 4911 u8 reserved_at_40[0x20];
e281682b 4912
b4ff3a36 4913 u8 reserved_at_60[0x18];
e281682b
SM		 4914 u8 admin_state[0x4];
4915 u8 state[0x4];
4916};
4917
4918enum {
cc9c82a8
EBE		 4919 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4920 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4921 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4922};
4923
fd4572b3
ED		 4924struct mlx5_ifc_arm_monitor_counter_in_bits {
4925 u8 opcode[0x10];
4926 u8 uid[0x10];
4927
4928 u8 reserved_at_20[0x10];
4929 u8 op_mod[0x10];
4930
4931 u8 reserved_at_40[0x20];
4932
4933 u8 reserved_at_60[0x20];
4934};
4935
4936struct mlx5_ifc_arm_monitor_counter_out_bits {
4937 u8 status[0x8];
4938 u8 reserved_at_8[0x18];
4939
4940 u8 syndrome[0x20];
4941
4942 u8 reserved_at_40[0x40];
4943};
4944
4945enum {
4946 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4947 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4948};
4949
4950enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4951 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4952 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4953 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4954 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4955 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4956 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4957};
4958
4959enum {
4c8b8518 4960 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4961};
4962
4963struct mlx5_ifc_monitor_counter_output_bits {
4964 u8 reserved_at_0[0x4];
4965 u8 type[0x4];
4966 u8 reserved_at_8[0x8];
4967 u8 counter[0x10];
4968
4969 u8 counter_group_id[0x20];
4970};
4971
4972#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4973#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4974#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4975 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4976
4977struct mlx5_ifc_set_monitor_counter_in_bits {
4978 u8 opcode[0x10];
4979 u8 uid[0x10];
4980
4981 u8 reserved_at_20[0x10];
4982 u8 op_mod[0x10];
4983
4984 u8 reserved_at_40[0x10];
4985 u8 num_of_counters[0x10];
4986
4987 u8 reserved_at_60[0x20];
4988
4989 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4990};
4991
4992struct mlx5_ifc_set_monitor_counter_out_bits {
4993 u8 status[0x8];
4994 u8 reserved_at_8[0x18];
4995
4996 u8 syndrome[0x20];
4997
4998 u8 reserved_at_40[0x40];
4999};
5000
e281682b
SM		 5001struct mlx5_ifc_query_vport_state_in_bits {
5002 u8 opcode[0x10];
b4ff3a36 5003 u8 reserved_at_10[0x10];
e281682b 5004
b4ff3a36 5005 u8 reserved_at_20[0x10];
e281682b
SM		 5006 u8 op_mod[0x10];
5007
5008 u8 other_vport[0x1];
b4ff3a36 5009 u8 reserved_at_41[0xf];
e281682b
SM		 5010 u8 vport_number[0x10];
5011
b4ff3a36 5012 u8 reserved_at_60[0x20];
e281682b
SM		 5013};
5014
61c5b5c9
MS		 5015struct mlx5_ifc_query_vnic_env_out_bits {
5016 u8 status[0x8];
5017 u8 reserved_at_8[0x18];
5018
5019 u8 syndrome[0x20];
5020
5021 u8 reserved_at_40[0x40];
5022
5023 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5024};
5025
5026enum {
5027 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5028};
5029
5030struct mlx5_ifc_query_vnic_env_in_bits {
5031 u8 opcode[0x10];
5032 u8 reserved_at_10[0x10];
5033
5034 u8 reserved_at_20[0x10];
5035 u8 op_mod[0x10];
5036
5037 u8 other_vport[0x1];
5038 u8 reserved_at_41[0xf];
5039 u8 vport_number[0x10];
5040
5041 u8 reserved_at_60[0x20];
5042};
5043
e281682b
SM		 5044struct mlx5_ifc_query_vport_counter_out_bits {
5045 u8 status[0x8];
b4ff3a36 5046 u8 reserved_at_8[0x18];
e281682b
SM		 5047
5048 u8 syndrome[0x20];
5049
b4ff3a36 5050 u8 reserved_at_40[0x40];
e281682b
SM		 5051
5052 struct mlx5_ifc_traffic_counter_bits received_errors;
5053
5054 struct mlx5_ifc_traffic_counter_bits transmit_errors;
5055
5056 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5057
5058 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5059
5060 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5061
5062 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5063
5064 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5065
5066 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5067
5068 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5069
5070 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5071
5072 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5073
5074 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5075
b4ff3a36 5076 u8 reserved_at_680[0xa00];
e281682b
SM		 5077};
5078
5079enum {
5080 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5081};
5082
5083struct mlx5_ifc_query_vport_counter_in_bits {
5084 u8 opcode[0x10];
b4ff3a36 5085 u8 reserved_at_10[0x10];
e281682b 5086
b4ff3a36 5087 u8 reserved_at_20[0x10];
e281682b
SM		 5088 u8 op_mod[0x10];
5089
5090 u8 other_vport[0x1];
b54ba277
MY		 5091 u8 reserved_at_41[0xb];
5092 u8 port_num[0x4];
e281682b
SM		 5093 u8 vport_number[0x10];
5094
b4ff3a36 5095 u8 reserved_at_60[0x60];
e281682b
SM		 5096
5097 u8 clear[0x1];
b4ff3a36 5098 u8 reserved_at_c1[0x1f];
e281682b 5099
b4ff3a36 5100 u8 reserved_at_e0[0x20];
e281682b
SM		 5101};
5102
5103struct mlx5_ifc_query_tis_out_bits {
5104 u8 status[0x8];
b4ff3a36 5105 u8 reserved_at_8[0x18];
e281682b
SM		 5106
5107 u8 syndrome[0x20];
5108
b4ff3a36 5109 u8 reserved_at_40[0x40];
e281682b
SM		 5110
5111 struct mlx5_ifc_tisc_bits tis_context;
5112};
5113
5114struct mlx5_ifc_query_tis_in_bits {
5115 u8 opcode[0x10];
b4ff3a36 5116 u8 reserved_at_10[0x10];
e281682b 5117
b4ff3a36 5118 u8 reserved_at_20[0x10];
e281682b
SM		 5119 u8 op_mod[0x10];
5120
b4ff3a36 5121 u8 reserved_at_40[0x8];
e281682b
SM		 5122 u8 tisn[0x18];
5123
b4ff3a36 5124 u8 reserved_at_60[0x20];
e281682b
SM		 5125};
5126
5127struct mlx5_ifc_query_tir_out_bits {
5128 u8 status[0x8];
b4ff3a36 5129 u8 reserved_at_8[0x18];
e281682b
SM		 5130
5131 u8 syndrome[0x20];
5132
b4ff3a36 5133 u8 reserved_at_40[0xc0];
e281682b
SM		 5134
5135 struct mlx5_ifc_tirc_bits tir_context;
5136};
5137
5138struct mlx5_ifc_query_tir_in_bits {
5139 u8 opcode[0x10];
b4ff3a36 5140 u8 reserved_at_10[0x10];
e281682b 5141
b4ff3a36 5142 u8 reserved_at_20[0x10];
e281682b
SM		 5143 u8 op_mod[0x10];
5144
b4ff3a36 5145 u8 reserved_at_40[0x8];
e281682b
SM		 5146 u8 tirn[0x18];
5147
b4ff3a36 5148 u8 reserved_at_60[0x20];
e281682b
SM		 5149};
5150
5151struct mlx5_ifc_query_srq_out_bits {
5152 u8 status[0x8];
b4ff3a36 5153 u8 reserved_at_8[0x18];
e281682b
SM		 5154
5155 u8 syndrome[0x20];
5156
b4ff3a36 5157 u8 reserved_at_40[0x40];
e281682b
SM		 5158
5159 struct mlx5_ifc_srqc_bits srq_context_entry;
5160
b4ff3a36 5161 u8 reserved_at_280[0x600];
e281682b 5162
b6ca09cb 5163 u8 pas[][0x40];
e281682b
SM		 5164};
5165
5166struct mlx5_ifc_query_srq_in_bits {
5167 u8 opcode[0x10];
b4ff3a36 5168 u8 reserved_at_10[0x10];
e281682b 5169
b4ff3a36 5170 u8 reserved_at_20[0x10];
e281682b
SM		 5171 u8 op_mod[0x10];
5172
b4ff3a36 5173 u8 reserved_at_40[0x8];
e281682b
SM		 5174 u8 srqn[0x18];
5175
b4ff3a36 5176 u8 reserved_at_60[0x20];
e281682b
SM		 5177};
5178
5179struct mlx5_ifc_query_sq_out_bits {
5180 u8 status[0x8];
b4ff3a36 5181 u8 reserved_at_8[0x18];
e281682b
SM		 5182
5183 u8 syndrome[0x20];
5184
b4ff3a36 5185 u8 reserved_at_40[0xc0];
e281682b
SM		 5186
5187 struct mlx5_ifc_sqc_bits sq_context;
5188};
5189
5190struct mlx5_ifc_query_sq_in_bits {
5191 u8 opcode[0x10];
b4ff3a36 5192 u8 reserved_at_10[0x10];
e281682b 5193
b4ff3a36 5194 u8 reserved_at_20[0x10];
e281682b
SM		 5195 u8 op_mod[0x10];
5196
b4ff3a36 5197 u8 reserved_at_40[0x8];
e281682b
SM		 5198 u8 sqn[0x18];
5199
b4ff3a36 5200 u8 reserved_at_60[0x20];
e281682b
SM		 5201};
5202
5203struct mlx5_ifc_query_special_contexts_out_bits {
5204 u8 status[0x8];
b4ff3a36 5205 u8 reserved_at_8[0x18];
e281682b
SM		 5206
5207 u8 syndrome[0x20];
5208
ec22eb53 5209 u8 dump_fill_mkey[0x20];
e281682b
SM		 5210
5211 u8 resd_lkey[0x20];
bcda1aca
AK		 5212
5213 u8 null_mkey[0x20];
5214
4b7296aa
OHT		 5215 u8 terminate_scatter_list_mkey[0x20];
5216
5217 u8 repeated_mkey[0x20];
5218
5219 u8 reserved_at_a0[0x20];
e281682b
SM		 5220};
5221
5222struct mlx5_ifc_query_special_contexts_in_bits {
5223 u8 opcode[0x10];
b4ff3a36 5224 u8 reserved_at_10[0x10];
e281682b 5225
b4ff3a36 5226 u8 reserved_at_20[0x10];
e281682b
SM		 5227 u8 op_mod[0x10];
5228
b4ff3a36 5229 u8 reserved_at_40[0x40];
e281682b
SM		 5230};
5231
813f8540
MHY		 5232struct mlx5_ifc_query_scheduling_element_out_bits {
5233 u8 opcode[0x10];
5234 u8 reserved_at_10[0x10];
5235
5236 u8 reserved_at_20[0x10];
5237 u8 op_mod[0x10];
5238
5239 u8 reserved_at_40[0xc0];
5240
5241 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5242
5243 u8 reserved_at_300[0x100];
5244};
5245
5246enum {
5247 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
214baf22 5248 SCHEDULING_HIERARCHY_NIC = 0x3,
813f8540
MHY		 5249};
5250
5251struct mlx5_ifc_query_scheduling_element_in_bits {
5252 u8 opcode[0x10];
5253 u8 reserved_at_10[0x10];
5254
5255 u8 reserved_at_20[0x10];
5256 u8 op_mod[0x10];
5257
5258 u8 scheduling_hierarchy[0x8];
5259 u8 reserved_at_48[0x18];
5260
5261 u8 scheduling_element_id[0x20];
5262
5263 u8 reserved_at_80[0x180];
5264};
5265
e281682b
SM		 5266struct mlx5_ifc_query_rqt_out_bits {
5267 u8 status[0x8];
b4ff3a36 5268 u8 reserved_at_8[0x18];
e281682b
SM		 5269
5270 u8 syndrome[0x20];
5271
b4ff3a36 5272 u8 reserved_at_40[0xc0];
e281682b
SM		 5273
5274 struct mlx5_ifc_rqtc_bits rqt_context;
5275};
5276
5277struct mlx5_ifc_query_rqt_in_bits {
5278 u8 opcode[0x10];
b4ff3a36 5279 u8 reserved_at_10[0x10];
e281682b 5280
b4ff3a36 5281 u8 reserved_at_20[0x10];
e281682b
SM		 5282 u8 op_mod[0x10];
5283
b4ff3a36 5284 u8 reserved_at_40[0x8];
e281682b
SM		 5285 u8 rqtn[0x18];
5286
b4ff3a36 5287 u8 reserved_at_60[0x20];
e281682b
SM		 5288};
5289
5290struct mlx5_ifc_query_rq_out_bits {
5291 u8 status[0x8];
b4ff3a36 5292 u8 reserved_at_8[0x18];
e281682b
SM		 5293
5294 u8 syndrome[0x20];
5295
b4ff3a36 5296 u8 reserved_at_40[0xc0];
e281682b
SM		 5297
5298 struct mlx5_ifc_rqc_bits rq_context;
5299};
5300
5301struct mlx5_ifc_query_rq_in_bits {
5302 u8 opcode[0x10];
b4ff3a36 5303 u8 reserved_at_10[0x10];
e281682b 5304
b4ff3a36 5305 u8 reserved_at_20[0x10];
e281682b
SM		 5306 u8 op_mod[0x10];
5307
b4ff3a36 5308 u8 reserved_at_40[0x8];
e281682b
SM		 5309 u8 rqn[0x18];
5310
b4ff3a36 5311 u8 reserved_at_60[0x20];
e281682b
SM		 5312};
5313
5314struct mlx5_ifc_query_roce_address_out_bits {
5315 u8 status[0x8];
b4ff3a36 5316 u8 reserved_at_8[0x18];
e281682b
SM		 5317
5318 u8 syndrome[0x20];
5319
b4ff3a36 5320 u8 reserved_at_40[0x40];
e281682b
SM		 5321
5322 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5323};
5324
5325struct mlx5_ifc_query_roce_address_in_bits {
5326 u8 opcode[0x10];
b4ff3a36 5327 u8 reserved_at_10[0x10];
e281682b 5328
b4ff3a36 5329 u8 reserved_at_20[0x10];
e281682b
SM		 5330 u8 op_mod[0x10];
5331
5332 u8 roce_address_index[0x10];
32f69e4b
DJ		 5333 u8 reserved_at_50[0xc];
5334 u8 vhca_port_num[0x4];
e281682b 5335
b4ff3a36 5336 u8 reserved_at_60[0x20];
e281682b
SM		 5337};
5338
5339struct mlx5_ifc_query_rmp_out_bits {
5340 u8 status[0x8];
b4ff3a36 5341 u8 reserved_at_8[0x18];
e281682b
SM		 5342
5343 u8 syndrome[0x20];
5344
b4ff3a36 5345 u8 reserved_at_40[0xc0];
e281682b
SM		 5346
5347 struct mlx5_ifc_rmpc_bits rmp_context;
5348};
5349
5350struct mlx5_ifc_query_rmp_in_bits {
5351 u8 opcode[0x10];
b4ff3a36 5352 u8 reserved_at_10[0x10];
e281682b 5353
b4ff3a36 5354 u8 reserved_at_20[0x10];
e281682b
SM		 5355 u8 op_mod[0x10];
5356
b4ff3a36 5357 u8 reserved_at_40[0x8];
e281682b
SM		 5358 u8 rmpn[0x18];
5359
b4ff3a36 5360 u8 reserved_at_60[0x20];
e281682b
SM		 5361};
5362
9b2e3723
PH		 5363struct mlx5_ifc_cqe_error_syndrome_bits {
5364 u8 hw_error_syndrome[0x8];
5365 u8 hw_syndrome_type[0x4];
5366 u8 reserved_at_c[0x4];
5367 u8 vendor_error_syndrome[0x8];
5368 u8 syndrome[0x8];
5369};
5370
5371struct mlx5_ifc_qp_context_extension_bits {
5372 u8 reserved_at_0[0x60];
5373
5374 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5375
5376 u8 reserved_at_80[0x580];
5377};
5378
5379struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5380 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5381
5382 u8 pas[0][0x40];
5383};
5384
5385struct mlx5_ifc_qp_pas_list_in_bits {
5386 struct mlx5_ifc_cmd_pas_bits pas[0];
5387};
5388
5389union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5390 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5391 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5392};
5393
e281682b
SM		 5394struct mlx5_ifc_query_qp_out_bits {
5395 u8 status[0x8];
b4ff3a36 5396 u8 reserved_at_8[0x18];
e281682b
SM		 5397
5398 u8 syndrome[0x20];
5399
3fc2a9e8 5400 u8 reserved_at_40[0x40];
e281682b
SM		 5401
5402 u8 opt_param_mask[0x20];
5403
3fc2a9e8 5404 u8 ece[0x20];
e281682b
SM		 5405
5406 struct mlx5_ifc_qpc_bits qpc;
5407
b4ff3a36 5408 u8 reserved_at_800[0x80];
e281682b 5409
9b2e3723 5410 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
e281682b
SM		 5411};
5412
5413struct mlx5_ifc_query_qp_in_bits {
5414 u8 opcode[0x10];
b4ff3a36 5415 u8 reserved_at_10[0x10];
e281682b 5416
b4ff3a36 5417 u8 reserved_at_20[0x10];
e281682b
SM		 5418 u8 op_mod[0x10];
5419
9b2e3723
PH		 5420 u8 qpc_ext[0x1];
5421 u8 reserved_at_41[0x7];
e281682b
SM		 5422 u8 qpn[0x18];
5423
b4ff3a36 5424 u8 reserved_at_60[0x20];
e281682b
SM		 5425};
5426
5427struct mlx5_ifc_query_q_counter_out_bits {
5428 u8 status[0x8];
b4ff3a36 5429 u8 reserved_at_8[0x18];
e281682b
SM		 5430
5431 u8 syndrome[0x20];
5432
b4ff3a36 5433 u8 reserved_at_40[0x40];
e281682b
SM		 5434
5435 u8 rx_write_requests[0x20];
5436
b4ff3a36 5437 u8 reserved_at_a0[0x20];
e281682b
SM		 5438
5439 u8 rx_read_requests[0x20];
5440
b4ff3a36 5441 u8 reserved_at_e0[0x20];
e281682b
SM		 5442
5443 u8 rx_atomic_requests[0x20];
5444
b4ff3a36 5445 u8 reserved_at_120[0x20];
e281682b
SM		 5446
5447 u8 rx_dct_connect[0x20];
5448
b4ff3a36 5449 u8 reserved_at_160[0x20];
e281682b
SM		 5450
5451 u8 out_of_buffer[0x20];
5452
b4ff3a36 5453 u8 reserved_at_1a0[0x20];
e281682b
SM		 5454
5455 u8 out_of_sequence[0x20];
5456
7486216b
SM		 5457 u8 reserved_at_1e0[0x20];
5458
5459 u8 duplicate_request[0x20];
5460
5461 u8 reserved_at_220[0x20];
5462
5463 u8 rnr_nak_retry_err[0x20];
5464
5465 u8 reserved_at_260[0x20];
5466
5467 u8 packet_seq_err[0x20];
5468
5469 u8 reserved_at_2a0[0x20];
5470
5471 u8 implied_nak_seq_err[0x20];
5472
5473 u8 reserved_at_2e0[0x20];
5474
5475 u8 local_ack_timeout_err[0x20];
5476
58dcb60a
PP		 5477 u8 reserved_at_320[0xa0];
5478
5479 u8 resp_local_length_error[0x20];
5480
5481 u8 req_local_length_error[0x20];
5482
5483 u8 resp_local_qp_error[0x20];
5484
5485 u8 local_operation_error[0x20];
5486
5487 u8 resp_local_protection[0x20];
5488
5489 u8 req_local_protection[0x20];
5490
5491 u8 resp_cqe_error[0x20];
5492
5493 u8 req_cqe_error[0x20];
5494
5495 u8 req_mw_binding[0x20];
5496
5497 u8 req_bad_response[0x20];
5498
5499 u8 req_remote_invalid_request[0x20];
5500
5501 u8 resp_remote_invalid_request[0x20];
5502
5503 u8 req_remote_access_errors[0x20];
5504
5505 u8 resp_remote_access_errors[0x20];
5506
5507 u8 req_remote_operation_errors[0x20];
5508
5509 u8 req_transport_retries_exceeded[0x20];
5510
5511 u8 cq_overflow[0x20];
5512
5513 u8 resp_cqe_flush_error[0x20];
5514
5515 u8 req_cqe_flush_error[0x20];
5516
8fd5b75d
LR		 5517 u8 reserved_at_620[0x20];
5518
5519 u8 roce_adp_retrans[0x20];
5520
5521 u8 roce_adp_retrans_to[0x20];
5522
5523 u8 roce_slow_restart[0x20];
5524
5525 u8 roce_slow_restart_cnps[0x20];
5526
5527 u8 roce_slow_restart_trans[0x20];
5528
5529 u8 reserved_at_6e0[0x120];
e281682b
SM		 5530};
5531
5532struct mlx5_ifc_query_q_counter_in_bits {
5533 u8 opcode[0x10];
b4ff3a36 5534 u8 reserved_at_10[0x10];
e281682b 5535
b4ff3a36 5536 u8 reserved_at_20[0x10];
e281682b
SM		 5537 u8 op_mod[0x10];
5538
b4ff3a36 5539 u8 reserved_at_40[0x80];
e281682b
SM		 5540
5541 u8 clear[0x1];
b4ff3a36 5542 u8 reserved_at_c1[0x1f];
e281682b 5543
b4ff3a36 5544 u8 reserved_at_e0[0x18];
e281682b
SM		 5545 u8 counter_set_id[0x8];
5546};
5547
5548struct mlx5_ifc_query_pages_out_bits {
5549 u8 status[0x8];
b4ff3a36 5550 u8 reserved_at_8[0x18];
e281682b
SM		 5551
5552 u8 syndrome[0x20];
5553
591905ba
BW		 5554 u8 embedded_cpu_function[0x1];
5555 u8 reserved_at_41[0xf];
e281682b
SM		 5556 u8 function_id[0x10];
5557
5558 u8 num_pages[0x20];
5559};
5560
5561enum {
5562 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5563 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5564 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5565};
5566
5567struct mlx5_ifc_query_pages_in_bits {
5568 u8 opcode[0x10];
b4ff3a36 5569 u8 reserved_at_10[0x10];
e281682b 5570
b4ff3a36 5571 u8 reserved_at_20[0x10];
e281682b
SM		 5572 u8 op_mod[0x10];
5573
591905ba
BW		 5574 u8 embedded_cpu_function[0x1];
5575 u8 reserved_at_41[0xf];
e281682b
SM		 5576 u8 function_id[0x10];
5577
b4ff3a36 5578 u8 reserved_at_60[0x20];
e281682b
SM		 5579};
5580
5581struct mlx5_ifc_query_nic_vport_context_out_bits {
5582 u8 status[0x8];
b4ff3a36 5583 u8 reserved_at_8[0x18];
e281682b
SM		 5584
5585 u8 syndrome[0x20];
5586
b4ff3a36 5587 u8 reserved_at_40[0x40];
e281682b
SM		 5588
5589 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5590};
5591
5592struct mlx5_ifc_query_nic_vport_context_in_bits {
5593 u8 opcode[0x10];
b4ff3a36 5594 u8 reserved_at_10[0x10];
e281682b 5595
b4ff3a36 5596 u8 reserved_at_20[0x10];
e281682b
SM		 5597 u8 op_mod[0x10];
5598
5599 u8 other_vport[0x1];
b4ff3a36 5600 u8 reserved_at_41[0xf];
e281682b
SM		 5601 u8 vport_number[0x10];
5602
b4ff3a36 5603 u8 reserved_at_60[0x5];
e281682b 5604 u8 allowed_list_type[0x3];
b4ff3a36 5605 u8 reserved_at_68[0x18];
e281682b
SM		 5606};
5607
5608struct mlx5_ifc_query_mkey_out_bits {
5609 u8 status[0x8];
b4ff3a36 5610 u8 reserved_at_8[0x18];
e281682b
SM		 5611
5612 u8 syndrome[0x20];
5613
b4ff3a36 5614 u8 reserved_at_40[0x40];
e281682b
SM		 5615
5616 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5617
b4ff3a36 5618 u8 reserved_at_280[0x600];
e281682b
SM		 5619
5620 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5621
5622 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5623};
5624
5625struct mlx5_ifc_query_mkey_in_bits {
5626 u8 opcode[0x10];
b4ff3a36 5627 u8 reserved_at_10[0x10];
e281682b 5628
b4ff3a36 5629 u8 reserved_at_20[0x10];
e281682b
SM		 5630 u8 op_mod[0x10];
5631
b4ff3a36 5632 u8 reserved_at_40[0x8];
e281682b
SM		 5633 u8 mkey_index[0x18];
5634
5635 u8 pg_access[0x1];
b4ff3a36 5636 u8 reserved_at_61[0x1f];
e281682b
SM		 5637};
5638
5639struct mlx5_ifc_query_mad_demux_out_bits {
5640 u8 status[0x8];
b4ff3a36 5641 u8 reserved_at_8[0x18];
e281682b
SM		 5642
5643 u8 syndrome[0x20];
5644
b4ff3a36 5645 u8 reserved_at_40[0x40];
e281682b
SM		 5646
5647 u8 mad_dumux_parameters_block[0x20];
5648};
5649
5650struct mlx5_ifc_query_mad_demux_in_bits {
5651 u8 opcode[0x10];
b4ff3a36 5652 u8 reserved_at_10[0x10];
e281682b 5653
b4ff3a36 5654 u8 reserved_at_20[0x10];
e281682b
SM		 5655 u8 op_mod[0x10];
5656
b4ff3a36 5657 u8 reserved_at_40[0x40];
e281682b
SM		 5658};
5659
5660struct mlx5_ifc_query_l2_table_entry_out_bits {
5661 u8 status[0x8];
b4ff3a36 5662 u8 reserved_at_8[0x18];
e281682b
SM		 5663
5664 u8 syndrome[0x20];
5665
b4ff3a36 5666 u8 reserved_at_40[0xa0];
e281682b 5667
b4ff3a36 5668 u8 reserved_at_e0[0x13];
e281682b
SM		 5669 u8 vlan_valid[0x1];
5670 u8 vlan[0xc];
5671
5672 struct mlx5_ifc_mac_address_layout_bits mac_address;
5673
b4ff3a36 5674 u8 reserved_at_140[0xc0];
e281682b
SM		 5675};
5676
5677struct mlx5_ifc_query_l2_table_entry_in_bits {
5678 u8 opcode[0x10];
b4ff3a36 5679 u8 reserved_at_10[0x10];
e281682b 5680
b4ff3a36 5681 u8 reserved_at_20[0x10];
e281682b
SM		 5682 u8 op_mod[0x10];
5683
b4ff3a36 5684 u8 reserved_at_40[0x60];
e281682b 5685
b4ff3a36 5686 u8 reserved_at_a0[0x8];
e281682b
SM		 5687 u8 table_index[0x18];
5688
b4ff3a36 5689 u8 reserved_at_c0[0x140];
e281682b
SM		 5690};
5691
5692struct mlx5_ifc_query_issi_out_bits {
5693 u8 status[0x8];
b4ff3a36 5694 u8 reserved_at_8[0x18];
e281682b
SM		 5695
5696 u8 syndrome[0x20];
5697
b4ff3a36 5698 u8 reserved_at_40[0x10];
e281682b
SM		 5699 u8 current_issi[0x10];
5700
b4ff3a36 5701 u8 reserved_at_60[0xa0];
e281682b 5702
b4ff3a36 5703 u8 reserved_at_100[76][0x8];
e281682b
SM		 5704 u8 supported_issi_dw0[0x20];
5705};
5706
5707struct mlx5_ifc_query_issi_in_bits {
5708 u8 opcode[0x10];
b4ff3a36 5709 u8 reserved_at_10[0x10];
e281682b 5710
b4ff3a36 5711 u8 reserved_at_20[0x10];
e281682b
SM		 5712 u8 op_mod[0x10];
5713
b4ff3a36 5714 u8 reserved_at_40[0x40];
e281682b
SM		 5715};
5716
0dbc6fe0
SM		 5717struct mlx5_ifc_set_driver_version_out_bits {
5718 u8 status[0x8];
5719 u8 reserved_0[0x18];
5720
5721 u8 syndrome[0x20];
5722 u8 reserved_1[0x40];
5723};
5724
5725struct mlx5_ifc_set_driver_version_in_bits {
5726 u8 opcode[0x10];
5727 u8 reserved_0[0x10];
5728
5729 u8 reserved_1[0x10];
5730 u8 op_mod[0x10];
5731
5732 u8 reserved_2[0x40];
5733 u8 driver_version[64][0x8];
5734};
5735
e281682b
SM		 5736struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5737 u8 status[0x8];
b4ff3a36 5738 u8 reserved_at_8[0x18];
e281682b
SM		 5739
5740 u8 syndrome[0x20];
5741
b4ff3a36 5742 u8 reserved_at_40[0x40];
e281682b 5743
b6ca09cb 5744 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5745};
5746
5747struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5748 u8 opcode[0x10];
b4ff3a36 5749 u8 reserved_at_10[0x10];
e281682b 5750
b4ff3a36 5751 u8 reserved_at_20[0x10];
e281682b
SM		 5752 u8 op_mod[0x10];
5753
5754 u8 other_vport[0x1];
b4ff3a36 5755 u8 reserved_at_41[0xb];
707c4602 5756 u8 port_num[0x4];
e281682b
SM		 5757 u8 vport_number[0x10];
5758
b4ff3a36 5759 u8 reserved_at_60[0x10];
e281682b
SM		 5760 u8 pkey_index[0x10];
5761};
5762
eff901d3
EC		 5763enum {
5764 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5765 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5766 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5767};
5768
e281682b
SM		 5769struct mlx5_ifc_query_hca_vport_gid_out_bits {
5770 u8 status[0x8];
b4ff3a36 5771 u8 reserved_at_8[0x18];
e281682b
SM		 5772
5773 u8 syndrome[0x20];
5774
b4ff3a36 5775 u8 reserved_at_40[0x20];
e281682b
SM		 5776
5777 u8 gids_num[0x10];
b4ff3a36 5778 u8 reserved_at_70[0x10];
e281682b 5779
b6ca09cb 5780 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5781};
5782
5783struct mlx5_ifc_query_hca_vport_gid_in_bits {
5784 u8 opcode[0x10];
b4ff3a36 5785 u8 reserved_at_10[0x10];
e281682b 5786
b4ff3a36 5787 u8 reserved_at_20[0x10];
e281682b
SM		 5788 u8 op_mod[0x10];
5789
5790 u8 other_vport[0x1];
b4ff3a36 5791 u8 reserved_at_41[0xb];
707c4602 5792 u8 port_num[0x4];
e281682b
SM		 5793 u8 vport_number[0x10];
5794
b4ff3a36 5795 u8 reserved_at_60[0x10];
e281682b
SM		 5796 u8 gid_index[0x10];
5797};
5798
5799struct mlx5_ifc_query_hca_vport_context_out_bits {
5800 u8 status[0x8];
b4ff3a36 5801 u8 reserved_at_8[0x18];
e281682b
SM		 5802
5803 u8 syndrome[0x20];
5804
b4ff3a36 5805 u8 reserved_at_40[0x40];
e281682b
SM		 5806
5807 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5808};
5809
5810struct mlx5_ifc_query_hca_vport_context_in_bits {
5811 u8 opcode[0x10];
b4ff3a36 5812 u8 reserved_at_10[0x10];
e281682b 5813
b4ff3a36 5814 u8 reserved_at_20[0x10];
e281682b
SM		 5815 u8 op_mod[0x10];
5816
5817 u8 other_vport[0x1];
b4ff3a36 5818 u8 reserved_at_41[0xb];
707c4602 5819 u8 port_num[0x4];
e281682b
SM		 5820 u8 vport_number[0x10];
5821
b4ff3a36 5822 u8 reserved_at_60[0x20];
e281682b
SM		 5823};
5824
5825struct mlx5_ifc_query_hca_cap_out_bits {
5826 u8 status[0x8];
b4ff3a36 5827 u8 reserved_at_8[0x18];
e281682b
SM		 5828
5829 u8 syndrome[0x20];
5830
b4ff3a36 5831 u8 reserved_at_40[0x40];
e281682b
SM		 5832
5833 union mlx5_ifc_hca_cap_union_bits capability;
5834};
5835
5836struct mlx5_ifc_query_hca_cap_in_bits {
5837 u8 opcode[0x10];
b4ff3a36 5838 u8 reserved_at_10[0x10];
e281682b 5839
b4ff3a36 5840 u8 reserved_at_20[0x10];
e281682b
SM		 5841 u8 op_mod[0x10];
5842
97b5484e
AV		 5843 u8 other_function[0x1];
5844 u8 reserved_at_41[0xf];
5845 u8 function_id[0x10];
5846
5847 u8 reserved_at_60[0x20];
e281682b
SM		 5848};
5849
97b5484e
AV		 5850struct mlx5_ifc_other_hca_cap_bits {
5851 u8 roce[0x1];
d32d7c52 5852 u8 reserved_at_1[0x27f];
97b5484e
AV		 5853};
5854
5855struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5856 u8 status[0x8];
d32d7c52 5857 u8 reserved_at_8[0x18];
e281682b
SM		 5858
5859 u8 syndrome[0x20];
5860
d32d7c52 5861 u8 reserved_at_40[0x40];
e281682b 5862
97b5484e
AV		 5863 struct mlx5_ifc_other_hca_cap_bits other_capability;
5864};
5865
5866struct mlx5_ifc_query_other_hca_cap_in_bits {
5867 u8 opcode[0x10];
d32d7c52 5868 u8 reserved_at_10[0x10];
97b5484e 5869
d32d7c52 5870 u8 reserved_at_20[0x10];
97b5484e
AV		 5871 u8 op_mod[0x10];
5872
d32d7c52 5873 u8 reserved_at_40[0x10];
97b5484e
AV		 5874 u8 function_id[0x10];
5875
d32d7c52 5876 u8 reserved_at_60[0x20];
97b5484e
AV		 5877};
5878
5879struct mlx5_ifc_modify_other_hca_cap_out_bits {
5880 u8 status[0x8];
d32d7c52 5881 u8 reserved_at_8[0x18];
97b5484e
AV		 5882
5883 u8 syndrome[0x20];
5884
d32d7c52 5885 u8 reserved_at_40[0x40];
97b5484e
AV		 5886};
5887
5888struct mlx5_ifc_modify_other_hca_cap_in_bits {
5889 u8 opcode[0x10];
d32d7c52 5890 u8 reserved_at_10[0x10];
97b5484e 5891
d32d7c52 5892 u8 reserved_at_20[0x10];
97b5484e
AV		 5893 u8 op_mod[0x10];
5894
d32d7c52 5895 u8 reserved_at_40[0x10];
97b5484e
AV		 5896 u8 function_id[0x10];
5897 u8 field_select[0x20];
5898
5899 struct mlx5_ifc_other_hca_cap_bits other_capability;
5900};
5901
5902struct mlx5_ifc_flow_table_context_bits {
5903 u8 reformat_en[0x1];
5904 u8 decap_en[0x1];
5905 u8 sw_owner[0x1];
5906 u8 termination_table[0x1];
5907 u8 table_miss_action[0x4];
e281682b 5908 u8 level[0x8];
97b5484e 5909 u8 reserved_at_10[0x8];
e281682b
SM		 5910 u8 log_size[0x8];
5911
97b5484e
AV		 5912 u8 reserved_at_20[0x8];
5913 u8 table_miss_id[0x18];
5914
5915 u8 reserved_at_40[0x8];
5916 u8 lag_master_next_table_id[0x18];
5917
5918 u8 reserved_at_60[0x60];
5919
5920 u8 sw_owner_icm_root_1[0x40];
5921
5922 u8 sw_owner_icm_root_0[0x40];
5923
5924};
5925
5926struct mlx5_ifc_query_flow_table_out_bits {
5927 u8 status[0x8];
5928 u8 reserved_at_8[0x18];
5929
5930 u8 syndrome[0x20];
5931
5932 u8 reserved_at_40[0x80];
5933
5934 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5935};
5936
5937struct mlx5_ifc_query_flow_table_in_bits {
5938 u8 opcode[0x10];
b4ff3a36 5939 u8 reserved_at_10[0x10];
e281682b 5940
b4ff3a36 5941 u8 reserved_at_20[0x10];
e281682b
SM		 5942 u8 op_mod[0x10];
5943
b4ff3a36 5944 u8 reserved_at_40[0x40];
e281682b
SM		 5945
5946 u8 table_type[0x8];
b4ff3a36 5947 u8 reserved_at_88[0x18];
e281682b 5948
b4ff3a36 5949 u8 reserved_at_a0[0x8];
e281682b
SM		 5950 u8 table_id[0x18];
5951
b4ff3a36 5952 u8 reserved_at_c0[0x140];
e281682b
SM		 5953};
5954
5955struct mlx5_ifc_query_fte_out_bits {
5956 u8 status[0x8];
b4ff3a36 5957 u8 reserved_at_8[0x18];
e281682b
SM		 5958
5959 u8 syndrome[0x20];
5960
b4ff3a36 5961 u8 reserved_at_40[0x1c0];
e281682b
SM		 5962
5963 struct mlx5_ifc_flow_context_bits flow_context;
5964};
5965
5966struct mlx5_ifc_query_fte_in_bits {
5967 u8 opcode[0x10];
b4ff3a36 5968 u8 reserved_at_10[0x10];
e281682b 5969
b4ff3a36 5970 u8 reserved_at_20[0x10];
e281682b
SM		 5971 u8 op_mod[0x10];
5972
b4ff3a36 5973 u8 reserved_at_40[0x40];
e281682b
SM		 5974
5975 u8 table_type[0x8];
b4ff3a36 5976 u8 reserved_at_88[0x18];
e281682b 5977
b4ff3a36 5978 u8 reserved_at_a0[0x8];
e281682b
SM		 5979 u8 table_id[0x18];
5980
b4ff3a36 5981 u8 reserved_at_c0[0x40];
e281682b
SM		 5982
5983 u8 flow_index[0x20];
5984
b4ff3a36 5985 u8 reserved_at_120[0xe0];
e281682b
SM		 5986};
5987
e7e2519e
MG		 5988struct mlx5_ifc_match_definer_format_0_bits {
5989 u8 reserved_at_0[0x100];
5990
5991 u8 metadata_reg_c_0[0x20];
5992
5993 u8 metadata_reg_c_1[0x20];
5994
5995 u8 outer_dmac_47_16[0x20];
5996
5997 u8 outer_dmac_15_0[0x10];
5998 u8 outer_ethertype[0x10];
5999
6000 u8 reserved_at_180[0x1];
6001 u8 sx_sniffer[0x1];
6002 u8 functional_lb[0x1];
6003 u8 outer_ip_frag[0x1];
6004 u8 outer_qp_type[0x2];
6005 u8 outer_encap_type[0x2];
6006 u8 port_number[0x2];
6007 u8 outer_l3_type[0x2];
6008 u8 outer_l4_type[0x2];
6009 u8 outer_first_vlan_type[0x2];
6010 u8 outer_first_vlan_prio[0x3];
6011 u8 outer_first_vlan_cfi[0x1];
6012 u8 outer_first_vlan_vid[0xc];
6013
6014 u8 outer_l4_type_ext[0x4];
6015 u8 reserved_at_1a4[0x2];
6016 u8 outer_ipsec_layer[0x2];
6017 u8 outer_l2_type[0x2];
6018 u8 force_lb[0x1];
6019 u8 outer_l2_ok[0x1];
6020 u8 outer_l3_ok[0x1];
6021 u8 outer_l4_ok[0x1];
6022 u8 outer_second_vlan_type[0x2];
6023 u8 outer_second_vlan_prio[0x3];
6024 u8 outer_second_vlan_cfi[0x1];
6025 u8 outer_second_vlan_vid[0xc];
6026
6027 u8 outer_smac_47_16[0x20];
6028
6029 u8 outer_smac_15_0[0x10];
6030 u8 inner_ipv4_checksum_ok[0x1];
6031 u8 inner_l4_checksum_ok[0x1];
6032 u8 outer_ipv4_checksum_ok[0x1];
6033 u8 outer_l4_checksum_ok[0x1];
6034 u8 inner_l3_ok[0x1];
6035 u8 inner_l4_ok[0x1];
6036 u8 outer_l3_ok_duplicate[0x1];
6037 u8 outer_l4_ok_duplicate[0x1];
6038 u8 outer_tcp_cwr[0x1];
6039 u8 outer_tcp_ece[0x1];
6040 u8 outer_tcp_urg[0x1];
6041 u8 outer_tcp_ack[0x1];
6042 u8 outer_tcp_psh[0x1];
6043 u8 outer_tcp_rst[0x1];
6044 u8 outer_tcp_syn[0x1];
6045 u8 outer_tcp_fin[0x1];
6046};
6047
6048struct mlx5_ifc_match_definer_format_22_bits {
6049 u8 reserved_at_0[0x100];
6050
6051 u8 outer_ip_src_addr[0x20];
6052
6053 u8 outer_ip_dest_addr[0x20];
6054
6055 u8 outer_l4_sport[0x10];
6056 u8 outer_l4_dport[0x10];
6057
6058 u8 reserved_at_160[0x1];
6059 u8 sx_sniffer[0x1];
6060 u8 functional_lb[0x1];
6061 u8 outer_ip_frag[0x1];
6062 u8 outer_qp_type[0x2];
6063 u8 outer_encap_type[0x2];
6064 u8 port_number[0x2];
6065 u8 outer_l3_type[0x2];
6066 u8 outer_l4_type[0x2];
6067 u8 outer_first_vlan_type[0x2];
6068 u8 outer_first_vlan_prio[0x3];
6069 u8 outer_first_vlan_cfi[0x1];
6070 u8 outer_first_vlan_vid[0xc];
6071
6072 u8 metadata_reg_c_0[0x20];
6073
6074 u8 outer_dmac_47_16[0x20];
6075
6076 u8 outer_smac_47_16[0x20];
6077
6078 u8 outer_smac_15_0[0x10];
6079 u8 outer_dmac_15_0[0x10];
6080};
6081
6082struct mlx5_ifc_match_definer_format_23_bits {
6083 u8 reserved_at_0[0x100];
6084
6085 u8 inner_ip_src_addr[0x20];
6086
6087 u8 inner_ip_dest_addr[0x20];
6088
6089 u8 inner_l4_sport[0x10];
6090 u8 inner_l4_dport[0x10];
6091
6092 u8 reserved_at_160[0x1];
6093 u8 sx_sniffer[0x1];
6094 u8 functional_lb[0x1];
6095 u8 inner_ip_frag[0x1];
6096 u8 inner_qp_type[0x2];
6097 u8 inner_encap_type[0x2];
6098 u8 port_number[0x2];
6099 u8 inner_l3_type[0x2];
6100 u8 inner_l4_type[0x2];
6101 u8 inner_first_vlan_type[0x2];
6102 u8 inner_first_vlan_prio[0x3];
6103 u8 inner_first_vlan_cfi[0x1];
6104 u8 inner_first_vlan_vid[0xc];
6105
6106 u8 tunnel_header_0[0x20];
6107
6108 u8 inner_dmac_47_16[0x20];
6109
6110 u8 inner_smac_47_16[0x20];
6111
6112 u8 inner_smac_15_0[0x10];
6113 u8 inner_dmac_15_0[0x10];
6114};
6115
6116struct mlx5_ifc_match_definer_format_29_bits {
6117 u8 reserved_at_0[0xc0];
6118
6119 u8 outer_ip_dest_addr[0x80];
6120
6121 u8 outer_ip_src_addr[0x80];
6122
6123 u8 outer_l4_sport[0x10];
6124 u8 outer_l4_dport[0x10];
6125
6126 u8 reserved_at_1e0[0x20];
6127};
6128
6129struct mlx5_ifc_match_definer_format_30_bits {
6130 u8 reserved_at_0[0xa0];
6131
6132 u8 outer_ip_dest_addr[0x80];
6133
6134 u8 outer_ip_src_addr[0x80];
6135
6136 u8 outer_dmac_47_16[0x20];
6137
6138 u8 outer_smac_47_16[0x20];
6139
6140 u8 outer_smac_15_0[0x10];
6141 u8 outer_dmac_15_0[0x10];
6142};
6143
6144struct mlx5_ifc_match_definer_format_31_bits {
6145 u8 reserved_at_0[0xc0];
6146
6147 u8 inner_ip_dest_addr[0x80];
6148
6149 u8 inner_ip_src_addr[0x80];
6150
6151 u8 inner_l4_sport[0x10];
6152 u8 inner_l4_dport[0x10];
6153
6154 u8 reserved_at_1e0[0x20];
6155};
6156
6157struct mlx5_ifc_match_definer_format_32_bits {
6158 u8 reserved_at_0[0xa0];
6159
6160 u8 inner_ip_dest_addr[0x80];
6161
6162 u8 inner_ip_src_addr[0x80];
6163
6164 u8 inner_dmac_47_16[0x20];
6165
6166 u8 inner_smac_47_16[0x20];
6167
6168 u8 inner_smac_15_0[0x10];
6169 u8 inner_dmac_15_0[0x10];
6170};
6171
f1543c7a
YK		 6172enum {
6173 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6174};
6175
6176#define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6177#define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6178#define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6179#define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6180
6181struct mlx5_ifc_match_definer_match_mask_bits {
6182 u8 reserved_at_1c0[5][0x20];
6183 u8 match_dw_8[0x20];
6184 u8 match_dw_7[0x20];
6185 u8 match_dw_6[0x20];
6186 u8 match_dw_5[0x20];
6187 u8 match_dw_4[0x20];
6188 u8 match_dw_3[0x20];
6189 u8 match_dw_2[0x20];
6190 u8 match_dw_1[0x20];
6191 u8 match_dw_0[0x20];
6192
6193 u8 match_byte_7[0x8];
6194 u8 match_byte_6[0x8];
6195 u8 match_byte_5[0x8];
6196 u8 match_byte_4[0x8];
6197
6198 u8 match_byte_3[0x8];
6199 u8 match_byte_2[0x8];
6200 u8 match_byte_1[0x8];
6201 u8 match_byte_0[0x8];
6202};
6203
e7e2519e
MG		 6204struct mlx5_ifc_match_definer_bits {
6205 u8 modify_field_select[0x40];
6206
6207 u8 reserved_at_40[0x40];
6208
6209 u8 reserved_at_80[0x10];
6210 u8 format_id[0x10];
6211
f1543c7a
YK		 6212 u8 reserved_at_a0[0x60];
6213
6214 u8 format_select_dw3[0x8];
6215 u8 format_select_dw2[0x8];
6216 u8 format_select_dw1[0x8];
6217 u8 format_select_dw0[0x8];
6218
6219 u8 format_select_dw7[0x8];
6220 u8 format_select_dw6[0x8];
6221 u8 format_select_dw5[0x8];
6222 u8 format_select_dw4[0x8];
6223
6224 u8 reserved_at_100[0x18];
6225 u8 format_select_dw8[0x8];
6226
6227 u8 reserved_at_120[0x20];
6228
6229 u8 format_select_byte3[0x8];
6230 u8 format_select_byte2[0x8];
6231 u8 format_select_byte1[0x8];
6232 u8 format_select_byte0[0x8];
6233
6234 u8 format_select_byte7[0x8];
6235 u8 format_select_byte6[0x8];
6236 u8 format_select_byte5[0x8];
6237 u8 format_select_byte4[0x8];
6238
6239 u8 reserved_at_180[0x40];
e7e2519e 6240
f1543c7a
YK		 6241 union {
6242 struct {
6243 u8 match_mask[16][0x20];
6244 };
6245 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6246 };
e7e2519e
MG		 6247};
6248
6249struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6250 u8 opcode[0x10];
6251 u8 uid[0x10];
6252
6253 u8 vhca_tunnel_id[0x10];
6254 u8 obj_type[0x10];
6255
6256 u8 obj_id[0x20];
6257
f5d23ee1
JL		 6258 u8 reserved_at_60[0x3];
6259 u8 log_obj_range[0x5];
6260 u8 reserved_at_68[0x18];
e7e2519e
MG		 6261};
6262
6263struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6264 u8 status[0x8];
6265 u8 reserved_at_8[0x18];
6266
6267 u8 syndrome[0x20];
6268
6269 u8 obj_id[0x20];
6270
6271 u8 reserved_at_60[0x20];
6272};
6273
6274struct mlx5_ifc_create_match_definer_in_bits {
6275 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6276
6277 struct mlx5_ifc_match_definer_bits obj_context;
6278};
6279
6280struct mlx5_ifc_create_match_definer_out_bits {
6281 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6282};
6283
e281682b
SM		 6284enum {
6285 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6286 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6287 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 6288 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 6289 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 6290 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
0f2a6c3b 6291 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
e281682b
SM		 6292};
6293
6294struct mlx5_ifc_query_flow_group_out_bits {
6295 u8 status[0x8];
b4ff3a36 6296 u8 reserved_at_8[0x18];
e281682b
SM		 6297
6298 u8 syndrome[0x20];
6299
b4ff3a36 6300 u8 reserved_at_40[0xa0];
e281682b
SM		 6301
6302 u8 start_flow_index[0x20];
6303
b4ff3a36 6304 u8 reserved_at_100[0x20];
e281682b
SM		 6305
6306 u8 end_flow_index[0x20];
6307
b4ff3a36 6308 u8 reserved_at_140[0xa0];
e281682b 6309
b4ff3a36 6310 u8 reserved_at_1e0[0x18];
e281682b
SM		 6311 u8 match_criteria_enable[0x8];
6312
6313 struct mlx5_ifc_fte_match_param_bits match_criteria;
6314
b4ff3a36 6315 u8 reserved_at_1200[0xe00];
e281682b
SM		 6316};
6317
6318struct mlx5_ifc_query_flow_group_in_bits {
6319 u8 opcode[0x10];
b4ff3a36 6320 u8 reserved_at_10[0x10];
e281682b 6321
b4ff3a36 6322 u8 reserved_at_20[0x10];
e281682b
SM		 6323 u8 op_mod[0x10];
6324
b4ff3a36 6325 u8 reserved_at_40[0x40];
e281682b
SM		 6326
6327 u8 table_type[0x8];
b4ff3a36 6328 u8 reserved_at_88[0x18];
e281682b 6329
b4ff3a36 6330 u8 reserved_at_a0[0x8];
e281682b
SM		 6331 u8 table_id[0x18];
6332
6333 u8 group_id[0x20];
6334
b4ff3a36 6335 u8 reserved_at_e0[0x120];
e281682b
SM		 6336};
6337
9dc0b289
AV		 6338struct mlx5_ifc_query_flow_counter_out_bits {
6339 u8 status[0x8];
6340 u8 reserved_at_8[0x18];
6341
6342 u8 syndrome[0x20];
6343
6344 u8 reserved_at_40[0x40];
6345
b6ca09cb 6346 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 6347};
6348
6349struct mlx5_ifc_query_flow_counter_in_bits {
6350 u8 opcode[0x10];
6351 u8 reserved_at_10[0x10];
6352
6353 u8 reserved_at_20[0x10];
6354 u8 op_mod[0x10];
6355
6356 u8 reserved_at_40[0x80];
6357
6358 u8 clear[0x1];
6359 u8 reserved_at_c1[0xf];
6360 u8 num_of_counters[0x10];
6361
a8ffcc74 6362 u8 flow_counter_id[0x20];
9dc0b289
AV		 6363};
6364
d6666753
SM		 6365struct mlx5_ifc_query_esw_vport_context_out_bits {
6366 u8 status[0x8];
b4ff3a36 6367 u8 reserved_at_8[0x18];
d6666753
SM		 6368
6369 u8 syndrome[0x20];
6370
b4ff3a36 6371 u8 reserved_at_40[0x40];
d6666753
SM		 6372
6373 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6374};
6375
6376struct mlx5_ifc_query_esw_vport_context_in_bits {
6377 u8 opcode[0x10];
b4ff3a36 6378 u8 reserved_at_10[0x10];
d6666753 6379
b4ff3a36 6380 u8 reserved_at_20[0x10];
d6666753
SM		 6381 u8 op_mod[0x10];
6382
6383 u8 other_vport[0x1];
b4ff3a36 6384 u8 reserved_at_41[0xf];
d6666753
SM		 6385 u8 vport_number[0x10];
6386
b4ff3a36 6387 u8 reserved_at_60[0x20];
d6666753
SM		 6388};
6389
6390struct mlx5_ifc_modify_esw_vport_context_out_bits {
6391 u8 status[0x8];
b4ff3a36 6392 u8 reserved_at_8[0x18];
d6666753
SM		 6393
6394 u8 syndrome[0x20];
6395
b4ff3a36 6396 u8 reserved_at_40[0x40];
d6666753
SM		 6397};
6398
6399struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 6400 u8 reserved_at_0[0x1b];
6401 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 6402 u8 vport_cvlan_insert[0x1];
6403 u8 vport_svlan_insert[0x1];
6404 u8 vport_cvlan_strip[0x1];
6405 u8 vport_svlan_strip[0x1];
6406};
6407
6408struct mlx5_ifc_modify_esw_vport_context_in_bits {
6409 u8 opcode[0x10];
b4ff3a36 6410 u8 reserved_at_10[0x10];
d6666753 6411
b4ff3a36 6412 u8 reserved_at_20[0x10];
d6666753
SM		 6413 u8 op_mod[0x10];
6414
6415 u8 other_vport[0x1];
b4ff3a36 6416 u8 reserved_at_41[0xf];
d6666753
SM		 6417 u8 vport_number[0x10];
6418
6419 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6420
6421 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6422};
6423
e281682b
SM		 6424struct mlx5_ifc_query_eq_out_bits {
6425 u8 status[0x8];
b4ff3a36 6426 u8 reserved_at_8[0x18];
e281682b
SM		 6427
6428 u8 syndrome[0x20];
6429
b4ff3a36 6430 u8 reserved_at_40[0x40];
e281682b
SM		 6431
6432 struct mlx5_ifc_eqc_bits eq_context_entry;
6433
b4ff3a36 6434 u8 reserved_at_280[0x40];
e281682b
SM		 6435
6436 u8 event_bitmask[0x40];
6437
b4ff3a36 6438 u8 reserved_at_300[0x580];
e281682b 6439
b6ca09cb 6440 u8 pas[][0x40];
e281682b
SM		 6441};
6442
6443struct mlx5_ifc_query_eq_in_bits {
6444 u8 opcode[0x10];
b4ff3a36 6445 u8 reserved_at_10[0x10];
e281682b 6446
b4ff3a36 6447 u8 reserved_at_20[0x10];
e281682b
SM		 6448 u8 op_mod[0x10];
6449
b4ff3a36 6450 u8 reserved_at_40[0x18];
e281682b
SM		 6451 u8 eq_number[0x8];
6452
b4ff3a36 6453 u8 reserved_at_60[0x20];
e281682b
SM		 6454};
6455
60786f09 6456struct mlx5_ifc_packet_reformat_context_in_bits {
67133eaa
YK		 6457 u8 reformat_type[0x8];
6458 u8 reserved_at_8[0x4];
6459 u8 reformat_param_0[0x4];
6460 u8 reserved_at_10[0x6];
60786f09 6461 u8 reformat_data_size[0xa];
7adbde20 6462
67133eaa
YK		 6463 u8 reformat_param_1[0x8];
6464 u8 reserved_at_28[0x8];
60786f09 6465 u8 reformat_data[2][0x8];
7adbde20 6466
b6ca09cb 6467 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 6468};
6469
60786f09 6470struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 6471 u8 status[0x8];
6472 u8 reserved_at_8[0x18];
6473
6474 u8 syndrome[0x20];
6475
6476 u8 reserved_at_40[0xa0];
6477
b6ca09cb 6478 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 6479};
6480
60786f09 6481struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 6482 u8 opcode[0x10];
6483 u8 reserved_at_10[0x10];
6484
6485 u8 reserved_at_20[0x10];
6486 u8 op_mod[0x10];
6487
60786f09 6488 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6489
6490 u8 reserved_at_60[0xa0];
6491};
6492
60786f09 6493struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6494 u8 status[0x8];
6495 u8 reserved_at_8[0x18];
6496
6497 u8 syndrome[0x20];
6498
60786f09 6499 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6500
6501 u8 reserved_at_60[0x20];
6502};
6503
67133eaa
YK		 6504enum {
6505 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6506 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6507 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6508};
6509
97b5484e 6510enum mlx5_reformat_ctx_type {
60786f09
MB		 6511 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6512 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 6513 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6514 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6515 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
3afee4ed
LR		 6516 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6517 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6518 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
67133eaa
YK		 6519 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6520 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
8385c51f
LN		 6521 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6522 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
e0e7a386
MB		 6523};
6524
60786f09 6525struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6526 u8 opcode[0x10];
6527 u8 reserved_at_10[0x10];
6528
6529 u8 reserved_at_20[0x10];
6530 u8 op_mod[0x10];
6531
6532 u8 reserved_at_40[0xa0];
6533
60786f09 6534 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 6535};
6536
60786f09 6537struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6538 u8 status[0x8];
6539 u8 reserved_at_8[0x18];
6540
6541 u8 syndrome[0x20];
6542
6543 u8 reserved_at_40[0x40];
6544};
6545
60786f09 6546struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6547 u8 opcode[0x10];
6548 u8 reserved_at_10[0x10];
6549
6550 u8 reserved_20[0x10];
6551 u8 op_mod[0x10];
6552
60786f09 6553 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6554
6555 u8 reserved_60[0x20];
6556};
6557
2a69cb9f
OG		 6558struct mlx5_ifc_set_action_in_bits {
6559 u8 action_type[0x4];
6560 u8 field[0xc];
6561 u8 reserved_at_10[0x3];
6562 u8 offset[0x5];
6563 u8 reserved_at_18[0x3];
6564 u8 length[0x5];
6565
6566 u8 data[0x20];
6567};
6568
6569struct mlx5_ifc_add_action_in_bits {
6570 u8 action_type[0x4];
6571 u8 field[0xc];
6572 u8 reserved_at_10[0x10];
6573
6574 u8 data[0x20];
6575};
6576
31d8bde1
HI		 6577struct mlx5_ifc_copy_action_in_bits {
6578 u8 action_type[0x4];
6579 u8 src_field[0xc];
6580 u8 reserved_at_10[0x3];
6581 u8 src_offset[0x5];
6582 u8 reserved_at_18[0x3];
6583 u8 length[0x5];
6584
6585 u8 reserved_at_20[0x4];
6586 u8 dst_field[0xc];
6587 u8 reserved_at_30[0x3];
6588 u8 dst_offset[0x5];
6589 u8 reserved_at_38[0x8];
6590};
6591
d65dbedf
HN		 6592union mlx5_ifc_set_add_copy_action_in_auto_bits {
6593 struct mlx5_ifc_set_action_in_bits set_action_in;
6594 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 6595 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 6596 u8 reserved_at_0[0x40];
6597};
6598
6599enum {
6600 MLX5_ACTION_TYPE_SET = 0x1,
6601 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 6602 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 6603};
6604
6605enum {
6606 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6607 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6608 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6609 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6610 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6611 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6612 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6613 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6614 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6615 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6616 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6617 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6618 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6619 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6620 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6621 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6622 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6623 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6624 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6625 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6626 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6627 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 6628 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 6629 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 6630 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6631 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 6632 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 6633 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6634 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6635 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6636 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6637 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 6638 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6639 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 6640 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6641 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 6642 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
67133eaa
YK		 6643 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6644 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
2a69cb9f
OG		 6645};
6646
6647struct mlx5_ifc_alloc_modify_header_context_out_bits {
6648 u8 status[0x8];
6649 u8 reserved_at_8[0x18];
6650
6651 u8 syndrome[0x20];
6652
6653 u8 modify_header_id[0x20];
6654
6655 u8 reserved_at_60[0x20];
6656};
6657
6658struct mlx5_ifc_alloc_modify_header_context_in_bits {
6659 u8 opcode[0x10];
6660 u8 reserved_at_10[0x10];
6661
6662 u8 reserved_at_20[0x10];
6663 u8 op_mod[0x10];
6664
6665 u8 reserved_at_40[0x20];
6666
6667 u8 table_type[0x8];
6668 u8 reserved_at_68[0x10];
6669 u8 num_of_actions[0x8];
6670
29056207 6671 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
2a69cb9f
OG		 6672};
6673
6674struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6675 u8 status[0x8];
6676 u8 reserved_at_8[0x18];
6677
6678 u8 syndrome[0x20];
6679
6680 u8 reserved_at_40[0x40];
6681};
6682
6683struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6684 u8 opcode[0x10];
6685 u8 reserved_at_10[0x10];
6686
6687 u8 reserved_at_20[0x10];
6688 u8 op_mod[0x10];
6689
6690 u8 modify_header_id[0x20];
6691
6692 u8 reserved_at_60[0x20];
6693};
6694
ab0da5a5
YH		 6695struct mlx5_ifc_query_modify_header_context_in_bits {
6696 u8 opcode[0x10];
6697 u8 uid[0x10];
6698
6699 u8 reserved_at_20[0x10];
6700 u8 op_mod[0x10];
6701
6702 u8 modify_header_id[0x20];
6703
6704 u8 reserved_at_60[0xa0];
6705};
6706
e281682b
SM		 6707struct mlx5_ifc_query_dct_out_bits {
6708 u8 status[0x8];
b4ff3a36 6709 u8 reserved_at_8[0x18];
e281682b
SM		 6710
6711 u8 syndrome[0x20];
6712
b4ff3a36 6713 u8 reserved_at_40[0x40];
e281682b
SM		 6714
6715 struct mlx5_ifc_dctc_bits dct_context_entry;
6716
b4ff3a36 6717 u8 reserved_at_280[0x180];
e281682b
SM		 6718};
6719
6720struct mlx5_ifc_query_dct_in_bits {
6721 u8 opcode[0x10];
b4ff3a36 6722 u8 reserved_at_10[0x10];
e281682b 6723
b4ff3a36 6724 u8 reserved_at_20[0x10];
e281682b
SM		 6725 u8 op_mod[0x10];
6726
b4ff3a36 6727 u8 reserved_at_40[0x8];
e281682b
SM		 6728 u8 dctn[0x18];
6729
b4ff3a36 6730 u8 reserved_at_60[0x20];
e281682b
SM		 6731};
6732
6733struct mlx5_ifc_query_cq_out_bits {
6734 u8 status[0x8];
b4ff3a36 6735 u8 reserved_at_8[0x18];
e281682b
SM		 6736
6737 u8 syndrome[0x20];
6738
b4ff3a36 6739 u8 reserved_at_40[0x40];
e281682b
SM		 6740
6741 struct mlx5_ifc_cqc_bits cq_context;
6742
b4ff3a36 6743 u8 reserved_at_280[0x600];
e281682b 6744
b6ca09cb 6745 u8 pas[][0x40];
e281682b
SM		 6746};
6747
6748struct mlx5_ifc_query_cq_in_bits {
6749 u8 opcode[0x10];
b4ff3a36 6750 u8 reserved_at_10[0x10];
e281682b 6751
b4ff3a36 6752 u8 reserved_at_20[0x10];
e281682b
SM		 6753 u8 op_mod[0x10];
6754
b4ff3a36 6755 u8 reserved_at_40[0x8];
e281682b
SM		 6756 u8 cqn[0x18];
6757
b4ff3a36 6758 u8 reserved_at_60[0x20];
e281682b
SM		 6759};
6760
6761struct mlx5_ifc_query_cong_status_out_bits {
6762 u8 status[0x8];
b4ff3a36 6763 u8 reserved_at_8[0x18];
e281682b
SM		 6764
6765 u8 syndrome[0x20];
6766
b4ff3a36 6767 u8 reserved_at_40[0x20];
e281682b
SM		 6768
6769 u8 enable[0x1];
6770 u8 tag_enable[0x1];
b4ff3a36 6771 u8 reserved_at_62[0x1e];
e281682b
SM		 6772};
6773
6774struct mlx5_ifc_query_cong_status_in_bits {
6775 u8 opcode[0x10];
b4ff3a36 6776 u8 reserved_at_10[0x10];
e281682b 6777
b4ff3a36 6778 u8 reserved_at_20[0x10];
e281682b
SM		 6779 u8 op_mod[0x10];
6780
b4ff3a36 6781 u8 reserved_at_40[0x18];
e281682b
SM		 6782 u8 priority[0x4];
6783 u8 cong_protocol[0x4];
6784
b4ff3a36 6785 u8 reserved_at_60[0x20];
e281682b
SM		 6786};
6787
6788struct mlx5_ifc_query_cong_statistics_out_bits {
6789 u8 status[0x8];
b4ff3a36 6790 u8 reserved_at_8[0x18];
e281682b
SM		 6791
6792 u8 syndrome[0x20];
6793
b4ff3a36 6794 u8 reserved_at_40[0x40];
e281682b 6795
e1f24a79 6796 u8 rp_cur_flows[0x20];
e281682b
SM		 6797
6798 u8 sum_flows[0x20];
6799
e1f24a79 6800 u8 rp_cnp_ignored_high[0x20];
e281682b 6801
e1f24a79 6802 u8 rp_cnp_ignored_low[0x20];
e281682b 6803
e1f24a79 6804 u8 rp_cnp_handled_high[0x20];
e281682b 6805
e1f24a79 6806 u8 rp_cnp_handled_low[0x20];
e281682b 6807
b4ff3a36 6808 u8 reserved_at_140[0x100];
e281682b
SM		 6809
6810 u8 time_stamp_high[0x20];
6811
6812 u8 time_stamp_low[0x20];
6813
6814 u8 accumulators_period[0x20];
6815
e1f24a79 6816 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6817
e1f24a79 6818 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6819
e1f24a79 6820 u8 np_cnp_sent_high[0x20];
e281682b 6821
e1f24a79 6822 u8 np_cnp_sent_low[0x20];
e281682b 6823
b4ff3a36 6824 u8 reserved_at_320[0x560];
e281682b
SM		 6825};
6826
6827struct mlx5_ifc_query_cong_statistics_in_bits {
6828 u8 opcode[0x10];
b4ff3a36 6829 u8 reserved_at_10[0x10];
e281682b 6830
b4ff3a36 6831 u8 reserved_at_20[0x10];
e281682b
SM		 6832 u8 op_mod[0x10];
6833
6834 u8 clear[0x1];
b4ff3a36 6835 u8 reserved_at_41[0x1f];
e281682b 6836
b4ff3a36 6837 u8 reserved_at_60[0x20];
e281682b
SM		 6838};
6839
6840struct mlx5_ifc_query_cong_params_out_bits {
6841 u8 status[0x8];
b4ff3a36 6842 u8 reserved_at_8[0x18];
e281682b
SM		 6843
6844 u8 syndrome[0x20];
6845
b4ff3a36 6846 u8 reserved_at_40[0x40];
e281682b
SM		 6847
6848 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6849};
6850
6851struct mlx5_ifc_query_cong_params_in_bits {
6852 u8 opcode[0x10];
b4ff3a36 6853 u8 reserved_at_10[0x10];
e281682b 6854
b4ff3a36 6855 u8 reserved_at_20[0x10];
e281682b
SM		 6856 u8 op_mod[0x10];
6857
b4ff3a36 6858 u8 reserved_at_40[0x1c];
e281682b
SM		 6859 u8 cong_protocol[0x4];
6860
b4ff3a36 6861 u8 reserved_at_60[0x20];
e281682b
SM		 6862};
6863
6864struct mlx5_ifc_query_adapter_out_bits {
6865 u8 status[0x8];
b4ff3a36 6866 u8 reserved_at_8[0x18];
e281682b
SM		 6867
6868 u8 syndrome[0x20];
6869
b4ff3a36 6870 u8 reserved_at_40[0x40];
e281682b
SM		 6871
6872 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6873};
6874
6875struct mlx5_ifc_query_adapter_in_bits {
6876 u8 opcode[0x10];
b4ff3a36 6877 u8 reserved_at_10[0x10];
e281682b 6878
b4ff3a36 6879 u8 reserved_at_20[0x10];
e281682b
SM		 6880 u8 op_mod[0x10];
6881
b4ff3a36 6882 u8 reserved_at_40[0x40];
e281682b
SM		 6883};
6884
6885struct mlx5_ifc_qp_2rst_out_bits {
6886 u8 status[0x8];
b4ff3a36 6887 u8 reserved_at_8[0x18];
e281682b
SM		 6888
6889 u8 syndrome[0x20];
6890
b4ff3a36 6891 u8 reserved_at_40[0x40];
e281682b
SM		 6892};
6893
6894struct mlx5_ifc_qp_2rst_in_bits {
6895 u8 opcode[0x10];
4ac63ec7 6896 u8 uid[0x10];
e281682b 6897
b4ff3a36 6898 u8 reserved_at_20[0x10];
e281682b
SM		 6899 u8 op_mod[0x10];
6900
b4ff3a36 6901 u8 reserved_at_40[0x8];
e281682b
SM		 6902 u8 qpn[0x18];
6903
b4ff3a36 6904 u8 reserved_at_60[0x20];
e281682b
SM		 6905};
6906
6907struct mlx5_ifc_qp_2err_out_bits {
6908 u8 status[0x8];
b4ff3a36 6909 u8 reserved_at_8[0x18];
e281682b
SM		 6910
6911 u8 syndrome[0x20];
6912
b4ff3a36 6913 u8 reserved_at_40[0x40];
e281682b
SM		 6914};
6915
6916struct mlx5_ifc_qp_2err_in_bits {
6917 u8 opcode[0x10];
4ac63ec7 6918 u8 uid[0x10];
e281682b 6919
b4ff3a36 6920 u8 reserved_at_20[0x10];
e281682b
SM		 6921 u8 op_mod[0x10];
6922
b4ff3a36 6923 u8 reserved_at_40[0x8];
e281682b
SM		 6924 u8 qpn[0x18];
6925
b4ff3a36 6926 u8 reserved_at_60[0x20];
e281682b
SM		 6927};
6928
6929struct mlx5_ifc_page_fault_resume_out_bits {
6930 u8 status[0x8];
b4ff3a36 6931 u8 reserved_at_8[0x18];
e281682b
SM		 6932
6933 u8 syndrome[0x20];
6934
b4ff3a36 6935 u8 reserved_at_40[0x40];
e281682b
SM		 6936};
6937
6938struct mlx5_ifc_page_fault_resume_in_bits {
6939 u8 opcode[0x10];
b4ff3a36 6940 u8 reserved_at_10[0x10];
e281682b 6941
b4ff3a36 6942 u8 reserved_at_20[0x10];
e281682b
SM		 6943 u8 op_mod[0x10];
6944
6945 u8 error[0x1];
b4ff3a36 6946 u8 reserved_at_41[0x4];
223cdc72
AK		 6947 u8 page_fault_type[0x3];
6948 u8 wq_number[0x18];
e281682b 6949
223cdc72
AK		 6950 u8 reserved_at_60[0x8];
6951 u8 token[0x18];
e281682b
SM		 6952};
6953
6954struct mlx5_ifc_nop_out_bits {
6955 u8 status[0x8];
b4ff3a36 6956 u8 reserved_at_8[0x18];
e281682b
SM		 6957
6958 u8 syndrome[0x20];
6959
b4ff3a36 6960 u8 reserved_at_40[0x40];
e281682b
SM		 6961};
6962
6963struct mlx5_ifc_nop_in_bits {
6964 u8 opcode[0x10];
b4ff3a36 6965 u8 reserved_at_10[0x10];
e281682b 6966
b4ff3a36 6967 u8 reserved_at_20[0x10];
e281682b
SM		 6968 u8 op_mod[0x10];
6969
b4ff3a36 6970 u8 reserved_at_40[0x40];
e281682b
SM		 6971};
6972
6973struct mlx5_ifc_modify_vport_state_out_bits {
6974 u8 status[0x8];
b4ff3a36 6975 u8 reserved_at_8[0x18];
e281682b
SM		 6976
6977 u8 syndrome[0x20];
6978
b4ff3a36 6979 u8 reserved_at_40[0x40];
e281682b
SM		 6980};
6981
6982struct mlx5_ifc_modify_vport_state_in_bits {
6983 u8 opcode[0x10];
b4ff3a36 6984 u8 reserved_at_10[0x10];
e281682b 6985
b4ff3a36 6986 u8 reserved_at_20[0x10];
e281682b
SM		 6987 u8 op_mod[0x10];
6988
6989 u8 other_vport[0x1];
b4ff3a36 6990 u8 reserved_at_41[0xf];
e281682b
SM		 6991 u8 vport_number[0x10];
6992
b4ff3a36 6993 u8 reserved_at_60[0x18];
e281682b 6994 u8 admin_state[0x4];
b4ff3a36 6995 u8 reserved_at_7c[0x4];
e281682b
SM		 6996};
6997
6998struct mlx5_ifc_modify_tis_out_bits {
6999 u8 status[0x8];
b4ff3a36 7000 u8 reserved_at_8[0x18];
e281682b
SM		 7001
7002 u8 syndrome[0x20];
7003
b4ff3a36 7004 u8 reserved_at_40[0x40];
e281682b
SM		 7005};
7006
75850d0b 7007struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 7008 u8 reserved_at_0[0x20];
75850d0b 7009
84df61eb
AH		 7010 u8 reserved_at_20[0x1d];
7011 u8 lag_tx_port_affinity[0x1];
7012 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 7013 u8 prio[0x1];
7014};
7015
e281682b
SM		 7016struct mlx5_ifc_modify_tis_in_bits {
7017 u8 opcode[0x10];
bd371975 7018 u8 uid[0x10];
e281682b 7019
b4ff3a36 7020 u8 reserved_at_20[0x10];
e281682b
SM		 7021 u8 op_mod[0x10];
7022
b4ff3a36 7023 u8 reserved_at_40[0x8];
e281682b
SM		 7024 u8 tisn[0x18];
7025
b4ff3a36 7026 u8 reserved_at_60[0x20];
e281682b 7027
75850d0b 7028 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 7029
b4ff3a36 7030 u8 reserved_at_c0[0x40];
e281682b
SM		 7031
7032 struct mlx5_ifc_tisc_bits ctx;
7033};
7034
d9eea403 7035struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 7036 u8 reserved_at_0[0x20];
d9eea403 7037
b4ff3a36 7038 u8 reserved_at_20[0x1b];
66189961 7039 u8 self_lb_en[0x1];
bdfc028d
TT		 7040 u8 reserved_at_3c[0x1];
7041 u8 hash[0x1];
7042 u8 reserved_at_3e[0x1];
eaee12f0 7043 u8 packet_merge[0x1];
d9eea403
AS		 7044};
7045
e281682b
SM		 7046struct mlx5_ifc_modify_tir_out_bits {
7047 u8 status[0x8];
b4ff3a36 7048 u8 reserved_at_8[0x18];
e281682b
SM		 7049
7050 u8 syndrome[0x20];
7051
b4ff3a36 7052 u8 reserved_at_40[0x40];
e281682b
SM		 7053};
7054
7055struct mlx5_ifc_modify_tir_in_bits {
7056 u8 opcode[0x10];
bd371975 7057 u8 uid[0x10];
e281682b 7058
b4ff3a36 7059 u8 reserved_at_20[0x10];
e281682b
SM		 7060 u8 op_mod[0x10];
7061
b4ff3a36 7062 u8 reserved_at_40[0x8];
e281682b
SM		 7063 u8 tirn[0x18];
7064
b4ff3a36 7065 u8 reserved_at_60[0x20];
e281682b 7066
d9eea403 7067 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 7068
b4ff3a36 7069 u8 reserved_at_c0[0x40];
e281682b
SM		 7070
7071 struct mlx5_ifc_tirc_bits ctx;
7072};
7073
7074struct mlx5_ifc_modify_sq_out_bits {
7075 u8 status[0x8];
b4ff3a36 7076 u8 reserved_at_8[0x18];
e281682b
SM		 7077
7078 u8 syndrome[0x20];
7079
b4ff3a36 7080 u8 reserved_at_40[0x40];
e281682b
SM		 7081};
7082
7083struct mlx5_ifc_modify_sq_in_bits {
7084 u8 opcode[0x10];
430ae0d5 7085 u8 uid[0x10];
e281682b 7086
b4ff3a36 7087 u8 reserved_at_20[0x10];
e281682b
SM		 7088 u8 op_mod[0x10];
7089
7090 u8 sq_state[0x4];
b4ff3a36 7091 u8 reserved_at_44[0x4];
e281682b
SM		 7092 u8 sqn[0x18];
7093
b4ff3a36 7094 u8 reserved_at_60[0x20];
e281682b
SM		 7095
7096 u8 modify_bitmask[0x40];
7097
b4ff3a36 7098 u8 reserved_at_c0[0x40];
e281682b
SM		 7099
7100 struct mlx5_ifc_sqc_bits ctx;
7101};
7102
813f8540
MHY		 7103struct mlx5_ifc_modify_scheduling_element_out_bits {
7104 u8 status[0x8];
7105 u8 reserved_at_8[0x18];
7106
7107 u8 syndrome[0x20];
7108
7109 u8 reserved_at_40[0x1c0];
7110};
7111
7112enum {
7113 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7114 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7115};
7116
7117struct mlx5_ifc_modify_scheduling_element_in_bits {
7118 u8 opcode[0x10];
7119 u8 reserved_at_10[0x10];
7120
7121 u8 reserved_at_20[0x10];
7122 u8 op_mod[0x10];
7123
7124 u8 scheduling_hierarchy[0x8];
7125 u8 reserved_at_48[0x18];
7126
7127 u8 scheduling_element_id[0x20];
7128
7129 u8 reserved_at_80[0x20];
7130
7131 u8 modify_bitmask[0x20];
7132
7133 u8 reserved_at_c0[0x40];
7134
7135 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7136
7137 u8 reserved_at_300[0x100];
7138};
7139
e281682b
SM		 7140struct mlx5_ifc_modify_rqt_out_bits {
7141 u8 status[0x8];
b4ff3a36 7142 u8 reserved_at_8[0x18];
e281682b
SM		 7143
7144 u8 syndrome[0x20];
7145
b4ff3a36 7146 u8 reserved_at_40[0x40];
e281682b
SM		 7147};
7148
5c50368f 7149struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 7150 u8 reserved_at_0[0x20];
5c50368f 7151
b4ff3a36 7152 u8 reserved_at_20[0x1f];
5c50368f
AS		 7153 u8 rqn_list[0x1];
7154};
7155
e281682b
SM		 7156struct mlx5_ifc_modify_rqt_in_bits {
7157 u8 opcode[0x10];
bd371975 7158 u8 uid[0x10];
e281682b 7159
b4ff3a36 7160 u8 reserved_at_20[0x10];
e281682b
SM		 7161 u8 op_mod[0x10];
7162
b4ff3a36 7163 u8 reserved_at_40[0x8];
e281682b
SM		 7164 u8 rqtn[0x18];
7165
b4ff3a36 7166 u8 reserved_at_60[0x20];
e281682b 7167
5c50368f 7168 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 7169
b4ff3a36 7170 u8 reserved_at_c0[0x40];
e281682b
SM		 7171
7172 struct mlx5_ifc_rqtc_bits ctx;
7173};
7174
7175struct mlx5_ifc_modify_rq_out_bits {
7176 u8 status[0x8];
b4ff3a36 7177 u8 reserved_at_8[0x18];
e281682b
SM		 7178
7179 u8 syndrome[0x20];
7180
b4ff3a36 7181 u8 reserved_at_40[0x40];
e281682b
SM		 7182};
7183
83b502a1
AV		 7184enum {
7185 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 7186 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 7187 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 7188};
7189
e281682b
SM		 7190struct mlx5_ifc_modify_rq_in_bits {
7191 u8 opcode[0x10];
d269b3af 7192 u8 uid[0x10];
e281682b 7193
b4ff3a36 7194 u8 reserved_at_20[0x10];
e281682b
SM		 7195 u8 op_mod[0x10];
7196
7197 u8 rq_state[0x4];
b4ff3a36 7198 u8 reserved_at_44[0x4];
e281682b
SM		 7199 u8 rqn[0x18];
7200
b4ff3a36 7201 u8 reserved_at_60[0x20];
e281682b
SM		 7202
7203 u8 modify_bitmask[0x40];
7204
b4ff3a36 7205 u8 reserved_at_c0[0x40];
e281682b
SM		 7206
7207 struct mlx5_ifc_rqc_bits ctx;
7208};
7209
7210struct mlx5_ifc_modify_rmp_out_bits {
7211 u8 status[0x8];
b4ff3a36 7212 u8 reserved_at_8[0x18];
e281682b
SM		 7213
7214 u8 syndrome[0x20];
7215
b4ff3a36 7216 u8 reserved_at_40[0x40];
e281682b
SM		 7217};
7218
01949d01 7219struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 7220 u8 reserved_at_0[0x20];
01949d01 7221
b4ff3a36 7222 u8 reserved_at_20[0x1f];
01949d01
HA		 7223 u8 lwm[0x1];
7224};
7225
e281682b
SM		 7226struct mlx5_ifc_modify_rmp_in_bits {
7227 u8 opcode[0x10];
a0d8c054 7228 u8 uid[0x10];
e281682b 7229
b4ff3a36 7230 u8 reserved_at_20[0x10];
e281682b
SM		 7231 u8 op_mod[0x10];
7232
7233 u8 rmp_state[0x4];
b4ff3a36 7234 u8 reserved_at_44[0x4];
e281682b
SM		 7235 u8 rmpn[0x18];
7236
b4ff3a36 7237 u8 reserved_at_60[0x20];
e281682b 7238
01949d01 7239 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 7240
b4ff3a36 7241 u8 reserved_at_c0[0x40];
e281682b
SM		 7242
7243 struct mlx5_ifc_rmpc_bits ctx;
7244};
7245
7246struct mlx5_ifc_modify_nic_vport_context_out_bits {
7247 u8 status[0x8];
b4ff3a36 7248 u8 reserved_at_8[0x18];
e281682b
SM		 7249
7250 u8 syndrome[0x20];
7251
b4ff3a36 7252 u8 reserved_at_40[0x40];
e281682b
SM		 7253};
7254
7255struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 7256 u8 reserved_at_0[0x12];
7257 u8 affiliation[0x1];
c74d90c1 7258 u8 reserved_at_13[0x1];
bded747b
HN		 7259 u8 disable_uc_local_lb[0x1];
7260 u8 disable_mc_local_lb[0x1];
23898c76
NO		 7261 u8 node_guid[0x1];
7262 u8 port_guid[0x1];
9def7121 7263 u8 min_inline[0x1];
d82b7318
SM		 7264 u8 mtu[0x1];
7265 u8 change_event[0x1];
7266 u8 promisc[0x1];
e281682b
SM		 7267 u8 permanent_address[0x1];
7268 u8 addresses_list[0x1];
7269 u8 roce_en[0x1];
b4ff3a36 7270 u8 reserved_at_1f[0x1];
e281682b
SM		 7271};
7272
7273struct mlx5_ifc_modify_nic_vport_context_in_bits {
7274 u8 opcode[0x10];
b4ff3a36 7275 u8 reserved_at_10[0x10];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_20[0x10];
e281682b
SM		 7278 u8 op_mod[0x10];
7279
7280 u8 other_vport[0x1];
b4ff3a36 7281 u8 reserved_at_41[0xf];
e281682b
SM		 7282 u8 vport_number[0x10];
7283
7284 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7285
b4ff3a36 7286 u8 reserved_at_80[0x780];
e281682b
SM		 7287
7288 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7289};
7290
7291struct mlx5_ifc_modify_hca_vport_context_out_bits {
7292 u8 status[0x8];
b4ff3a36 7293 u8 reserved_at_8[0x18];
e281682b
SM		 7294
7295 u8 syndrome[0x20];
7296
b4ff3a36 7297 u8 reserved_at_40[0x40];
e281682b
SM		 7298};
7299
7300struct mlx5_ifc_modify_hca_vport_context_in_bits {
7301 u8 opcode[0x10];
b4ff3a36 7302 u8 reserved_at_10[0x10];
e281682b 7303
b4ff3a36 7304 u8 reserved_at_20[0x10];
e281682b
SM		 7305 u8 op_mod[0x10];
7306
7307 u8 other_vport[0x1];
b4ff3a36 7308 u8 reserved_at_41[0xb];
707c4602 7309 u8 port_num[0x4];
e281682b
SM		 7310 u8 vport_number[0x10];
7311
b4ff3a36 7312 u8 reserved_at_60[0x20];
e281682b
SM		 7313
7314 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7315};
7316
7317struct mlx5_ifc_modify_cq_out_bits {
7318 u8 status[0x8];
b4ff3a36 7319 u8 reserved_at_8[0x18];
e281682b
SM		 7320
7321 u8 syndrome[0x20];
7322
b4ff3a36 7323 u8 reserved_at_40[0x40];
e281682b
SM		 7324};
7325
7326enum {
7327 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7328 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7329};
7330
7331struct mlx5_ifc_modify_cq_in_bits {
7332 u8 opcode[0x10];
9ba481e2 7333 u8 uid[0x10];
e281682b 7334
b4ff3a36 7335 u8 reserved_at_20[0x10];
e281682b
SM		 7336 u8 op_mod[0x10];
7337
b4ff3a36 7338 u8 reserved_at_40[0x8];
e281682b
SM		 7339 u8 cqn[0x18];
7340
7341 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7342
7343 struct mlx5_ifc_cqc_bits cq_context;
7344
7a32f296 7345 u8 reserved_at_280[0x60];
bd371975
LR		 7346
7347 u8 cq_umem_valid[0x1];
7a32f296
ES		 7348 u8 reserved_at_2e1[0x1f];
7349
7350 u8 reserved_at_300[0x580];
e281682b 7351
b6ca09cb 7352 u8 pas[][0x40];
e281682b
SM		 7353};
7354
7355struct mlx5_ifc_modify_cong_status_out_bits {
7356 u8 status[0x8];
b4ff3a36 7357 u8 reserved_at_8[0x18];
e281682b
SM		 7358
7359 u8 syndrome[0x20];
7360
b4ff3a36 7361 u8 reserved_at_40[0x40];
e281682b
SM		 7362};
7363
7364struct mlx5_ifc_modify_cong_status_in_bits {
7365 u8 opcode[0x10];
b4ff3a36 7366 u8 reserved_at_10[0x10];
e281682b 7367
b4ff3a36 7368 u8 reserved_at_20[0x10];
e281682b
SM		 7369 u8 op_mod[0x10];
7370
b4ff3a36 7371 u8 reserved_at_40[0x18];
e281682b
SM		 7372 u8 priority[0x4];
7373 u8 cong_protocol[0x4];
7374
7375 u8 enable[0x1];
7376 u8 tag_enable[0x1];
b4ff3a36 7377 u8 reserved_at_62[0x1e];
e281682b
SM		 7378};
7379
7380struct mlx5_ifc_modify_cong_params_out_bits {
7381 u8 status[0x8];
b4ff3a36 7382 u8 reserved_at_8[0x18];
e281682b
SM		 7383
7384 u8 syndrome[0x20];
7385
b4ff3a36 7386 u8 reserved_at_40[0x40];
e281682b
SM		 7387};
7388
7389struct mlx5_ifc_modify_cong_params_in_bits {
7390 u8 opcode[0x10];
b4ff3a36 7391 u8 reserved_at_10[0x10];
e281682b 7392
b4ff3a36 7393 u8 reserved_at_20[0x10];
e281682b
SM		 7394 u8 op_mod[0x10];
7395
b4ff3a36 7396 u8 reserved_at_40[0x1c];
e281682b
SM		 7397 u8 cong_protocol[0x4];
7398
7399 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7400
b4ff3a36 7401 u8 reserved_at_80[0x80];
e281682b
SM		 7402
7403 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7404};
7405
7406struct mlx5_ifc_manage_pages_out_bits {
7407 u8 status[0x8];
b4ff3a36 7408 u8 reserved_at_8[0x18];
e281682b
SM		 7409
7410 u8 syndrome[0x20];
7411
7412 u8 output_num_entries[0x20];
7413
b4ff3a36 7414 u8 reserved_at_60[0x20];
e281682b 7415
b6ca09cb 7416 u8 pas[][0x40];
e281682b
SM		 7417};
7418
7419enum {
7420 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7421 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7422 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7423};
7424
7425struct mlx5_ifc_manage_pages_in_bits {
7426 u8 opcode[0x10];
b4ff3a36 7427 u8 reserved_at_10[0x10];
e281682b 7428
b4ff3a36 7429 u8 reserved_at_20[0x10];
e281682b
SM		 7430 u8 op_mod[0x10];
7431
591905ba
BW		 7432 u8 embedded_cpu_function[0x1];
7433 u8 reserved_at_41[0xf];
e281682b
SM		 7434 u8 function_id[0x10];
7435
7436 u8 input_num_entries[0x20];
7437
b6ca09cb 7438 u8 pas[][0x40];
e281682b
SM		 7439};
7440
7441struct mlx5_ifc_mad_ifc_out_bits {
7442 u8 status[0x8];
b4ff3a36 7443 u8 reserved_at_8[0x18];
e281682b
SM		 7444
7445 u8 syndrome[0x20];
7446
b4ff3a36 7447 u8 reserved_at_40[0x40];
e281682b
SM		 7448
7449 u8 response_mad_packet[256][0x8];
7450};
7451
7452struct mlx5_ifc_mad_ifc_in_bits {
7453 u8 opcode[0x10];
b4ff3a36 7454 u8 reserved_at_10[0x10];
e281682b 7455
b4ff3a36 7456 u8 reserved_at_20[0x10];
e281682b
SM		 7457 u8 op_mod[0x10];
7458
7459 u8 remote_lid[0x10];
b4ff3a36 7460 u8 reserved_at_50[0x8];
e281682b
SM		 7461 u8 port[0x8];
7462
b4ff3a36 7463 u8 reserved_at_60[0x20];
e281682b
SM		 7464
7465 u8 mad[256][0x8];
7466};
7467
7468struct mlx5_ifc_init_hca_out_bits {
7469 u8 status[0x8];
b4ff3a36 7470 u8 reserved_at_8[0x18];
e281682b
SM		 7471
7472 u8 syndrome[0x20];
7473
b4ff3a36 7474 u8 reserved_at_40[0x40];
e281682b
SM		 7475};
7476
7477struct mlx5_ifc_init_hca_in_bits {
7478 u8 opcode[0x10];
b4ff3a36 7479 u8 reserved_at_10[0x10];
e281682b 7480
b4ff3a36 7481 u8 reserved_at_20[0x10];
e281682b
SM		 7482 u8 op_mod[0x10];
7483
0372c546
YH		 7484 u8 reserved_at_40[0x20];
7485
7486 u8 reserved_at_60[0x2];
7487 u8 sw_vhca_id[0xe];
7488 u8 reserved_at_70[0x10];
7489
8737f818 7490 u8 sw_owner_id[4][0x20];
e281682b
SM		 7491};
7492
7493struct mlx5_ifc_init2rtr_qp_out_bits {
7494 u8 status[0x8];
b4ff3a36 7495 u8 reserved_at_8[0x18];
e281682b
SM		 7496
7497 u8 syndrome[0x20];
7498
6b646a7e
LR		 7499 u8 reserved_at_40[0x20];
7500 u8 ece[0x20];
e281682b
SM		 7501};
7502
7503struct mlx5_ifc_init2rtr_qp_in_bits {
7504 u8 opcode[0x10];
4ac63ec7 7505 u8 uid[0x10];
e281682b 7506
b4ff3a36 7507 u8 reserved_at_20[0x10];
e281682b
SM		 7508 u8 op_mod[0x10];
7509
b4ff3a36 7510 u8 reserved_at_40[0x8];
e281682b
SM		 7511 u8 qpn[0x18];
7512
b4ff3a36 7513 u8 reserved_at_60[0x20];
e281682b
SM		 7514
7515 u8 opt_param_mask[0x20];
7516
6b646a7e 7517 u8 ece[0x20];
e281682b
SM		 7518
7519 struct mlx5_ifc_qpc_bits qpc;
7520
b4ff3a36 7521 u8 reserved_at_800[0x80];
e281682b
SM		 7522};
7523
7524struct mlx5_ifc_init2init_qp_out_bits {
7525 u8 status[0x8];
b4ff3a36 7526 u8 reserved_at_8[0x18];
e281682b
SM		 7527
7528 u8 syndrome[0x20];
7529
ab183d46
LR		 7530 u8 reserved_at_40[0x20];
7531 u8 ece[0x20];
e281682b
SM		 7532};
7533
7534struct mlx5_ifc_init2init_qp_in_bits {
7535 u8 opcode[0x10];
4ac63ec7 7536 u8 uid[0x10];
e281682b 7537
b4ff3a36 7538 u8 reserved_at_20[0x10];
e281682b
SM		 7539 u8 op_mod[0x10];
7540
b4ff3a36 7541 u8 reserved_at_40[0x8];
e281682b
SM		 7542 u8 qpn[0x18];
7543
b4ff3a36 7544 u8 reserved_at_60[0x20];
e281682b
SM		 7545
7546 u8 opt_param_mask[0x20];
7547
ab183d46 7548 u8 ece[0x20];
e281682b
SM		 7549
7550 struct mlx5_ifc_qpc_bits qpc;
7551
b4ff3a36 7552 u8 reserved_at_800[0x80];
e281682b
SM		 7553};
7554
7555struct mlx5_ifc_get_dropped_packet_log_out_bits {
7556 u8 status[0x8];
b4ff3a36 7557 u8 reserved_at_8[0x18];
e281682b
SM		 7558
7559 u8 syndrome[0x20];
7560
b4ff3a36 7561 u8 reserved_at_40[0x40];
e281682b
SM		 7562
7563 u8 packet_headers_log[128][0x8];
7564
7565 u8 packet_syndrome[64][0x8];
7566};
7567
7568struct mlx5_ifc_get_dropped_packet_log_in_bits {
7569 u8 opcode[0x10];
b4ff3a36 7570 u8 reserved_at_10[0x10];
e281682b 7571
b4ff3a36 7572 u8 reserved_at_20[0x10];
e281682b
SM		 7573 u8 op_mod[0x10];
7574
b4ff3a36 7575 u8 reserved_at_40[0x40];
e281682b
SM		 7576};
7577
7578struct mlx5_ifc_gen_eqe_in_bits {
7579 u8 opcode[0x10];
b4ff3a36 7580 u8 reserved_at_10[0x10];
e281682b 7581
b4ff3a36 7582 u8 reserved_at_20[0x10];
e281682b
SM		 7583 u8 op_mod[0x10];
7584
b4ff3a36 7585 u8 reserved_at_40[0x18];
e281682b
SM		 7586 u8 eq_number[0x8];
7587
b4ff3a36 7588 u8 reserved_at_60[0x20];
e281682b
SM		 7589
7590 u8 eqe[64][0x8];
7591};
7592
7593struct mlx5_ifc_gen_eq_out_bits {
7594 u8 status[0x8];
b4ff3a36 7595 u8 reserved_at_8[0x18];
e281682b
SM		 7596
7597 u8 syndrome[0x20];
7598
b4ff3a36 7599 u8 reserved_at_40[0x40];
e281682b
SM		 7600};
7601
7602struct mlx5_ifc_enable_hca_out_bits {
7603 u8 status[0x8];
b4ff3a36 7604 u8 reserved_at_8[0x18];
e281682b
SM		 7605
7606 u8 syndrome[0x20];
7607
b4ff3a36 7608 u8 reserved_at_40[0x20];
e281682b
SM		 7609};
7610
7611struct mlx5_ifc_enable_hca_in_bits {
7612 u8 opcode[0x10];
b4ff3a36 7613 u8 reserved_at_10[0x10];
e281682b 7614
b4ff3a36 7615 u8 reserved_at_20[0x10];
e281682b
SM		 7616 u8 op_mod[0x10];
7617
22e939a9
BW		 7618 u8 embedded_cpu_function[0x1];
7619 u8 reserved_at_41[0xf];
e281682b
SM		 7620 u8 function_id[0x10];
7621
b4ff3a36 7622 u8 reserved_at_60[0x20];
e281682b
SM		 7623};
7624
7625struct mlx5_ifc_drain_dct_out_bits {
7626 u8 status[0x8];
b4ff3a36 7627 u8 reserved_at_8[0x18];
e281682b
SM		 7628
7629 u8 syndrome[0x20];
7630
b4ff3a36 7631 u8 reserved_at_40[0x40];
e281682b
SM		 7632};
7633
7634struct mlx5_ifc_drain_dct_in_bits {
7635 u8 opcode[0x10];
774ea6ee 7636 u8 uid[0x10];
e281682b 7637
b4ff3a36 7638 u8 reserved_at_20[0x10];
e281682b
SM		 7639 u8 op_mod[0x10];
7640
b4ff3a36 7641 u8 reserved_at_40[0x8];
e281682b
SM		 7642 u8 dctn[0x18];
7643
b4ff3a36 7644 u8 reserved_at_60[0x20];
e281682b
SM		 7645};
7646
7647struct mlx5_ifc_disable_hca_out_bits {
7648 u8 status[0x8];
b4ff3a36 7649 u8 reserved_at_8[0x18];
e281682b
SM		 7650
7651 u8 syndrome[0x20];
7652
b4ff3a36 7653 u8 reserved_at_40[0x20];
e281682b
SM		 7654};
7655
7656struct mlx5_ifc_disable_hca_in_bits {
7657 u8 opcode[0x10];
b4ff3a36 7658 u8 reserved_at_10[0x10];
e281682b 7659
b4ff3a36 7660 u8 reserved_at_20[0x10];
e281682b
SM		 7661 u8 op_mod[0x10];
7662
22e939a9
BW		 7663 u8 embedded_cpu_function[0x1];
7664 u8 reserved_at_41[0xf];
e281682b
SM		 7665 u8 function_id[0x10];
7666
b4ff3a36 7667 u8 reserved_at_60[0x20];
e281682b
SM		 7668};
7669
7670struct mlx5_ifc_detach_from_mcg_out_bits {
7671 u8 status[0x8];
b4ff3a36 7672 u8 reserved_at_8[0x18];
e281682b
SM		 7673
7674 u8 syndrome[0x20];
7675
b4ff3a36 7676 u8 reserved_at_40[0x40];
e281682b
SM		 7677};
7678
7679struct mlx5_ifc_detach_from_mcg_in_bits {
7680 u8 opcode[0x10];
bd371975 7681 u8 uid[0x10];
e281682b 7682
b4ff3a36 7683 u8 reserved_at_20[0x10];
e281682b
SM		 7684 u8 op_mod[0x10];
7685
b4ff3a36 7686 u8 reserved_at_40[0x8];
e281682b
SM		 7687 u8 qpn[0x18];
7688
b4ff3a36 7689 u8 reserved_at_60[0x20];
e281682b
SM		 7690
7691 u8 multicast_gid[16][0x8];
7692};
7693
7486216b
SM		 7694struct mlx5_ifc_destroy_xrq_out_bits {
7695 u8 status[0x8];
7696 u8 reserved_at_8[0x18];
7697
7698 u8 syndrome[0x20];
7699
7700 u8 reserved_at_40[0x40];
7701};
7702
7703struct mlx5_ifc_destroy_xrq_in_bits {
7704 u8 opcode[0x10];
a0d8c054 7705 u8 uid[0x10];
7486216b
SM		 7706
7707 u8 reserved_at_20[0x10];
7708 u8 op_mod[0x10];
7709
7710 u8 reserved_at_40[0x8];
7711 u8 xrqn[0x18];
7712
7713 u8 reserved_at_60[0x20];
7714};
7715
e281682b
SM		 7716struct mlx5_ifc_destroy_xrc_srq_out_bits {
7717 u8 status[0x8];
b4ff3a36 7718 u8 reserved_at_8[0x18];
e281682b
SM		 7719
7720 u8 syndrome[0x20];
7721
b4ff3a36 7722 u8 reserved_at_40[0x40];
e281682b
SM		 7723};
7724
7725struct mlx5_ifc_destroy_xrc_srq_in_bits {
7726 u8 opcode[0x10];
a0d8c054 7727 u8 uid[0x10];
e281682b 7728
b4ff3a36 7729 u8 reserved_at_20[0x10];
e281682b
SM		 7730 u8 op_mod[0x10];
7731
b4ff3a36 7732 u8 reserved_at_40[0x8];
e281682b
SM		 7733 u8 xrc_srqn[0x18];
7734
b4ff3a36 7735 u8 reserved_at_60[0x20];
e281682b
SM		 7736};
7737
7738struct mlx5_ifc_destroy_tis_out_bits {
7739 u8 status[0x8];
b4ff3a36 7740 u8 reserved_at_8[0x18];
e281682b
SM		 7741
7742 u8 syndrome[0x20];
7743
b4ff3a36 7744 u8 reserved_at_40[0x40];
e281682b
SM		 7745};
7746
7747struct mlx5_ifc_destroy_tis_in_bits {
7748 u8 opcode[0x10];
bd371975 7749 u8 uid[0x10];
e281682b 7750
b4ff3a36 7751 u8 reserved_at_20[0x10];
e281682b
SM		 7752 u8 op_mod[0x10];
7753
b4ff3a36 7754 u8 reserved_at_40[0x8];
e281682b
SM		 7755 u8 tisn[0x18];
7756
b4ff3a36 7757 u8 reserved_at_60[0x20];
e281682b
SM		 7758};
7759
7760struct mlx5_ifc_destroy_tir_out_bits {
7761 u8 status[0x8];
b4ff3a36 7762 u8 reserved_at_8[0x18];
e281682b
SM		 7763
7764 u8 syndrome[0x20];
7765
b4ff3a36 7766 u8 reserved_at_40[0x40];
e281682b
SM		 7767};
7768
7769struct mlx5_ifc_destroy_tir_in_bits {
7770 u8 opcode[0x10];
bd371975 7771 u8 uid[0x10];
e281682b 7772
b4ff3a36 7773 u8 reserved_at_20[0x10];
e281682b
SM		 7774 u8 op_mod[0x10];
7775
b4ff3a36 7776 u8 reserved_at_40[0x8];
e281682b
SM		 7777 u8 tirn[0x18];
7778
b4ff3a36 7779 u8 reserved_at_60[0x20];
e281682b
SM		 7780};
7781
7782struct mlx5_ifc_destroy_srq_out_bits {
7783 u8 status[0x8];
b4ff3a36 7784 u8 reserved_at_8[0x18];
e281682b
SM		 7785
7786 u8 syndrome[0x20];
7787
b4ff3a36 7788 u8 reserved_at_40[0x40];
e281682b
SM		 7789};
7790
7791struct mlx5_ifc_destroy_srq_in_bits {
7792 u8 opcode[0x10];
a0d8c054 7793 u8 uid[0x10];
e281682b 7794
b4ff3a36 7795 u8 reserved_at_20[0x10];
e281682b
SM		 7796 u8 op_mod[0x10];
7797
b4ff3a36 7798 u8 reserved_at_40[0x8];
e281682b
SM		 7799 u8 srqn[0x18];
7800
b4ff3a36 7801 u8 reserved_at_60[0x20];
e281682b
SM		 7802};
7803
7804struct mlx5_ifc_destroy_sq_out_bits {
7805 u8 status[0x8];
b4ff3a36 7806 u8 reserved_at_8[0x18];
e281682b
SM		 7807
7808 u8 syndrome[0x20];
7809
b4ff3a36 7810 u8 reserved_at_40[0x40];
e281682b
SM		 7811};
7812
7813struct mlx5_ifc_destroy_sq_in_bits {
7814 u8 opcode[0x10];
430ae0d5 7815 u8 uid[0x10];
e281682b 7816
b4ff3a36 7817 u8 reserved_at_20[0x10];
e281682b
SM		 7818 u8 op_mod[0x10];
7819
b4ff3a36 7820 u8 reserved_at_40[0x8];
e281682b
SM		 7821 u8 sqn[0x18];
7822
b4ff3a36 7823 u8 reserved_at_60[0x20];
e281682b
SM		 7824};
7825
813f8540
MHY		 7826struct mlx5_ifc_destroy_scheduling_element_out_bits {
7827 u8 status[0x8];
7828 u8 reserved_at_8[0x18];
7829
7830 u8 syndrome[0x20];
7831
7832 u8 reserved_at_40[0x1c0];
7833};
7834
7835struct mlx5_ifc_destroy_scheduling_element_in_bits {
7836 u8 opcode[0x10];
7837 u8 reserved_at_10[0x10];
7838
7839 u8 reserved_at_20[0x10];
7840 u8 op_mod[0x10];
7841
7842 u8 scheduling_hierarchy[0x8];
7843 u8 reserved_at_48[0x18];
7844
7845 u8 scheduling_element_id[0x20];
7846
7847 u8 reserved_at_80[0x180];
7848};
7849
e281682b
SM		 7850struct mlx5_ifc_destroy_rqt_out_bits {
7851 u8 status[0x8];
b4ff3a36 7852 u8 reserved_at_8[0x18];
e281682b
SM		 7853
7854 u8 syndrome[0x20];
7855
b4ff3a36 7856 u8 reserved_at_40[0x40];
e281682b
SM		 7857};
7858
7859struct mlx5_ifc_destroy_rqt_in_bits {
7860 u8 opcode[0x10];
bd371975 7861 u8 uid[0x10];
e281682b 7862
b4ff3a36 7863 u8 reserved_at_20[0x10];
e281682b
SM		 7864 u8 op_mod[0x10];
7865
b4ff3a36 7866 u8 reserved_at_40[0x8];
e281682b
SM		 7867 u8 rqtn[0x18];
7868
b4ff3a36 7869 u8 reserved_at_60[0x20];
e281682b
SM		 7870};
7871
7872struct mlx5_ifc_destroy_rq_out_bits {
7873 u8 status[0x8];
b4ff3a36 7874 u8 reserved_at_8[0x18];
e281682b
SM		 7875
7876 u8 syndrome[0x20];
7877
b4ff3a36 7878 u8 reserved_at_40[0x40];
e281682b
SM		 7879};
7880
7881struct mlx5_ifc_destroy_rq_in_bits {
7882 u8 opcode[0x10];
d269b3af 7883 u8 uid[0x10];
e281682b 7884
b4ff3a36 7885 u8 reserved_at_20[0x10];
e281682b
SM		 7886 u8 op_mod[0x10];
7887
b4ff3a36 7888 u8 reserved_at_40[0x8];
e281682b
SM		 7889 u8 rqn[0x18];
7890
b4ff3a36 7891 u8 reserved_at_60[0x20];
e281682b
SM		 7892};
7893
c1e0bfc1
MG		 7894struct mlx5_ifc_set_delay_drop_params_in_bits {
7895 u8 opcode[0x10];
7896 u8 reserved_at_10[0x10];
7897
7898 u8 reserved_at_20[0x10];
7899 u8 op_mod[0x10];
7900
7901 u8 reserved_at_40[0x20];
7902
7903 u8 reserved_at_60[0x10];
7904 u8 delay_drop_timeout[0x10];
7905};
7906
7907struct mlx5_ifc_set_delay_drop_params_out_bits {
7908 u8 status[0x8];
7909 u8 reserved_at_8[0x18];
7910
7911 u8 syndrome[0x20];
7912
7913 u8 reserved_at_40[0x40];
7914};
7915
e281682b
SM		 7916struct mlx5_ifc_destroy_rmp_out_bits {
7917 u8 status[0x8];
b4ff3a36 7918 u8 reserved_at_8[0x18];
e281682b
SM		 7919
7920 u8 syndrome[0x20];
7921
b4ff3a36 7922 u8 reserved_at_40[0x40];
e281682b
SM		 7923};
7924
7925struct mlx5_ifc_destroy_rmp_in_bits {
7926 u8 opcode[0x10];
a0d8c054 7927 u8 uid[0x10];
e281682b 7928
b4ff3a36 7929 u8 reserved_at_20[0x10];
e281682b
SM		 7930 u8 op_mod[0x10];
7931
b4ff3a36 7932 u8 reserved_at_40[0x8];
e281682b
SM		 7933 u8 rmpn[0x18];
7934
b4ff3a36 7935 u8 reserved_at_60[0x20];
e281682b
SM		 7936};
7937
7938struct mlx5_ifc_destroy_qp_out_bits {
7939 u8 status[0x8];
b4ff3a36 7940 u8 reserved_at_8[0x18];
e281682b
SM		 7941
7942 u8 syndrome[0x20];
7943
b4ff3a36 7944 u8 reserved_at_40[0x40];
e281682b
SM		 7945};
7946
7947struct mlx5_ifc_destroy_qp_in_bits {
7948 u8 opcode[0x10];
4ac63ec7 7949 u8 uid[0x10];
e281682b 7950
b4ff3a36 7951 u8 reserved_at_20[0x10];
e281682b
SM		 7952 u8 op_mod[0x10];
7953
b4ff3a36 7954 u8 reserved_at_40[0x8];
e281682b
SM		 7955 u8 qpn[0x18];
7956
b4ff3a36 7957 u8 reserved_at_60[0x20];
e281682b
SM		 7958};
7959
7960struct mlx5_ifc_destroy_psv_out_bits {
7961 u8 status[0x8];
b4ff3a36 7962 u8 reserved_at_8[0x18];
e281682b
SM		 7963
7964 u8 syndrome[0x20];
7965
b4ff3a36 7966 u8 reserved_at_40[0x40];
e281682b
SM		 7967};
7968
7969struct mlx5_ifc_destroy_psv_in_bits {
7970 u8 opcode[0x10];
b4ff3a36 7971 u8 reserved_at_10[0x10];
e281682b 7972
b4ff3a36 7973 u8 reserved_at_20[0x10];
e281682b
SM		 7974 u8 op_mod[0x10];
7975
b4ff3a36 7976 u8 reserved_at_40[0x8];
e281682b
SM		 7977 u8 psvn[0x18];
7978
b4ff3a36 7979 u8 reserved_at_60[0x20];
e281682b
SM		 7980};
7981
7982struct mlx5_ifc_destroy_mkey_out_bits {
7983 u8 status[0x8];
b4ff3a36 7984 u8 reserved_at_8[0x18];
e281682b
SM		 7985
7986 u8 syndrome[0x20];
7987
b4ff3a36 7988 u8 reserved_at_40[0x40];
e281682b
SM		 7989};
7990
7991struct mlx5_ifc_destroy_mkey_in_bits {
7992 u8 opcode[0x10];
8a06a79b 7993 u8 uid[0x10];
e281682b 7994
b4ff3a36 7995 u8 reserved_at_20[0x10];
e281682b
SM		 7996 u8 op_mod[0x10];
7997
b4ff3a36 7998 u8 reserved_at_40[0x8];
e281682b
SM		 7999 u8 mkey_index[0x18];
8000
b4ff3a36 8001 u8 reserved_at_60[0x20];
e281682b
SM		 8002};
8003
8004struct mlx5_ifc_destroy_flow_table_out_bits {
8005 u8 status[0x8];
b4ff3a36 8006 u8 reserved_at_8[0x18];
e281682b
SM		 8007
8008 u8 syndrome[0x20];
8009
b4ff3a36 8010 u8 reserved_at_40[0x40];
e281682b
SM		 8011};
8012
8013struct mlx5_ifc_destroy_flow_table_in_bits {
8014 u8 opcode[0x10];
b4ff3a36 8015 u8 reserved_at_10[0x10];
e281682b 8016
b4ff3a36 8017 u8 reserved_at_20[0x10];
e281682b
SM		 8018 u8 op_mod[0x10];
8019
7d5e1423
SM		 8020 u8 other_vport[0x1];
8021 u8 reserved_at_41[0xf];
8022 u8 vport_number[0x10];
8023
8024 u8 reserved_at_60[0x20];
e281682b
SM		 8025
8026 u8 table_type[0x8];
b4ff3a36 8027 u8 reserved_at_88[0x18];
e281682b 8028
b4ff3a36 8029 u8 reserved_at_a0[0x8];
e281682b
SM		 8030 u8 table_id[0x18];
8031
b4ff3a36 8032 u8 reserved_at_c0[0x140];
e281682b
SM		 8033};
8034
8035struct mlx5_ifc_destroy_flow_group_out_bits {
8036 u8 status[0x8];
b4ff3a36 8037 u8 reserved_at_8[0x18];
e281682b
SM		 8038
8039 u8 syndrome[0x20];
8040
b4ff3a36 8041 u8 reserved_at_40[0x40];
e281682b
SM		 8042};
8043
8044struct mlx5_ifc_destroy_flow_group_in_bits {
8045 u8 opcode[0x10];
b4ff3a36 8046 u8 reserved_at_10[0x10];
e281682b 8047
b4ff3a36 8048 u8 reserved_at_20[0x10];
e281682b
SM		 8049 u8 op_mod[0x10];
8050
7d5e1423
SM		 8051 u8 other_vport[0x1];
8052 u8 reserved_at_41[0xf];
8053 u8 vport_number[0x10];
8054
8055 u8 reserved_at_60[0x20];
e281682b
SM		 8056
8057 u8 table_type[0x8];
b4ff3a36 8058 u8 reserved_at_88[0x18];
e281682b 8059
b4ff3a36 8060 u8 reserved_at_a0[0x8];
e281682b
SM		 8061 u8 table_id[0x18];
8062
8063 u8 group_id[0x20];
8064
b4ff3a36 8065 u8 reserved_at_e0[0x120];
e281682b
SM		 8066};
8067
8068struct mlx5_ifc_destroy_eq_out_bits {
8069 u8 status[0x8];
b4ff3a36 8070 u8 reserved_at_8[0x18];
e281682b
SM		 8071
8072 u8 syndrome[0x20];
8073
b4ff3a36 8074 u8 reserved_at_40[0x40];
e281682b
SM		 8075};
8076
8077struct mlx5_ifc_destroy_eq_in_bits {
8078 u8 opcode[0x10];
b4ff3a36 8079 u8 reserved_at_10[0x10];
e281682b 8080
b4ff3a36 8081 u8 reserved_at_20[0x10];
e281682b
SM		 8082 u8 op_mod[0x10];
8083
b4ff3a36 8084 u8 reserved_at_40[0x18];
e281682b
SM		 8085 u8 eq_number[0x8];
8086
b4ff3a36 8087 u8 reserved_at_60[0x20];
e281682b
SM		 8088};
8089
8090struct mlx5_ifc_destroy_dct_out_bits {
8091 u8 status[0x8];
b4ff3a36 8092 u8 reserved_at_8[0x18];
e281682b
SM		 8093
8094 u8 syndrome[0x20];
8095
b4ff3a36 8096 u8 reserved_at_40[0x40];
e281682b
SM		 8097};
8098
8099struct mlx5_ifc_destroy_dct_in_bits {
8100 u8 opcode[0x10];
774ea6ee 8101 u8 uid[0x10];
e281682b 8102
b4ff3a36 8103 u8 reserved_at_20[0x10];
e281682b
SM		 8104 u8 op_mod[0x10];
8105
b4ff3a36 8106 u8 reserved_at_40[0x8];
e281682b
SM		 8107 u8 dctn[0x18];
8108
b4ff3a36 8109 u8 reserved_at_60[0x20];
e281682b
SM		 8110};
8111
8112struct mlx5_ifc_destroy_cq_out_bits {
8113 u8 status[0x8];
b4ff3a36 8114 u8 reserved_at_8[0x18];
e281682b
SM		 8115
8116 u8 syndrome[0x20];
8117
b4ff3a36 8118 u8 reserved_at_40[0x40];
e281682b
SM		 8119};
8120
8121struct mlx5_ifc_destroy_cq_in_bits {
8122 u8 opcode[0x10];
9ba481e2 8123 u8 uid[0x10];
e281682b 8124
b4ff3a36 8125 u8 reserved_at_20[0x10];
e281682b
SM		 8126 u8 op_mod[0x10];
8127
b4ff3a36 8128 u8 reserved_at_40[0x8];
e281682b
SM		 8129 u8 cqn[0x18];
8130
b4ff3a36 8131 u8 reserved_at_60[0x20];
e281682b
SM		 8132};
8133
8134struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8135 u8 status[0x8];
b4ff3a36 8136 u8 reserved_at_8[0x18];
e281682b
SM		 8137
8138 u8 syndrome[0x20];
8139
b4ff3a36 8140 u8 reserved_at_40[0x40];
e281682b
SM		 8141};
8142
8143struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8144 u8 opcode[0x10];
b4ff3a36 8145 u8 reserved_at_10[0x10];
e281682b 8146
b4ff3a36 8147 u8 reserved_at_20[0x10];
e281682b
SM		 8148 u8 op_mod[0x10];
8149
b4ff3a36 8150 u8 reserved_at_40[0x20];
e281682b 8151
b4ff3a36 8152 u8 reserved_at_60[0x10];
e281682b
SM		 8153 u8 vxlan_udp_port[0x10];
8154};
8155
8156struct mlx5_ifc_delete_l2_table_entry_out_bits {
8157 u8 status[0x8];
b4ff3a36 8158 u8 reserved_at_8[0x18];
e281682b
SM		 8159
8160 u8 syndrome[0x20];
8161
b4ff3a36 8162 u8 reserved_at_40[0x40];
e281682b
SM		 8163};
8164
8165struct mlx5_ifc_delete_l2_table_entry_in_bits {
8166 u8 opcode[0x10];
b4ff3a36 8167 u8 reserved_at_10[0x10];
e281682b 8168
b4ff3a36 8169 u8 reserved_at_20[0x10];
e281682b
SM		 8170 u8 op_mod[0x10];
8171
b4ff3a36 8172 u8 reserved_at_40[0x60];
e281682b 8173
b4ff3a36 8174 u8 reserved_at_a0[0x8];
e281682b
SM		 8175 u8 table_index[0x18];
8176
b4ff3a36 8177 u8 reserved_at_c0[0x140];
e281682b
SM		 8178};
8179
8180struct mlx5_ifc_delete_fte_out_bits {
8181 u8 status[0x8];
b4ff3a36 8182 u8 reserved_at_8[0x18];
e281682b
SM		 8183
8184 u8 syndrome[0x20];
8185
b4ff3a36 8186 u8 reserved_at_40[0x40];
e281682b
SM		 8187};
8188
8189struct mlx5_ifc_delete_fte_in_bits {
8190 u8 opcode[0x10];
b4ff3a36 8191 u8 reserved_at_10[0x10];
e281682b 8192
b4ff3a36 8193 u8 reserved_at_20[0x10];
e281682b
SM		 8194 u8 op_mod[0x10];
8195
7d5e1423
SM		 8196 u8 other_vport[0x1];
8197 u8 reserved_at_41[0xf];
8198 u8 vport_number[0x10];
8199
8200 u8 reserved_at_60[0x20];
e281682b
SM		 8201
8202 u8 table_type[0x8];
b4ff3a36 8203 u8 reserved_at_88[0x18];
e281682b 8204
b4ff3a36 8205 u8 reserved_at_a0[0x8];
e281682b
SM		 8206 u8 table_id[0x18];
8207
b4ff3a36 8208 u8 reserved_at_c0[0x40];
e281682b
SM		 8209
8210 u8 flow_index[0x20];
8211
b4ff3a36 8212 u8 reserved_at_120[0xe0];
e281682b
SM		 8213};
8214
8215struct mlx5_ifc_dealloc_xrcd_out_bits {
8216 u8 status[0x8];
b4ff3a36 8217 u8 reserved_at_8[0x18];
e281682b
SM		 8218
8219 u8 syndrome[0x20];
8220
b4ff3a36 8221 u8 reserved_at_40[0x40];
e281682b
SM		 8222};
8223
8224struct mlx5_ifc_dealloc_xrcd_in_bits {
8225 u8 opcode[0x10];
bd371975 8226 u8 uid[0x10];
e281682b 8227
b4ff3a36 8228 u8 reserved_at_20[0x10];
e281682b
SM		 8229 u8 op_mod[0x10];
8230
b4ff3a36 8231 u8 reserved_at_40[0x8];
e281682b
SM		 8232 u8 xrcd[0x18];
8233
b4ff3a36 8234 u8 reserved_at_60[0x20];
e281682b
SM		 8235};
8236
8237struct mlx5_ifc_dealloc_uar_out_bits {
8238 u8 status[0x8];
b4ff3a36 8239 u8 reserved_at_8[0x18];
e281682b
SM		 8240
8241 u8 syndrome[0x20];
8242
b4ff3a36 8243 u8 reserved_at_40[0x40];
e281682b
SM		 8244};
8245
8246struct mlx5_ifc_dealloc_uar_in_bits {
8247 u8 opcode[0x10];
8de1e9b0 8248 u8 uid[0x10];
e281682b 8249
b4ff3a36 8250 u8 reserved_at_20[0x10];
e281682b
SM		 8251 u8 op_mod[0x10];
8252
b4ff3a36 8253 u8 reserved_at_40[0x8];
e281682b
SM		 8254 u8 uar[0x18];
8255
b4ff3a36 8256 u8 reserved_at_60[0x20];
e281682b
SM		 8257};
8258
8259struct mlx5_ifc_dealloc_transport_domain_out_bits {
8260 u8 status[0x8];
b4ff3a36 8261 u8 reserved_at_8[0x18];
e281682b
SM		 8262
8263 u8 syndrome[0x20];
8264
b4ff3a36 8265 u8 reserved_at_40[0x40];
e281682b
SM		 8266};
8267
8268struct mlx5_ifc_dealloc_transport_domain_in_bits {
8269 u8 opcode[0x10];
71bef2fd 8270 u8 uid[0x10];
e281682b 8271
b4ff3a36 8272 u8 reserved_at_20[0x10];
e281682b
SM		 8273 u8 op_mod[0x10];
8274
b4ff3a36 8275 u8 reserved_at_40[0x8];
e281682b
SM		 8276 u8 transport_domain[0x18];
8277
b4ff3a36 8278 u8 reserved_at_60[0x20];
e281682b
SM		 8279};
8280
8281struct mlx5_ifc_dealloc_q_counter_out_bits {
8282 u8 status[0x8];
b4ff3a36 8283 u8 reserved_at_8[0x18];
e281682b
SM		 8284
8285 u8 syndrome[0x20];
8286
b4ff3a36 8287 u8 reserved_at_40[0x40];
e281682b
SM		 8288};
8289
8290struct mlx5_ifc_dealloc_q_counter_in_bits {
8291 u8 opcode[0x10];
b4ff3a36 8292 u8 reserved_at_10[0x10];
e281682b 8293
b4ff3a36 8294 u8 reserved_at_20[0x10];
e281682b
SM		 8295 u8 op_mod[0x10];
8296
b4ff3a36 8297 u8 reserved_at_40[0x18];
e281682b
SM		 8298 u8 counter_set_id[0x8];
8299
b4ff3a36 8300 u8 reserved_at_60[0x20];
e281682b
SM		 8301};
8302
8303struct mlx5_ifc_dealloc_pd_out_bits {
8304 u8 status[0x8];
b4ff3a36 8305 u8 reserved_at_8[0x18];
e281682b
SM		 8306
8307 u8 syndrome[0x20];
8308
b4ff3a36 8309 u8 reserved_at_40[0x40];
e281682b
SM		 8310};
8311
8312struct mlx5_ifc_dealloc_pd_in_bits {
8313 u8 opcode[0x10];
bd371975 8314 u8 uid[0x10];
e281682b 8315
b4ff3a36 8316 u8 reserved_at_20[0x10];
e281682b
SM		 8317 u8 op_mod[0x10];
8318
b4ff3a36 8319 u8 reserved_at_40[0x8];
e281682b
SM		 8320 u8 pd[0x18];
8321
b4ff3a36 8322 u8 reserved_at_60[0x20];
e281682b
SM		 8323};
8324
9dc0b289
AV		 8325struct mlx5_ifc_dealloc_flow_counter_out_bits {
8326 u8 status[0x8];
8327 u8 reserved_at_8[0x18];
8328
8329 u8 syndrome[0x20];
8330
8331 u8 reserved_at_40[0x40];
8332};
8333
8334struct mlx5_ifc_dealloc_flow_counter_in_bits {
8335 u8 opcode[0x10];
8336 u8 reserved_at_10[0x10];
8337
8338 u8 reserved_at_20[0x10];
8339 u8 op_mod[0x10];
8340
a8ffcc74 8341 u8 flow_counter_id[0x20];
9dc0b289
AV		 8342
8343 u8 reserved_at_60[0x20];
8344};
8345
7486216b
SM		 8346struct mlx5_ifc_create_xrq_out_bits {
8347 u8 status[0x8];
8348 u8 reserved_at_8[0x18];
8349
8350 u8 syndrome[0x20];
8351
8352 u8 reserved_at_40[0x8];
8353 u8 xrqn[0x18];
8354
8355 u8 reserved_at_60[0x20];
8356};
8357
8358struct mlx5_ifc_create_xrq_in_bits {
8359 u8 opcode[0x10];
a0d8c054 8360 u8 uid[0x10];
7486216b
SM		 8361
8362 u8 reserved_at_20[0x10];
8363 u8 op_mod[0x10];
8364
8365 u8 reserved_at_40[0x40];
8366
8367 struct mlx5_ifc_xrqc_bits xrq_context;
8368};
8369
e281682b
SM		 8370struct mlx5_ifc_create_xrc_srq_out_bits {
8371 u8 status[0x8];
b4ff3a36 8372 u8 reserved_at_8[0x18];
e281682b
SM		 8373
8374 u8 syndrome[0x20];
8375
b4ff3a36 8376 u8 reserved_at_40[0x8];
e281682b
SM		 8377 u8 xrc_srqn[0x18];
8378
b4ff3a36 8379 u8 reserved_at_60[0x20];
e281682b
SM		 8380};
8381
8382struct mlx5_ifc_create_xrc_srq_in_bits {
8383 u8 opcode[0x10];
a0d8c054 8384 u8 uid[0x10];
e281682b 8385
b4ff3a36 8386 u8 reserved_at_20[0x10];
e281682b
SM		 8387 u8 op_mod[0x10];
8388
b4ff3a36 8389 u8 reserved_at_40[0x40];
e281682b
SM		 8390
8391 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8392
99b77fef
YH		 8393 u8 reserved_at_280[0x60];
8394
bd371975 8395 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 8396 u8 reserved_at_2e1[0x1f];
8397
8398 u8 reserved_at_300[0x580];
e281682b 8399
b6ca09cb 8400 u8 pas[][0x40];
e281682b
SM		 8401};
8402
8403struct mlx5_ifc_create_tis_out_bits {
8404 u8 status[0x8];
b4ff3a36 8405 u8 reserved_at_8[0x18];
e281682b
SM		 8406
8407 u8 syndrome[0x20];
8408
b4ff3a36 8409 u8 reserved_at_40[0x8];
e281682b
SM		 8410 u8 tisn[0x18];
8411
b4ff3a36 8412 u8 reserved_at_60[0x20];
e281682b
SM		 8413};
8414
8415struct mlx5_ifc_create_tis_in_bits {
8416 u8 opcode[0x10];
bd371975 8417 u8 uid[0x10];
e281682b 8418
b4ff3a36 8419 u8 reserved_at_20[0x10];
e281682b
SM		 8420 u8 op_mod[0x10];
8421
b4ff3a36 8422 u8 reserved_at_40[0xc0];
e281682b
SM		 8423
8424 struct mlx5_ifc_tisc_bits ctx;
8425};
8426
8427struct mlx5_ifc_create_tir_out_bits {
8428 u8 status[0x8];
3e070470 8429 u8 icm_address_63_40[0x18];
e281682b
SM		 8430
8431 u8 syndrome[0x20];
8432
3e070470 8433 u8 icm_address_39_32[0x8];
e281682b
SM		 8434 u8 tirn[0x18];
8435
3e070470 8436 u8 icm_address_31_0[0x20];
e281682b
SM		 8437};
8438
8439struct mlx5_ifc_create_tir_in_bits {
8440 u8 opcode[0x10];
bd371975 8441 u8 uid[0x10];
e281682b 8442
b4ff3a36 8443 u8 reserved_at_20[0x10];
e281682b
SM		 8444 u8 op_mod[0x10];
8445
b4ff3a36 8446 u8 reserved_at_40[0xc0];
e281682b
SM		 8447
8448 struct mlx5_ifc_tirc_bits ctx;
8449};
8450
8451struct mlx5_ifc_create_srq_out_bits {
8452 u8 status[0x8];
b4ff3a36 8453 u8 reserved_at_8[0x18];
e281682b
SM		 8454
8455 u8 syndrome[0x20];
8456
b4ff3a36 8457 u8 reserved_at_40[0x8];
e281682b
SM		 8458 u8 srqn[0x18];
8459
b4ff3a36 8460 u8 reserved_at_60[0x20];
e281682b
SM		 8461};
8462
8463struct mlx5_ifc_create_srq_in_bits {
8464 u8 opcode[0x10];
a0d8c054 8465 u8 uid[0x10];
e281682b 8466
b4ff3a36 8467 u8 reserved_at_20[0x10];
e281682b
SM		 8468 u8 op_mod[0x10];
8469
b4ff3a36 8470 u8 reserved_at_40[0x40];
e281682b
SM		 8471
8472 struct mlx5_ifc_srqc_bits srq_context_entry;
8473
b4ff3a36 8474 u8 reserved_at_280[0x600];
e281682b 8475
b6ca09cb 8476 u8 pas[][0x40];
e281682b
SM		 8477};
8478
8479struct mlx5_ifc_create_sq_out_bits {
8480 u8 status[0x8];
b4ff3a36 8481 u8 reserved_at_8[0x18];
e281682b
SM		 8482
8483 u8 syndrome[0x20];
8484
b4ff3a36 8485 u8 reserved_at_40[0x8];
e281682b
SM		 8486 u8 sqn[0x18];
8487
b4ff3a36 8488 u8 reserved_at_60[0x20];
e281682b
SM		 8489};
8490
8491struct mlx5_ifc_create_sq_in_bits {
8492 u8 opcode[0x10];
430ae0d5 8493 u8 uid[0x10];
e281682b 8494
b4ff3a36 8495 u8 reserved_at_20[0x10];
e281682b
SM		 8496 u8 op_mod[0x10];
8497
b4ff3a36 8498 u8 reserved_at_40[0xc0];
e281682b
SM		 8499
8500 struct mlx5_ifc_sqc_bits ctx;
8501};
8502
813f8540
MHY		 8503struct mlx5_ifc_create_scheduling_element_out_bits {
8504 u8 status[0x8];
8505 u8 reserved_at_8[0x18];
8506
8507 u8 syndrome[0x20];
8508
8509 u8 reserved_at_40[0x40];
8510
8511 u8 scheduling_element_id[0x20];
8512
8513 u8 reserved_at_a0[0x160];
8514};
8515
8516struct mlx5_ifc_create_scheduling_element_in_bits {
8517 u8 opcode[0x10];
8518 u8 reserved_at_10[0x10];
8519
8520 u8 reserved_at_20[0x10];
8521 u8 op_mod[0x10];
8522
8523 u8 scheduling_hierarchy[0x8];
8524 u8 reserved_at_48[0x18];
8525
8526 u8 reserved_at_60[0xa0];
8527
8528 struct mlx5_ifc_scheduling_context_bits scheduling_context;
8529
8530 u8 reserved_at_300[0x100];
8531};
8532
e281682b
SM		 8533struct mlx5_ifc_create_rqt_out_bits {
8534 u8 status[0x8];
b4ff3a36 8535 u8 reserved_at_8[0x18];
e281682b
SM		 8536
8537 u8 syndrome[0x20];
8538
b4ff3a36 8539 u8 reserved_at_40[0x8];
e281682b
SM		 8540 u8 rqtn[0x18];
8541
b4ff3a36 8542 u8 reserved_at_60[0x20];
e281682b
SM		 8543};
8544
8545struct mlx5_ifc_create_rqt_in_bits {
8546 u8 opcode[0x10];
bd371975 8547 u8 uid[0x10];
e281682b 8548
b4ff3a36 8549 u8 reserved_at_20[0x10];
e281682b
SM		 8550 u8 op_mod[0x10];
8551
b4ff3a36 8552 u8 reserved_at_40[0xc0];
e281682b
SM		 8553
8554 struct mlx5_ifc_rqtc_bits rqt_context;
8555};
8556
8557struct mlx5_ifc_create_rq_out_bits {
8558 u8 status[0x8];
b4ff3a36 8559 u8 reserved_at_8[0x18];
e281682b
SM		 8560
8561 u8 syndrome[0x20];
8562
b4ff3a36 8563 u8 reserved_at_40[0x8];
e281682b
SM		 8564 u8 rqn[0x18];
8565
b4ff3a36 8566 u8 reserved_at_60[0x20];
e281682b
SM		 8567};
8568
8569struct mlx5_ifc_create_rq_in_bits {
8570 u8 opcode[0x10];
d269b3af 8571 u8 uid[0x10];
e281682b 8572
b4ff3a36 8573 u8 reserved_at_20[0x10];
e281682b
SM		 8574 u8 op_mod[0x10];
8575
b4ff3a36 8576 u8 reserved_at_40[0xc0];
e281682b
SM		 8577
8578 struct mlx5_ifc_rqc_bits ctx;
8579};
8580
8581struct mlx5_ifc_create_rmp_out_bits {
8582 u8 status[0x8];
b4ff3a36 8583 u8 reserved_at_8[0x18];
e281682b
SM		 8584
8585 u8 syndrome[0x20];
8586
b4ff3a36 8587 u8 reserved_at_40[0x8];
e281682b
SM		 8588 u8 rmpn[0x18];
8589
b4ff3a36 8590 u8 reserved_at_60[0x20];
e281682b
SM		 8591};
8592
8593struct mlx5_ifc_create_rmp_in_bits {
8594 u8 opcode[0x10];
a0d8c054 8595 u8 uid[0x10];
e281682b 8596
b4ff3a36 8597 u8 reserved_at_20[0x10];
e281682b
SM		 8598 u8 op_mod[0x10];
8599
b4ff3a36 8600 u8 reserved_at_40[0xc0];
e281682b
SM		 8601
8602 struct mlx5_ifc_rmpc_bits ctx;
8603};
8604
8605struct mlx5_ifc_create_qp_out_bits {
8606 u8 status[0x8];
b4ff3a36 8607 u8 reserved_at_8[0x18];
e281682b
SM		 8608
8609 u8 syndrome[0x20];
8610
b4ff3a36 8611 u8 reserved_at_40[0x8];
e281682b
SM		 8612 u8 qpn[0x18];
8613
6b646a7e 8614 u8 ece[0x20];
e281682b
SM		 8615};
8616
8617struct mlx5_ifc_create_qp_in_bits {
8618 u8 opcode[0x10];
4ac63ec7 8619 u8 uid[0x10];
e281682b 8620
b4ff3a36 8621 u8 reserved_at_20[0x10];
e281682b
SM		 8622 u8 op_mod[0x10];
8623
9b2e3723
PH		 8624 u8 qpc_ext[0x1];
8625 u8 reserved_at_41[0x7];
4dca6509 8626 u8 input_qpn[0x18];
e281682b 8627
4dca6509 8628 u8 reserved_at_60[0x20];
e281682b
SM		 8629 u8 opt_param_mask[0x20];
8630
6b646a7e 8631 u8 ece[0x20];
e281682b
SM		 8632
8633 struct mlx5_ifc_qpc_bits qpc;
8634
bd371975
LR		 8635 u8 reserved_at_800[0x60];
8636
8637 u8 wq_umem_valid[0x1];
8638 u8 reserved_at_861[0x1f];
e281682b 8639
b6ca09cb 8640 u8 pas[][0x40];
e281682b
SM		 8641};
8642
8643struct mlx5_ifc_create_psv_out_bits {
8644 u8 status[0x8];
b4ff3a36 8645 u8 reserved_at_8[0x18];
e281682b
SM		 8646
8647 u8 syndrome[0x20];
8648
b4ff3a36 8649 u8 reserved_at_40[0x40];
e281682b 8650
b4ff3a36 8651 u8 reserved_at_80[0x8];
e281682b
SM		 8652 u8 psv0_index[0x18];
8653
b4ff3a36 8654 u8 reserved_at_a0[0x8];
e281682b
SM		 8655 u8 psv1_index[0x18];
8656
b4ff3a36 8657 u8 reserved_at_c0[0x8];
e281682b
SM		 8658 u8 psv2_index[0x18];
8659
b4ff3a36 8660 u8 reserved_at_e0[0x8];
e281682b
SM		 8661 u8 psv3_index[0x18];
8662};
8663
8664struct mlx5_ifc_create_psv_in_bits {
8665 u8 opcode[0x10];
b4ff3a36 8666 u8 reserved_at_10[0x10];
e281682b 8667
b4ff3a36 8668 u8 reserved_at_20[0x10];
e281682b
SM		 8669 u8 op_mod[0x10];
8670
8671 u8 num_psv[0x4];
b4ff3a36 8672 u8 reserved_at_44[0x4];
e281682b
SM		 8673 u8 pd[0x18];
8674
b4ff3a36 8675 u8 reserved_at_60[0x20];
e281682b
SM		 8676};
8677
8678struct mlx5_ifc_create_mkey_out_bits {
8679 u8 status[0x8];
b4ff3a36 8680 u8 reserved_at_8[0x18];
e281682b
SM		 8681
8682 u8 syndrome[0x20];
8683
b4ff3a36 8684 u8 reserved_at_40[0x8];
e281682b
SM		 8685 u8 mkey_index[0x18];
8686
b4ff3a36 8687 u8 reserved_at_60[0x20];
e281682b
SM		 8688};
8689
8690struct mlx5_ifc_create_mkey_in_bits {
8691 u8 opcode[0x10];
8a06a79b 8692 u8 uid[0x10];
e281682b 8693
b4ff3a36 8694 u8 reserved_at_20[0x10];
e281682b
SM		 8695 u8 op_mod[0x10];
8696
b4ff3a36 8697 u8 reserved_at_40[0x20];
e281682b
SM		 8698
8699 u8 pg_access[0x1];
bd371975
LR		 8700 u8 mkey_umem_valid[0x1];
8701 u8 reserved_at_62[0x1e];
e281682b
SM		 8702
8703 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8704
b4ff3a36 8705 u8 reserved_at_280[0x80];
e281682b
SM		 8706
8707 u8 translations_octword_actual_size[0x20];
8708
b4ff3a36 8709 u8 reserved_at_320[0x560];
e281682b 8710
b6ca09cb 8711 u8 klm_pas_mtt[][0x20];
e281682b
SM		 8712};
8713
97b5484e
AV		 8714enum {
8715 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8716 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8717 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8718 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8719 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8720 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8721 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8722};
8723
e281682b
SM		 8724struct mlx5_ifc_create_flow_table_out_bits {
8725 u8 status[0x8];
97b5484e 8726 u8 icm_address_63_40[0x18];
e281682b
SM		 8727
8728 u8 syndrome[0x20];
8729
97b5484e 8730 u8 icm_address_39_32[0x8];
e281682b
SM		 8731 u8 table_id[0x18];
8732
97b5484e 8733 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 8734};
8735
e281682b
SM		 8736struct mlx5_ifc_create_flow_table_in_bits {
8737 u8 opcode[0x10];
f484da84 8738 u8 uid[0x10];
e281682b 8739
b4ff3a36 8740 u8 reserved_at_20[0x10];
e281682b
SM		 8741 u8 op_mod[0x10];
8742
7d5e1423
SM		 8743 u8 other_vport[0x1];
8744 u8 reserved_at_41[0xf];
8745 u8 vport_number[0x10];
8746
8747 u8 reserved_at_60[0x20];
e281682b
SM		 8748
8749 u8 table_type[0x8];
b4ff3a36 8750 u8 reserved_at_88[0x18];
e281682b 8751
b4ff3a36 8752 u8 reserved_at_a0[0x20];
e281682b 8753
0c90e9c6 8754 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 8755};
8756
8757struct mlx5_ifc_create_flow_group_out_bits {
8758 u8 status[0x8];
b4ff3a36 8759 u8 reserved_at_8[0x18];
e281682b
SM		 8760
8761 u8 syndrome[0x20];
8762
b4ff3a36 8763 u8 reserved_at_40[0x8];
e281682b
SM		 8764 u8 group_id[0x18];
8765
b4ff3a36 8766 u8 reserved_at_60[0x20];
e281682b
SM		 8767};
8768
e7e2519e
MG		 8769enum {
8770 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8771 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8772};
8773
e281682b 8774enum {
71c6e863
AL		 8775 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8776 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8777 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8778 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 8779};
8780
8781struct mlx5_ifc_create_flow_group_in_bits {
8782 u8 opcode[0x10];
b4ff3a36 8783 u8 reserved_at_10[0x10];
e281682b 8784
b4ff3a36 8785 u8 reserved_at_20[0x10];
e281682b
SM		 8786 u8 op_mod[0x10];
8787
7d5e1423
SM		 8788 u8 other_vport[0x1];
8789 u8 reserved_at_41[0xf];
8790 u8 vport_number[0x10];
8791
8792 u8 reserved_at_60[0x20];
e281682b
SM		 8793
8794 u8 table_type[0x8];
e7e2519e
MG		 8795 u8 reserved_at_88[0x4];
8796 u8 group_type[0x4];
8797 u8 reserved_at_90[0x10];
e281682b 8798
b4ff3a36 8799 u8 reserved_at_a0[0x8];
e281682b
SM		 8800 u8 table_id[0x18];
8801
3e99df87
SK		 8802 u8 source_eswitch_owner_vhca_id_valid[0x1];
8803
8804 u8 reserved_at_c1[0x1f];
e281682b
SM		 8805
8806 u8 start_flow_index[0x20];
8807
b4ff3a36 8808 u8 reserved_at_100[0x20];
e281682b
SM		 8809
8810 u8 end_flow_index[0x20];
8811
e7e2519e
MG		 8812 u8 reserved_at_140[0x10];
8813 u8 match_definer_id[0x10];
8814
8815 u8 reserved_at_160[0x80];
e281682b 8816
b4ff3a36 8817 u8 reserved_at_1e0[0x18];
e281682b
SM		 8818 u8 match_criteria_enable[0x8];
8819
8820 struct mlx5_ifc_fte_match_param_bits match_criteria;
8821
b4ff3a36 8822 u8 reserved_at_1200[0xe00];
e281682b
SM		 8823};
8824
8825struct mlx5_ifc_create_eq_out_bits {
8826 u8 status[0x8];
b4ff3a36 8827 u8 reserved_at_8[0x18];
e281682b
SM		 8828
8829 u8 syndrome[0x20];
8830
b4ff3a36 8831 u8 reserved_at_40[0x18];
e281682b
SM		 8832 u8 eq_number[0x8];
8833
b4ff3a36 8834 u8 reserved_at_60[0x20];
e281682b
SM		 8835};
8836
8837struct mlx5_ifc_create_eq_in_bits {
8838 u8 opcode[0x10];
c191f934 8839 u8 uid[0x10];
e281682b 8840
b4ff3a36 8841 u8 reserved_at_20[0x10];
e281682b
SM		 8842 u8 op_mod[0x10];
8843
b4ff3a36 8844 u8 reserved_at_40[0x40];
e281682b
SM		 8845
8846 struct mlx5_ifc_eqc_bits eq_context_entry;
8847
b4ff3a36 8848 u8 reserved_at_280[0x40];
e281682b 8849
b9a7ba55 8850 u8 event_bitmask[4][0x40];
e281682b 8851
b9a7ba55 8852 u8 reserved_at_3c0[0x4c0];
e281682b 8853
b6ca09cb 8854 u8 pas[][0x40];
e281682b
SM		 8855};
8856
8857struct mlx5_ifc_create_dct_out_bits {
8858 u8 status[0x8];
b4ff3a36 8859 u8 reserved_at_8[0x18];
e281682b
SM		 8860
8861 u8 syndrome[0x20];
8862
b4ff3a36 8863 u8 reserved_at_40[0x8];
e281682b
SM		 8864 u8 dctn[0x18];
8865
a645a89d 8866 u8 ece[0x20];
e281682b
SM		 8867};
8868
8869struct mlx5_ifc_create_dct_in_bits {
8870 u8 opcode[0x10];
774ea6ee 8871 u8 uid[0x10];
e281682b 8872
b4ff3a36 8873 u8 reserved_at_20[0x10];
e281682b
SM		 8874 u8 op_mod[0x10];
8875
b4ff3a36 8876 u8 reserved_at_40[0x40];
e281682b
SM		 8877
8878 struct mlx5_ifc_dctc_bits dct_context_entry;
8879
b4ff3a36 8880 u8 reserved_at_280[0x180];
e281682b
SM		 8881};
8882
8883struct mlx5_ifc_create_cq_out_bits {
8884 u8 status[0x8];
b4ff3a36 8885 u8 reserved_at_8[0x18];
e281682b
SM		 8886
8887 u8 syndrome[0x20];
8888
b4ff3a36 8889 u8 reserved_at_40[0x8];
e281682b
SM		 8890 u8 cqn[0x18];
8891
b4ff3a36 8892 u8 reserved_at_60[0x20];
e281682b
SM		 8893};
8894
8895struct mlx5_ifc_create_cq_in_bits {
8896 u8 opcode[0x10];
9ba481e2 8897 u8 uid[0x10];
e281682b 8898
b4ff3a36 8899 u8 reserved_at_20[0x10];
e281682b
SM		 8900 u8 op_mod[0x10];
8901
b4ff3a36 8902 u8 reserved_at_40[0x40];
e281682b
SM		 8903
8904 struct mlx5_ifc_cqc_bits cq_context;
8905
bd371975
LR		 8906 u8 reserved_at_280[0x60];
8907
8908 u8 cq_umem_valid[0x1];
8909 u8 reserved_at_2e1[0x59f];
e281682b 8910
b6ca09cb 8911 u8 pas[][0x40];
e281682b
SM		 8912};
8913
8914struct mlx5_ifc_config_int_moderation_out_bits {
8915 u8 status[0x8];
b4ff3a36 8916 u8 reserved_at_8[0x18];
e281682b
SM		 8917
8918 u8 syndrome[0x20];
8919
b4ff3a36 8920 u8 reserved_at_40[0x4];
e281682b
SM		 8921 u8 min_delay[0xc];
8922 u8 int_vector[0x10];
8923
b4ff3a36 8924 u8 reserved_at_60[0x20];
e281682b
SM		 8925};
8926
8927enum {
8928 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8929 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8930};
8931
8932struct mlx5_ifc_config_int_moderation_in_bits {
8933 u8 opcode[0x10];
b4ff3a36 8934 u8 reserved_at_10[0x10];
e281682b 8935
b4ff3a36 8936 u8 reserved_at_20[0x10];
e281682b
SM		 8937 u8 op_mod[0x10];
8938
b4ff3a36 8939 u8 reserved_at_40[0x4];
e281682b
SM		 8940 u8 min_delay[0xc];
8941 u8 int_vector[0x10];
8942
b4ff3a36 8943 u8 reserved_at_60[0x20];
e281682b
SM		 8944};
8945
8946struct mlx5_ifc_attach_to_mcg_out_bits {
8947 u8 status[0x8];
b4ff3a36 8948 u8 reserved_at_8[0x18];
e281682b
SM		 8949
8950 u8 syndrome[0x20];
8951
b4ff3a36 8952 u8 reserved_at_40[0x40];
e281682b
SM		 8953};
8954
8955struct mlx5_ifc_attach_to_mcg_in_bits {
8956 u8 opcode[0x10];
bd371975 8957 u8 uid[0x10];
e281682b 8958
b4ff3a36 8959 u8 reserved_at_20[0x10];
e281682b
SM		 8960 u8 op_mod[0x10];
8961
b4ff3a36 8962 u8 reserved_at_40[0x8];
e281682b
SM		 8963 u8 qpn[0x18];
8964
b4ff3a36 8965 u8 reserved_at_60[0x20];
e281682b
SM		 8966
8967 u8 multicast_gid[16][0x8];
8968};
8969
7486216b
SM		 8970struct mlx5_ifc_arm_xrq_out_bits {
8971 u8 status[0x8];
8972 u8 reserved_at_8[0x18];
8973
8974 u8 syndrome[0x20];
8975
8976 u8 reserved_at_40[0x40];
8977};
8978
8979struct mlx5_ifc_arm_xrq_in_bits {
8980 u8 opcode[0x10];
8981 u8 reserved_at_10[0x10];
8982
8983 u8 reserved_at_20[0x10];
8984 u8 op_mod[0x10];
8985
8986 u8 reserved_at_40[0x8];
8987 u8 xrqn[0x18];
8988
8989 u8 reserved_at_60[0x10];
8990 u8 lwm[0x10];
8991};
8992
e281682b
SM		 8993struct mlx5_ifc_arm_xrc_srq_out_bits {
8994 u8 status[0x8];
b4ff3a36 8995 u8 reserved_at_8[0x18];
e281682b
SM		 8996
8997 u8 syndrome[0x20];
8998
b4ff3a36 8999 u8 reserved_at_40[0x40];
e281682b
SM		 9000};
9001
9002enum {
9003 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
9004};
9005
9006struct mlx5_ifc_arm_xrc_srq_in_bits {
9007 u8 opcode[0x10];
a0d8c054 9008 u8 uid[0x10];
e281682b 9009
b4ff3a36 9010 u8 reserved_at_20[0x10];
e281682b
SM		 9011 u8 op_mod[0x10];
9012
b4ff3a36 9013 u8 reserved_at_40[0x8];
e281682b
SM		 9014 u8 xrc_srqn[0x18];
9015
b4ff3a36 9016 u8 reserved_at_60[0x10];
e281682b
SM		 9017 u8 lwm[0x10];
9018};
9019
9020struct mlx5_ifc_arm_rq_out_bits {
9021 u8 status[0x8];
b4ff3a36 9022 u8 reserved_at_8[0x18];
e281682b
SM		 9023
9024 u8 syndrome[0x20];
9025
b4ff3a36 9026 u8 reserved_at_40[0x40];
e281682b
SM		 9027};
9028
9029enum {
7486216b
SM		 9030 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9031 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 9032};
9033
9034struct mlx5_ifc_arm_rq_in_bits {
9035 u8 opcode[0x10];
a0d8c054 9036 u8 uid[0x10];
e281682b 9037
b4ff3a36 9038 u8 reserved_at_20[0x10];
e281682b
SM		 9039 u8 op_mod[0x10];
9040
b4ff3a36 9041 u8 reserved_at_40[0x8];
e281682b
SM		 9042 u8 srq_number[0x18];
9043
b4ff3a36 9044 u8 reserved_at_60[0x10];
e281682b
SM		 9045 u8 lwm[0x10];
9046};
9047
9048struct mlx5_ifc_arm_dct_out_bits {
9049 u8 status[0x8];
b4ff3a36 9050 u8 reserved_at_8[0x18];
e281682b
SM		 9051
9052 u8 syndrome[0x20];
9053
b4ff3a36 9054 u8 reserved_at_40[0x40];
e281682b
SM		 9055};
9056
9057struct mlx5_ifc_arm_dct_in_bits {
9058 u8 opcode[0x10];
b4ff3a36 9059 u8 reserved_at_10[0x10];
e281682b 9060
b4ff3a36 9061 u8 reserved_at_20[0x10];
e281682b
SM		 9062 u8 op_mod[0x10];
9063
b4ff3a36 9064 u8 reserved_at_40[0x8];
e281682b
SM		 9065 u8 dct_number[0x18];
9066
b4ff3a36 9067 u8 reserved_at_60[0x20];
e281682b
SM		 9068};
9069
9070struct mlx5_ifc_alloc_xrcd_out_bits {
9071 u8 status[0x8];
b4ff3a36 9072 u8 reserved_at_8[0x18];
e281682b
SM		 9073
9074 u8 syndrome[0x20];
9075
b4ff3a36 9076 u8 reserved_at_40[0x8];
e281682b
SM		 9077 u8 xrcd[0x18];
9078
b4ff3a36 9079 u8 reserved_at_60[0x20];
e281682b
SM		 9080};
9081
9082struct mlx5_ifc_alloc_xrcd_in_bits {
9083 u8 opcode[0x10];
bd371975 9084 u8 uid[0x10];
e281682b 9085
b4ff3a36 9086 u8 reserved_at_20[0x10];
e281682b
SM		 9087 u8 op_mod[0x10];
9088
b4ff3a36 9089 u8 reserved_at_40[0x40];
e281682b
SM		 9090};
9091
9092struct mlx5_ifc_alloc_uar_out_bits {
9093 u8 status[0x8];
b4ff3a36 9094 u8 reserved_at_8[0x18];
e281682b
SM		 9095
9096 u8 syndrome[0x20];
9097
b4ff3a36 9098 u8 reserved_at_40[0x8];
e281682b
SM		 9099 u8 uar[0x18];
9100
b4ff3a36 9101 u8 reserved_at_60[0x20];
e281682b
SM		 9102};
9103
9104struct mlx5_ifc_alloc_uar_in_bits {
9105 u8 opcode[0x10];
8de1e9b0 9106 u8 uid[0x10];
e281682b 9107
b4ff3a36 9108 u8 reserved_at_20[0x10];
e281682b
SM		 9109 u8 op_mod[0x10];
9110
b4ff3a36 9111 u8 reserved_at_40[0x40];
e281682b
SM		 9112};
9113
9114struct mlx5_ifc_alloc_transport_domain_out_bits {
9115 u8 status[0x8];
b4ff3a36 9116 u8 reserved_at_8[0x18];
e281682b
SM		 9117
9118 u8 syndrome[0x20];
9119
b4ff3a36 9120 u8 reserved_at_40[0x8];
e281682b
SM		 9121 u8 transport_domain[0x18];
9122
b4ff3a36 9123 u8 reserved_at_60[0x20];
e281682b
SM		 9124};
9125
9126struct mlx5_ifc_alloc_transport_domain_in_bits {
9127 u8 opcode[0x10];
71bef2fd 9128 u8 uid[0x10];
e281682b 9129
b4ff3a36 9130 u8 reserved_at_20[0x10];
e281682b
SM		 9131 u8 op_mod[0x10];
9132
b4ff3a36 9133 u8 reserved_at_40[0x40];
e281682b
SM		 9134};
9135
9136struct mlx5_ifc_alloc_q_counter_out_bits {
9137 u8 status[0x8];
b4ff3a36 9138 u8 reserved_at_8[0x18];
e281682b
SM		 9139
9140 u8 syndrome[0x20];
9141
b4ff3a36 9142 u8 reserved_at_40[0x18];
e281682b
SM		 9143 u8 counter_set_id[0x8];
9144
b4ff3a36 9145 u8 reserved_at_60[0x20];
e281682b
SM		 9146};
9147
9148struct mlx5_ifc_alloc_q_counter_in_bits {
9149 u8 opcode[0x10];
2acc7957 9150 u8 uid[0x10];
e281682b 9151
b4ff3a36 9152 u8 reserved_at_20[0x10];
e281682b
SM		 9153 u8 op_mod[0x10];
9154
b4ff3a36 9155 u8 reserved_at_40[0x40];
e281682b
SM		 9156};
9157
9158struct mlx5_ifc_alloc_pd_out_bits {
9159 u8 status[0x8];
b4ff3a36 9160 u8 reserved_at_8[0x18];
e281682b
SM		 9161
9162 u8 syndrome[0x20];
9163
b4ff3a36 9164 u8 reserved_at_40[0x8];
e281682b
SM		 9165 u8 pd[0x18];
9166
b4ff3a36 9167 u8 reserved_at_60[0x20];
e281682b
SM		 9168};
9169
9170struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 9171 u8 opcode[0x10];
bd371975 9172 u8 uid[0x10];
9dc0b289
AV		 9173
9174 u8 reserved_at_20[0x10];
9175 u8 op_mod[0x10];
9176
9177 u8 reserved_at_40[0x40];
9178};
9179
9180struct mlx5_ifc_alloc_flow_counter_out_bits {
9181 u8 status[0x8];
9182 u8 reserved_at_8[0x18];
9183
9184 u8 syndrome[0x20];
9185
a8ffcc74 9186 u8 flow_counter_id[0x20];
9dc0b289
AV		 9187
9188 u8 reserved_at_60[0x20];
9189};
9190
9191struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 9192 u8 opcode[0x10];
b4ff3a36 9193 u8 reserved_at_10[0x10];
e281682b 9194
b4ff3a36 9195 u8 reserved_at_20[0x10];
e281682b
SM		 9196 u8 op_mod[0x10];
9197
8536a6bf
GT		 9198 u8 reserved_at_40[0x38];
9199 u8 flow_counter_bulk[0x8];
e281682b
SM		 9200};
9201
9202struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9203 u8 status[0x8];
b4ff3a36 9204 u8 reserved_at_8[0x18];
e281682b
SM		 9205
9206 u8 syndrome[0x20];
9207
b4ff3a36 9208 u8 reserved_at_40[0x40];
e281682b
SM		 9209};
9210
9211struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9212 u8 opcode[0x10];
b4ff3a36 9213 u8 reserved_at_10[0x10];
e281682b 9214
b4ff3a36 9215 u8 reserved_at_20[0x10];
e281682b
SM		 9216 u8 op_mod[0x10];
9217
b4ff3a36 9218 u8 reserved_at_40[0x20];
e281682b 9219
b4ff3a36 9220 u8 reserved_at_60[0x10];
e281682b
SM		 9221 u8 vxlan_udp_port[0x10];
9222};
9223
37e92a9d 9224struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 9225 u8 status[0x8];
9226 u8 reserved_at_8[0x18];
9227
9228 u8 syndrome[0x20];
9229
9230 u8 reserved_at_40[0x40];
9231};
9232
1326034b
YH		 9233struct mlx5_ifc_set_pp_rate_limit_context_bits {
9234 u8 rate_limit[0x20];
9235
9236 u8 burst_upper_bound[0x20];
9237
9238 u8 reserved_at_40[0x10];
9239 u8 typical_packet_size[0x10];
9240
9241 u8 reserved_at_60[0x120];
9242};
9243
37e92a9d 9244struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 9245 u8 opcode[0x10];
1326034b 9246 u8 uid[0x10];
7486216b
SM		 9247
9248 u8 reserved_at_20[0x10];
9249 u8 op_mod[0x10];
9250
9251 u8 reserved_at_40[0x10];
9252 u8 rate_limit_index[0x10];
9253
9254 u8 reserved_at_60[0x20];
9255
1326034b 9256 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 9257};
9258
e281682b
SM		 9259struct mlx5_ifc_access_register_out_bits {
9260 u8 status[0x8];
b4ff3a36 9261 u8 reserved_at_8[0x18];
e281682b
SM		 9262
9263 u8 syndrome[0x20];
9264
b4ff3a36 9265 u8 reserved_at_40[0x40];
e281682b 9266
b6ca09cb 9267 u8 register_data[][0x20];
e281682b
SM		 9268};
9269
9270enum {
9271 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9272 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9273};
9274
9275struct mlx5_ifc_access_register_in_bits {
9276 u8 opcode[0x10];
b4ff3a36 9277 u8 reserved_at_10[0x10];
e281682b 9278
b4ff3a36 9279 u8 reserved_at_20[0x10];
e281682b
SM		 9280 u8 op_mod[0x10];
9281
b4ff3a36 9282 u8 reserved_at_40[0x10];
e281682b
SM		 9283 u8 register_id[0x10];
9284
9285 u8 argument[0x20];
9286
b6ca09cb 9287 u8 register_data[][0x20];
e281682b
SM		 9288};
9289
9290struct mlx5_ifc_sltp_reg_bits {
9291 u8 status[0x4];
9292 u8 version[0x4];
9293 u8 local_port[0x8];
9294 u8 pnat[0x2];
b4ff3a36 9295 u8 reserved_at_12[0x2];
e281682b 9296 u8 lane[0x4];
b4ff3a36 9297 u8 reserved_at_18[0x8];
e281682b 9298
b4ff3a36 9299 u8 reserved_at_20[0x20];
e281682b 9300
b4ff3a36 9301 u8 reserved_at_40[0x7];
e281682b
SM		 9302 u8 polarity[0x1];
9303 u8 ob_tap0[0x8];
9304 u8 ob_tap1[0x8];
9305 u8 ob_tap2[0x8];
9306
b4ff3a36 9307 u8 reserved_at_60[0xc];
e281682b
SM		 9308 u8 ob_preemp_mode[0x4];
9309 u8 ob_reg[0x8];
9310 u8 ob_bias[0x8];
9311
b4ff3a36 9312 u8 reserved_at_80[0x20];
e281682b
SM		 9313};
9314
9315struct mlx5_ifc_slrg_reg_bits {
9316 u8 status[0x4];
9317 u8 version[0x4];
9318 u8 local_port[0x8];
9319 u8 pnat[0x2];
b4ff3a36 9320 u8 reserved_at_12[0x2];
e281682b 9321 u8 lane[0x4];
b4ff3a36 9322 u8 reserved_at_18[0x8];
e281682b
SM		 9323
9324 u8 time_to_link_up[0x10];
b4ff3a36 9325 u8 reserved_at_30[0xc];
e281682b
SM		 9326 u8 grade_lane_speed[0x4];
9327
9328 u8 grade_version[0x8];
9329 u8 grade[0x18];
9330
b4ff3a36 9331 u8 reserved_at_60[0x4];
e281682b
SM		 9332 u8 height_grade_type[0x4];
9333 u8 height_grade[0x18];
9334
9335 u8 height_dz[0x10];
9336 u8 height_dv[0x10];
9337
b4ff3a36 9338 u8 reserved_at_a0[0x10];
e281682b
SM		 9339 u8 height_sigma[0x10];
9340
b4ff3a36 9341 u8 reserved_at_c0[0x20];
e281682b 9342
b4ff3a36 9343 u8 reserved_at_e0[0x4];
e281682b
SM		 9344 u8 phase_grade_type[0x4];
9345 u8 phase_grade[0x18];
9346
b4ff3a36 9347 u8 reserved_at_100[0x8];
e281682b 9348 u8 phase_eo_pos[0x8];
b4ff3a36 9349 u8 reserved_at_110[0x8];
e281682b
SM		 9350 u8 phase_eo_neg[0x8];
9351
9352 u8 ffe_set_tested[0x10];
9353 u8 test_errors_per_lane[0x10];
9354};
9355
9356struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 9357 u8 reserved_at_0[0x8];
e281682b 9358 u8 local_port[0x8];
b4ff3a36 9359 u8 reserved_at_10[0x10];
e281682b 9360
b4ff3a36 9361 u8 reserved_at_20[0x1c];
e281682b
SM		 9362 u8 vl_hw_cap[0x4];
9363
b4ff3a36 9364 u8 reserved_at_40[0x1c];
e281682b
SM		 9365 u8 vl_admin[0x4];
9366
b4ff3a36 9367 u8 reserved_at_60[0x1c];
e281682b
SM		 9368 u8 vl_operational[0x4];
9369};
9370
9371struct mlx5_ifc_pude_reg_bits {
9372 u8 swid[0x8];
9373 u8 local_port[0x8];
b4ff3a36 9374 u8 reserved_at_10[0x4];
e281682b 9375 u8 admin_status[0x4];
b4ff3a36 9376 u8 reserved_at_18[0x4];
e281682b
SM		 9377 u8 oper_status[0x4];
9378
b4ff3a36 9379 u8 reserved_at_20[0x60];
e281682b
SM		 9380};
9381
9382struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 9383 u8 reserved_at_0[0x1];
7486216b 9384 u8 an_disable_admin[0x1];
e7e31ca4
BW		 9385 u8 an_disable_cap[0x1];
9386 u8 reserved_at_3[0x5];
e281682b 9387 u8 local_port[0x8];
b4ff3a36 9388 u8 reserved_at_10[0xd];
e281682b
SM		 9389 u8 proto_mask[0x3];
9390
7486216b 9391 u8 an_status[0x4];
dc392fc5
MB		 9392 u8 reserved_at_24[0xc];
9393 u8 data_rate_oper[0x10];
a0a89989
AL		 9394
9395 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 9396
9397 u8 eth_proto_capability[0x20];
9398
9399 u8 ib_link_width_capability[0x10];
9400 u8 ib_proto_capability[0x10];
9401
a0a89989 9402 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 9403
9404 u8 eth_proto_admin[0x20];
9405
9406 u8 ib_link_width_admin[0x10];
9407 u8 ib_proto_admin[0x10];
9408
a0a89989 9409 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 9410
9411 u8 eth_proto_oper[0x20];
9412
9413 u8 ib_link_width_oper[0x10];
9414 u8 ib_proto_oper[0x10];
9415
5b4793f8
EBE		 9416 u8 reserved_at_160[0x1c];
9417 u8 connector_type[0x4];
e281682b
SM		 9418
9419 u8 eth_proto_lp_advertise[0x20];
9420
b4ff3a36 9421 u8 reserved_at_1a0[0x60];
e281682b
SM		 9422};
9423
7d5e1423
SM		 9424struct mlx5_ifc_mlcr_reg_bits {
9425 u8 reserved_at_0[0x8];
9426 u8 local_port[0x8];
9427 u8 reserved_at_10[0x20];
9428
9429 u8 beacon_duration[0x10];
9430 u8 reserved_at_40[0x10];
9431
9432 u8 beacon_remain[0x10];
9433};
9434
e281682b 9435struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 9436 u8 reserved_at_0[0x20];
e281682b
SM		 9437
9438 u8 algorithm_options[0x10];
b4ff3a36 9439 u8 reserved_at_30[0x4];
e281682b
SM		 9440 u8 repetitions_mode[0x4];
9441 u8 num_of_repetitions[0x8];
9442
9443 u8 grade_version[0x8];
9444 u8 height_grade_type[0x4];
9445 u8 phase_grade_type[0x4];
9446 u8 height_grade_weight[0x8];
9447 u8 phase_grade_weight[0x8];
9448
9449 u8 gisim_measure_bits[0x10];
9450 u8 adaptive_tap_measure_bits[0x10];
9451
9452 u8 ber_bath_high_error_threshold[0x10];
9453 u8 ber_bath_mid_error_threshold[0x10];
9454
9455 u8 ber_bath_low_error_threshold[0x10];
9456 u8 one_ratio_high_threshold[0x10];
9457
9458 u8 one_ratio_high_mid_threshold[0x10];
9459 u8 one_ratio_low_mid_threshold[0x10];
9460
9461 u8 one_ratio_low_threshold[0x10];
9462 u8 ndeo_error_threshold[0x10];
9463
9464 u8 mixer_offset_step_size[0x10];
b4ff3a36 9465 u8 reserved_at_110[0x8];
e281682b
SM		 9466 u8 mix90_phase_for_voltage_bath[0x8];
9467
9468 u8 mixer_offset_start[0x10];
9469 u8 mixer_offset_end[0x10];
9470
b4ff3a36 9471 u8 reserved_at_140[0x15];
e281682b
SM		 9472 u8 ber_test_time[0xb];
9473};
9474
9475struct mlx5_ifc_pspa_reg_bits {
9476 u8 swid[0x8];
9477 u8 local_port[0x8];
9478 u8 sub_port[0x8];
b4ff3a36 9479 u8 reserved_at_18[0x8];
e281682b 9480
b4ff3a36 9481 u8 reserved_at_20[0x20];
e281682b
SM		 9482};
9483
9484struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 9485 u8 reserved_at_0[0x8];
e281682b 9486 u8 local_port[0x8];
b4ff3a36 9487 u8 reserved_at_10[0x5];
e281682b 9488 u8 prio[0x3];
b4ff3a36 9489 u8 reserved_at_18[0x6];
e281682b
SM		 9490 u8 mode[0x2];
9491
b4ff3a36 9492 u8 reserved_at_20[0x20];
e281682b 9493
b4ff3a36 9494 u8 reserved_at_40[0x10];
e281682b
SM		 9495 u8 min_threshold[0x10];
9496
b4ff3a36 9497 u8 reserved_at_60[0x10];
e281682b
SM		 9498 u8 max_threshold[0x10];
9499
b4ff3a36 9500 u8 reserved_at_80[0x10];
e281682b
SM		 9501 u8 mark_probability_denominator[0x10];
9502
b4ff3a36 9503 u8 reserved_at_a0[0x60];
e281682b
SM		 9504};
9505
9506struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 9507 u8 reserved_at_0[0x8];
e281682b 9508 u8 local_port[0x8];
b4ff3a36 9509 u8 reserved_at_10[0x10];
e281682b 9510
b4ff3a36 9511 u8 reserved_at_20[0x60];
e281682b 9512
b4ff3a36 9513 u8 reserved_at_80[0x1c];
e281682b
SM		 9514 u8 wrps_admin[0x4];
9515
b4ff3a36 9516 u8 reserved_at_a0[0x1c];
e281682b
SM		 9517 u8 wrps_status[0x4];
9518
b4ff3a36 9519 u8 reserved_at_c0[0x8];
e281682b 9520 u8 up_threshold[0x8];
b4ff3a36 9521 u8 reserved_at_d0[0x8];
e281682b
SM		 9522 u8 down_threshold[0x8];
9523
b4ff3a36 9524 u8 reserved_at_e0[0x20];
e281682b 9525
b4ff3a36 9526 u8 reserved_at_100[0x1c];
e281682b
SM		 9527 u8 srps_admin[0x4];
9528
b4ff3a36 9529 u8 reserved_at_120[0x1c];
e281682b
SM		 9530 u8 srps_status[0x4];
9531
b4ff3a36 9532 u8 reserved_at_140[0x40];
e281682b
SM		 9533};
9534
9535struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 9536 u8 reserved_at_0[0x8];
e281682b 9537 u8 local_port[0x8];
b4ff3a36 9538 u8 reserved_at_10[0x10];
e281682b 9539
b4ff3a36 9540 u8 reserved_at_20[0x8];
e281682b 9541 u8 lb_cap[0x8];
b4ff3a36 9542 u8 reserved_at_30[0x8];
e281682b
SM		 9543 u8 lb_en[0x8];
9544};
9545
9546struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 9547 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 9548 u8 local_port[0x8];
9549 u8 reserved_at_10[0x10];
e281682b 9550
4b5b9c7d 9551 u8 reserved_at_20[0x20];
e281682b 9552
4b5b9c7d
SA		 9553 u8 port_profile_mode[0x8];
9554 u8 static_port_profile[0x8];
9555 u8 active_port_profile[0x8];
9556 u8 reserved_at_58[0x8];
e281682b 9557
4b5b9c7d
SA		 9558 u8 retransmission_active[0x8];
9559 u8 fec_mode_active[0x18];
e281682b 9560
4b5b9c7d
SA		 9561 u8 rs_fec_correction_bypass_cap[0x4];
9562 u8 reserved_at_84[0x8];
9563 u8 fec_override_cap_56g[0x4];
9564 u8 fec_override_cap_100g[0x4];
9565 u8 fec_override_cap_50g[0x4];
9566 u8 fec_override_cap_25g[0x4];
9567 u8 fec_override_cap_10g_40g[0x4];
9568
9569 u8 rs_fec_correction_bypass_admin[0x4];
9570 u8 reserved_at_a4[0x8];
9571 u8 fec_override_admin_56g[0x4];
9572 u8 fec_override_admin_100g[0x4];
9573 u8 fec_override_admin_50g[0x4];
9574 u8 fec_override_admin_25g[0x4];
9575 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 9576
9577 u8 fec_override_cap_400g_8x[0x10];
9578 u8 fec_override_cap_200g_4x[0x10];
9579
9580 u8 fec_override_cap_100g_2x[0x10];
9581 u8 fec_override_cap_50g_1x[0x10];
9582
9583 u8 fec_override_admin_400g_8x[0x10];
9584 u8 fec_override_admin_200g_4x[0x10];
9585
9586 u8 fec_override_admin_100g_2x[0x10];
9587 u8 fec_override_admin_50g_1x[0x10];
ce28f0fd
AL		 9588
9589 u8 reserved_at_140[0x140];
e281682b
SM		 9590};
9591
9592struct mlx5_ifc_ppcnt_reg_bits {
9593 u8 swid[0x8];
9594 u8 local_port[0x8];
9595 u8 pnat[0x2];
b4ff3a36 9596 u8 reserved_at_12[0x8];
e281682b
SM		 9597 u8 grp[0x6];
9598
9599 u8 clr[0x1];
b4ff3a36 9600 u8 reserved_at_21[0x1c];
e281682b
SM		 9601 u8 prio_tc[0x3];
9602
9603 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9604};
9605
4039049b
AL		 9606struct mlx5_ifc_mpein_reg_bits {
9607 u8 reserved_at_0[0x2];
9608 u8 depth[0x6];
9609 u8 pcie_index[0x8];
9610 u8 node[0x8];
9611 u8 reserved_at_18[0x8];
9612
9613 u8 capability_mask[0x20];
9614
9615 u8 reserved_at_40[0x8];
9616 u8 link_width_enabled[0x8];
9617 u8 link_speed_enabled[0x10];
9618
9619 u8 lane0_physical_position[0x8];
9620 u8 link_width_active[0x8];
9621 u8 link_speed_active[0x10];
9622
9623 u8 num_of_pfs[0x10];
9624 u8 num_of_vfs[0x10];
9625
9626 u8 bdf0[0x10];
9627 u8 reserved_at_b0[0x10];
9628
9629 u8 max_read_request_size[0x4];
9630 u8 max_payload_size[0x4];
9631 u8 reserved_at_c8[0x5];
9632 u8 pwr_status[0x3];
9633 u8 port_type[0x4];
9634 u8 reserved_at_d4[0xb];
9635 u8 lane_reversal[0x1];
9636
9637 u8 reserved_at_e0[0x14];
9638 u8 pci_power[0xc];
9639
9640 u8 reserved_at_100[0x20];
9641
9642 u8 device_status[0x10];
9643 u8 port_state[0x8];
9644 u8 reserved_at_138[0x8];
9645
9646 u8 reserved_at_140[0x10];
9647 u8 receiver_detect_result[0x10];
9648
9649 u8 reserved_at_160[0x20];
9650};
9651
8ed1a630
GP		 9652struct mlx5_ifc_mpcnt_reg_bits {
9653 u8 reserved_at_0[0x8];
9654 u8 pcie_index[0x8];
9655 u8 reserved_at_10[0xa];
9656 u8 grp[0x6];
9657
9658 u8 clr[0x1];
9659 u8 reserved_at_21[0x1f];
9660
9661 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9662};
9663
e281682b 9664struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 9665 u8 reserved_at_0[0x3];
e281682b 9666 u8 single_mac[0x1];
b4ff3a36 9667 u8 reserved_at_4[0x4];
e281682b
SM		 9668 u8 local_port[0x8];
9669 u8 mac_47_32[0x10];
9670
9671 u8 mac_31_0[0x20];
9672
b4ff3a36 9673 u8 reserved_at_40[0x40];
e281682b
SM		 9674};
9675
9676struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 9677 u8 reserved_at_0[0x8];
e281682b 9678 u8 local_port[0x8];
b4ff3a36 9679 u8 reserved_at_10[0x10];
e281682b
SM		 9680
9681 u8 max_mtu[0x10];
b4ff3a36 9682 u8 reserved_at_30[0x10];
e281682b
SM		 9683
9684 u8 admin_mtu[0x10];
b4ff3a36 9685 u8 reserved_at_50[0x10];
e281682b
SM		 9686
9687 u8 oper_mtu[0x10];
b4ff3a36 9688 u8 reserved_at_70[0x10];
e281682b
SM		 9689};
9690
9691struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 9692 u8 reserved_at_0[0x8];
e281682b 9693 u8 module[0x8];
b4ff3a36 9694 u8 reserved_at_10[0x10];
e281682b 9695
b4ff3a36 9696 u8 reserved_at_20[0x18];
e281682b
SM		 9697 u8 attenuation_5g[0x8];
9698
b4ff3a36 9699 u8 reserved_at_40[0x18];
e281682b
SM		 9700 u8 attenuation_7g[0x8];
9701
b4ff3a36 9702 u8 reserved_at_60[0x18];
e281682b
SM		 9703 u8 attenuation_12g[0x8];
9704};
9705
9706struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 9707 u8 reserved_at_0[0x8];
e281682b 9708 u8 module[0x8];
b4ff3a36 9709 u8 reserved_at_10[0xc];
e281682b
SM		 9710 u8 module_status[0x4];
9711
b4ff3a36 9712 u8 reserved_at_20[0x60];
e281682b
SM		 9713};
9714
9715struct mlx5_ifc_pmpc_reg_bits {
9716 u8 module_state_updated[32][0x8];
9717};
9718
9719struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 9720 u8 reserved_at_0[0x4];
e281682b
SM		 9721 u8 mlpn_status[0x4];
9722 u8 local_port[0x8];
b4ff3a36 9723 u8 reserved_at_10[0x10];
e281682b
SM		 9724
9725 u8 e[0x1];
b4ff3a36 9726 u8 reserved_at_21[0x1f];
e281682b
SM		 9727};
9728
9729struct mlx5_ifc_pmlp_reg_bits {
9730 u8 rxtx[0x1];
b4ff3a36 9731 u8 reserved_at_1[0x7];
e281682b 9732 u8 local_port[0x8];
b4ff3a36 9733 u8 reserved_at_10[0x8];
e281682b
SM		 9734 u8 width[0x8];
9735
9736 u8 lane0_module_mapping[0x20];
9737
9738 u8 lane1_module_mapping[0x20];
9739
9740 u8 lane2_module_mapping[0x20];
9741
9742 u8 lane3_module_mapping[0x20];
9743
b4ff3a36 9744 u8 reserved_at_a0[0x160];
e281682b
SM		 9745};
9746
9747struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 9748 u8 reserved_at_0[0x8];
e281682b 9749 u8 module[0x8];
b4ff3a36 9750 u8 reserved_at_10[0x4];
e281682b 9751 u8 admin_status[0x4];
b4ff3a36 9752 u8 reserved_at_18[0x4];
e281682b
SM		 9753 u8 oper_status[0x4];
9754
9755 u8 ase[0x1];
9756 u8 ee[0x1];
b4ff3a36 9757 u8 reserved_at_22[0x1c];
e281682b
SM		 9758 u8 e[0x2];
9759
b4ff3a36 9760 u8 reserved_at_40[0x40];
e281682b
SM		 9761};
9762
9763struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 9764 u8 reserved_at_0[0x4];
e281682b 9765 u8 profile_id[0xc];
b4ff3a36 9766 u8 reserved_at_10[0x4];
e281682b 9767 u8 proto_mask[0x4];
b4ff3a36 9768 u8 reserved_at_18[0x8];
e281682b 9769
b4ff3a36 9770 u8 reserved_at_20[0x10];
e281682b
SM		 9771 u8 lane_speed[0x10];
9772
b4ff3a36 9773 u8 reserved_at_40[0x17];
e281682b
SM		 9774 u8 lpbf[0x1];
9775 u8 fec_mode_policy[0x8];
9776
9777 u8 retransmission_capability[0x8];
9778 u8 fec_mode_capability[0x18];
9779
9780 u8 retransmission_support_admin[0x8];
9781 u8 fec_mode_support_admin[0x18];
9782
9783 u8 retransmission_request_admin[0x8];
9784 u8 fec_mode_request_admin[0x18];
9785
b4ff3a36 9786 u8 reserved_at_c0[0x80];
e281682b
SM		 9787};
9788
9789struct mlx5_ifc_plib_reg_bits {
b4ff3a36 9790 u8 reserved_at_0[0x8];
e281682b 9791 u8 local_port[0x8];
b4ff3a36 9792 u8 reserved_at_10[0x8];
e281682b
SM		 9793 u8 ib_port[0x8];
9794
b4ff3a36 9795 u8 reserved_at_20[0x60];
e281682b
SM		 9796};
9797
9798struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 9799 u8 reserved_at_0[0x8];
e281682b 9800 u8 local_port[0x8];
b4ff3a36 9801 u8 reserved_at_10[0xd];
e281682b
SM		 9802 u8 lbf_mode[0x3];
9803
b4ff3a36 9804 u8 reserved_at_20[0x20];
e281682b
SM		 9805};
9806
9807struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 9808 u8 reserved_at_0[0x8];
e281682b 9809 u8 local_port[0x8];
b4ff3a36 9810 u8 reserved_at_10[0x10];
e281682b
SM		 9811
9812 u8 dic[0x1];
b4ff3a36 9813 u8 reserved_at_21[0x19];
e281682b 9814 u8 ipg[0x4];
b4ff3a36 9815 u8 reserved_at_3e[0x2];
e281682b
SM		 9816};
9817
9818struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 9819 u8 reserved_at_0[0x8];
e281682b 9820 u8 local_port[0x8];
b4ff3a36 9821 u8 reserved_at_10[0x10];
e281682b 9822
b4ff3a36 9823 u8 reserved_at_20[0xe0];
e281682b
SM		 9824
9825 u8 port_filter[8][0x20];
9826
9827 u8 port_filter_update_en[8][0x20];
9828};
9829
9830struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9831 u8 reserved_at_0[0x8];
e281682b 9832 u8 local_port[0x8];
2afa609f
IK		 9833 u8 reserved_at_10[0xb];
9834 u8 ppan_mask_n[0x1];
9835 u8 minor_stall_mask[0x1];
9836 u8 critical_stall_mask[0x1];
9837 u8 reserved_at_1e[0x2];
e281682b
SM		 9838
9839 u8 ppan[0x4];
b4ff3a36 9840 u8 reserved_at_24[0x4];
e281682b 9841 u8 prio_mask_tx[0x8];
b4ff3a36 9842 u8 reserved_at_30[0x8];
e281682b
SM		 9843 u8 prio_mask_rx[0x8];
9844
9845 u8 pptx[0x1];
9846 u8 aptx[0x1];
2afa609f
IK		 9847 u8 pptx_mask_n[0x1];
9848 u8 reserved_at_43[0x5];
e281682b 9849 u8 pfctx[0x8];
b4ff3a36 9850 u8 reserved_at_50[0x10];
e281682b
SM		 9851
9852 u8 pprx[0x1];
9853 u8 aprx[0x1];
2afa609f
IK		 9854 u8 pprx_mask_n[0x1];
9855 u8 reserved_at_63[0x5];
e281682b 9856 u8 pfcrx[0x8];
b4ff3a36 9857 u8 reserved_at_70[0x10];
e281682b 9858
2afa609f
IK		 9859 u8 device_stall_minor_watermark[0x10];
9860 u8 device_stall_critical_watermark[0x10];
9861
9862 u8 reserved_at_a0[0x60];
e281682b
SM		 9863};
9864
9865struct mlx5_ifc_pelc_reg_bits {
9866 u8 op[0x4];
b4ff3a36 9867 u8 reserved_at_4[0x4];
e281682b 9868 u8 local_port[0x8];
b4ff3a36 9869 u8 reserved_at_10[0x10];
e281682b
SM		 9870
9871 u8 op_admin[0x8];
9872 u8 op_capability[0x8];
9873 u8 op_request[0x8];
9874 u8 op_active[0x8];
9875
9876 u8 admin[0x40];
9877
9878 u8 capability[0x40];
9879
9880 u8 request[0x40];
9881
9882 u8 active[0x40];
9883
b4ff3a36 9884 u8 reserved_at_140[0x80];
e281682b
SM		 9885};
9886
9887struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9888 u8 reserved_at_0[0x8];
e281682b 9889 u8 local_port[0x8];
b4ff3a36 9890 u8 reserved_at_10[0x10];
e281682b 9891
b4ff3a36 9892 u8 reserved_at_20[0xc];
e281682b 9893 u8 error_count[0x4];
b4ff3a36 9894 u8 reserved_at_30[0x10];
e281682b 9895
b4ff3a36 9896 u8 reserved_at_40[0xc];
e281682b 9897 u8 lane[0x4];
b4ff3a36 9898 u8 reserved_at_50[0x8];
e281682b
SM		 9899 u8 error_type[0x8];
9900};
9901
5e022dd3
EBE		 9902struct mlx5_ifc_mpegc_reg_bits {
9903 u8 reserved_at_0[0x30];
9904 u8 field_select[0x10];
9905
9906 u8 tx_overflow_sense[0x1];
9907 u8 mark_cqe[0x1];
9908 u8 mark_cnp[0x1];
9909 u8 reserved_at_43[0x1b];
9910 u8 tx_lossy_overflow_oper[0x2];
9911
9912 u8 reserved_at_60[0x100];
9913};
9914
ae02d415
EBE		 9915enum {
9916 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9917 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9918 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9919};
9920
9921struct mlx5_ifc_mtutc_reg_bits {
9922 u8 reserved_at_0[0x1c];
9923 u8 operation[0x4];
9924
9925 u8 freq_adjustment[0x20];
9926
9927 u8 reserved_at_40[0x40];
9928
9929 u8 utc_sec[0x20];
9930
9931 u8 reserved_at_a0[0x2];
9932 u8 utc_nsec[0x1e];
9933
9934 u8 time_adjustment[0x20];
9935};
9936
cfdcbcea 9937struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9938 u8 reserved_at_0[0x68];
9939 u8 fec_50G_per_lane_in_pplm[0x1];
9940 u8 reserved_at_69[0x4];
0af5107c 9941 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9942 u8 reserved_at_6e[0x4];
9943 u8 ptys_extended_ethernet[0x1];
9944 u8 reserved_at_73[0x3];
2fcb12df 9945 u8 pfcc_mask[0x1];
67daf118
SA		 9946 u8 reserved_at_77[0x3];
9947 u8 per_lane_error_counters[0x1];
2dba0797 9948 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9949 u8 ptys_connector_type[0x1];
9950 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9951 u8 ppcnt_discard_group[0x1];
9952 u8 ppcnt_statistical_group[0x1];
9953};
9954
df5f1361
HN		 9955struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9956 u8 port_access_reg_cap_mask_127_to_96[0x20];
9957 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9958
9959 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9960 u8 pplm[0x1];
9961 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9962
9963 u8 port_access_reg_cap_mask_31_to_13[0x13];
9964 u8 pbmc[0x1];
9965 u8 pptb[0x1];
75370eb0
ED		 9966 u8 port_access_reg_cap_mask_10_to_09[0x2];
9967 u8 ppcnt[0x1];
9968 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9969};
9970
cfdcbcea
GP		 9971struct mlx5_ifc_pcam_reg_bits {
9972 u8 reserved_at_0[0x8];
9973 u8 feature_group[0x8];
9974 u8 reserved_at_10[0x8];
9975 u8 access_reg_group[0x8];
9976
9977 u8 reserved_at_20[0x20];
9978
9979 union {
df5f1361 9980 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9981 u8 reserved_at_0[0x80];
9982 } port_access_reg_cap_mask;
9983
9984 u8 reserved_at_c0[0x80];
9985
9986 union {
9987 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9988 u8 reserved_at_0[0x80];
9989 } feature_cap_mask;
9990
9991 u8 reserved_at_1c0[0xc0];
9992};
9993
9994struct mlx5_ifc_mcam_enhanced_features_bits {
271907ee
GP		 9995 u8 reserved_at_0[0x5d];
9996 u8 mcia_32dwords[0x1];
976a859c
AL		 9997 u8 out_pulse_duration_ns[0x1];
9998 u8 npps_period[0x1];
9999 u8 reserved_at_60[0xa];
72fb3b60 10000 u8 reset_state[0x1];
ae02d415
EBE		 10001 u8 ptpcyc2realtime_modify[0x1];
10002 u8 reserved_at_6c[0x2];
4039049b
AL		 10003 u8 pci_status_and_power[0x1];
10004 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 10005 u8 mark_tx_action_cnp[0x1];
10006 u8 mark_tx_action_cqe[0x1];
10007 u8 dynamic_tx_overflow[0x1];
10008 u8 reserved_at_77[0x4];
5405fa26 10009 u8 pcie_outbound_stalled[0x1];
efae7f78 10010 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 10011 u8 mtpps_enh_out_per_adj[0x1];
10012 u8 mtpps_fs[0x1];
cfdcbcea
GP		 10013 u8 pcie_performance_group[0x1];
10014};
10015
0ab87743
OG		 10016struct mlx5_ifc_mcam_access_reg_bits {
10017 u8 reserved_at_0[0x1c];
10018 u8 mcda[0x1];
10019 u8 mcc[0x1];
10020 u8 mcqi[0x1];
a82e0b5b 10021 u8 mcqs[0x1];
0ab87743 10022
5e022dd3
EBE		 10023 u8 regs_95_to_87[0x9];
10024 u8 mpegc[0x1];
ae02d415
EBE		 10025 u8 mtutc[0x1];
10026 u8 regs_84_to_68[0x11];
eff8ea8f
FD		 10027 u8 tracer_registers[0x4];
10028
502e82b9
AL		 10029 u8 regs_63_to_46[0x12];
10030 u8 mrtc[0x1];
10031 u8 regs_44_to_32[0xd];
10032
0ab87743
OG		 10033 u8 regs_31_to_0[0x20];
10034};
10035
f397464e
EBE		 10036struct mlx5_ifc_mcam_access_reg_bits1 {
10037 u8 regs_127_to_96[0x20];
10038
10039 u8 regs_95_to_64[0x20];
10040
10041 u8 regs_63_to_32[0x20];
10042
10043 u8 regs_31_to_0[0x20];
10044};
10045
10046struct mlx5_ifc_mcam_access_reg_bits2 {
10047 u8 regs_127_to_99[0x1d];
10048 u8 mirc[0x1];
10049 u8 regs_97_to_96[0x2];
10050
10051 u8 regs_95_to_64[0x20];
10052
10053 u8 regs_63_to_32[0x20];
10054
10055 u8 regs_31_to_0[0x20];
10056};
10057
cfdcbcea
GP		 10058struct mlx5_ifc_mcam_reg_bits {
10059 u8 reserved_at_0[0x8];
10060 u8 feature_group[0x8];
10061 u8 reserved_at_10[0x8];
10062 u8 access_reg_group[0x8];
10063
10064 u8 reserved_at_20[0x20];
10065
10066 union {
0ab87743 10067 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 10068 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10069 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 10070 u8 reserved_at_0[0x80];
10071 } mng_access_reg_cap_mask;
10072
10073 u8 reserved_at_c0[0x80];
10074
10075 union {
10076 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10077 u8 reserved_at_0[0x80];
10078 } mng_feature_cap_mask;
10079
10080 u8 reserved_at_1c0[0x80];
10081};
10082
c02762eb
HN		 10083struct mlx5_ifc_qcam_access_reg_cap_mask {
10084 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
10085 u8 qpdpm[0x1];
10086 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
10087 u8 qdpm[0x1];
10088 u8 qpts[0x1];
10089 u8 qcap[0x1];
10090 u8 qcam_access_reg_cap_mask_0[0x1];
10091};
10092
10093struct mlx5_ifc_qcam_qos_feature_cap_mask {
10094 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
10095 u8 qpts_trust_both[0x1];
10096};
10097
10098struct mlx5_ifc_qcam_reg_bits {
10099 u8 reserved_at_0[0x8];
10100 u8 feature_group[0x8];
10101 u8 reserved_at_10[0x8];
10102 u8 access_reg_group[0x8];
10103 u8 reserved_at_20[0x20];
10104
10105 union {
10106 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10107 u8 reserved_at_0[0x80];
10108 } qos_access_reg_cap_mask;
10109
10110 u8 reserved_at_c0[0x80];
10111
10112 union {
10113 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10114 u8 reserved_at_0[0x80];
10115 } qos_feature_cap_mask;
10116
10117 u8 reserved_at_1c0[0x80];
10118};
10119
0b9055a1
MS		 10120struct mlx5_ifc_core_dump_reg_bits {
10121 u8 reserved_at_0[0x18];
10122 u8 core_dump_type[0x8];
10123
10124 u8 reserved_at_20[0x30];
10125 u8 vhca_id[0x10];
10126
10127 u8 reserved_at_60[0x8];
10128 u8 qpn[0x18];
10129 u8 reserved_at_80[0x180];
10130};
10131
e281682b 10132struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 10133 u8 reserved_at_0[0x8];
e281682b 10134 u8 local_port[0x8];
b4ff3a36 10135 u8 reserved_at_10[0x10];
e281682b
SM		 10136
10137 u8 port_capability_mask[4][0x20];
10138};
10139
10140struct mlx5_ifc_paos_reg_bits {
10141 u8 swid[0x8];
10142 u8 local_port[0x8];
b4ff3a36 10143 u8 reserved_at_10[0x4];
e281682b 10144 u8 admin_status[0x4];
b4ff3a36 10145 u8 reserved_at_18[0x4];
e281682b
SM		 10146 u8 oper_status[0x4];
10147
10148 u8 ase[0x1];
10149 u8 ee[0x1];
b4ff3a36 10150 u8 reserved_at_22[0x1c];
e281682b
SM		 10151 u8 e[0x2];
10152
b4ff3a36 10153 u8 reserved_at_40[0x40];
e281682b
SM		 10154};
10155
10156struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 10157 u8 reserved_at_0[0x8];
e281682b 10158 u8 opamp_group[0x8];
b4ff3a36 10159 u8 reserved_at_10[0xc];
e281682b
SM		 10160 u8 opamp_group_type[0x4];
10161
10162 u8 start_index[0x10];
b4ff3a36 10163 u8 reserved_at_30[0x4];
e281682b
SM		 10164 u8 num_of_indices[0xc];
10165
10166 u8 index_data[18][0x10];
10167};
10168
7d5e1423
SM		 10169struct mlx5_ifc_pcmr_reg_bits {
10170 u8 reserved_at_0[0x8];
10171 u8 local_port[0x8];
0dcaafc0 10172 u8 reserved_at_10[0x10];
0bc73ad4 10173
0dcaafc0
EB		 10174 u8 entropy_force_cap[0x1];
10175 u8 entropy_calc_cap[0x1];
10176 u8 entropy_gre_calc_cap[0x1];
0bc73ad4
AL		 10177 u8 reserved_at_23[0xf];
10178 u8 rx_ts_over_crc_cap[0x1];
10179 u8 reserved_at_33[0xb];
7d5e1423 10180 u8 fcs_cap[0x1];
0dcaafc0 10181 u8 reserved_at_3f[0x1];
0bc73ad4 10182
0dcaafc0
EB		 10183 u8 entropy_force[0x1];
10184 u8 entropy_calc[0x1];
10185 u8 entropy_gre_calc[0x1];
0bc73ad4
AL		 10186 u8 reserved_at_43[0xf];
10187 u8 rx_ts_over_crc[0x1];
10188 u8 reserved_at_53[0xb];
7d5e1423
SM		 10189 u8 fcs_chk[0x1];
10190 u8 reserved_at_5f[0x1];
10191};
10192
e281682b 10193struct mlx5_ifc_lane_2_module_mapping_bits {
fcb610a8
GP		 10194 u8 reserved_at_0[0x4];
10195 u8 rx_lane[0x4];
10196 u8 reserved_at_8[0x4];
10197 u8 tx_lane[0x4];
b4ff3a36 10198 u8 reserved_at_10[0x8];
e281682b
SM		 10199 u8 module[0x8];
10200};
10201
10202struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 10203 u8 reserved_at_0[0x6];
e281682b
SM		 10204 u8 lossy[0x1];
10205 u8 epsb[0x1];
ac77998b
MK		 10206 u8 reserved_at_8[0x8];
10207 u8 size[0x10];
e281682b
SM		 10208
10209 u8 xoff_threshold[0x10];
10210 u8 xon_threshold[0x10];
10211};
10212
10213struct mlx5_ifc_set_node_in_bits {
10214 u8 node_description[64][0x8];
10215};
10216
10217struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 10218 u8 reserved_at_0[0x18];
e281682b
SM		 10219 u8 power_settings_level[0x8];
10220
b4ff3a36 10221 u8 reserved_at_20[0x60];
e281682b
SM		 10222};
10223
10224struct mlx5_ifc_register_host_endianness_bits {
10225 u8 he[0x1];
b4ff3a36 10226 u8 reserved_at_1[0x1f];
e281682b 10227
b4ff3a36 10228 u8 reserved_at_20[0x60];
e281682b
SM		 10229};
10230
10231struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 10232 u8 reserved_at_0[0x20];
e281682b
SM		 10233
10234 u8 mkey[0x20];
10235
10236 u8 addressh_63_32[0x20];
10237
10238 u8 addressl_31_0[0x20];
10239};
10240
10241struct mlx5_ifc_ud_adrs_vector_bits {
10242 u8 dc_key[0x40];
10243
10244 u8 ext[0x1];
b4ff3a36 10245 u8 reserved_at_41[0x7];
e281682b
SM		 10246 u8 destination_qp_dct[0x18];
10247
10248 u8 static_rate[0x4];
10249 u8 sl_eth_prio[0x4];
10250 u8 fl[0x1];
10251 u8 mlid[0x7];
10252 u8 rlid_udp_sport[0x10];
10253
b4ff3a36 10254 u8 reserved_at_80[0x20];
e281682b
SM		 10255
10256 u8 rmac_47_16[0x20];
10257
10258 u8 rmac_15_0[0x10];
10259 u8 tclass[0x8];
10260 u8 hop_limit[0x8];
10261
b4ff3a36 10262 u8 reserved_at_e0[0x1];
e281682b 10263 u8 grh[0x1];
b4ff3a36 10264 u8 reserved_at_e2[0x2];
e281682b
SM		 10265 u8 src_addr_index[0x8];
10266 u8 flow_label[0x14];
10267
10268 u8 rgid_rip[16][0x8];
10269};
10270
10271struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 10272 u8 reserved_at_0[0x10];
e281682b
SM		 10273 u8 function_id[0x10];
10274
10275 u8 num_pages[0x20];
10276
b4ff3a36 10277 u8 reserved_at_40[0xa0];
e281682b
SM		 10278};
10279
10280struct mlx5_ifc_eqe_bits {
b4ff3a36 10281 u8 reserved_at_0[0x8];
e281682b 10282 u8 event_type[0x8];
b4ff3a36 10283 u8 reserved_at_10[0x8];
e281682b
SM		 10284 u8 event_sub_type[0x8];
10285
b4ff3a36 10286 u8 reserved_at_20[0xe0];
e281682b
SM		 10287
10288 union mlx5_ifc_event_auto_bits event_data;
10289
b4ff3a36 10290 u8 reserved_at_1e0[0x10];
e281682b 10291 u8 signature[0x8];
b4ff3a36 10292 u8 reserved_at_1f8[0x7];
e281682b
SM		 10293 u8 owner[0x1];
10294};
10295
10296enum {
10297 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10298};
10299
10300struct mlx5_ifc_cmd_queue_entry_bits {
10301 u8 type[0x8];
b4ff3a36 10302 u8 reserved_at_8[0x18];
e281682b
SM		 10303
10304 u8 input_length[0x20];
10305
10306 u8 input_mailbox_pointer_63_32[0x20];
10307
10308 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 10309 u8 reserved_at_77[0x9];
e281682b
SM		 10310
10311 u8 command_input_inline_data[16][0x8];
10312
10313 u8 command_output_inline_data[16][0x8];
10314
10315 u8 output_mailbox_pointer_63_32[0x20];
10316
10317 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 10318 u8 reserved_at_1b7[0x9];
e281682b
SM		 10319
10320 u8 output_length[0x20];
10321
10322 u8 token[0x8];
10323 u8 signature[0x8];
b4ff3a36 10324 u8 reserved_at_1f0[0x8];
e281682b
SM		 10325 u8 status[0x7];
10326 u8 ownership[0x1];
10327};
10328
10329struct mlx5_ifc_cmd_out_bits {
10330 u8 status[0x8];
b4ff3a36 10331 u8 reserved_at_8[0x18];
e281682b
SM		 10332
10333 u8 syndrome[0x20];
10334
10335 u8 command_output[0x20];
10336};
10337
10338struct mlx5_ifc_cmd_in_bits {
10339 u8 opcode[0x10];
b4ff3a36 10340 u8 reserved_at_10[0x10];
e281682b 10341
b4ff3a36 10342 u8 reserved_at_20[0x10];
e281682b
SM		 10343 u8 op_mod[0x10];
10344
b6ca09cb 10345 u8 command[][0x20];
e281682b
SM		 10346};
10347
10348struct mlx5_ifc_cmd_if_box_bits {
10349 u8 mailbox_data[512][0x8];
10350
b4ff3a36 10351 u8 reserved_at_1000[0x180];
e281682b
SM		 10352
10353 u8 next_pointer_63_32[0x20];
10354
10355 u8 next_pointer_31_10[0x16];
b4ff3a36 10356 u8 reserved_at_11b6[0xa];
e281682b
SM		 10357
10358 u8 block_number[0x20];
10359
b4ff3a36 10360 u8 reserved_at_11e0[0x8];
e281682b
SM		 10361 u8 token[0x8];
10362 u8 ctrl_signature[0x8];
10363 u8 signature[0x8];
10364};
10365
10366struct mlx5_ifc_mtt_bits {
10367 u8 ptag_63_32[0x20];
10368
10369 u8 ptag_31_8[0x18];
b4ff3a36 10370 u8 reserved_at_38[0x6];
e281682b
SM		 10371 u8 wr_en[0x1];
10372 u8 rd_en[0x1];
10373};
10374
928cfe87
TT		 10375struct mlx5_ifc_query_wol_rol_out_bits {
10376 u8 status[0x8];
10377 u8 reserved_at_8[0x18];
10378
10379 u8 syndrome[0x20];
10380
10381 u8 reserved_at_40[0x10];
10382 u8 rol_mode[0x8];
10383 u8 wol_mode[0x8];
10384
10385 u8 reserved_at_60[0x20];
10386};
10387
10388struct mlx5_ifc_query_wol_rol_in_bits {
10389 u8 opcode[0x10];
10390 u8 reserved_at_10[0x10];
10391
10392 u8 reserved_at_20[0x10];
10393 u8 op_mod[0x10];
10394
10395 u8 reserved_at_40[0x40];
10396};
10397
10398struct mlx5_ifc_set_wol_rol_out_bits {
10399 u8 status[0x8];
10400 u8 reserved_at_8[0x18];
10401
10402 u8 syndrome[0x20];
10403
10404 u8 reserved_at_40[0x40];
10405};
10406
10407struct mlx5_ifc_set_wol_rol_in_bits {
10408 u8 opcode[0x10];
10409 u8 reserved_at_10[0x10];
10410
10411 u8 reserved_at_20[0x10];
10412 u8 op_mod[0x10];
10413
10414 u8 rol_mode_valid[0x1];
10415 u8 wol_mode_valid[0x1];
10416 u8 reserved_at_42[0xe];
10417 u8 rol_mode[0x8];
10418 u8 wol_mode[0x8];
10419
10420 u8 reserved_at_60[0x20];
10421};
10422
e281682b
SM		 10423enum {
10424 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10425 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10426 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10427};
10428
10429enum {
10430 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10431 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10432 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10433};
10434
10435enum {
10436 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10437 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10438 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10439 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10440 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10441 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10442 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10443 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10444 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10445 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10446 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10447};
10448
10449struct mlx5_ifc_initial_seg_bits {
10450 u8 fw_rev_minor[0x10];
10451 u8 fw_rev_major[0x10];
10452
10453 u8 cmd_interface_rev[0x10];
10454 u8 fw_rev_subminor[0x10];
10455
b4ff3a36 10456 u8 reserved_at_40[0x40];
e281682b
SM		 10457
10458 u8 cmdq_phy_addr_63_32[0x20];
10459
10460 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 10461 u8 reserved_at_b4[0x2];
e281682b
SM		 10462 u8 nic_interface[0x2];
10463 u8 log_cmdq_size[0x4];
10464 u8 log_cmdq_stride[0x4];
10465
10466 u8 command_doorbell_vector[0x20];
10467
b4ff3a36 10468 u8 reserved_at_e0[0xf00];
e281682b
SM		 10469
10470 u8 initializing[0x1];
b4ff3a36 10471 u8 reserved_at_fe1[0x4];
e281682b 10472 u8 nic_interface_supported[0x3];
591905ba
BW		 10473 u8 embedded_cpu[0x1];
10474 u8 reserved_at_fe9[0x17];
e281682b
SM		 10475
10476 struct mlx5_ifc_health_buffer_bits health_buffer;
10477
10478 u8 no_dram_nic_offset[0x20];
10479
b4ff3a36 10480 u8 reserved_at_1220[0x6e40];
e281682b 10481
b4ff3a36 10482 u8 reserved_at_8060[0x1f];
e281682b
SM		 10483 u8 clear_int[0x1];
10484
10485 u8 health_syndrome[0x8];
10486 u8 health_counter[0x18];
10487
b4ff3a36 10488 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 10489};
10490
f9a1ef72
EE		 10491struct mlx5_ifc_mtpps_reg_bits {
10492 u8 reserved_at_0[0xc];
10493 u8 cap_number_of_pps_pins[0x4];
10494 u8 reserved_at_10[0x4];
10495 u8 cap_max_num_of_pps_in_pins[0x4];
10496 u8 reserved_at_18[0x4];
10497 u8 cap_max_num_of_pps_out_pins[0x4];
10498
976a859c
AL		 10499 u8 reserved_at_20[0x13];
10500 u8 cap_log_min_npps_period[0x5];
10501 u8 reserved_at_38[0x3];
10502 u8 cap_log_min_out_pulse_duration_ns[0x5];
10503
10504 u8 reserved_at_40[0x4];
f9a1ef72
EE		 10505 u8 cap_pin_3_mode[0x4];
10506 u8 reserved_at_48[0x4];
10507 u8 cap_pin_2_mode[0x4];
10508 u8 reserved_at_50[0x4];
10509 u8 cap_pin_1_mode[0x4];
10510 u8 reserved_at_58[0x4];
10511 u8 cap_pin_0_mode[0x4];
10512
10513 u8 reserved_at_60[0x4];
10514 u8 cap_pin_7_mode[0x4];
10515 u8 reserved_at_68[0x4];
10516 u8 cap_pin_6_mode[0x4];
10517 u8 reserved_at_70[0x4];
10518 u8 cap_pin_5_mode[0x4];
10519 u8 reserved_at_78[0x4];
10520 u8 cap_pin_4_mode[0x4];
10521
fa367688 10522 u8 field_select[0x20];
976a859c
AL		 10523 u8 reserved_at_a0[0x20];
10524
10525 u8 npps_period[0x40];
f9a1ef72
EE		 10526
10527 u8 enable[0x1];
10528 u8 reserved_at_101[0xb];
10529 u8 pattern[0x4];
10530 u8 reserved_at_110[0x4];
10531 u8 pin_mode[0x4];
10532 u8 pin[0x8];
10533
976a859c
AL		 10534 u8 reserved_at_120[0x2];
10535 u8 out_pulse_duration_ns[0x1e];
f9a1ef72
EE		 10536
10537 u8 time_stamp[0x40];
10538
10539 u8 out_pulse_duration[0x10];
10540 u8 out_periodic_adjustment[0x10];
fa367688 10541 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 10542
fa367688 10543 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 10544};
10545
10546struct mlx5_ifc_mtppse_reg_bits {
10547 u8 reserved_at_0[0x18];
10548 u8 pin[0x8];
10549 u8 event_arm[0x1];
10550 u8 reserved_at_21[0x1b];
10551 u8 event_generation_mode[0x4];
10552 u8 reserved_at_40[0x40];
10553};
10554
a82e0b5b
SA		 10555struct mlx5_ifc_mcqs_reg_bits {
10556 u8 last_index_flag[0x1];
10557 u8 reserved_at_1[0x7];
10558 u8 fw_device[0x8];
10559 u8 component_index[0x10];
10560
10561 u8 reserved_at_20[0x10];
10562 u8 identifier[0x10];
10563
10564 u8 reserved_at_40[0x17];
10565 u8 component_status[0x5];
10566 u8 component_update_state[0x4];
10567
10568 u8 last_update_state_changer_type[0x4];
10569 u8 last_update_state_changer_host_id[0x4];
10570 u8 reserved_at_68[0x18];
10571};
10572
47176289
OG		 10573struct mlx5_ifc_mcqi_cap_bits {
10574 u8 supported_info_bitmask[0x20];
10575
10576 u8 component_size[0x20];
10577
10578 u8 max_component_size[0x20];
10579
10580 u8 log_mcda_word_size[0x4];
10581 u8 reserved_at_64[0xc];
10582 u8 mcda_max_write_size[0x10];
10583
10584 u8 rd_en[0x1];
10585 u8 reserved_at_81[0x1];
10586 u8 match_chip_id[0x1];
10587 u8 match_psid[0x1];
10588 u8 check_user_timestamp[0x1];
10589 u8 match_base_guid_mac[0x1];
10590 u8 reserved_at_86[0x1a];
10591};
10592
a82e0b5b
SA		 10593struct mlx5_ifc_mcqi_version_bits {
10594 u8 reserved_at_0[0x2];
10595 u8 build_time_valid[0x1];
10596 u8 user_defined_time_valid[0x1];
10597 u8 reserved_at_4[0x14];
10598 u8 version_string_length[0x8];
10599
10600 u8 version[0x20];
10601
10602 u8 build_time[0x40];
10603
10604 u8 user_defined_time[0x40];
10605
10606 u8 build_tool_version[0x20];
10607
10608 u8 reserved_at_e0[0x20];
10609
10610 u8 version_string[92][0x8];
10611};
10612
10613struct mlx5_ifc_mcqi_activation_method_bits {
10614 u8 pending_server_ac_power_cycle[0x1];
10615 u8 pending_server_dc_power_cycle[0x1];
10616 u8 pending_server_reboot[0x1];
10617 u8 pending_fw_reset[0x1];
10618 u8 auto_activate[0x1];
10619 u8 all_hosts_sync[0x1];
10620 u8 device_hw_reset[0x1];
10621 u8 reserved_at_7[0x19];
10622};
10623
10624union mlx5_ifc_mcqi_reg_data_bits {
10625 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10626 struct mlx5_ifc_mcqi_version_bits mcqi_version;
10627 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10628};
10629
47176289
OG		 10630struct mlx5_ifc_mcqi_reg_bits {
10631 u8 read_pending_component[0x1];
10632 u8 reserved_at_1[0xf];
10633 u8 component_index[0x10];
10634
10635 u8 reserved_at_20[0x20];
10636
10637 u8 reserved_at_40[0x1b];
10638 u8 info_type[0x5];
10639
10640 u8 info_size[0x20];
10641
10642 u8 offset[0x20];
10643
10644 u8 reserved_at_a0[0x10];
10645 u8 data_size[0x10];
10646
b6ca09cb 10647 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 10648};
10649
10650struct mlx5_ifc_mcc_reg_bits {
10651 u8 reserved_at_0[0x4];
10652 u8 time_elapsed_since_last_cmd[0xc];
10653 u8 reserved_at_10[0x8];
10654 u8 instruction[0x8];
10655
10656 u8 reserved_at_20[0x10];
10657 u8 component_index[0x10];
10658
10659 u8 reserved_at_40[0x8];
10660 u8 update_handle[0x18];
10661
10662 u8 handle_owner_type[0x4];
10663 u8 handle_owner_host_id[0x4];
10664 u8 reserved_at_68[0x1];
10665 u8 control_progress[0x7];
10666 u8 error_code[0x8];
10667 u8 reserved_at_78[0x4];
10668 u8 control_state[0x4];
10669
10670 u8 component_size[0x20];
10671
10672 u8 reserved_at_a0[0x60];
10673};
10674
10675struct mlx5_ifc_mcda_reg_bits {
10676 u8 reserved_at_0[0x8];
10677 u8 update_handle[0x18];
10678
10679 u8 offset[0x20];
10680
10681 u8 reserved_at_40[0x10];
10682 u8 size[0x10];
10683
10684 u8 reserved_at_60[0x20];
10685
29056207 10686 u8 data[][0x20];
47176289
OG		 10687};
10688
72fb3b60
MS		 10689enum {
10690 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10691 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10692 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10693 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10694 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10695};
10696
06939536
MS		 10697enum {
10698 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10699 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10700};
10701
10702enum {
10703 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10704 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10705 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10706};
10707
10708struct mlx5_ifc_mfrl_reg_bits {
10709 u8 reserved_at_0[0x20];
10710
10711 u8 reserved_at_20[0x2];
10712 u8 pci_sync_for_fw_update_start[0x1];
10713 u8 pci_sync_for_fw_update_resp[0x2];
10714 u8 rst_type_sel[0x3];
72fb3b60
MS		 10715 u8 reserved_at_28[0x4];
10716 u8 reset_state[0x4];
06939536
MS		 10717 u8 reset_type[0x8];
10718 u8 reset_level[0x8];
10719};
10720
bab58ba1
EBE		 10721struct mlx5_ifc_mirc_reg_bits {
10722 u8 reserved_at_0[0x18];
10723 u8 status_code[0x8];
10724
10725 u8 reserved_at_20[0x20];
10726};
10727
36830159
MT		 10728struct mlx5_ifc_pddr_monitor_opcode_bits {
10729 u8 reserved_at_0[0x10];
10730 u8 monitor_opcode[0x10];
10731};
10732
10733union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10734 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10735 u8 reserved_at_0[0x20];
10736};
10737
10738enum {
10739 /* Monitor opcodes */
10740 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10741};
10742
10743struct mlx5_ifc_pddr_troubleshooting_page_bits {
10744 u8 reserved_at_0[0x10];
10745 u8 group_opcode[0x10];
10746
10747 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10748
10749 u8 reserved_at_40[0x20];
10750
10751 u8 status_message[59][0x20];
10752};
10753
10754union mlx5_ifc_pddr_reg_page_data_auto_bits {
10755 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10756 u8 reserved_at_0[0x7c0];
10757};
10758
10759enum {
10760 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10761};
10762
10763struct mlx5_ifc_pddr_reg_bits {
10764 u8 reserved_at_0[0x8];
10765 u8 local_port[0x8];
10766 u8 pnat[0x2];
10767 u8 reserved_at_12[0xe];
10768
10769 u8 reserved_at_20[0x18];
10770 u8 page_select[0x8];
10771
10772 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10773};
10774
5a1023de
AL		 10775struct mlx5_ifc_mrtc_reg_bits {
10776 u8 time_synced[0x1];
10777 u8 reserved_at_1[0x1f];
10778
10779 u8 reserved_at_20[0x20];
10780
10781 u8 time_h[0x20];
10782
10783 u8 time_l[0x20];
10784};
10785
e281682b
SM		 10786union mlx5_ifc_ports_control_registers_document_bits {
10787 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10788 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10789 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10790 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10791 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10792 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10793 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 10794 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10795 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 10796 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10797 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10798 struct mlx5_ifc_paos_reg_bits paos_reg;
10799 struct mlx5_ifc_pcap_reg_bits pcap_reg;
36830159
MT		 10800 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10801 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10802 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
e281682b
SM		 10803 struct mlx5_ifc_peir_reg_bits peir_reg;
10804 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10805 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 10806 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 10807 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10808 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10809 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10810 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10811 struct mlx5_ifc_plib_reg_bits plib_reg;
10812 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10813 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10814 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10815 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10816 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10817 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10818 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10819 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10820 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10821 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 10822 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 10823 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 10824 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10825 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10826 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10827 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10828 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10829 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10830 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 10831 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 10832 struct mlx5_ifc_pude_reg_bits pude_reg;
10833 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10834 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10835 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 10836 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10837 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 10838 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 10839 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10840 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 10841 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10842 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10843 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 10844 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 10845 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
ae02d415 10846 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
5a1023de 10847 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
b4ff3a36 10848 u8 reserved_at_0[0x60e0];
e281682b
SM		 10849};
10850
10851union mlx5_ifc_debug_enhancements_document_bits {
10852 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 10853 u8 reserved_at_0[0x200];
e281682b
SM		 10854};
10855
10856union mlx5_ifc_uplink_pci_interface_document_bits {
10857 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 10858 u8 reserved_at_0[0x20060];
b775516b
EC		 10859};
10860
2cc43b49
MG		 10861struct mlx5_ifc_set_flow_table_root_out_bits {
10862 u8 status[0x8];
b4ff3a36 10863 u8 reserved_at_8[0x18];
2cc43b49
MG		 10864
10865 u8 syndrome[0x20];
10866
b4ff3a36 10867 u8 reserved_at_40[0x40];
2cc43b49
MG		 10868};
10869
10870struct mlx5_ifc_set_flow_table_root_in_bits {
10871 u8 opcode[0x10];
b4ff3a36 10872 u8 reserved_at_10[0x10];
2cc43b49 10873
b4ff3a36 10874 u8 reserved_at_20[0x10];
2cc43b49
MG		 10875 u8 op_mod[0x10];
10876
7d5e1423
SM		 10877 u8 other_vport[0x1];
10878 u8 reserved_at_41[0xf];
10879 u8 vport_number[0x10];
10880
10881 u8 reserved_at_60[0x20];
2cc43b49
MG		 10882
10883 u8 table_type[0x8];
c3e666f1
MB		 10884 u8 reserved_at_88[0x7];
10885 u8 table_of_other_vport[0x1];
10886 u8 table_vport_number[0x10];
2cc43b49 10887
b4ff3a36 10888 u8 reserved_at_a0[0x8];
2cc43b49
MG		 10889 u8 table_id[0x18];
10890
500a3d0d
ES		 10891 u8 reserved_at_c0[0x8];
10892 u8 underlay_qpn[0x18];
c3e666f1
MB		 10893 u8 table_eswitch_owner_vhca_id_valid[0x1];
10894 u8 reserved_at_e1[0xf];
10895 u8 table_eswitch_owner_vhca_id[0x10];
10896 u8 reserved_at_100[0x100];
2cc43b49
MG		 10897};
10898
34a40e68 10899enum {
84df61eb
AH		 10900 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10901 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 10902};
10903
10904struct mlx5_ifc_modify_flow_table_out_bits {
10905 u8 status[0x8];
b4ff3a36 10906 u8 reserved_at_8[0x18];
34a40e68
MG		 10907
10908 u8 syndrome[0x20];
10909
b4ff3a36 10910 u8 reserved_at_40[0x40];
34a40e68
MG		 10911};
10912
10913struct mlx5_ifc_modify_flow_table_in_bits {
10914 u8 opcode[0x10];
b4ff3a36 10915 u8 reserved_at_10[0x10];
34a40e68 10916
b4ff3a36 10917 u8 reserved_at_20[0x10];
34a40e68
MG		 10918 u8 op_mod[0x10];
10919
7d5e1423
SM		 10920 u8 other_vport[0x1];
10921 u8 reserved_at_41[0xf];
10922 u8 vport_number[0x10];
34a40e68 10923
b4ff3a36 10924 u8 reserved_at_60[0x10];
34a40e68
MG		 10925 u8 modify_field_select[0x10];
10926
10927 u8 table_type[0x8];
b4ff3a36 10928 u8 reserved_at_88[0x18];
34a40e68 10929
b4ff3a36 10930 u8 reserved_at_a0[0x8];
34a40e68
MG		 10931 u8 table_id[0x18];
10932
0c90e9c6 10933 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 10934};
10935
4f3961ee
SM		 10936struct mlx5_ifc_ets_tcn_config_reg_bits {
10937 u8 g[0x1];
10938 u8 b[0x1];
10939 u8 r[0x1];
10940 u8 reserved_at_3[0x9];
10941 u8 group[0x4];
10942 u8 reserved_at_10[0x9];
10943 u8 bw_allocation[0x7];
10944
10945 u8 reserved_at_20[0xc];
10946 u8 max_bw_units[0x4];
10947 u8 reserved_at_30[0x8];
10948 u8 max_bw_value[0x8];
10949};
10950
10951struct mlx5_ifc_ets_global_config_reg_bits {
10952 u8 reserved_at_0[0x2];
10953 u8 r[0x1];
10954 u8 reserved_at_3[0x1d];
10955
10956 u8 reserved_at_20[0xc];
10957 u8 max_bw_units[0x4];
10958 u8 reserved_at_30[0x8];
10959 u8 max_bw_value[0x8];
10960};
10961
10962struct mlx5_ifc_qetc_reg_bits {
10963 u8 reserved_at_0[0x8];
10964 u8 port_number[0x8];
10965 u8 reserved_at_10[0x30];
10966
10967 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10968 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10969};
10970
415a64aa
HN		 10971struct mlx5_ifc_qpdpm_dscp_reg_bits {
10972 u8 e[0x1];
10973 u8 reserved_at_01[0x0b];
10974 u8 prio[0x04];
10975};
10976
10977struct mlx5_ifc_qpdpm_reg_bits {
10978 u8 reserved_at_0[0x8];
10979 u8 local_port[0x8];
10980 u8 reserved_at_10[0x10];
10981 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10982};
10983
10984struct mlx5_ifc_qpts_reg_bits {
10985 u8 reserved_at_0[0x8];
10986 u8 local_port[0x8];
10987 u8 reserved_at_10[0x2d];
10988 u8 trust_state[0x3];
10989};
10990
50b4a3c2
HN		 10991struct mlx5_ifc_pptb_reg_bits {
10992 u8 reserved_at_0[0x2];
10993 u8 mm[0x2];
10994 u8 reserved_at_4[0x4];
10995 u8 local_port[0x8];
10996 u8 reserved_at_10[0x6];
10997 u8 cm[0x1];
10998 u8 um[0x1];
10999 u8 pm[0x8];
11000
11001 u8 prio_x_buff[0x20];
11002
11003 u8 pm_msb[0x8];
11004 u8 reserved_at_48[0x10];
11005 u8 ctrl_buff[0x4];
11006 u8 untagged_buff[0x4];
11007};
11008
88b3d5c9
EBE		 11009struct mlx5_ifc_sbcam_reg_bits {
11010 u8 reserved_at_0[0x8];
11011 u8 feature_group[0x8];
11012 u8 reserved_at_10[0x8];
11013 u8 access_reg_group[0x8];
11014
11015 u8 reserved_at_20[0x20];
11016
11017 u8 sb_access_reg_cap_mask[4][0x20];
11018
11019 u8 reserved_at_c0[0x80];
11020
11021 u8 sb_feature_cap_mask[4][0x20];
11022
11023 u8 reserved_at_1c0[0x40];
11024
11025 u8 cap_total_buffer_size[0x20];
11026
11027 u8 cap_cell_size[0x10];
11028 u8 cap_max_pg_buffers[0x8];
11029 u8 cap_num_pool_supported[0x8];
11030
11031 u8 reserved_at_240[0x8];
11032 u8 cap_sbsr_stat_size[0x8];
11033 u8 cap_max_tclass_data[0x8];
11034 u8 cap_max_cpu_ingress_tclass_sb[0x8];
11035};
11036
50b4a3c2
HN		 11037struct mlx5_ifc_pbmc_reg_bits {
11038 u8 reserved_at_0[0x8];
11039 u8 local_port[0x8];
11040 u8 reserved_at_10[0x10];
11041
11042 u8 xoff_timer_value[0x10];
11043 u8 xoff_refresh[0x10];
11044
11045 u8 reserved_at_40[0x9];
11046 u8 fullness_threshold[0x7];
11047 u8 port_buffer_size[0x10];
11048
11049 struct mlx5_ifc_bufferx_reg_bits buffer[10];
11050
534b1204 11051 u8 reserved_at_2e0[0x80];
50b4a3c2
HN		 11052};
11053
4f3961ee
SM		 11054struct mlx5_ifc_qtct_reg_bits {
11055 u8 reserved_at_0[0x8];
11056 u8 port_number[0x8];
11057 u8 reserved_at_10[0xd];
11058 u8 prio[0x3];
11059
11060 u8 reserved_at_20[0x1d];
11061 u8 tclass[0x3];
11062};
11063
7d5e1423
SM		 11064struct mlx5_ifc_mcia_reg_bits {
11065 u8 l[0x1];
11066 u8 reserved_at_1[0x7];
11067 u8 module[0x8];
11068 u8 reserved_at_10[0x8];
11069 u8 status[0x8];
11070
11071 u8 i2c_device_address[0x8];
11072 u8 page_number[0x8];
11073 u8 device_address[0x10];
11074
11075 u8 reserved_at_40[0x10];
11076 u8 size[0x10];
11077
11078 u8 reserved_at_60[0x20];
11079
11080 u8 dword_0[0x20];
11081 u8 dword_1[0x20];
11082 u8 dword_2[0x20];
11083 u8 dword_3[0x20];
11084 u8 dword_4[0x20];
11085 u8 dword_5[0x20];
11086 u8 dword_6[0x20];
11087 u8 dword_7[0x20];
11088 u8 dword_8[0x20];
11089 u8 dword_9[0x20];
11090 u8 dword_10[0x20];
11091 u8 dword_11[0x20];
11092};
11093
7486216b
SM		 11094struct mlx5_ifc_dcbx_param_bits {
11095 u8 dcbx_cee_cap[0x1];
11096 u8 dcbx_ieee_cap[0x1];
11097 u8 dcbx_standby_cap[0x1];
c74d90c1 11098 u8 reserved_at_3[0x5];
7486216b
SM		 11099 u8 port_number[0x8];
11100 u8 reserved_at_10[0xa];
11101 u8 max_application_table_size[6];
11102 u8 reserved_at_20[0x15];
11103 u8 version_oper[0x3];
11104 u8 reserved_at_38[5];
11105 u8 version_admin[0x3];
11106 u8 willing_admin[0x1];
11107 u8 reserved_at_41[0x3];
11108 u8 pfc_cap_oper[0x4];
11109 u8 reserved_at_48[0x4];
11110 u8 pfc_cap_admin[0x4];
11111 u8 reserved_at_50[0x4];
11112 u8 num_of_tc_oper[0x4];
11113 u8 reserved_at_58[0x4];
11114 u8 num_of_tc_admin[0x4];
11115 u8 remote_willing[0x1];
11116 u8 reserved_at_61[3];
11117 u8 remote_pfc_cap[4];
11118 u8 reserved_at_68[0x14];
11119 u8 remote_num_of_tc[0x4];
11120 u8 reserved_at_80[0x18];
11121 u8 error[0x8];
11122 u8 reserved_at_a0[0x160];
11123};
84df61eb 11124
425a563a
MG		 11125enum {
11126 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
94db3317
EC		 11127 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11128 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
425a563a
MG		 11129};
11130
84df61eb 11131struct mlx5_ifc_lagc_bits {
c3e666f1 11132 u8 fdb_selection_mode[0x1];
425a563a
MG		 11133 u8 reserved_at_1[0x14];
11134 u8 port_select_mode[0x3];
11135 u8 reserved_at_18[0x5];
84df61eb
AH		 11136 u8 lag_state[0x3];
11137
8d1ac895
LC		 11138 u8 reserved_at_20[0xc];
11139 u8 active_port[0x4];
11140 u8 reserved_at_30[0x4];
84df61eb
AH		 11141 u8 tx_remap_affinity_2[0x4];
11142 u8 reserved_at_38[0x4];
11143 u8 tx_remap_affinity_1[0x4];
11144};
11145
11146struct mlx5_ifc_create_lag_out_bits {
11147 u8 status[0x8];
11148 u8 reserved_at_8[0x18];
11149
11150 u8 syndrome[0x20];
11151
11152 u8 reserved_at_40[0x40];
11153};
11154
11155struct mlx5_ifc_create_lag_in_bits {
11156 u8 opcode[0x10];
11157 u8 reserved_at_10[0x10];
11158
11159 u8 reserved_at_20[0x10];
11160 u8 op_mod[0x10];
11161
11162 struct mlx5_ifc_lagc_bits ctx;
11163};
11164
11165struct mlx5_ifc_modify_lag_out_bits {
11166 u8 status[0x8];
11167 u8 reserved_at_8[0x18];
11168
11169 u8 syndrome[0x20];
11170
11171 u8 reserved_at_40[0x40];
11172};
11173
11174struct mlx5_ifc_modify_lag_in_bits {
11175 u8 opcode[0x10];
11176 u8 reserved_at_10[0x10];
11177
11178 u8 reserved_at_20[0x10];
11179 u8 op_mod[0x10];
11180
11181 u8 reserved_at_40[0x20];
11182 u8 field_select[0x20];
11183
11184 struct mlx5_ifc_lagc_bits ctx;
11185};
11186
11187struct mlx5_ifc_query_lag_out_bits {
11188 u8 status[0x8];
11189 u8 reserved_at_8[0x18];
11190
11191 u8 syndrome[0x20];
11192
84df61eb
AH		 11193 struct mlx5_ifc_lagc_bits ctx;
11194};
11195
11196struct mlx5_ifc_query_lag_in_bits {
11197 u8 opcode[0x10];
11198 u8 reserved_at_10[0x10];
11199
11200 u8 reserved_at_20[0x10];
11201 u8 op_mod[0x10];
11202
11203 u8 reserved_at_40[0x40];
11204};
11205
11206struct mlx5_ifc_destroy_lag_out_bits {
11207 u8 status[0x8];
11208 u8 reserved_at_8[0x18];
11209
11210 u8 syndrome[0x20];
11211
11212 u8 reserved_at_40[0x40];
11213};
11214
11215struct mlx5_ifc_destroy_lag_in_bits {
11216 u8 opcode[0x10];
11217 u8 reserved_at_10[0x10];
11218
11219 u8 reserved_at_20[0x10];
11220 u8 op_mod[0x10];
11221
11222 u8 reserved_at_40[0x40];
11223};
11224
11225struct mlx5_ifc_create_vport_lag_out_bits {
11226 u8 status[0x8];
11227 u8 reserved_at_8[0x18];
11228
11229 u8 syndrome[0x20];
11230
11231 u8 reserved_at_40[0x40];
11232};
11233
11234struct mlx5_ifc_create_vport_lag_in_bits {
11235 u8 opcode[0x10];
11236 u8 reserved_at_10[0x10];
11237
11238 u8 reserved_at_20[0x10];
11239 u8 op_mod[0x10];
11240
11241 u8 reserved_at_40[0x40];
11242};
11243
11244struct mlx5_ifc_destroy_vport_lag_out_bits {
11245 u8 status[0x8];
11246 u8 reserved_at_8[0x18];
11247
11248 u8 syndrome[0x20];
11249
11250 u8 reserved_at_40[0x40];
11251};
11252
11253struct mlx5_ifc_destroy_vport_lag_in_bits {
11254 u8 opcode[0x10];
11255 u8 reserved_at_10[0x10];
11256
11257 u8 reserved_at_20[0x10];
11258 u8 op_mod[0x10];
11259
11260 u8 reserved_at_40[0x40];
11261};
11262
63f9c44b
MG		 11263enum {
11264 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11265 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11266};
11267
11268struct mlx5_ifc_modify_memic_in_bits {
11269 u8 opcode[0x10];
11270 u8 uid[0x10];
11271
11272 u8 reserved_at_20[0x10];
11273 u8 op_mod[0x10];
11274
11275 u8 reserved_at_40[0x20];
11276
11277 u8 reserved_at_60[0x18];
11278 u8 memic_operation_type[0x8];
11279
11280 u8 memic_start_addr[0x40];
11281
11282 u8 reserved_at_c0[0x140];
11283};
11284
11285struct mlx5_ifc_modify_memic_out_bits {
11286 u8 status[0x8];
11287 u8 reserved_at_8[0x18];
11288
11289 u8 syndrome[0x20];
11290
11291 u8 reserved_at_40[0x40];
11292
11293 u8 memic_operation_addr[0x40];
11294
11295 u8 reserved_at_c0[0x140];
11296};
11297
24da0016
AL		 11298struct mlx5_ifc_alloc_memic_in_bits {
11299 u8 opcode[0x10];
11300 u8 reserved_at_10[0x10];
11301
11302 u8 reserved_at_20[0x10];
11303 u8 op_mod[0x10];
11304
11305 u8 reserved_at_30[0x20];
11306
11307 u8 reserved_at_40[0x18];
11308 u8 log_memic_addr_alignment[0x8];
11309
11310 u8 range_start_addr[0x40];
11311
11312 u8 range_size[0x20];
11313
11314 u8 memic_size[0x20];
11315};
11316
11317struct mlx5_ifc_alloc_memic_out_bits {
11318 u8 status[0x8];
11319 u8 reserved_at_8[0x18];
11320
11321 u8 syndrome[0x20];
11322
11323 u8 memic_start_addr[0x40];
11324};
11325
11326struct mlx5_ifc_dealloc_memic_in_bits {
11327 u8 opcode[0x10];
11328 u8 reserved_at_10[0x10];
11329
11330 u8 reserved_at_20[0x10];
11331 u8 op_mod[0x10];
11332
11333 u8 reserved_at_40[0x40];
11334
11335 u8 memic_start_addr[0x40];
11336
11337 u8 memic_size[0x20];
11338
11339 u8 reserved_at_e0[0x20];
11340};
11341
11342struct mlx5_ifc_dealloc_memic_out_bits {
11343 u8 status[0x8];
11344 u8 reserved_at_8[0x18];
11345
11346 u8 syndrome[0x20];
11347
11348 u8 reserved_at_40[0x40];
11349};
11350
38b7ca92 11351struct mlx5_ifc_umem_bits {
6e3722ba 11352 u8 reserved_at_0[0x80];
38b7ca92 11353
4bf207d7
JG		 11354 u8 ats[0x1];
11355 u8 reserved_at_81[0x1a];
38b7ca92
YH		 11356 u8 log_page_size[0x5];
11357
11358 u8 page_offset[0x20];
11359
11360 u8 num_of_mtt[0x40];
11361
b6ca09cb 11362 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 11363};
11364
11365struct mlx5_ifc_uctx_bits {
9d43faac
YH		 11366 u8 cap[0x20];
11367
6e3722ba 11368 u8 reserved_at_20[0x160];
38b7ca92
YH		 11369};
11370
9fba2b9b
AL		 11371struct mlx5_ifc_sw_icm_bits {
11372 u8 modify_field_select[0x40];
11373
11374 u8 reserved_at_40[0x18];
11375 u8 log_sw_icm_size[0x8];
11376
11377 u8 reserved_at_60[0x20];
11378
11379 u8 sw_icm_start_addr[0x40];
11380
11381 u8 reserved_at_c0[0x140];
91a40a48 11382};
b169e64a
YK		 11383
11384struct mlx5_ifc_geneve_tlv_option_bits {
11385 u8 modify_field_select[0x40];
11386
11387 u8 reserved_at_40[0x18];
11388 u8 geneve_option_fte_index[0x8];
11389
11390 u8 option_class[0x10];
11391 u8 option_type[0x8];
11392 u8 reserved_at_78[0x3];
11393 u8 option_data_length[0x5];
11394
11395 u8 reserved_at_80[0x180];
9fba2b9b
AL		 11396};
11397
38b7ca92 11398struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 11399 u8 opcode[0x10];
11400 u8 uid[0x10];
11401
11402 u8 reserved_at_20[0x10];
11403 u8 op_mod[0x10];
11404
11405 u8 reserved_at_40[0x40];
11406
11407 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 11408};
11409
8a06a79b
EC		 11410struct mlx5_ifc_create_umem_out_bits {
11411 u8 status[0x8];
11412 u8 reserved_at_8[0x18];
11413
11414 u8 syndrome[0x20];
11415
11416 u8 reserved_at_40[0x8];
11417 u8 umem_id[0x18];
11418
11419 u8 reserved_at_60[0x20];
11420};
11421
11422struct mlx5_ifc_destroy_umem_in_bits {
11423 u8 opcode[0x10];
11424 u8 uid[0x10];
11425
11426 u8 reserved_at_20[0x10];
11427 u8 op_mod[0x10];
11428
11429 u8 reserved_at_40[0x8];
11430 u8 umem_id[0x18];
11431
11432 u8 reserved_at_60[0x20];
11433};
11434
11435struct mlx5_ifc_destroy_umem_out_bits {
11436 u8 status[0x8];
11437 u8 reserved_at_8[0x18];
11438
11439 u8 syndrome[0x20];
11440
11441 u8 reserved_at_40[0x40];
11442};
11443
38b7ca92 11444struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 11445 u8 opcode[0x10];
11446 u8 reserved_at_10[0x10];
11447
11448 u8 reserved_at_20[0x10];
11449 u8 op_mod[0x10];
11450
11451 u8 reserved_at_40[0x40];
11452
11453 struct mlx5_ifc_uctx_bits uctx;
11454};
11455
8a06a79b
EC		 11456struct mlx5_ifc_create_uctx_out_bits {
11457 u8 status[0x8];
11458 u8 reserved_at_8[0x18];
11459
11460 u8 syndrome[0x20];
11461
11462 u8 reserved_at_40[0x10];
11463 u8 uid[0x10];
11464
11465 u8 reserved_at_60[0x20];
11466};
11467
6e3722ba
YH		 11468struct mlx5_ifc_destroy_uctx_in_bits {
11469 u8 opcode[0x10];
11470 u8 reserved_at_10[0x10];
11471
11472 u8 reserved_at_20[0x10];
11473 u8 op_mod[0x10];
11474
11475 u8 reserved_at_40[0x10];
11476 u8 uid[0x10];
11477
11478 u8 reserved_at_60[0x20];
38b7ca92
YH		 11479};
11480
8a06a79b
EC		 11481struct mlx5_ifc_destroy_uctx_out_bits {
11482 u8 status[0x8];
11483 u8 reserved_at_8[0x18];
11484
11485 u8 syndrome[0x20];
11486
11487 u8 reserved_at_40[0x40];
11488};
11489
9fba2b9b
AL		 11490struct mlx5_ifc_create_sw_icm_in_bits {
11491 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11492 struct mlx5_ifc_sw_icm_bits sw_icm;
11493};
11494
b169e64a
YK		 11495struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11496 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11497 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11498};
11499
eff8ea8f
FD		 11500struct mlx5_ifc_mtrc_string_db_param_bits {
11501 u8 string_db_base_address[0x20];
11502
11503 u8 reserved_at_20[0x8];
11504 u8 string_db_size[0x18];
11505};
11506
11507struct mlx5_ifc_mtrc_cap_bits {
11508 u8 trace_owner[0x1];
11509 u8 trace_to_memory[0x1];
11510 u8 reserved_at_2[0x4];
11511 u8 trc_ver[0x2];
11512 u8 reserved_at_8[0x14];
11513 u8 num_string_db[0x4];
11514
11515 u8 first_string_trace[0x8];
11516 u8 num_string_trace[0x8];
11517 u8 reserved_at_30[0x28];
11518
11519 u8 log_max_trace_buffer_size[0x8];
11520
11521 u8 reserved_at_60[0x20];
11522
11523 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11524
11525 u8 reserved_at_280[0x180];
11526};
11527
11528struct mlx5_ifc_mtrc_conf_bits {
11529 u8 reserved_at_0[0x1c];
11530 u8 trace_mode[0x4];
11531 u8 reserved_at_20[0x18];
11532 u8 log_trace_buffer_size[0x8];
11533 u8 trace_mkey[0x20];
11534 u8 reserved_at_60[0x3a0];
11535};
11536
11537struct mlx5_ifc_mtrc_stdb_bits {
11538 u8 string_db_index[0x4];
11539 u8 reserved_at_4[0x4];
11540 u8 read_size[0x18];
11541 u8 start_offset[0x20];
b6ca09cb 11542 u8 string_db_data[];
eff8ea8f
FD		 11543};
11544
11545struct mlx5_ifc_mtrc_ctrl_bits {
11546 u8 trace_status[0x2];
11547 u8 reserved_at_2[0x2];
11548 u8 arm_event[0x1];
11549 u8 reserved_at_5[0xb];
11550 u8 modify_field_select[0x10];
11551 u8 reserved_at_20[0x2b];
11552 u8 current_timestamp52_32[0x15];
11553 u8 current_timestamp31_0[0x20];
11554 u8 reserved_at_80[0x180];
11555};
11556
c3a4e9f1
BW		 11557struct mlx5_ifc_host_params_context_bits {
11558 u8 host_number[0x8];
5ccf2770
BW		 11559 u8 reserved_at_8[0x7];
11560 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 11561 u8 host_num_of_vfs[0x10];
11562
86eec50b 11563 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 11564 u8 host_pci_bus[0x10];
11565
11566 u8 reserved_at_40[0x10];
11567 u8 host_pci_device[0x10];
11568
11569 u8 reserved_at_60[0x10];
11570 u8 host_pci_function[0x10];
11571
11572 u8 reserved_at_80[0x180];
11573};
11574
cd56f929 11575struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 11576 u8 opcode[0x10];
11577 u8 reserved_at_10[0x10];
11578
11579 u8 reserved_at_20[0x10];
11580 u8 op_mod[0x10];
11581
11582 u8 reserved_at_40[0x40];
11583};
11584
cd56f929 11585struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 11586 u8 status[0x8];
11587 u8 reserved_at_8[0x18];
11588
11589 u8 syndrome[0x20];
11590
11591 u8 reserved_at_40[0x40];
11592
11593 struct mlx5_ifc_host_params_context_bits host_params_context;
11594
11595 u8 reserved_at_280[0x180];
b6ca09cb 11596 u8 host_sf_enable[][0x40];
1759d322
PP		 11597};
11598
11599struct mlx5_ifc_sf_partition_bits {
11600 u8 reserved_at_0[0x10];
11601 u8 log_num_sf[0x8];
11602 u8 log_sf_bar_size[0x8];
11603};
11604
11605struct mlx5_ifc_query_sf_partitions_out_bits {
11606 u8 status[0x8];
11607 u8 reserved_at_8[0x18];
11608
11609 u8 syndrome[0x20];
11610
11611 u8 reserved_at_40[0x18];
11612 u8 num_sf_partitions[0x8];
11613
11614 u8 reserved_at_60[0x20];
11615
b6ca09cb 11616 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 11617};
11618
11619struct mlx5_ifc_query_sf_partitions_in_bits {
11620 u8 opcode[0x10];
11621 u8 reserved_at_10[0x10];
11622
11623 u8 reserved_at_20[0x10];
11624 u8 op_mod[0x10];
11625
11626 u8 reserved_at_40[0x40];
11627};
11628
11629struct mlx5_ifc_dealloc_sf_out_bits {
11630 u8 status[0x8];
11631 u8 reserved_at_8[0x18];
11632
11633 u8 syndrome[0x20];
11634
11635 u8 reserved_at_40[0x40];
11636};
11637
11638struct mlx5_ifc_dealloc_sf_in_bits {
11639 u8 opcode[0x10];
11640 u8 reserved_at_10[0x10];
11641
11642 u8 reserved_at_20[0x10];
11643 u8 op_mod[0x10];
11644
11645 u8 reserved_at_40[0x10];
11646 u8 function_id[0x10];
11647
11648 u8 reserved_at_60[0x20];
11649};
11650
11651struct mlx5_ifc_alloc_sf_out_bits {
11652 u8 status[0x8];
11653 u8 reserved_at_8[0x18];
11654
11655 u8 syndrome[0x20];
11656
11657 u8 reserved_at_40[0x40];
11658};
11659
11660struct mlx5_ifc_alloc_sf_in_bits {
11661 u8 opcode[0x10];
11662 u8 reserved_at_10[0x10];
11663
11664 u8 reserved_at_20[0x10];
11665 u8 op_mod[0x10];
11666
11667 u8 reserved_at_40[0x10];
11668 u8 function_id[0x10];
11669
11670 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 11671};
11672
e4075c44
YH		 11673struct mlx5_ifc_affiliated_event_header_bits {
11674 u8 reserved_at_0[0x10];
11675 u8 obj_type[0x10];
11676
11677 u8 obj_id[0x20];
11678};
11679
a12ff35e 11680enum {
49e27134
PP		 11681 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11682 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11683 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
f5d23ee1 11684 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
a12ff35e
EBE		 11685};
11686
11687enum {
11688 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 11689 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 11690 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
f5d23ee1 11691 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
8385c51f 11692 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
2b58f6d9
RS		 11693};
11694
11695enum {
11696 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
2b58f6d9
RS		 11697};
11698
3afee4ed
LR		 11699enum {
11700 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11701 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11702 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11703 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11704};
11705
11706enum {
11707 MLX5_IPSEC_ASO_MODE = 0x0,
11708 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11709 MLX5_IPSEC_ASO_INC_SN = 0x2,
11710};
11711
11712struct mlx5_ifc_ipsec_aso_bits {
11713 u8 valid[0x1];
11714 u8 reserved_at_201[0x1];
11715 u8 mode[0x2];
11716 u8 window_sz[0x2];
11717 u8 soft_lft_arm[0x1];
11718 u8 hard_lft_arm[0x1];
11719 u8 remove_flow_enable[0x1];
11720 u8 esn_event_arm[0x1];
11721 u8 reserved_at_20a[0x16];
11722
11723 u8 remove_flow_pkt_cnt[0x20];
11724
11725 u8 remove_flow_soft_lft[0x20];
11726
11727 u8 reserved_at_260[0x80];
11728
11729 u8 mode_parameter[0x20];
11730
11731 u8 replay_protection_window[0x100];
11732};
11733
2b58f6d9
RS		 11734struct mlx5_ifc_ipsec_obj_bits {
11735 u8 modify_field_select[0x40];
11736 u8 full_offload[0x1];
11737 u8 reserved_at_41[0x1];
11738 u8 esn_en[0x1];
11739 u8 esn_overlap[0x1];
11740 u8 reserved_at_44[0x2];
11741 u8 icv_length[0x2];
11742 u8 reserved_at_48[0x4];
11743 u8 aso_return_reg[0x4];
11744 u8 reserved_at_50[0x10];
11745
11746 u8 esn_msb[0x20];
11747
11748 u8 reserved_at_80[0x8];
11749 u8 dekn[0x18];
11750
11751 u8 salt[0x20];
11752
11753 u8 implicit_iv[0x40];
11754
3afee4ed
LR		 11755 u8 reserved_at_100[0x8];
11756 u8 ipsec_aso_access_pd[0x18];
11757 u8 reserved_at_120[0xe0];
11758
11759 struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
2b58f6d9
RS		 11760};
11761
11762struct mlx5_ifc_create_ipsec_obj_in_bits {
11763 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11764 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11765};
11766
11767enum {
11768 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11769 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11770};
11771
11772struct mlx5_ifc_query_ipsec_obj_out_bits {
11773 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11774 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11775};
11776
11777struct mlx5_ifc_modify_ipsec_obj_in_bits {
11778 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11779 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 11780};
11781
23cc83c6
EH		 11782enum {
11783 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11784};
11785
11786enum {
11787 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
11788 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
11789 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11790 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11791};
11792
11793#define MLX5_MACSEC_ASO_INC_SN 0x2
11794#define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11795
8385c51f
LN		 11796struct mlx5_ifc_macsec_aso_bits {
11797 u8 valid[0x1];
11798 u8 reserved_at_1[0x1];
11799 u8 mode[0x2];
11800 u8 window_size[0x2];
11801 u8 soft_lifetime_arm[0x1];
11802 u8 hard_lifetime_arm[0x1];
11803 u8 remove_flow_enable[0x1];
11804 u8 epn_event_arm[0x1];
11805 u8 reserved_at_a[0x16];
11806
11807 u8 remove_flow_packet_count[0x20];
11808
11809 u8 remove_flow_soft_lifetime[0x20];
11810
11811 u8 reserved_at_60[0x80];
11812
11813 u8 mode_parameter[0x20];
11814
11815 u8 replay_protection_window[8][0x20];
11816};
11817
11818struct mlx5_ifc_macsec_offload_obj_bits {
11819 u8 modify_field_select[0x40];
11820
11821 u8 confidentiality_en[0x1];
11822 u8 reserved_at_41[0x1];
21803630
EH		 11823 u8 epn_en[0x1];
11824 u8 epn_overlap[0x1];
8385c51f
LN		 11825 u8 reserved_at_44[0x2];
11826 u8 confidentiality_offset[0x2];
11827 u8 reserved_at_48[0x4];
11828 u8 aso_return_reg[0x4];
11829 u8 reserved_at_50[0x10];
11830
21803630 11831 u8 epn_msb[0x20];
8385c51f
LN		 11832
11833 u8 reserved_at_80[0x8];
11834 u8 dekn[0x18];
11835
11836 u8 reserved_at_a0[0x20];
11837
11838 u8 sci[0x40];
11839
11840 u8 reserved_at_100[0x8];
11841 u8 macsec_aso_access_pd[0x18];
11842
11843 u8 reserved_at_120[0x60];
11844
11845 u8 salt[3][0x20];
11846
11847 u8 reserved_at_1e0[0x20];
11848
11849 struct mlx5_ifc_macsec_aso_bits macsec_aso;
11850};
11851
11852struct mlx5_ifc_create_macsec_obj_in_bits {
11853 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11854 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11855};
11856
23cc83c6
EH		 11857struct mlx5_ifc_modify_macsec_obj_in_bits {
11858 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11859 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11860};
11861
11862enum {
11863 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
11864 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
11865};
11866
11867struct mlx5_ifc_query_macsec_obj_out_bits {
11868 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11869 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11870};
11871
a12ff35e
EBE		 11872struct mlx5_ifc_encryption_key_obj_bits {
11873 u8 modify_field_select[0x40];
11874
11875 u8 reserved_at_40[0x14];
11876 u8 key_size[0x4];
11877 u8 reserved_at_58[0x4];
11878 u8 key_type[0x4];
11879
11880 u8 reserved_at_60[0x8];
11881 u8 pd[0x18];
11882
11883 u8 reserved_at_80[0x180];
11884 u8 key[8][0x20];
11885
11886 u8 reserved_at_300[0x500];
11887};
11888
11889struct mlx5_ifc_create_encryption_key_in_bits {
11890 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11891 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11892};
11893
f5d23ee1
JL		 11894enum {
11895 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
11896 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
11897 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
11898 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
11899};
11900
11901struct mlx5_ifc_flow_meter_parameters_bits {
11902 u8 valid[0x1];
11903 u8 bucket_overflow[0x1];
11904 u8 start_color[0x2];
11905 u8 both_buckets_on_green[0x1];
11906 u8 reserved_at_5[0x1];
11907 u8 meter_mode[0x2];
11908 u8 reserved_at_8[0x18];
11909
11910 u8 reserved_at_20[0x20];
11911
11912 u8 reserved_at_40[0x3];
11913 u8 cbs_exponent[0x5];
11914 u8 cbs_mantissa[0x8];
11915 u8 reserved_at_50[0x3];
11916 u8 cir_exponent[0x5];
11917 u8 cir_mantissa[0x8];
11918
11919 u8 reserved_at_60[0x20];
11920
11921 u8 reserved_at_80[0x3];
11922 u8 ebs_exponent[0x5];
11923 u8 ebs_mantissa[0x8];
11924 u8 reserved_at_90[0x3];
11925 u8 eir_exponent[0x5];
11926 u8 eir_mantissa[0x8];
11927
11928 u8 reserved_at_a0[0x60];
11929};
11930
11931struct mlx5_ifc_flow_meter_aso_obj_bits {
11932 u8 modify_field_select[0x40];
11933
11934 u8 reserved_at_40[0x40];
11935
11936 u8 reserved_at_80[0x8];
11937 u8 meter_aso_access_pd[0x18];
11938
11939 u8 reserved_at_a0[0x160];
11940
11941 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11942};
11943
11944struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11945 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11946 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11947};
11948
2a297089
CM		 11949struct mlx5_ifc_sampler_obj_bits {
11950 u8 modify_field_select[0x40];
11951
11952 u8 table_type[0x8];
11953 u8 level[0x8];
11954 u8 reserved_at_50[0xf];
11955 u8 ignore_flow_level[0x1];
11956
11957 u8 sample_ratio[0x20];
11958
11959 u8 reserved_at_80[0x8];
11960 u8 sample_table_id[0x18];
11961
11962 u8 reserved_at_a0[0x8];
11963 u8 default_table_id[0x18];
11964
11965 u8 sw_steering_icm_address_rx[0x40];
11966 u8 sw_steering_icm_address_tx[0x40];
11967
11968 u8 reserved_at_140[0xa0];
11969};
11970
11971struct mlx5_ifc_create_sampler_obj_in_bits {
11972 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11973 struct mlx5_ifc_sampler_obj_bits sampler_object;
11974};
11975
1ab6dc35
YK		 11976struct mlx5_ifc_query_sampler_obj_out_bits {
11977 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11978 struct mlx5_ifc_sampler_obj_bits sampler_object;
11979};
11980
a12ff35e
EBE		 11981enum {
11982 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11983 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11984};
11985
11986enum {
bd673da6
SM		 11987 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11988 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
8385c51f 11989 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4,
a12ff35e
EBE		 11990};
11991
11992struct mlx5_ifc_tls_static_params_bits {
11993 u8 const_2[0x2];
11994 u8 tls_version[0x4];
11995 u8 const_1[0x2];
11996 u8 reserved_at_8[0x14];
11997 u8 encryption_standard[0x4];
11998
11999 u8 reserved_at_20[0x20];
12000
12001 u8 initial_record_number[0x40];
12002
12003 u8 resync_tcp_sn[0x20];
12004
12005 u8 gcm_iv[0x20];
12006
12007 u8 implicit_iv[0x40];
12008
12009 u8 reserved_at_100[0x8];
12010 u8 dek_index[0x18];
12011
12012 u8 reserved_at_120[0xe0];
12013};
12014
12015struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 12016 u8 next_record_tcp_sn[0x20];
12017
12018 u8 hw_resync_tcp_sn[0x20];
12019
12020 u8 record_tracker_state[0x2];
12021 u8 auth_state[0x2];
2d1b69ed 12022 u8 reserved_at_44[0x4];
a12ff35e
EBE		 12023 u8 hw_offset_record_number[0x18];
12024};
12025
1dcb6c36
EC		 12026enum {
12027 MLX5_MTT_PERM_READ = 1 << 0,
12028 MLX5_MTT_PERM_WRITE = 1 << 1,
12029 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12030};
12031
adfdaff3
YH		 12032enum {
12033 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
12034 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
12035};
12036
12037struct mlx5_ifc_suspend_vhca_in_bits {
12038 u8 opcode[0x10];
12039 u8 uid[0x10];
12040
12041 u8 reserved_at_20[0x10];
12042 u8 op_mod[0x10];
12043
12044 u8 reserved_at_40[0x10];
12045 u8 vhca_id[0x10];
12046
12047 u8 reserved_at_60[0x20];
12048};
12049
12050struct mlx5_ifc_suspend_vhca_out_bits {
12051 u8 status[0x8];
12052 u8 reserved_at_8[0x18];
12053
12054 u8 syndrome[0x20];
12055
12056 u8 reserved_at_40[0x40];
12057};
12058
12059enum {
12060 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
12061 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
12062};
12063
12064struct mlx5_ifc_resume_vhca_in_bits {
12065 u8 opcode[0x10];
12066 u8 uid[0x10];
12067
12068 u8 reserved_at_20[0x10];
12069 u8 op_mod[0x10];
12070
12071 u8 reserved_at_40[0x10];
12072 u8 vhca_id[0x10];
12073
12074 u8 reserved_at_60[0x20];
12075};
12076
12077struct mlx5_ifc_resume_vhca_out_bits {
12078 u8 status[0x8];
12079 u8 reserved_at_8[0x18];
12080
12081 u8 syndrome[0x20];
12082
12083 u8 reserved_at_40[0x40];
12084};
12085
12086struct mlx5_ifc_query_vhca_migration_state_in_bits {
12087 u8 opcode[0x10];
12088 u8 uid[0x10];
12089
12090 u8 reserved_at_20[0x10];
12091 u8 op_mod[0x10];
12092
c943a937
SD		 12093 u8 incremental[0x1];
12094 u8 reserved_at_41[0xf];
adfdaff3
YH		 12095 u8 vhca_id[0x10];
12096
12097 u8 reserved_at_60[0x20];
12098};
12099
12100struct mlx5_ifc_query_vhca_migration_state_out_bits {
12101 u8 status[0x8];
12102 u8 reserved_at_8[0x18];
12103
12104 u8 syndrome[0x20];
12105
12106 u8 reserved_at_40[0x40];
12107
12108 u8 required_umem_size[0x20];
12109
12110 u8 reserved_at_a0[0x160];
12111};
12112
12113struct mlx5_ifc_save_vhca_state_in_bits {
12114 u8 opcode[0x10];
12115 u8 uid[0x10];
12116
12117 u8 reserved_at_20[0x10];
12118 u8 op_mod[0x10];
12119
c943a937
SD		 12120 u8 incremental[0x1];
12121 u8 set_track[0x1];
12122 u8 reserved_at_42[0xe];
adfdaff3
YH		 12123 u8 vhca_id[0x10];
12124
12125 u8 reserved_at_60[0x20];
12126
12127 u8 va[0x40];
12128
12129 u8 mkey[0x20];
12130
12131 u8 size[0x20];
12132};
12133
12134struct mlx5_ifc_save_vhca_state_out_bits {
12135 u8 status[0x8];
12136 u8 reserved_at_8[0x18];
12137
12138 u8 syndrome[0x20];
12139
12140 u8 actual_image_size[0x20];
12141
12142 u8 reserved_at_60[0x20];
12143};
12144
12145struct mlx5_ifc_load_vhca_state_in_bits {
12146 u8 opcode[0x10];
12147 u8 uid[0x10];
12148
12149 u8 reserved_at_20[0x10];
12150 u8 op_mod[0x10];
12151
12152 u8 reserved_at_40[0x10];
12153 u8 vhca_id[0x10];
12154
12155 u8 reserved_at_60[0x20];
12156
12157 u8 va[0x40];
12158
12159 u8 mkey[0x20];
12160
12161 u8 size[0x20];
12162};
12163
12164struct mlx5_ifc_load_vhca_state_out_bits {
12165 u8 status[0x8];
12166 u8 reserved_at_8[0x18];
12167
12168 u8 syndrome[0x20];
12169
12170 u8 reserved_at_40[0x40];
12171};
12172
a1be74c5
YH		 12173struct mlx5_ifc_adv_virtualization_cap_bits {
12174 u8 reserved_at_0[0x3];
12175 u8 pg_track_log_max_num[0x5];
12176 u8 pg_track_max_num_range[0x8];
12177 u8 pg_track_log_min_addr_space[0x8];
12178 u8 pg_track_log_max_addr_space[0x8];
12179
12180 u8 reserved_at_20[0x3];
12181 u8 pg_track_log_min_msg_size[0x5];
12182 u8 reserved_at_28[0x3];
12183 u8 pg_track_log_max_msg_size[0x5];
12184 u8 reserved_at_30[0x3];
12185 u8 pg_track_log_min_page_size[0x5];
12186 u8 reserved_at_38[0x3];
12187 u8 pg_track_log_max_page_size[0x5];
12188
12189 u8 reserved_at_40[0x7c0];
12190};
12191
12192struct mlx5_ifc_page_track_report_entry_bits {
12193 u8 dirty_address_high[0x20];
12194
12195 u8 dirty_address_low[0x20];
12196};
12197
12198enum {
12199 MLX5_PAGE_TRACK_STATE_TRACKING,
12200 MLX5_PAGE_TRACK_STATE_REPORTING,
12201 MLX5_PAGE_TRACK_STATE_ERROR,
12202};
12203
12204struct mlx5_ifc_page_track_range_bits {
12205 u8 start_address[0x40];
12206
12207 u8 length[0x40];
12208};
12209
12210struct mlx5_ifc_page_track_bits {
12211 u8 modify_field_select[0x40];
12212
12213 u8 reserved_at_40[0x10];
12214 u8 vhca_id[0x10];
12215
12216 u8 reserved_at_60[0x20];
12217
12218 u8 state[0x4];
12219 u8 track_type[0x4];
12220 u8 log_addr_space_size[0x8];
12221 u8 reserved_at_90[0x3];
12222 u8 log_page_size[0x5];
12223 u8 reserved_at_98[0x3];
12224 u8 log_msg_size[0x5];
12225
12226 u8 reserved_at_a0[0x8];
12227 u8 reporting_qpn[0x18];
12228
12229 u8 reserved_at_c0[0x18];
12230 u8 num_ranges[0x8];
12231
12232 u8 reserved_at_e0[0x20];
12233
12234 u8 range_start_address[0x40];
12235
12236 u8 length[0x40];
12237
12238 struct mlx5_ifc_page_track_range_bits track_range[0];
12239};
12240
12241struct mlx5_ifc_create_page_track_obj_in_bits {
12242 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12243 struct mlx5_ifc_page_track_bits obj_context;
12244};
12245
12246struct mlx5_ifc_modify_page_track_obj_in_bits {
12247 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12248 struct mlx5_ifc_page_track_bits obj_context;
12249};
12250
d29b796a 12251#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)